Unified Coverage Report :: Group Instance : attest_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1432

1

T15

1

T16

3

T9

2

auto[1]

1553

1

T5

1

T16

1

T9

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T27	1		T23	1		T7	1
auto[134217728:268435455]	86	1			T24	1		T36	1		T6	2
auto[268435456:402653183]	87	1			T23	1		T89	1		T46	1
auto[402653184:536870911]	65	1			T5	1		T27	1		T89	1
auto[536870912:671088639]	102	1			T16	1		T9	1		T17	1
auto[671088640:805306367]	96	1			T27	1		T23	1		T6	1
auto[805306368:939524095]	108	1			T28	1		T44	2		T137	1
auto[939524096:1073741823]	109	1			T136	1		T6	1		T110	2
auto[1073741824:1207959551]	84	1			T27	2		T29	1		T44	1
auto[1207959552:1342177279]	100	1			T17	1		T139	1		T137	1
auto[1342177280:1476395007]	87	1			T17	1		T211	1		T89	1
auto[1476395008:1610612735]	88	1			T24	3		T36	1		T7	2
auto[1610612736:1744830463]	96	1			T27	1		T36	1		T6	1
auto[1744830464:1879048191]	74	1			T211	1		T30	2		T7	2
auto[1879048192:2013265919]	92	1			T16	1		T206	2		T61	2
auto[2013265920:2147483647]	98	1			T28	1		T24	1		T206	1
auto[2147483648:2281701375]	110	1			T28	1		T90	1		T30	1
auto[2281701376:2415919103]	98	1			T9	1		T28	1		T211	1
auto[2415919104:2550136831]	91	1			T6	1		T106	1		T210	1
auto[2550136832:2684354559]	94	1			T9	1		T23	1		T28	1
auto[2684354560:2818572287]	94	1			T90	1		T46	1		T106	1
auto[2818572288:2952790015]	107	1			T43	2		T36	1		T92	1
auto[2952790016:3087007743]	84	1			T15	1		T23	1		T36	2
auto[3087007744:3221225471]	91	1			T16	1		T46	1		T7	2
auto[3221225472:3355443199]	102	1			T36	1		T106	1		T7	1
auto[3355443200:3489660927]	96	1			T27	1		T61	2		T58	1
auto[3489660928:3623878655]	89	1			T16	1		T23	1		T24	1
auto[3623878656:3758096383]	107	1			T9	1		T89	1		T7	1
auto[3758096384:3892314111]	96	1			T258	1		T54	1		T69	1
auto[3892314112:4026531839]	86	1			T110	1		T7	2		T54	1
auto[4026531840:4160749567]	87	1			T7	2		T205	1		T61	2
auto[4160749568:4294967295]	86	1			T36	1		T137	1		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T23	1		T25	1		T270	1
auto[0:134217727]	auto[1]	53	1			T27	1		T7	1		T208	1
auto[134217728:268435455]	auto[0]	35	1			T24	1		T36	1		T6	1
auto[134217728:268435455]	auto[1]	51	1			T6	1		T7	1		T336	1
auto[268435456:402653183]	auto[0]	46	1			T23	1		T89	1		T46	1
auto[268435456:402653183]	auto[1]	41	1			T6	2		T7	1		T54	1
auto[402653184:536870911]	auto[0]	36	1			T24	1		T137	1		T61	1
auto[402653184:536870911]	auto[1]	29	1			T5	1		T27	1		T89	1
auto[536870912:671088639]	auto[0]	42	1			T6	1		T110	1		T258	1
auto[536870912:671088639]	auto[1]	60	1			T16	1		T9	1		T17	1
auto[671088640:805306367]	auto[0]	45	1			T23	1		T7	1		T92	1
auto[671088640:805306367]	auto[1]	51	1			T27	1		T6	1		T252	1
auto[805306368:939524095]	auto[0]	52	1			T44	1		T137	1		T6	1
auto[805306368:939524095]	auto[1]	56	1			T28	1		T44	1		T206	1
auto[939524096:1073741823]	auto[0]	57	1			T7	2		T33	1		T26	2
auto[939524096:1073741823]	auto[1]	52	1			T136	1		T6	1		T110	2
auto[1073741824:1207959551]	auto[0]	37	1			T27	1		T7	3		T258	1
auto[1073741824:1207959551]	auto[1]	47	1			T27	1		T29	1		T44	1
auto[1207959552:1342177279]	auto[0]	48	1			T139	1		T7	2		T26	1
auto[1207959552:1342177279]	auto[1]	52	1			T17	1		T137	1		T6	2
auto[1342177280:1476395007]	auto[0]	44	1			T211	1		T44	1		T106	1
auto[1342177280:1476395007]	auto[1]	43	1			T17	1		T89	1		T110	2
auto[1476395008:1610612735]	auto[0]	45	1			T24	3		T36	1		T7	2
auto[1476395008:1610612735]	auto[1]	43	1			T61	1		T336	1		T70	1
auto[1610612736:1744830463]	auto[0]	46	1			T27	1		T205	1		T61	2
auto[1610612736:1744830463]	auto[1]	50	1			T36	1		T6	1		T30	1
auto[1744830464:1879048191]	auto[0]	36	1			T30	1		T7	1		T205	1
auto[1744830464:1879048191]	auto[1]	38	1			T211	1		T30	1		T7	1
auto[1879048192:2013265919]	auto[0]	45	1			T16	1		T71	1		T342	1
auto[1879048192:2013265919]	auto[1]	47	1			T206	2		T61	2		T263	1
auto[2013265920:2147483647]	auto[0]	46	1			T24	1		T206	1		T93	1
auto[2013265920:2147483647]	auto[1]	52	1			T28	1		T7	1		T61	1
auto[2147483648:2281701375]	auto[0]	53	1			T7	1		T26	1		T417	1
auto[2147483648:2281701375]	auto[1]	57	1			T28	1		T90	1		T30	1
auto[2281701376:2415919103]	auto[0]	53	1			T9	1		T28	1		T54	1
auto[2281701376:2415919103]	auto[1]	45	1			T211	1		T110	1		T61	1
auto[2415919104:2550136831]	auto[0]	41	1			T106	1		T210	1		T7	1
auto[2415919104:2550136831]	auto[1]	50	1			T6	1		T64	1		T92	1
auto[2550136832:2684354559]	auto[0]	49	1			T9	1		T23	1		T43	1
auto[2550136832:2684354559]	auto[1]	45	1			T28	1		T136	1		T7	1
auto[2684354560:2818572287]	auto[0]	45	1			T90	1		T106	1		T144	1
auto[2684354560:2818572287]	auto[1]	49	1			T46	1		T7	1		T61	1
auto[2818572288:2952790015]	auto[0]	51	1			T43	2		T36	1		T92	1
auto[2818572288:2952790015]	auto[1]	56	1			T61	1		T58	1		T252	1
auto[2952790016:3087007743]	auto[0]	41	1			T15	1		T23	1		T36	1
auto[2952790016:3087007743]	auto[1]	43	1			T36	1		T263	1		T262	1
auto[3087007744:3221225471]	auto[0]	41	1			T16	1		T46	1		T7	2
auto[3087007744:3221225471]	auto[1]	50	1			T159	1		T61	1		T26	1
auto[3221225472:3355443199]	auto[0]	44	1			T36	1		T106	1		T7	1
auto[3221225472:3355443199]	auto[1]	58	1			T65	1		T270	1		T231	1
auto[3355443200:3489660927]	auto[0]	49	1			T27	1		T52	1		T214	1
auto[3355443200:3489660927]	auto[1]	47	1			T61	2		T58	1		T433	1
auto[3489660928:3623878655]	auto[0]	46	1			T16	1		T23	1		T24	1
auto[3489660928:3623878655]	auto[1]	43	1			T7	2		T61	1		T418	1
auto[3623878656:3758096383]	auto[0]	55	1			T7	1		T61	1		T19	1
auto[3623878656:3758096383]	auto[1]	52	1			T9	1		T89	1		T25	1
auto[3758096384:3892314111]	auto[0]	45	1			T258	1		T54	1		T144	1
auto[3758096384:3892314111]	auto[1]	51	1			T69	1		T61	1		T19	2
auto[3892314112:4026531839]	auto[0]	38	1			T54	1		T67	2		T263	1
auto[3892314112:4026531839]	auto[1]	48	1			T110	1		T7	2		T144	2
auto[4026531840:4160749567]	auto[0]	38	1			T205	1		T66	1		T231	1
auto[4026531840:4160749567]	auto[1]	49	1			T7	2		T61	2		T336	1
auto[4160749568:4294967295]	auto[0]	41	1			T137	1		T7	1		T408	1
auto[4160749568:4294967295]	auto[1]	45	1			T36	1		T258	1		T64	1