Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6154

1

T15

1

T16

8

T9

5

auto[1]

286

1

T17

3

T137

2

T144

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2603	1			T16	3		T9	2		T17	3
auto[134217728:268435455]	139	1			T23	1		T28	1		T89	1
auto[268435456:402653183]	141	1			T23	1		T137	2		T6	1
auto[402653184:536870911]	130	1			T16	1		T28	1		T29	1
auto[536870912:671088639]	126	1			T16	1		T27	1		T110	1
auto[671088640:805306367]	141	1			T211	1		T6	1		T7	2
auto[805306368:939524095]	131	1			T9	1		T89	2		T36	2
auto[939524096:1073741823]	136	1			T27	1		T24	2		T206	1
auto[1073741824:1207959551]	123	1			T6	1		T206	2		T7	1
auto[1207959552:1342177279]	136	1			T28	1		T137	1		T6	1
auto[1342177280:1476395007]	124	1			T16	1		T9	1		T17	1
auto[1476395008:1610612735]	132	1			T27	1		T23	1		T28	1
auto[1610612736:1744830463]	123	1			T23	1		T211	1		T36	1
auto[1744830464:1879048191]	124	1			T17	1		T89	1		T46	1
auto[1879048192:2013265919]	125	1			T27	1		T24	1		T6	1
auto[2013265920:2147483647]	106	1			T24	1		T36	1		T206	1
auto[2147483648:2281701375]	115	1			T27	1		T23	1		T90	1
auto[2281701376:2415919103]	115	1			T27	1		T23	1		T28	2
auto[2415919104:2550136831]	101	1			T23	1		T24	1		T139	1
auto[2550136832:2684354559]	121	1			T17	1		T24	1		T206	1
auto[2684354560:2818572287]	133	1			T90	1		T44	1		T6	1
auto[2818572288:2952790015]	126	1			T27	1		T6	1		T206	1
auto[2952790016:3087007743]	129	1			T23	1		T36	1		T137	1
auto[3087007744:3221225471]	123	1			T27	1		T23	1		T46	1
auto[3221225472:3355443199]	113	1			T9	1		T17	1		T36	1
auto[3355443200:3489660927]	129	1			T27	2		T28	2		T211	1
auto[3489660928:3623878655]	111	1			T24	1		T36	1		T136	1
auto[3623878656:3758096383]	107	1			T43	1		T7	1		T64	1
auto[3758096384:3892314111]	96	1			T16	1		T27	1		T89	1
auto[3892314112:4026531839]	126	1			T28	1		T36	1		T137	1
auto[4026531840:4160749567]	117	1			T15	1		T23	1		T24	1
auto[4160749568:4294967295]	138	1			T16	1		T206	1		T61	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2592	1			T16	3		T9	2		T17	3
auto[0:134217727]	auto[1]	11	1			T302	1		T287	1		T436	1
auto[134217728:268435455]	auto[0]	133	1			T23	1		T28	1		T89	1
auto[134217728:268435455]	auto[1]	6	1			T144	1		T308	1		T432	1
auto[268435456:402653183]	auto[0]	130	1			T23	1		T137	1		T6	1
auto[268435456:402653183]	auto[1]	11	1			T137	1		T159	2		T311	1
auto[402653184:536870911]	auto[0]	124	1			T16	1		T28	1		T29	1
auto[402653184:536870911]	auto[1]	6	1			T144	1		T243	1		T308	1
auto[536870912:671088639]	auto[0]	119	1			T16	1		T27	1		T110	1
auto[536870912:671088639]	auto[1]	7	1			T426	1		T436	1		T428	1
auto[671088640:805306367]	auto[0]	133	1			T211	1		T6	1		T7	2
auto[671088640:805306367]	auto[1]	8	1			T311	2		T429	1		T244	1
auto[805306368:939524095]	auto[0]	118	1			T9	1		T89	2		T36	2
auto[805306368:939524095]	auto[1]	13	1			T311	2		T243	1		T245	1
auto[939524096:1073741823]	auto[0]	126	1			T27	1		T24	2		T206	1
auto[939524096:1073741823]	auto[1]	10	1			T266	1		T396	1		T284	1
auto[1073741824:1207959551]	auto[0]	120	1			T6	1		T206	2		T7	1
auto[1073741824:1207959551]	auto[1]	3	1			T250	1		T288	1		T425	1
auto[1207959552:1342177279]	auto[0]	123	1			T28	1		T137	1		T6	1
auto[1207959552:1342177279]	auto[1]	13	1			T144	1		T250	1		T426	1
auto[1342177280:1476395007]	auto[0]	116	1			T16	1		T9	1		T17	1
auto[1342177280:1476395007]	auto[1]	8	1			T159	1		T426	1		T436	2
auto[1476395008:1610612735]	auto[0]	121	1			T27	1		T23	1		T28	1
auto[1476395008:1610612735]	auto[1]	11	1			T144	1		T311	1		T243	1
auto[1610612736:1744830463]	auto[0]	112	1			T23	1		T211	1		T36	1
auto[1610612736:1744830463]	auto[1]	11	1			T311	1		T250	1		T287	1
auto[1744830464:1879048191]	auto[0]	116	1			T89	1		T46	1		T136	1
auto[1744830464:1879048191]	auto[1]	8	1			T17	1		T137	1		T288	1
auto[1879048192:2013265919]	auto[0]	114	1			T27	1		T24	1		T6	1
auto[1879048192:2013265919]	auto[1]	11	1			T302	1		T243	1		T429	1
auto[2013265920:2147483647]	auto[0]	99	1			T24	1		T36	1		T206	1
auto[2013265920:2147483647]	auto[1]	7	1			T287	1		T245	1		T429	1
auto[2147483648:2281701375]	auto[0]	107	1			T27	1		T23	1		T90	1
auto[2147483648:2281701375]	auto[1]	8	1			T159	1		T311	1		T287	1
auto[2281701376:2415919103]	auto[0]	107	1			T27	1		T23	1		T28	2
auto[2281701376:2415919103]	auto[1]	8	1			T311	1		T287	1		T288	1
auto[2415919104:2550136831]	auto[0]	95	1			T23	1		T24	1		T139	1
auto[2415919104:2550136831]	auto[1]	6	1			T429	1		T426	1		T437	1
auto[2550136832:2684354559]	auto[0]	113	1			T24	1		T206	1		T7	3
auto[2550136832:2684354559]	auto[1]	8	1			T17	1		T159	1		T243	1
auto[2684354560:2818572287]	auto[0]	119	1			T90	1		T44	1		T6	1
auto[2684354560:2818572287]	auto[1]	14	1			T250	1		T243	1		T438	1
auto[2818572288:2952790015]	auto[0]	119	1			T27	1		T6	1		T206	1
auto[2818572288:2952790015]	auto[1]	7	1			T144	1		T250	1		T266	1
auto[2952790016:3087007743]	auto[0]	123	1			T23	1		T36	1		T137	1
auto[2952790016:3087007743]	auto[1]	6	1			T250	1		T243	1		T288	1
auto[3087007744:3221225471]	auto[0]	115	1			T27	1		T23	1		T46	1
auto[3087007744:3221225471]	auto[1]	8	1			T159	1		T243	1		T288	1
auto[3221225472:3355443199]	auto[0]	104	1			T9	1		T36	1		T6	1
auto[3221225472:3355443199]	auto[1]	9	1			T17	1		T250	2		T266	1
auto[3355443200:3489660927]	auto[0]	112	1			T27	2		T28	2		T211	1
auto[3355443200:3489660927]	auto[1]	17	1			T159	2		T214	1		T287	1
auto[3489660928:3623878655]	auto[0]	102	1			T24	1		T36	1		T136	1
auto[3489660928:3623878655]	auto[1]	9	1			T144	1		T250	1		T430	1
auto[3623878656:3758096383]	auto[0]	102	1			T43	1		T7	1		T64	1
auto[3623878656:3758096383]	auto[1]	5	1			T430	1		T429	1		T379	1
auto[3758096384:3892314111]	auto[0]	88	1			T16	1		T27	1		T89	1
auto[3758096384:3892314111]	auto[1]	8	1			T214	1		T288	2		T308	1
auto[3892314112:4026531839]	auto[0]	110	1			T28	1		T36	1		T137	1
auto[3892314112:4026531839]	auto[1]	16	1			T144	1		T250	3		T287	1
auto[4026531840:4160749567]	auto[0]	111	1			T15	1		T23	1		T24	1
auto[4026531840:4160749567]	auto[1]	6	1			T243	1		T438	1		T284	1
auto[4160749568:4294967295]	auto[0]	131	1			T16	1		T206	1		T61	1
auto[4160749568:4294967295]	auto[1]	7	1			T243	1		T429	1		T426	1