Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3930

1

T15

2

T16

2

T9

8

auto[1]

2043

1

T5

2

T16

6

T27

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	208	1			T23	2		T61	2		T26	2
auto[134217728:268435455]	184	1			T23	2		T89	2		T36	2
auto[268435456:402653183]	194	1			T89	2		T44	2		T137	2
auto[402653184:536870911]	214	1			T16	2		T90	2		T36	2
auto[536870912:671088639]	162	1			T211	2		T36	2		T6	2
auto[671088640:805306367]	244	1			T9	2		T30	2		T110	2
auto[805306368:939524095]	164	1			T23	2		T136	2		T6	2
auto[939524096:1073741823]	222	1			T27	2		T206	2		T7	2
auto[1073741824:1207959551]	200	1			T24	4		T110	2		T106	2
auto[1207959552:1342177279]	158	1			T16	2		T17	2		T23	2
auto[1342177280:1476395007]	200	1			T44	2		T6	4		T110	2
auto[1476395008:1610612735]	176	1			T27	4		T28	2		T36	4
auto[1610612736:1744830463]	188	1			T23	2		T28	2		T89	2
auto[1744830464:1879048191]	194	1			T17	2		T36	4		T206	2
auto[1879048192:2013265919]	166	1			T5	2		T27	2		T28	2
auto[2013265920:2147483647]	164	1			T16	2		T28	2		T211	2
auto[2147483648:2281701375]	177	1			T206	2		T110	2		T106	2
auto[2281701376:2415919103]	174	1			T27	2		T44	2		T6	4
auto[2415919104:2550136831]	190	1			T24	2		T36	2		T137	2
auto[2550136832:2684354559]	196	1			T210	2		T7	4		T54	2
auto[2684354560:2818572287]	183	1			T43	2		T7	2		T258	2
auto[2818572288:2952790015]	202	1			T44	2		T24	2		T30	2
auto[2952790016:3087007743]	182	1			T27	2		T23	2		T24	2
auto[3087007744:3221225471]	184	1			T9	2		T89	2		T46	2
auto[3221225472:3355443199]	172	1			T206	2		T208	2		T54	2
auto[3355443200:3489660927]	160	1			T43	2		T24	2		T139	2
auto[3489660928:3623878655]	182	1			T16	2		T9	2		T211	2
auto[3623878656:3758096383]	186	1			T46	2		T137	2		T7	2
auto[3758096384:3892314111]	184	1			T6	2		T110	2		T7	2
auto[3892314112:4026531839]	195	1			T9	2		T30	2		T7	2
auto[4026531840:4160749567]	180	1			T15	2		T90	2		T7	4
auto[4160749568:4294967295]	188	1			T17	2		T27	2		T28	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	142	1			T61	2		T26	2		T263	2
auto[0:134217727]	auto[1]	66	1			T23	2		T71	2		T275	2
auto[134217728:268435455]	auto[0]	140	1			T36	2		T106	2		T7	4
auto[134217728:268435455]	auto[1]	44	1			T23	2		T89	2		T92	2
auto[268435456:402653183]	auto[0]	124	1			T89	2		T6	2		T205	2
auto[268435456:402653183]	auto[1]	70	1			T44	2		T137	2		T7	4
auto[402653184:536870911]	auto[0]	132	1			T90	2		T36	2		T46	2
auto[402653184:536870911]	auto[1]	82	1			T16	2		T6	2		T7	2
auto[536870912:671088639]	auto[0]	106	1			T36	2		T6	2		T69	2
auto[536870912:671088639]	auto[1]	56	1			T211	2		T106	2		T61	2
auto[671088640:805306367]	auto[0]	154	1			T9	2		T30	2		T110	2
auto[671088640:805306367]	auto[1]	90	1			T25	2		T378	2		T71	2
auto[805306368:939524095]	auto[0]	114	1			T23	2		T206	2		T7	4
auto[805306368:939524095]	auto[1]	50	1			T136	2		T6	2		T7	2
auto[939524096:1073741823]	auto[0]	152	1			T206	2		T7	2		T144	2
auto[939524096:1073741823]	auto[1]	70	1			T27	2		T336	2		T434	2
auto[1073741824:1207959551]	auto[0]	130	1			T24	2		T110	2		T7	2
auto[1073741824:1207959551]	auto[1]	70	1			T24	2		T106	2		T336	2
auto[1207959552:1342177279]	auto[0]	104	1			T17	2		T23	2		T7	2
auto[1207959552:1342177279]	auto[1]	54	1			T16	2		T72	2		T39	2
auto[1342177280:1476395007]	auto[0]	144	1			T110	2		T7	2		T52	2
auto[1342177280:1476395007]	auto[1]	56	1			T44	2		T6	4		T61	2
auto[1476395008:1610612735]	auto[0]	106	1			T27	4		T28	2		T36	2
auto[1476395008:1610612735]	auto[1]	70	1			T36	2		T7	8		T54	2
auto[1610612736:1744830463]	auto[0]	116	1			T28	2		T24	2		T144	2
auto[1610612736:1744830463]	auto[1]	72	1			T23	2		T89	2		T270	2
auto[1744830464:1879048191]	auto[0]	126	1			T17	2		T36	2		T206	2
auto[1744830464:1879048191]	auto[1]	68	1			T36	2		T7	2		T222	2
auto[1879048192:2013265919]	auto[0]	106	1			T28	2		T137	2		T6	2
auto[1879048192:2013265919]	auto[1]	60	1			T5	2		T27	2		T29	2
auto[2013265920:2147483647]	auto[0]	112	1			T28	2		T211	2		T6	2
auto[2013265920:2147483647]	auto[1]	52	1			T16	2		T252	2		T94	2
auto[2147483648:2281701375]	auto[0]	118	1			T206	2		T7	2		T128	2
auto[2147483648:2281701375]	auto[1]	59	1			T110	2		T106	2		T92	2
auto[2281701376:2415919103]	auto[0]	106	1			T27	2		T6	4		T110	4
auto[2281701376:2415919103]	auto[1]	68	1			T44	2		T7	2		T252	2
auto[2415919104:2550136831]	auto[0]	124	1			T24	2		T36	2		T137	2
auto[2415919104:2550136831]	auto[1]	66	1			T258	4		T61	2		T433	2
auto[2550136832:2684354559]	auto[0]	120	1			T7	2		T54	2		T144	2
auto[2550136832:2684354559]	auto[1]	76	1			T210	2		T7	2		T33	2
auto[2684354560:2818572287]	auto[0]	106	1			T43	2		T7	2		T258	2
auto[2684354560:2818572287]	auto[1]	77	1			T252	2		T302	4		T229	2
auto[2818572288:2952790015]	auto[0]	136	1			T30	2		T7	2		T61	6
auto[2818572288:2952790015]	auto[1]	66	1			T44	2		T24	2		T7	2
auto[2952790016:3087007743]	auto[0]	126	1			T27	2		T23	2		T7	2
auto[2952790016:3087007743]	auto[1]	56	1			T24	2		T7	2		T216	2
auto[3087007744:3221225471]	auto[0]	128	1			T9	2		T89	2		T46	2
auto[3087007744:3221225471]	auto[1]	56	1			T7	2		T61	2		T433	2
auto[3221225472:3355443199]	auto[0]	112	1			T54	2		T144	2		T26	2
auto[3221225472:3355443199]	auto[1]	60	1			T206	2		T208	2		T159	2
auto[3355443200:3489660927]	auto[0]	114	1			T24	2		T7	2		T54	2
auto[3355443200:3489660927]	auto[1]	46	1			T43	2		T139	2		T30	2
auto[3489660928:3623878655]	auto[0]	128	1			T16	2		T9	2		T43	2
auto[3489660928:3623878655]	auto[1]	54	1			T211	2		T61	2		T269	2
auto[3623878656:3758096383]	auto[0]	116	1			T137	2		T7	2		T144	2
auto[3623878656:3758096383]	auto[1]	70	1			T46	2		T61	2		T222	2
auto[3758096384:3892314111]	auto[0]	98	1			T110	2		T64	2		T104	2
auto[3758096384:3892314111]	auto[1]	86	1			T6	2		T7	2		T258	4
auto[3892314112:4026531839]	auto[0]	128	1			T9	2		T30	2		T7	2
auto[3892314112:4026531839]	auto[1]	67	1			T267	2		T81	2		T161	2
auto[4026531840:4160749567]	auto[0]	124	1			T15	2		T90	2		T7	4
auto[4026531840:4160749567]	auto[1]	56	1			T159	4		T439	2		T81	2
auto[4160749568:4294967295]	auto[0]	138	1			T17	2		T27	2		T6	2
auto[4160749568:4294967295]	auto[1]	50	1			T28	2		T7	2		T33	2