Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4089 1 T5 2 T16 4 T9 10
auto[1] 1881 1 T15 2 T16 4 T17 6



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 184 1 T89 2 T6 2 T210 2
auto[134217728:268435455] 206 1 T211 2 T36 2 T137 2
auto[268435456:402653183] 197 1 T9 2 T23 2 T89 2
auto[402653184:536870911] 198 1 T43 2 T24 2 T36 4
auto[536870912:671088639] 238 1 T5 2 T16 2 T28 4
auto[671088640:805306367] 172 1 T16 2 T17 2 T44 2
auto[805306368:939524095] 176 1 T9 2 T27 2 T89 2
auto[939524096:1073741823] 180 1 T9 2 T27 2 T6 6
auto[1073741824:1207959551] 190 1 T36 4 T7 4 T25 4
auto[1207959552:1342177279] 170 1 T27 2 T23 2 T28 2
auto[1342177280:1476395007] 182 1 T7 2 T61 4 T263 2
auto[1476395008:1610612735] 182 1 T24 2 T110 2 T7 4
auto[1610612736:1744830463] 196 1 T28 2 T30 2 T7 4
auto[1744830464:1879048191] 202 1 T16 2 T17 2 T6 2
auto[1879048192:2013265919] 196 1 T211 2 T7 2 T54 2
auto[2013265920:2147483647] 162 1 T27 2 T89 2 T90 2
auto[2147483648:2281701375] 172 1 T44 2 T136 2 T7 2
auto[2281701376:2415919103] 198 1 T211 2 T24 2 T6 2
auto[2415919104:2550136831] 196 1 T23 2 T29 2 T43 2
auto[2550136832:2684354559] 190 1 T28 2 T43 2 T24 2
auto[2684354560:2818572287] 212 1 T23 2 T7 2 T205 2
auto[2818572288:2952790015] 164 1 T27 2 T110 2 T7 2
auto[2952790016:3087007743] 186 1 T23 2 T6 4 T206 2
auto[3087007744:3221225471] 198 1 T16 2 T44 2 T137 2
auto[3221225472:3355443199] 180 1 T9 4 T17 2 T23 2
auto[3355443200:3489660927] 148 1 T137 4 T258 2 T144 2
auto[3489660928:3623878655] 174 1 T36 2 T206 2 T110 2
auto[3623878656:3758096383] 172 1 T24 2 T6 2 T7 2
auto[3758096384:3892314111] 194 1 T27 2 T7 6 T61 8
auto[3892314112:4026531839] 176 1 T46 2 T110 2 T7 4
auto[4026531840:4160749567] 177 1 T15 2 T27 2 T36 2
auto[4160749568:4294967295] 202 1 T90 2 T24 4 T139 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 120 1 T89 2 T210 2 T7 2
auto[0:134217727] auto[1] 64 1 T6 2 T7 2 T54 2
auto[134217728:268435455] auto[0] 136 1 T36 2 T6 2 T258 2
auto[134217728:268435455] auto[1] 70 1 T211 2 T137 2 T6 2
auto[268435456:402653183] auto[0] 140 1 T9 2 T89 2 T36 2
auto[268435456:402653183] auto[1] 57 1 T23 2 T6 2 T252 2
auto[402653184:536870911] auto[0] 128 1 T43 2 T36 4 T205 2
auto[402653184:536870911] auto[1] 70 1 T24 2 T206 2 T7 2
auto[536870912:671088639] auto[0] 150 1 T5 2 T16 2 T28 2
auto[536870912:671088639] auto[1] 88 1 T28 2 T206 2 T7 2
auto[671088640:805306367] auto[0] 130 1 T44 2 T6 2 T7 4
auto[671088640:805306367] auto[1] 42 1 T16 2 T17 2 T128 2
auto[805306368:939524095] auto[0] 112 1 T9 2 T27 2 T89 2
auto[805306368:939524095] auto[1] 64 1 T136 2 T52 2 T216 2
auto[939524096:1073741823] auto[0] 120 1 T9 2 T6 4 T106 2
auto[939524096:1073741823] auto[1] 60 1 T27 2 T6 2 T30 4
auto[1073741824:1207959551] auto[0] 134 1 T36 4 T7 4 T25 2
auto[1073741824:1207959551] auto[1] 56 1 T25 2 T257 2 T81 2
auto[1207959552:1342177279] auto[0] 110 1 T27 2 T46 2 T7 4
auto[1207959552:1342177279] auto[1] 60 1 T23 2 T28 2 T144 2
auto[1342177280:1476395007] auto[0] 134 1 T7 2 T61 4 T263 2
auto[1342177280:1476395007] auto[1] 48 1 T214 2 T423 2 T225 2
auto[1476395008:1610612735] auto[0] 130 1 T24 2 T110 2 T7 4
auto[1476395008:1610612735] auto[1] 52 1 T34 2 T47 2 T86 2
auto[1610612736:1744830463] auto[0] 140 1 T7 4 T205 2 T61 4
auto[1610612736:1744830463] auto[1] 56 1 T28 2 T30 2 T67 2
auto[1744830464:1879048191] auto[0] 140 1 T6 2 T106 2 T7 2
auto[1744830464:1879048191] auto[1] 62 1 T16 2 T17 2 T159 2
auto[1879048192:2013265919] auto[0] 130 1 T211 2 T7 2 T54 2
auto[1879048192:2013265919] auto[1] 66 1 T61 4 T387 2 T72 2
auto[2013265920:2147483647] auto[0] 106 1 T27 2 T144 2 T26 2
auto[2013265920:2147483647] auto[1] 56 1 T89 2 T90 2 T206 2
auto[2147483648:2281701375] auto[0] 132 1 T44 2 T136 2 T7 2
auto[2147483648:2281701375] auto[1] 40 1 T336 2 T51 2 T356 2
auto[2281701376:2415919103] auto[0] 142 1 T211 2 T6 2 T61 6
auto[2281701376:2415919103] auto[1] 56 1 T24 2 T110 2 T434 2
auto[2415919104:2550136831] auto[0] 126 1 T43 2 T258 2 T54 2
auto[2415919104:2550136831] auto[1] 70 1 T23 2 T29 2 T52 2
auto[2550136832:2684354559] auto[0] 128 1 T43 2 T24 2 T110 2
auto[2550136832:2684354559] auto[1] 62 1 T28 2 T204 2 T214 2
auto[2684354560:2818572287] auto[0] 152 1 T23 2 T7 2 T54 2
auto[2684354560:2818572287] auto[1] 60 1 T205 2 T51 2 T434 2
auto[2818572288:2952790015] auto[0] 118 1 T27 2 T110 2 T33 2
auto[2818572288:2952790015] auto[1] 46 1 T7 2 T25 2 T61 2
auto[2952790016:3087007743] auto[0] 108 1 T23 2 T6 2 T54 2
auto[2952790016:3087007743] auto[1] 78 1 T6 2 T206 2 T7 2
auto[3087007744:3221225471] auto[0] 132 1 T16 2 T144 2 T61 2
auto[3087007744:3221225471] auto[1] 66 1 T44 2 T137 2 T206 2
auto[3221225472:3355443199] auto[0] 118 1 T9 4 T7 2 T69 2
auto[3221225472:3355443199] auto[1] 62 1 T17 2 T23 2 T417 2
auto[3355443200:3489660927] auto[0] 118 1 T137 4 T258 2 T144 2
auto[3355443200:3489660927] auto[1] 30 1 T434 2 T225 2 T278 2
auto[3489660928:3623878655] auto[0] 112 1 T110 2 T7 2 T61 2
auto[3489660928:3623878655] auto[1] 62 1 T36 2 T206 2 T7 2
auto[3623878656:3758096383] auto[0] 114 1 T24 2 T6 2 T7 2
auto[3623878656:3758096383] auto[1] 58 1 T418 2 T267 2 T51 2
auto[3758096384:3892314111] auto[0] 150 1 T7 4 T61 8 T26 2
auto[3758096384:3892314111] auto[1] 44 1 T27 2 T7 2 T66 2
auto[3892314112:4026531839] auto[0] 116 1 T7 4 T26 2 T45 2
auto[3892314112:4026531839] auto[1] 60 1 T46 2 T110 2 T81 2
auto[4026531840:4160749567] auto[0] 121 1 T27 2 T36 2 T110 2
auto[4026531840:4160749567] auto[1] 56 1 T15 2 T252 2 T433 2
auto[4160749568:4294967295] auto[0] 142 1 T24 2 T7 2 T61 4
auto[4160749568:4294967295] auto[1] 60 1 T90 2 T24 2 T139 2