Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.10 98.07 98.42 100.00 99.11 98.41 91.54


Total test records in report: 1076
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T177 /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1287058878 May 11 03:51:34 PM PDT 24 May 11 03:51:35 PM PDT 24 78792536 ps
T1010 /workspace/coverage/default/16.keymgr_random.3326419517 May 11 03:51:17 PM PDT 24 May 11 03:51:21 PM PDT 24 52921684 ps
T1011 /workspace/coverage/default/35.keymgr_smoke.2004579717 May 11 03:52:28 PM PDT 24 May 11 03:52:33 PM PDT 24 249219772 ps
T1012 /workspace/coverage/default/39.keymgr_smoke.1897825830 May 11 03:52:46 PM PDT 24 May 11 03:52:49 PM PDT 24 90332309 ps
T1013 /workspace/coverage/default/44.keymgr_direct_to_disabled.2077018158 May 11 03:53:05 PM PDT 24 May 11 03:53:29 PM PDT 24 333066974 ps
T1014 /workspace/coverage/default/17.keymgr_direct_to_disabled.364526347 May 11 03:51:33 PM PDT 24 May 11 03:51:35 PM PDT 24 77350696 ps
T1015 /workspace/coverage/default/25.keymgr_smoke.2224927228 May 11 03:51:53 PM PDT 24 May 11 03:51:59 PM PDT 24 219698280 ps
T1016 /workspace/coverage/default/26.keymgr_sideload_aes.1111175998 May 11 03:51:56 PM PDT 24 May 11 03:52:23 PM PDT 24 1065265717 ps
T1017 /workspace/coverage/default/6.keymgr_smoke.1010284441 May 11 03:50:33 PM PDT 24 May 11 03:50:40 PM PDT 24 1037029602 ps
T1018 /workspace/coverage/default/26.keymgr_sideload_otbn.4194383580 May 11 03:51:56 PM PDT 24 May 11 03:52:00 PM PDT 24 79876734 ps
T1019 /workspace/coverage/default/40.keymgr_smoke.2223030518 May 11 03:52:53 PM PDT 24 May 11 03:53:04 PM PDT 24 609144710 ps
T1020 /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1411607977 May 11 03:51:13 PM PDT 24 May 11 03:51:16 PM PDT 24 43984543 ps
T1021 /workspace/coverage/default/14.keymgr_custom_cm.2047533540 May 11 03:51:13 PM PDT 24 May 11 03:51:20 PM PDT 24 4889035523 ps
T1022 /workspace/coverage/default/1.keymgr_sideload_kmac.1796626627 May 11 03:50:08 PM PDT 24 May 11 03:50:11 PM PDT 24 106533485 ps
T1023 /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3031361190 May 11 03:51:11 PM PDT 24 May 11 03:51:15 PM PDT 24 125628203 ps
T1024 /workspace/coverage/default/5.keymgr_sync_async_fault_cross.146680129 May 11 03:50:33 PM PDT 24 May 11 03:50:36 PM PDT 24 75123372 ps
T1025 /workspace/coverage/default/11.keymgr_smoke.982958430 May 11 03:50:53 PM PDT 24 May 11 03:50:56 PM PDT 24 133319827 ps
T1026 /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2403152370 May 11 03:50:49 PM PDT 24 May 11 03:51:23 PM PDT 24 2086495492 ps
T1027 /workspace/coverage/default/33.keymgr_sideload_protect.1902315502 May 11 03:52:28 PM PDT 24 May 11 03:52:31 PM PDT 24 773853947 ps
T1028 /workspace/coverage/default/5.keymgr_sideload_protect.3032070472 May 11 03:50:34 PM PDT 24 May 11 03:50:38 PM PDT 24 71565710 ps
T1029 /workspace/coverage/default/18.keymgr_direct_to_disabled.24932996 May 11 03:51:24 PM PDT 24 May 11 03:51:27 PM PDT 24 284606258 ps
T1030 /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3706833431 May 11 03:52:30 PM PDT 24 May 11 03:52:36 PM PDT 24 147847730 ps
T1031 /workspace/coverage/default/12.keymgr_sideload_kmac.1270048279 May 11 03:50:58 PM PDT 24 May 11 03:51:18 PM PDT 24 715554853 ps
T1032 /workspace/coverage/default/6.keymgr_sideload_otbn.881659788 May 11 03:50:32 PM PDT 24 May 11 03:50:35 PM PDT 24 22653660 ps
T237 /workspace/coverage/default/24.keymgr_stress_all.375874404 May 11 03:51:52 PM PDT 24 May 11 03:55:04 PM PDT 24 8130450154 ps
T1033 /workspace/coverage/default/37.keymgr_custom_cm.1292465156 May 11 03:52:38 PM PDT 24 May 11 03:52:42 PM PDT 24 88391891 ps
T1034 /workspace/coverage/default/11.keymgr_random.2037029252 May 11 03:50:55 PM PDT 24 May 11 03:51:01 PM PDT 24 373320578 ps
T443 /workspace/coverage/default/40.keymgr_cfg_regwen.3022006444 May 11 03:52:51 PM PDT 24 May 11 03:53:58 PM PDT 24 2515678810 ps
T160 /workspace/coverage/default/22.keymgr_custom_cm.2862841062 May 11 03:51:43 PM PDT 24 May 11 03:51:48 PM PDT 24 124608227 ps
T1035 /workspace/coverage/default/16.keymgr_sideload.1853514493 May 11 03:51:16 PM PDT 24 May 11 03:51:47 PM PDT 24 1315190281 ps
T1036 /workspace/coverage/default/15.keymgr_random.3008951102 May 11 03:51:15 PM PDT 24 May 11 03:51:36 PM PDT 24 965999054 ps
T398 /workspace/coverage/default/41.keymgr_lc_disable.3550270720 May 11 03:52:53 PM PDT 24 May 11 03:53:02 PM PDT 24 136155701 ps
T1037 /workspace/coverage/default/10.keymgr_stress_all.171882090 May 11 03:50:57 PM PDT 24 May 11 03:51:27 PM PDT 24 904442056 ps
T383 /workspace/coverage/default/29.keymgr_sideload.2120762808 May 11 03:52:10 PM PDT 24 May 11 03:52:13 PM PDT 24 32175533 ps
T1038 /workspace/coverage/default/23.keymgr_sideload_aes.2124994208 May 11 03:51:47 PM PDT 24 May 11 03:51:50 PM PDT 24 153507481 ps
T1039 /workspace/coverage/default/18.keymgr_sideload_otbn.259382169 May 11 03:51:25 PM PDT 24 May 11 03:51:28 PM PDT 24 223838430 ps
T1040 /workspace/coverage/default/42.keymgr_sideload_protect.1641161701 May 11 03:53:04 PM PDT 24 May 11 03:53:23 PM PDT 24 126757639 ps
T1041 /workspace/coverage/default/16.keymgr_sideload_aes.1080801981 May 11 03:51:21 PM PDT 24 May 11 03:51:24 PM PDT 24 38494997 ps
T1042 /workspace/coverage/default/30.keymgr_smoke.892634791 May 11 03:52:12 PM PDT 24 May 11 03:52:27 PM PDT 24 676882443 ps
T1043 /workspace/coverage/default/10.keymgr_smoke.3470166868 May 11 03:50:49 PM PDT 24 May 11 03:50:51 PM PDT 24 23539047 ps
T1044 /workspace/coverage/default/13.keymgr_sideload_protect.580060133 May 11 03:51:11 PM PDT 24 May 11 03:51:14 PM PDT 24 73217514 ps
T1045 /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1800157267 May 11 03:51:51 PM PDT 24 May 11 03:51:56 PM PDT 24 476757019 ps
T324 /workspace/coverage/default/46.keymgr_random.3941841156 May 11 03:53:11 PM PDT 24 May 11 03:53:27 PM PDT 24 74509966 ps
T1046 /workspace/coverage/default/18.keymgr_smoke.4253122644 May 11 03:51:31 PM PDT 24 May 11 03:51:34 PM PDT 24 118968315 ps
T1047 /workspace/coverage/default/44.keymgr_cfg_regwen.3504446429 May 11 03:53:05 PM PDT 24 May 11 03:53:26 PM PDT 24 231729144 ps
T1048 /workspace/coverage/default/27.keymgr_direct_to_disabled.3475108452 May 11 03:52:06 PM PDT 24 May 11 03:52:24 PM PDT 24 902531163 ps
T1049 /workspace/coverage/default/35.keymgr_sideload_kmac.3064755007 May 11 03:52:32 PM PDT 24 May 11 03:52:40 PM PDT 24 299101425 ps
T1050 /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.292433890 May 11 03:52:30 PM PDT 24 May 11 03:52:37 PM PDT 24 198766931 ps
T1051 /workspace/coverage/default/23.keymgr_random.2588360911 May 11 03:51:47 PM PDT 24 May 11 03:51:52 PM PDT 24 238691600 ps
T1052 /workspace/coverage/default/26.keymgr_sideload_protect.2588886583 May 11 03:52:06 PM PDT 24 May 11 03:52:11 PM PDT 24 152793208 ps
T1053 /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3390146033 May 11 03:53:23 PM PDT 24 May 11 03:53:31 PM PDT 24 183475094 ps
T1054 /workspace/coverage/default/4.keymgr_sync_async_fault_cross.688273805 May 11 03:50:26 PM PDT 24 May 11 03:50:30 PM PDT 24 67735338 ps
T1055 /workspace/coverage/default/16.keymgr_sideload_protect.516546797 May 11 03:51:21 PM PDT 24 May 11 03:51:24 PM PDT 24 126667111 ps
T1056 /workspace/coverage/default/4.keymgr_cfg_regwen.1283602708 May 11 03:50:28 PM PDT 24 May 11 03:50:31 PM PDT 24 31313361 ps
T111 /workspace/coverage/default/0.keymgr_sec_cm.780819502 May 11 03:50:04 PM PDT 24 May 11 03:50:15 PM PDT 24 1234642560 ps
T1057 /workspace/coverage/default/37.keymgr_sync_async_fault_cross.121267520 May 11 03:52:40 PM PDT 24 May 11 03:52:43 PM PDT 24 57959145 ps
T1058 /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1168150833 May 11 03:53:17 PM PDT 24 May 11 03:54:20 PM PDT 24 4973753615 ps
T1059 /workspace/coverage/default/6.keymgr_sideload_kmac.4256383144 May 11 03:50:32 PM PDT 24 May 11 03:50:34 PM PDT 24 23542118 ps
T1060 /workspace/coverage/default/13.keymgr_alert_test.3999167102 May 11 03:51:11 PM PDT 24 May 11 03:51:13 PM PDT 24 22072840 ps
T1061 /workspace/coverage/default/27.keymgr_alert_test.1718855163 May 11 03:52:05 PM PDT 24 May 11 03:52:06 PM PDT 24 12595490 ps
T1062 /workspace/coverage/default/41.keymgr_sideload_protect.4033691678 May 11 03:53:01 PM PDT 24 May 11 03:53:21 PM PDT 24 52682148 ps
T1063 /workspace/coverage/default/26.keymgr_direct_to_disabled.1843654739 May 11 03:51:55 PM PDT 24 May 11 03:51:59 PM PDT 24 72489706 ps
T1064 /workspace/coverage/default/8.keymgr_sw_invalid_input.2296112642 May 11 03:50:42 PM PDT 24 May 11 03:51:26 PM PDT 24 1242727083 ps
T1065 /workspace/coverage/default/12.keymgr_sw_invalid_input.1655766450 May 11 03:51:02 PM PDT 24 May 11 03:51:07 PM PDT 24 165994718 ps
T384 /workspace/coverage/default/31.keymgr_cfg_regwen.1276801708 May 11 03:52:17 PM PDT 24 May 11 03:52:44 PM PDT 24 487949929 ps
T1066 /workspace/coverage/default/47.keymgr_alert_test.983029279 May 11 03:53:12 PM PDT 24 May 11 03:53:24 PM PDT 24 11161237 ps
T1067 /workspace/coverage/default/48.keymgr_sideload_protect.2491666685 May 11 03:53:17 PM PDT 24 May 11 03:53:29 PM PDT 24 263781218 ps
T1068 /workspace/coverage/default/7.keymgr_sideload.1247092817 May 11 03:50:34 PM PDT 24 May 11 03:51:15 PM PDT 24 3579174467 ps
T1069 /workspace/coverage/default/2.keymgr_sideload_otbn.1894809132 May 11 03:50:17 PM PDT 24 May 11 03:50:26 PM PDT 24 363613059 ps
T1070 /workspace/coverage/default/7.keymgr_alert_test.4089503008 May 11 03:50:44 PM PDT 24 May 11 03:50:45 PM PDT 24 20838238 ps
T1071 /workspace/coverage/default/37.keymgr_smoke.876098971 May 11 03:52:42 PM PDT 24 May 11 03:53:08 PM PDT 24 4553621508 ps
T1072 /workspace/coverage/default/28.keymgr_custom_cm.3857300592 May 11 03:52:07 PM PDT 24 May 11 03:52:27 PM PDT 24 676458194 ps
T1073 /workspace/coverage/default/1.keymgr_smoke.343671532 May 11 03:50:06 PM PDT 24 May 11 03:50:11 PM PDT 24 147567242 ps
T1074 /workspace/coverage/default/24.keymgr_random.3064986031 May 11 03:51:52 PM PDT 24 May 11 03:51:57 PM PDT 24 56266599 ps
T1075 /workspace/coverage/default/49.keymgr_sideload_otbn.158321117 May 11 03:53:24 PM PDT 24 May 11 03:53:31 PM PDT 24 203703748 ps
T1076 /workspace/coverage/default/47.keymgr_sideload_otbn.505541252 May 11 03:53:16 PM PDT 24 May 11 03:53:33 PM PDT 24 719557299 ps

Test location /workspace/coverage/default/26.keymgr_custom_cm.3153323245
Short name T9
Test name
Test status
Simulation time 99082334 ps
CPU time 3.17 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 214872 kb
Host smart-6ed4e6ac-cb52-4530-8c08-74e40ee14c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153323245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3153323245
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3058196151
Short name T7
Test name
Test status
Simulation time 4247116872 ps
CPU time 69.54 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 222772 kb
Host smart-db5fdb4b-6131-4118-af4e-9ff1ec80829a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058196151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3058196151
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2340653317
Short name T61
Test name
Test status
Simulation time 928653133 ps
CPU time 23.51 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:47 PM PDT 24
Peak memory 215624 kb
Host smart-37d3283f-8d60-4f82-afe6-eb791f9b68e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340653317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2340653317
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3727530081
Short name T27
Test name
Test status
Simulation time 116215157 ps
CPU time 5.07 seconds
Started May 11 03:52:47 PM PDT 24
Finished May 11 03:52:52 PM PDT 24
Peak memory 218432 kb
Host smart-68a607d9-f95f-42ba-8386-819d7eb34b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727530081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3727530081
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2719941409
Short name T13
Test name
Test status
Simulation time 1418299383 ps
CPU time 29.98 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:50:57 PM PDT 24
Peak memory 236204 kb
Host smart-3901077e-25ac-4cd7-a6c0-63124f8b0ecd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719941409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2719941409
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3699115966
Short name T128
Test name
Test status
Simulation time 174224024 ps
CPU time 4.79 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:27 PM PDT 24
Peak memory 219776 kb
Host smart-6b4e9acc-7ab0-4b50-a029-c325cd411cc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699115966 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3699115966
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1274104582
Short name T6
Test name
Test status
Simulation time 1585822671 ps
CPU time 11.13 seconds
Started May 11 03:52:20 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 214420 kb
Host smart-8a2c665d-5c1d-43a0-8574-bf0da558b163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274104582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1274104582
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.475598087
Short name T121
Test name
Test status
Simulation time 572425716 ps
CPU time 5.21 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 213944 kb
Host smart-47d35cfa-32d7-4f50-8604-e818bb22a884
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475598087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.475598087
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1704972222
Short name T243
Test name
Test status
Simulation time 1608309099 ps
CPU time 15.33 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:37 PM PDT 24
Peak memory 215540 kb
Host smart-77068e10-bfeb-403e-b538-ba348623cefc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704972222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1704972222
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3616329932
Short name T23
Test name
Test status
Simulation time 209634139 ps
CPU time 5.96 seconds
Started May 11 03:53:01 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 219576 kb
Host smart-b957e45f-e94b-445a-a078-8d88971dddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616329932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3616329932
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2363149344
Short name T47
Test name
Test status
Simulation time 154101445 ps
CPU time 2.53 seconds
Started May 11 03:53:21 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 214556 kb
Host smart-89317e57-a609-4dcd-b186-e7c66fa71033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363149344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2363149344
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3285037371
Short name T159
Test name
Test status
Simulation time 108184822 ps
CPU time 6.27 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 222600 kb
Host smart-c1bf7614-37e9-4ee2-aaa5-048d5980aba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285037371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3285037371
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3427482069
Short name T110
Test name
Test status
Simulation time 409597888 ps
CPU time 7.06 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:41 PM PDT 24
Peak memory 222984 kb
Host smart-560487a5-361a-4d40-9d45-1ed2391e4643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427482069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3427482069
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.139630383
Short name T225
Test name
Test status
Simulation time 7836970408 ps
CPU time 48.99 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:52:59 PM PDT 24
Peak memory 222764 kb
Host smart-a70b18e8-c744-411b-91cb-8563f614ea39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139630383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.139630383
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.891344484
Short name T36
Test name
Test status
Simulation time 74380081 ps
CPU time 4.36 seconds
Started May 11 03:52:05 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 222680 kb
Host smart-895c277d-72ce-4449-bfe2-a40336b0912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891344484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.891344484
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3534863134
Short name T426
Test name
Test status
Simulation time 1537864272 ps
CPU time 63.4 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:53:14 PM PDT 24
Peak memory 215684 kb
Host smart-dfcfa683-2082-4cf8-bca8-6bda40603de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534863134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3534863134
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3547408538
Short name T71
Test name
Test status
Simulation time 843021258 ps
CPU time 33.68 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:54:00 PM PDT 24
Peak memory 222648 kb
Host smart-9da08ac7-e643-43cd-aaf2-9751b38cb3a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547408538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3547408538
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3774616485
Short name T144
Test name
Test status
Simulation time 3505255972 ps
CPU time 93.78 seconds
Started May 11 03:50:30 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 215372 kb
Host smart-da403b01-35af-4ff9-8636-d675395bbc6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774616485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3774616485
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3668838003
Short name T131
Test name
Test status
Simulation time 360544361 ps
CPU time 5.4 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:41 PM PDT 24
Peak memory 209004 kb
Host smart-776ca553-ef54-42ff-8e87-639161f909e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668838003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3668838003
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3901858082
Short name T24
Test name
Test status
Simulation time 1095629762 ps
CPU time 11.69 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:53:00 PM PDT 24
Peak memory 220188 kb
Host smart-4a137616-ca38-4c54-a9a8-d341595c2504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901858082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3901858082
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1419032199
Short name T81
Test name
Test status
Simulation time 21707497310 ps
CPU time 155.26 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:55:12 PM PDT 24
Peak memory 222196 kb
Host smart-c237b8c2-ad80-4148-b992-2f5dfa67431b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419032199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1419032199
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1491627371
Short name T353
Test name
Test status
Simulation time 269612829 ps
CPU time 14.72 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:17 PM PDT 24
Peak memory 215780 kb
Host smart-9a02d0b3-e413-4d34-bc00-34448849530a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491627371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1491627371
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.736118310
Short name T278
Test name
Test status
Simulation time 979769294 ps
CPU time 34.15 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:32 PM PDT 24
Peak memory 222696 kb
Host smart-2286422d-4aa7-46df-b731-dd4e6ce1ed27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736118310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.736118310
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.456973021
Short name T149
Test name
Test status
Simulation time 180634326 ps
CPU time 5.78 seconds
Started May 11 03:32:30 PM PDT 24
Finished May 11 03:32:36 PM PDT 24
Peak memory 218864 kb
Host smart-8381c40c-7763-48fd-b641-dbdc535d1ef4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456973021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.456973021
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.810012659
Short name T17
Test name
Test status
Simulation time 138271454 ps
CPU time 2.66 seconds
Started May 11 03:51:29 PM PDT 24
Finished May 11 03:51:32 PM PDT 24
Peak memory 214512 kb
Host smart-99115192-9c1f-42db-b768-758f320073f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810012659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.810012659
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2772118258
Short name T39
Test name
Test status
Simulation time 71882678 ps
CPU time 2.92 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:14 PM PDT 24
Peak memory 208852 kb
Host smart-d6aaa62b-6ba3-4912-8a1b-c1d0a209365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772118258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2772118258
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2313056648
Short name T283
Test name
Test status
Simulation time 5058101855 ps
CPU time 134.64 seconds
Started May 11 03:51:26 PM PDT 24
Finished May 11 03:53:41 PM PDT 24
Peak memory 222624 kb
Host smart-7adb97b3-fa5f-41a6-861b-1d5797b76dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313056648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2313056648
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3936274539
Short name T239
Test name
Test status
Simulation time 512457549 ps
CPU time 27.92 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 217528 kb
Host smart-f5d0ac0c-7a74-4e39-a9e7-f1e69e0768ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936274539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3936274539
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.536133605
Short name T22
Test name
Test status
Simulation time 108342105 ps
CPU time 5.02 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:52:53 PM PDT 24
Peak memory 209756 kb
Host smart-642f633b-56b4-490e-a669-475f3750b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536133605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.536133605
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2672983526
Short name T230
Test name
Test status
Simulation time 259791309 ps
CPU time 3.16 seconds
Started May 11 03:50:21 PM PDT 24
Finished May 11 03:50:24 PM PDT 24
Peak memory 218724 kb
Host smart-9dff8de4-28e2-4c73-8a85-95a9fa305291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672983526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2672983526
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3244294261
Short name T380
Test name
Test status
Simulation time 1450747854 ps
CPU time 11.3 seconds
Started May 11 03:50:17 PM PDT 24
Finished May 11 03:50:29 PM PDT 24
Peak memory 214420 kb
Host smart-4a8e01e0-4e83-4606-9015-c36491facd08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244294261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3244294261
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.956984083
Short name T279
Test name
Test status
Simulation time 1073474576 ps
CPU time 4.46 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 214540 kb
Host smart-7e642d81-d4ce-460b-b0b3-314311f99264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956984083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.956984083
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.256596237
Short name T161
Test name
Test status
Simulation time 623491616 ps
CPU time 9.95 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:53:03 PM PDT 24
Peak memory 222828 kb
Host smart-a65a965b-df68-4e10-b141-c520d6163094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256596237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.256596237
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3572784356
Short name T164
Test name
Test status
Simulation time 1373613264 ps
CPU time 35.88 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 213764 kb
Host smart-8851bfab-0822-4cdc-b179-4b749f57bfd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572784356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3572784356
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2085962112
Short name T250
Test name
Test status
Simulation time 574624810 ps
CPU time 15.49 seconds
Started May 11 03:52:49 PM PDT 24
Finished May 11 03:53:05 PM PDT 24
Peak memory 214524 kb
Host smart-61729406-a80f-4d31-b10d-5b905fca246b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2085962112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2085962112
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2622804435
Short name T261
Test name
Test status
Simulation time 6462824740 ps
CPU time 59.81 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:53:54 PM PDT 24
Peak memory 222716 kb
Host smart-bd409827-37ef-40fe-94b0-11172a54ea2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622804435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2622804435
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.148844640
Short name T194
Test name
Test status
Simulation time 15489000 ps
CPU time 0.95 seconds
Started May 11 03:50:52 PM PDT 24
Finished May 11 03:50:53 PM PDT 24
Peak memory 206120 kb
Host smart-6c9b5119-e591-4beb-9244-24882c0ea01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148844640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.148844640
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1737002299
Short name T216
Test name
Test status
Simulation time 552945196 ps
CPU time 9.82 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:53 PM PDT 24
Peak memory 214384 kb
Host smart-13eb6c21-f104-4e61-ab24-583ecd71b5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737002299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1737002299
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2820476698
Short name T170
Test name
Test status
Simulation time 573257560 ps
CPU time 3.51 seconds
Started May 11 03:32:22 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 213828 kb
Host smart-fb1f9a51-957e-4880-afdf-f43f63a64e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820476698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2820476698
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1990296783
Short name T302
Test name
Test status
Simulation time 760977557 ps
CPU time 10.65 seconds
Started May 11 03:51:51 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 214584 kb
Host smart-21c87778-9053-4594-8efd-dc67a606ec23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990296783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1990296783
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3748561338
Short name T226
Test name
Test status
Simulation time 156006292 ps
CPU time 3.64 seconds
Started May 11 03:50:21 PM PDT 24
Finished May 11 03:50:25 PM PDT 24
Peak memory 208928 kb
Host smart-7b5fc68a-859b-483c-8035-7ba1d696f114
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748561338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3748561338
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1276801708
Short name T384
Test name
Test status
Simulation time 487949929 ps
CPU time 26.5 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 214520 kb
Host smart-28ee411e-4249-47a7-b4d8-5942e77a7266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276801708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1276801708
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3713425752
Short name T318
Test name
Test status
Simulation time 1220945133 ps
CPU time 45.05 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:53:08 PM PDT 24
Peak memory 222684 kb
Host smart-9a396963-b351-460f-8cec-d5675f0152fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713425752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3713425752
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2147571802
Short name T31
Test name
Test status
Simulation time 208197219 ps
CPU time 3.12 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:42 PM PDT 24
Peak memory 222712 kb
Host smart-83bf83b0-a46c-43a9-aa44-1757fe9da4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147571802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2147571802
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2732744257
Short name T93
Test name
Test status
Simulation time 1450087860 ps
CPU time 3.66 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 214388 kb
Host smart-bb0128a1-b077-4571-a17c-1ed2b614cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732744257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2732744257
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2437885175
Short name T366
Test name
Test status
Simulation time 291832350 ps
CPU time 2.61 seconds
Started May 11 03:50:35 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 209440 kb
Host smart-7fb3ad77-7414-4106-b89c-0963d585232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437885175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2437885175
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.33909097
Short name T162
Test name
Test status
Simulation time 530124402 ps
CPU time 5.04 seconds
Started May 11 03:52:14 PM PDT 24
Finished May 11 03:52:20 PM PDT 24
Peak memory 217720 kb
Host smart-550214ac-49df-4a1a-acf9-e1d9ecd3caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33909097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.33909097
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1642975379
Short name T82
Test name
Test status
Simulation time 535872929 ps
CPU time 4.71 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:52:53 PM PDT 24
Peak memory 217656 kb
Host smart-756c50a2-d1cd-4d98-a789-6a4d9928491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642975379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1642975379
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2841211823
Short name T192
Test name
Test status
Simulation time 1020846659 ps
CPU time 19.83 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 208588 kb
Host smart-6259eb73-9e82-44a5-9779-8fce43c9b55b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841211823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2841211823
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3473696092
Short name T303
Test name
Test status
Simulation time 532976561 ps
CPU time 13.15 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:22 PM PDT 24
Peak memory 216876 kb
Host smart-faf03eae-dd67-4111-9891-e1df9bf82fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473696092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3473696092
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3563802822
Short name T273
Test name
Test status
Simulation time 62247693 ps
CPU time 2.55 seconds
Started May 11 03:51:16 PM PDT 24
Finished May 11 03:51:19 PM PDT 24
Peak memory 211364 kb
Host smart-54fb121d-a201-4614-b5f0-df72382f51f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563802822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3563802822
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1465518910
Short name T379
Test name
Test status
Simulation time 118059327 ps
CPU time 6.76 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:28 PM PDT 24
Peak memory 214560 kb
Host smart-5737fa08-36e8-4c93-8add-927d0a7c669d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465518910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1465518910
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.623852840
Short name T49
Test name
Test status
Simulation time 600535383 ps
CPU time 23.67 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 221484 kb
Host smart-dcad3f3b-9cca-4884-847c-d55f2ff2b580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623852840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.623852840
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1217008021
Short name T310
Test name
Test status
Simulation time 210760700 ps
CPU time 3.34 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:50:46 PM PDT 24
Peak memory 215088 kb
Host smart-fe31db87-97fc-46e2-99c3-50ff532327ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217008021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1217008021
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1418489091
Short name T163
Test name
Test status
Simulation time 64717734 ps
CPU time 4.53 seconds
Started May 11 03:52:13 PM PDT 24
Finished May 11 03:52:18 PM PDT 24
Peak memory 222956 kb
Host smart-29b3b3b7-eaf8-464f-9c34-157ea91f35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418489091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1418489091
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3733709432
Short name T105
Test name
Test status
Simulation time 475195372 ps
CPU time 15.49 seconds
Started May 11 03:50:23 PM PDT 24
Finished May 11 03:50:39 PM PDT 24
Peak memory 208612 kb
Host smart-d108f782-04c1-41fd-b95b-7625e7c49a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733709432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3733709432
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.757256131
Short name T166
Test name
Test status
Simulation time 1521710849 ps
CPU time 8.8 seconds
Started May 11 03:32:28 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 209172 kb
Host smart-f9a90813-69d7-41ce-af6e-8251e84a979c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757256131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.757256131
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1522304918
Short name T172
Test name
Test status
Simulation time 428455017 ps
CPU time 5.01 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 213736 kb
Host smart-2362be2c-40ad-4788-98ae-94898f3da445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522304918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1522304918
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2862841062
Short name T160
Test name
Test status
Simulation time 124608227 ps
CPU time 4.24 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:51:48 PM PDT 24
Peak memory 218116 kb
Host smart-9608892d-9e36-430f-84ee-38f04bf44863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862841062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2862841062
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3962375699
Short name T220
Test name
Test status
Simulation time 378786540 ps
CPU time 9.97 seconds
Started May 11 03:50:12 PM PDT 24
Finished May 11 03:50:23 PM PDT 24
Peak memory 222644 kb
Host smart-5c63087a-eae9-4391-8e93-2668bea6f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962375699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3962375699
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1130463559
Short name T312
Test name
Test status
Simulation time 94390344 ps
CPU time 4.44 seconds
Started May 11 03:50:57 PM PDT 24
Finished May 11 03:51:02 PM PDT 24
Peak memory 211004 kb
Host smart-19bd48e3-d71a-4d53-9e6b-9d582aa1dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130463559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1130463559
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3751396467
Short name T293
Test name
Test status
Simulation time 65945780 ps
CPU time 3.07 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:50:59 PM PDT 24
Peak memory 207028 kb
Host smart-9855c0d8-f013-46e5-abd0-f4521c0099c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751396467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3751396467
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3021185399
Short name T284
Test name
Test status
Simulation time 169164359 ps
CPU time 3.31 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 214492 kb
Host smart-e5d1d153-1c34-489e-a04f-1153315d9961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021185399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3021185399
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4039116999
Short name T428
Test name
Test status
Simulation time 2410172842 ps
CPU time 121.21 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:54:32 PM PDT 24
Peak memory 214792 kb
Host smart-abe5beed-d84f-4dbe-810d-9cd98a222c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039116999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4039116999
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1429162149
Short name T176
Test name
Test status
Simulation time 184737624 ps
CPU time 3.98 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 210704 kb
Host smart-7f9ceef1-98ef-4ed1-b459-12f36a174636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429162149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1429162149
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1946837265
Short name T15
Test name
Test status
Simulation time 140369902 ps
CPU time 4.29 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:01 PM PDT 24
Peak memory 218392 kb
Host smart-e7ec053f-a8da-4f3d-bc0f-0f0dce180b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946837265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1946837265
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1350617887
Short name T68
Test name
Test status
Simulation time 146617346 ps
CPU time 2.17 seconds
Started May 11 03:50:40 PM PDT 24
Finished May 11 03:50:43 PM PDT 24
Peak memory 215336 kb
Host smart-e8f565da-5f39-4277-a354-c95369c1b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350617887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1350617887
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1854030878
Short name T26
Test name
Test status
Simulation time 554743203 ps
CPU time 4.77 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:11 PM PDT 24
Peak memory 214424 kb
Host smart-8a90f202-70ab-4a5d-9a9a-3586f149fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854030878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1854030878
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2276741466
Short name T224
Test name
Test status
Simulation time 73733435 ps
CPU time 2.45 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:22 PM PDT 24
Peak memory 206832 kb
Host smart-0d3cf093-ed00-4d54-933c-0ce23f49b45f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276741466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2276741466
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.375874404
Short name T237
Test name
Test status
Simulation time 8130450154 ps
CPU time 191.41 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:55:04 PM PDT 24
Peak memory 222736 kb
Host smart-6c74dfe3-0024-4b49-a072-2adbfab81b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375874404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.375874404
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3061216720
Short name T766
Test name
Test status
Simulation time 276324198 ps
CPU time 3.69 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 208688 kb
Host smart-abc8176a-04f4-4c4a-82e4-34fac3464904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061216720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3061216720
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1144781126
Short name T370
Test name
Test status
Simulation time 255491424 ps
CPU time 7.4 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:52:03 PM PDT 24
Peak memory 210252 kb
Host smart-d0693475-f927-4136-8613-d81bef0be11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144781126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1144781126
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1492219693
Short name T385
Test name
Test status
Simulation time 2327460204 ps
CPU time 31.04 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:38 PM PDT 24
Peak memory 221444 kb
Host smart-08277909-78d0-4113-9ea1-d84f2778130c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492219693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1492219693
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2154875447
Short name T421
Test name
Test status
Simulation time 588823933 ps
CPU time 1.96 seconds
Started May 11 03:52:25 PM PDT 24
Finished May 11 03:52:28 PM PDT 24
Peak memory 210172 kb
Host smart-0ea06f05-6fb8-4934-8f5f-b60f03009ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154875447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2154875447
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.909983716
Short name T632
Test name
Test status
Simulation time 257568623 ps
CPU time 2.88 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 207004 kb
Host smart-580c24c0-5a51-448f-9d63-b9d30cd376c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909983716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.909983716
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1611961714
Short name T1008
Test name
Test status
Simulation time 342892761 ps
CPU time 2.49 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 214516 kb
Host smart-f2b70287-c9f9-4a07-823d-47d5094ac778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611961714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1611961714
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1585299658
Short name T179
Test name
Test status
Simulation time 6180312028 ps
CPU time 57.3 seconds
Started May 11 03:32:41 PM PDT 24
Finished May 11 03:33:39 PM PDT 24
Peak memory 214132 kb
Host smart-f7341abc-ad7f-438b-a6da-8a781794f72b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585299658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1585299658
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4036312020
Short name T124
Test name
Test status
Simulation time 224413019 ps
CPU time 3.42 seconds
Started May 11 03:32:11 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 213768 kb
Host smart-adf78e02-9864-43b9-be7e-f7d71017b926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036312020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4036312020
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1586381366
Short name T168
Test name
Test status
Simulation time 1762350696 ps
CPU time 8.67 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:19 PM PDT 24
Peak memory 209004 kb
Host smart-c1f73e5d-ac58-481e-bc80-0f5bc55acf7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586381366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1586381366
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2657524171
Short name T123
Test name
Test status
Simulation time 144473311 ps
CPU time 4.78 seconds
Started May 11 03:32:20 PM PDT 24
Finished May 11 03:32:25 PM PDT 24
Peak memory 209172 kb
Host smart-f7615782-efe2-446b-a231-6d5f7d0dd348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657524171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2657524171
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_random.1307330781
Short name T358
Test name
Test status
Simulation time 119162544 ps
CPU time 3.82 seconds
Started May 11 03:50:52 PM PDT 24
Finished May 11 03:50:56 PM PDT 24
Peak memory 218696 kb
Host smart-2ced1553-a394-469b-b10e-2e9196d0b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307330781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1307330781
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1283648006
Short name T333
Test name
Test status
Simulation time 107972554 ps
CPU time 2.86 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:50:59 PM PDT 24
Peak memory 208392 kb
Host smart-7149fc2f-64b8-4e61-bea7-73f886759ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283648006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1283648006
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.836068192
Short name T365
Test name
Test status
Simulation time 136113811 ps
CPU time 2.57 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:12 PM PDT 24
Peak memory 207324 kb
Host smart-2b6a4819-3003-45aa-a6e0-01655e28c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836068192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.836068192
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3911775466
Short name T391
Test name
Test status
Simulation time 1255494596 ps
CPU time 10.09 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 222700 kb
Host smart-9e484390-2737-478e-b772-30e8a3b2acc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911775466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3911775466
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.154727284
Short name T342
Test name
Test status
Simulation time 102597700 ps
CPU time 4.88 seconds
Started May 11 03:51:20 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 222688 kb
Host smart-21d346c8-ed50-4edb-b2c4-1a38a9f1518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154727284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.154727284
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.843528262
Short name T207
Test name
Test status
Simulation time 171105890 ps
CPU time 5.02 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 209908 kb
Host smart-f9ce265a-2ba1-4b96-8b28-2748bf5ed1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843528262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.843528262
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.821396347
Short name T966
Test name
Test status
Simulation time 418598177 ps
CPU time 5.19 seconds
Started May 11 03:52:08 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 220236 kb
Host smart-dc1d5f05-ca85-4cd3-ae88-bbdcbbd047dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821396347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.821396347
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3289467420
Short name T236
Test name
Test status
Simulation time 227114588 ps
CPU time 6.97 seconds
Started May 11 03:52:35 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 209920 kb
Host smart-7497dff4-04b6-4bda-90c0-bfa443e15a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289467420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3289467420
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3601513288
Short name T242
Test name
Test status
Simulation time 97312845 ps
CPU time 5.73 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:53:01 PM PDT 24
Peak memory 214504 kb
Host smart-aa110151-b520-4cae-9849-ef5900c8c116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601513288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3601513288
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.4260073425
Short name T238
Test name
Test status
Simulation time 732348056 ps
CPU time 2.85 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 207952 kb
Host smart-cd7912de-42c2-4b78-a1b4-418a6d4e2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260073425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.4260073425
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.855978368
Short name T317
Test name
Test status
Simulation time 1738604819 ps
CPU time 5.4 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 219560 kb
Host smart-bc23430f-fcbe-4908-b454-b5d16171ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855978368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.855978368
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1451030048
Short name T256
Test name
Test status
Simulation time 744582621 ps
CPU time 41.66 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:51:24 PM PDT 24
Peak memory 215480 kb
Host smart-dd1ed4de-f75c-4fbf-a7e0-1ca693b50221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451030048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1451030048
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3931036520
Short name T563
Test name
Test status
Simulation time 140681528 ps
CPU time 1.44 seconds
Started May 11 03:32:07 PM PDT 24
Finished May 11 03:32:09 PM PDT 24
Peak memory 205540 kb
Host smart-55d70dfa-b2ee-4905-a36d-dbeee537bc0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931036520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
931036520
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3410686855
Short name T488
Test name
Test status
Simulation time 44756183 ps
CPU time 1.4 seconds
Started May 11 03:32:07 PM PDT 24
Finished May 11 03:32:09 PM PDT 24
Peak memory 213772 kb
Host smart-5bafea39-15d3-4d72-958f-882f7e00272c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410686855 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3410686855
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3450356037
Short name T509
Test name
Test status
Simulation time 18303767 ps
CPU time 1.14 seconds
Started May 11 03:32:08 PM PDT 24
Finished May 11 03:32:10 PM PDT 24
Peak memory 205548 kb
Host smart-be1e34ba-389b-424a-9c36-589b27495fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450356037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3450356037
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.894421418
Short name T576
Test name
Test status
Simulation time 13402209 ps
CPU time 0.76 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:10 PM PDT 24
Peak memory 205364 kb
Host smart-8e0295b4-ba97-408a-a1ba-7f40a69edf6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894421418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.894421418
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.61548155
Short name T504
Test name
Test status
Simulation time 20708507 ps
CPU time 1.65 seconds
Started May 11 03:32:07 PM PDT 24
Finished May 11 03:32:09 PM PDT 24
Peak memory 205648 kb
Host smart-21bf6648-f0f8-4a9a-bf45-8cc8e53aced6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61548155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same
_csr_outstanding.61548155
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2758501461
Short name T125
Test name
Test status
Simulation time 189676396 ps
CPU time 3.32 seconds
Started May 11 03:32:08 PM PDT 24
Finished May 11 03:32:12 PM PDT 24
Peak memory 222108 kb
Host smart-e7440add-7636-4796-b057-21b9278e4ddb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758501461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2758501461
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3813226385
Short name T167
Test name
Test status
Simulation time 70254029 ps
CPU time 2.8 seconds
Started May 11 03:32:07 PM PDT 24
Finished May 11 03:32:11 PM PDT 24
Peak memory 213860 kb
Host smart-68b4f2a5-4281-42c8-8463-aaf36c5aba92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813226385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3813226385
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.237001564
Short name T544
Test name
Test status
Simulation time 994409888 ps
CPU time 15.37 seconds
Started May 11 03:32:07 PM PDT 24
Finished May 11 03:32:23 PM PDT 24
Peak memory 205572 kb
Host smart-ecf76b53-53c1-4e06-a64d-56cab838f68b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237001564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.237001564
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2475931393
Short name T146
Test name
Test status
Simulation time 137393702 ps
CPU time 1.2 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:11 PM PDT 24
Peak memory 205592 kb
Host smart-4f1740ee-fe1e-4f75-82b3-177a2935a0c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475931393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
475931393
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2104283528
Short name T142
Test name
Test status
Simulation time 52144609 ps
CPU time 2.02 seconds
Started May 11 03:32:06 PM PDT 24
Finished May 11 03:32:08 PM PDT 24
Peak memory 213724 kb
Host smart-0086875d-fec4-46b5-9a93-e0caea757518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104283528 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2104283528
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.185611749
Short name T145
Test name
Test status
Simulation time 15111832 ps
CPU time 1.3 seconds
Started May 11 03:32:08 PM PDT 24
Finished May 11 03:32:10 PM PDT 24
Peak memory 205564 kb
Host smart-09bb1395-1a6b-4ab0-97cd-1320eabd0cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185611749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.185611749
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3755881011
Short name T543
Test name
Test status
Simulation time 15745794 ps
CPU time 0.81 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:10 PM PDT 24
Peak memory 205244 kb
Host smart-bad5aebb-1b03-4bbf-aec4-7f4d39cb29a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755881011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3755881011
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2952516398
Short name T530
Test name
Test status
Simulation time 35234073 ps
CPU time 2.61 seconds
Started May 11 03:32:06 PM PDT 24
Finished May 11 03:32:09 PM PDT 24
Peak memory 213840 kb
Host smart-2329da3a-eb7b-4bb2-8249-6e1319b55adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952516398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2952516398
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.449348047
Short name T560
Test name
Test status
Simulation time 254929508 ps
CPU time 4.84 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 213928 kb
Host smart-6789b055-75e2-49aa-b282-ef61ceba5ce0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449348047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.449348047
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.983047795
Short name T549
Test name
Test status
Simulation time 3019399897 ps
CPU time 17.26 seconds
Started May 11 03:32:09 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 214016 kb
Host smart-b56fbd82-ddd2-4b14-b6ac-83badc312e2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983047795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.983047795
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3512728902
Short name T141
Test name
Test status
Simulation time 132237006 ps
CPU time 2.38 seconds
Started May 11 03:32:14 PM PDT 24
Finished May 11 03:32:17 PM PDT 24
Peak memory 216172 kb
Host smart-8b4687d6-f8cc-45fd-a859-fdb361f63a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512728902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3512728902
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.744681312
Short name T184
Test name
Test status
Simulation time 51123832 ps
CPU time 1.24 seconds
Started May 11 03:32:34 PM PDT 24
Finished May 11 03:32:36 PM PDT 24
Peak memory 213908 kb
Host smart-4110571e-0a96-4c65-89eb-ccf5d886611b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744681312 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.744681312
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3097869209
Short name T505
Test name
Test status
Simulation time 17426039 ps
CPU time 1.24 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:32 PM PDT 24
Peak memory 205572 kb
Host smart-e5a3006b-2ebc-47a4-897a-e93b65e0461b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097869209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3097869209
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.716497080
Short name T467
Test name
Test status
Simulation time 11122742 ps
CPU time 0.86 seconds
Started May 11 03:32:28 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 205344 kb
Host smart-26616049-e98f-4b1e-a52a-c1100b37e141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716497080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.716497080
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3997176371
Short name T546
Test name
Test status
Simulation time 197798914 ps
CPU time 1.8 seconds
Started May 11 03:32:28 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 205512 kb
Host smart-6cd60528-ed36-4df3-95ee-928868a41c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997176371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3997176371
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.816688735
Short name T187
Test name
Test status
Simulation time 1146619857 ps
CPU time 6.18 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 214040 kb
Host smart-52aea50a-9c7f-45b0-9819-f005eff15e27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816688735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.816688735
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1842404811
Short name T468
Test name
Test status
Simulation time 701218256 ps
CPU time 16.52 seconds
Started May 11 03:32:30 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 214044 kb
Host smart-74659a58-1235-4ff1-b4ba-3232a26234b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842404811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1842404811
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2693910914
Short name T508
Test name
Test status
Simulation time 113177249 ps
CPU time 2.37 seconds
Started May 11 03:32:34 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 213896 kb
Host smart-7265ca5f-da8c-434b-b8c0-5b02eece6f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693910914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2693910914
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4190861784
Short name T130
Test name
Test status
Simulation time 21809157 ps
CPU time 1.55 seconds
Started May 11 03:32:33 PM PDT 24
Finished May 11 03:32:35 PM PDT 24
Peak memory 213872 kb
Host smart-783c939c-b0e7-4593-84f3-955fe4380beb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190861784 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4190861784
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2240078870
Short name T459
Test name
Test status
Simulation time 58205531 ps
CPU time 1.14 seconds
Started May 11 03:32:29 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 205392 kb
Host smart-64a9ee59-562c-4e88-9881-b9a659f0253a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240078870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2240078870
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3590308835
Short name T506
Test name
Test status
Simulation time 53360870 ps
CPU time 0.81 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 205264 kb
Host smart-160173c4-53a8-403e-b1cf-413df2239157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590308835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3590308835
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3663210339
Short name T484
Test name
Test status
Simulation time 133954057 ps
CPU time 2.07 seconds
Started May 11 03:32:34 PM PDT 24
Finished May 11 03:32:36 PM PDT 24
Peak memory 205584 kb
Host smart-a7f3535b-43f6-478b-9155-2366f9a69498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663210339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3663210339
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3086732674
Short name T558
Test name
Test status
Simulation time 311016585 ps
CPU time 4.27 seconds
Started May 11 03:32:27 PM PDT 24
Finished May 11 03:32:32 PM PDT 24
Peak memory 214040 kb
Host smart-3b821955-5c07-46b2-b639-655245350250
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086732674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3086732674
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3170440645
Short name T499
Test name
Test status
Simulation time 193384467 ps
CPU time 4.41 seconds
Started May 11 03:32:30 PM PDT 24
Finished May 11 03:32:35 PM PDT 24
Peak memory 220296 kb
Host smart-c584b29f-7414-45c3-a162-b03a4352bd03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170440645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3170440645
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3946642159
Short name T556
Test name
Test status
Simulation time 247785894 ps
CPU time 1.95 seconds
Started May 11 03:32:29 PM PDT 24
Finished May 11 03:32:31 PM PDT 24
Peak memory 213772 kb
Host smart-7f2d8376-1712-49fe-8ec4-02c94c54259e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946642159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3946642159
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2795536298
Short name T188
Test name
Test status
Simulation time 36763502 ps
CPU time 1.39 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 213824 kb
Host smart-0acce231-9f8f-4dc8-805f-595d25b612f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795536298 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2795536298
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2911388237
Short name T461
Test name
Test status
Simulation time 137573593 ps
CPU time 1.17 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:33 PM PDT 24
Peak memory 205604 kb
Host smart-79e837b5-4671-462c-a233-3945104f8d84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911388237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2911388237
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4074503645
Short name T201
Test name
Test status
Simulation time 47699769 ps
CPU time 0.89 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:33 PM PDT 24
Peak memory 205336 kb
Host smart-1c5eaf54-50c0-4e76-8922-ca3ebae42517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074503645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4074503645
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4196440620
Short name T498
Test name
Test status
Simulation time 446048321 ps
CPU time 2.09 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:34 PM PDT 24
Peak memory 205640 kb
Host smart-17cfc42c-f52d-46d7-9a24-f93283e4f53a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196440620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4196440620
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2005664191
Short name T182
Test name
Test status
Simulation time 115327142 ps
CPU time 2.26 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 218492 kb
Host smart-68138af9-e296-4d04-b5b1-37a8b82aa23e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005664191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2005664191
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.563264628
Short name T552
Test name
Test status
Simulation time 209952544 ps
CPU time 4.45 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 214008 kb
Host smart-c40ba747-3fed-4621-b264-32ed9a9c900c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563264628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.563264628
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4150757175
Short name T534
Test name
Test status
Simulation time 203465908 ps
CPU time 2.95 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 213856 kb
Host smart-679b689e-ed91-4aec-9ab6-5f8e11f8174b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150757175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4150757175
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4269831325
Short name T477
Test name
Test status
Simulation time 227390897 ps
CPU time 3.54 seconds
Started May 11 03:32:34 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 209200 kb
Host smart-a62718a9-ec27-43ee-9465-15792ea280a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269831325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4269831325
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1469754697
Short name T548
Test name
Test status
Simulation time 14537530 ps
CPU time 1.13 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:33 PM PDT 24
Peak memory 205684 kb
Host smart-3b16ca2d-5aa0-4b4a-933b-b8ddf25196ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469754697 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1469754697
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1647244479
Short name T551
Test name
Test status
Simulation time 26577498 ps
CPU time 1.2 seconds
Started May 11 03:32:32 PM PDT 24
Finished May 11 03:32:34 PM PDT 24
Peak memory 205488 kb
Host smart-e599c1e2-908a-4591-9e97-573435b6cfb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647244479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1647244479
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1752700846
Short name T448
Test name
Test status
Simulation time 17360334 ps
CPU time 0.83 seconds
Started May 11 03:32:31 PM PDT 24
Finished May 11 03:32:33 PM PDT 24
Peak memory 205348 kb
Host smart-3d22b59a-4d94-4856-8868-3a55a6f216b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752700846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1752700846
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1969481858
Short name T575
Test name
Test status
Simulation time 46263650 ps
CPU time 1.62 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 205572 kb
Host smart-d6b2e1d0-20b3-4a5b-9954-1f0b77b61061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969481858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1969481858
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2160902196
Short name T157
Test name
Test status
Simulation time 229745029 ps
CPU time 8.76 seconds
Started May 11 03:32:30 PM PDT 24
Finished May 11 03:32:39 PM PDT 24
Peak memory 213948 kb
Host smart-ccb11c51-5c81-4c14-8fb7-ef6070b20bb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160902196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2160902196
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.617803421
Short name T129
Test name
Test status
Simulation time 114871217 ps
CPU time 2.47 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 214996 kb
Host smart-b3fe5bef-23e9-4e8f-9e6d-7cfcfbaa66da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617803421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.617803421
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3362696450
Short name T486
Test name
Test status
Simulation time 21451893 ps
CPU time 1.68 seconds
Started May 11 03:32:33 PM PDT 24
Finished May 11 03:32:36 PM PDT 24
Peak memory 213872 kb
Host smart-14b5f931-ef4e-4aed-8e96-259fd5baf76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362696450 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3362696450
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4234553873
Short name T464
Test name
Test status
Simulation time 49391027 ps
CPU time 0.75 seconds
Started May 11 03:32:33 PM PDT 24
Finished May 11 03:32:34 PM PDT 24
Peak memory 205344 kb
Host smart-e6b380fe-f90d-4eef-8e59-3fe8fe24a651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234553873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4234553873
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3714254986
Short name T491
Test name
Test status
Simulation time 206042382 ps
CPU time 2.46 seconds
Started May 11 03:32:29 PM PDT 24
Finished May 11 03:32:32 PM PDT 24
Peak memory 214072 kb
Host smart-65552d9e-e857-4f36-8792-18b0b8e600c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714254986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3714254986
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1958632572
Short name T547
Test name
Test status
Simulation time 522698090 ps
CPU time 8.86 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:48 PM PDT 24
Peak memory 214040 kb
Host smart-4e0f4378-cc44-4b11-8c7a-061a987e4b37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958632572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1958632572
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.622750716
Short name T553
Test name
Test status
Simulation time 691876038 ps
CPU time 6.5 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 213836 kb
Host smart-cc67e35b-ad40-444e-a8bc-8138b4c532e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622750716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.622750716
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3274504667
Short name T153
Test name
Test status
Simulation time 16851773 ps
CPU time 1.14 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 205496 kb
Host smart-1d0ddb89-8bfd-4116-a3fe-979ccbd3ff47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274504667 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3274504667
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2336766748
Short name T512
Test name
Test status
Simulation time 28382167 ps
CPU time 1.09 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:39 PM PDT 24
Peak memory 205468 kb
Host smart-e10b0f3f-6be4-48f7-9538-c1e755e05f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336766748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2336766748
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.781771590
Short name T517
Test name
Test status
Simulation time 33235337 ps
CPU time 0.76 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:36 PM PDT 24
Peak memory 205296 kb
Host smart-38f75cd2-b527-40db-882c-a8629907f8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781771590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.781771590
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2554459657
Short name T487
Test name
Test status
Simulation time 366900519 ps
CPU time 2.22 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205572 kb
Host smart-29e91381-1944-4c59-ad6d-483236756d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554459657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2554459657
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1550031323
Short name T490
Test name
Test status
Simulation time 225680178 ps
CPU time 2.53 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:41 PM PDT 24
Peak memory 222188 kb
Host smart-b875e662-3317-441e-a572-9e796370a16f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550031323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1550031323
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.985536282
Short name T573
Test name
Test status
Simulation time 1688697752 ps
CPU time 17.38 seconds
Started May 11 03:32:36 PM PDT 24
Finished May 11 03:32:54 PM PDT 24
Peak memory 213936 kb
Host smart-f58a8653-319f-4998-9291-6ee96747c6e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985536282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.985536282
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2593461913
Short name T514
Test name
Test status
Simulation time 53704344 ps
CPU time 2.18 seconds
Started May 11 03:32:34 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 213804 kb
Host smart-c1141bcb-293d-4363-9bd1-f6928823fb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593461913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2593461913
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4060372710
Short name T165
Test name
Test status
Simulation time 2790518273 ps
CPU time 9.9 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 213928 kb
Host smart-c63bfba1-a561-46bc-ba42-9e47c36ff54a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060372710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4060372710
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3770900982
Short name T541
Test name
Test status
Simulation time 116846143 ps
CPU time 1.63 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:39 PM PDT 24
Peak memory 213880 kb
Host smart-1d4b7c88-0dd5-4f96-842f-7b7ca84793ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770900982 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3770900982
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2226803539
Short name T496
Test name
Test status
Simulation time 72063534 ps
CPU time 1.29 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:37 PM PDT 24
Peak memory 205632 kb
Host smart-e2d3193e-26d9-4954-bada-10a29b83ace9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226803539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2226803539
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.710559314
Short name T478
Test name
Test status
Simulation time 9780317 ps
CPU time 0.76 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205308 kb
Host smart-3006a4f7-b7a1-409c-b941-0c2915c0bf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710559314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.710559314
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2820148516
Short name T522
Test name
Test status
Simulation time 353239826 ps
CPU time 2.38 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 205568 kb
Host smart-cdafbd7c-5252-47d9-83a6-cb94f7593ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820148516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2820148516
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1057809372
Short name T503
Test name
Test status
Simulation time 275420514 ps
CPU time 4.48 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 218820 kb
Host smart-d6ed186e-00f5-4f95-b738-089f105a5f2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057809372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1057809372
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3209223765
Short name T497
Test name
Test status
Simulation time 450329935 ps
CPU time 11.95 seconds
Started May 11 03:32:36 PM PDT 24
Finished May 11 03:32:48 PM PDT 24
Peak memory 214008 kb
Host smart-5b9f41db-572e-4a26-aa61-5e6cc983c01e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209223765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3209223765
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3611416497
Short name T479
Test name
Test status
Simulation time 91198350 ps
CPU time 1.59 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 213544 kb
Host smart-ecf79b4a-3af2-42cd-a47a-013d13c323ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611416497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3611416497
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1068396604
Short name T173
Test name
Test status
Simulation time 685668898 ps
CPU time 5.06 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 213748 kb
Host smart-cd02fb46-1d71-43f1-af69-884ed1aa03ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068396604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1068396604
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2864561681
Short name T202
Test name
Test status
Simulation time 157607695 ps
CPU time 1.2 seconds
Started May 11 03:32:33 PM PDT 24
Finished May 11 03:32:35 PM PDT 24
Peak memory 213852 kb
Host smart-1a025245-5891-42f3-a6b4-b6c19d6b1708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864561681 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2864561681
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3603672665
Short name T561
Test name
Test status
Simulation time 95200896 ps
CPU time 1.18 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:39 PM PDT 24
Peak memory 205548 kb
Host smart-af355241-aab9-4e15-ad5b-b018c13d7c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603672665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3603672665
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2028329027
Short name T521
Test name
Test status
Simulation time 82783134 ps
CPU time 0.68 seconds
Started May 11 03:32:32 PM PDT 24
Finished May 11 03:32:33 PM PDT 24
Peak memory 205352 kb
Host smart-7b5bfe41-ea0f-4fce-a9f8-0881532f21e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028329027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2028329027
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2583829869
Short name T550
Test name
Test status
Simulation time 420966881 ps
CPU time 2.68 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 214048 kb
Host smart-494f7b9a-56da-4803-94cf-5c522fc03425
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583829869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2583829869
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.45781237
Short name T533
Test name
Test status
Simulation time 451882106 ps
CPU time 2.93 seconds
Started May 11 03:32:41 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 213912 kb
Host smart-65702f44-41e6-424b-8d8e-398dfa970c76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45781237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.45781237
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1506168329
Short name T555
Test name
Test status
Simulation time 103890453 ps
CPU time 1.74 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 213964 kb
Host smart-d5a1f766-a0d7-4786-aca2-d11e30707f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506168329 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1506168329
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1187343009
Short name T557
Test name
Test status
Simulation time 43268113 ps
CPU time 1.13 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205572 kb
Host smart-2d0b2336-4c55-4ee0-af1b-246c8949ebc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187343009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1187343009
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1411428431
Short name T567
Test name
Test status
Simulation time 39239889 ps
CPU time 0.84 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:39 PM PDT 24
Peak memory 204936 kb
Host smart-d84517a3-73e9-4f51-87ff-303f07aca6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411428431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1411428431
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2085392265
Short name T471
Test name
Test status
Simulation time 59430002 ps
CPU time 1.48 seconds
Started May 11 03:32:42 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205612 kb
Host smart-3b58bbb7-6783-48b9-adf0-8cdacbc0cded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085392265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2085392265
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4047443733
Short name T180
Test name
Test status
Simulation time 207650039 ps
CPU time 6.46 seconds
Started May 11 03:32:36 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 213948 kb
Host smart-16edc329-1715-415a-bad4-97cbf3a0afc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047443733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4047443733
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.318193999
Short name T465
Test name
Test status
Simulation time 428530922 ps
CPU time 10.85 seconds
Started May 11 03:32:36 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 214012 kb
Host smart-9d46414a-dddd-4f68-9202-9558eeac4604
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318193999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.318193999
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3065771328
Short name T536
Test name
Test status
Simulation time 26949093 ps
CPU time 1.83 seconds
Started May 11 03:32:35 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 221736 kb
Host smart-aeb7b28e-f138-4f9a-b7f5-e7aefdec10f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065771328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3065771328
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3152452818
Short name T460
Test name
Test status
Simulation time 69912228 ps
CPU time 1.3 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 213836 kb
Host smart-9c4d8a53-0f21-4dea-a2e3-5d0ec47e655d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152452818 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3152452818
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.872723401
Short name T482
Test name
Test status
Simulation time 72592904 ps
CPU time 1.28 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205592 kb
Host smart-f572b4e6-1c52-4baa-9798-ec20914193ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872723401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.872723401
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2253508557
Short name T151
Test name
Test status
Simulation time 39132747 ps
CPU time 0.83 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205268 kb
Host smart-b69dbfec-101e-4455-80de-1ec1cf1ee0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253508557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2253508557
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1815412324
Short name T554
Test name
Test status
Simulation time 80764398 ps
CPU time 1.4 seconds
Started May 11 03:32:37 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205608 kb
Host smart-29084b0d-c8d1-4d34-a02e-17b436d8d377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815412324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1815412324
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2674713850
Short name T122
Test name
Test status
Simulation time 199588480 ps
CPU time 5.84 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 213932 kb
Host smart-706edfbc-ee27-4728-8753-fb91375cfeba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674713850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2674713850
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2669255544
Short name T132
Test name
Test status
Simulation time 220146237 ps
CPU time 1.53 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 213828 kb
Host smart-fdcaf360-7429-4a67-8773-dade38c6ff2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669255544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2669255544
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1733092811
Short name T171
Test name
Test status
Simulation time 229609998 ps
CPU time 5.19 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 208748 kb
Host smart-280804b8-5ac6-41c8-9d03-6b18def247dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733092811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1733092811
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1495270818
Short name T158
Test name
Test status
Simulation time 276052881 ps
CPU time 4.02 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 205404 kb
Host smart-361dfb2b-f520-4a2b-b967-1cbd3bb2d72e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495270818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
495270818
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1693453228
Short name T450
Test name
Test status
Simulation time 520717901 ps
CPU time 6.72 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:17 PM PDT 24
Peak memory 205576 kb
Host smart-7419e025-3dc0-456d-a69f-451375dcc632
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693453228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
693453228
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3413478386
Short name T516
Test name
Test status
Simulation time 25278810 ps
CPU time 1.43 seconds
Started May 11 03:32:11 PM PDT 24
Finished May 11 03:32:13 PM PDT 24
Peak memory 205476 kb
Host smart-7cc586d8-243a-4fe9-8e1f-5ceaee37fb89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413478386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
413478386
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4151110464
Short name T500
Test name
Test status
Simulation time 306145664 ps
CPU time 1.36 seconds
Started May 11 03:32:11 PM PDT 24
Finished May 11 03:32:13 PM PDT 24
Peak memory 205632 kb
Host smart-73734eeb-669a-49ed-a50d-de63d50fef0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151110464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4151110464
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2914125072
Short name T458
Test name
Test status
Simulation time 33897011 ps
CPU time 0.99 seconds
Started May 11 03:32:13 PM PDT 24
Finished May 11 03:32:14 PM PDT 24
Peak memory 205412 kb
Host smart-9cad7e28-fca8-4769-9c88-4bdc6e439227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914125072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2914125072
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3259270135
Short name T507
Test name
Test status
Simulation time 25780426 ps
CPU time 0.75 seconds
Started May 11 03:32:16 PM PDT 24
Finished May 11 03:32:18 PM PDT 24
Peak memory 205272 kb
Host smart-a1a71db3-5a85-46cd-a499-39a743443003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259270135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3259270135
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.515985303
Short name T538
Test name
Test status
Simulation time 60440251 ps
CPU time 2.33 seconds
Started May 11 03:32:12 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 205508 kb
Host smart-de3a881e-85c7-4e47-99ad-2099b8aab890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515985303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.515985303
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3195047875
Short name T150
Test name
Test status
Simulation time 200384396 ps
CPU time 4.57 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 214228 kb
Host smart-73a814e0-5791-4d01-a287-bb1cbc70aeae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195047875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3195047875
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2938803975
Short name T466
Test name
Test status
Simulation time 110081163 ps
CPU time 4.35 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 214092 kb
Host smart-dcaea216-f8aa-4e5d-9b7f-95d0d4327aeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938803975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2938803975
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3196134204
Short name T562
Test name
Test status
Simulation time 153003992 ps
CPU time 2.82 seconds
Started May 11 03:32:11 PM PDT 24
Finished May 11 03:32:14 PM PDT 24
Peak memory 213812 kb
Host smart-8c12fa54-d86e-4558-b6dc-bf298c7274ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196134204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3196134204
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2241859264
Short name T473
Test name
Test status
Simulation time 14140174 ps
CPU time 0.85 seconds
Started May 11 03:32:41 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205420 kb
Host smart-0b286ca9-7320-4b79-b1ce-8070cb2cb00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241859264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2241859264
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3643424321
Short name T476
Test name
Test status
Simulation time 12828598 ps
CPU time 0.89 seconds
Started May 11 03:32:41 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 205372 kb
Host smart-bf6ce353-fe5d-4418-b5ab-bd72d2584999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643424321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3643424321
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1927083466
Short name T198
Test name
Test status
Simulation time 14145603 ps
CPU time 0.83 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205404 kb
Host smart-7f11d7d2-6bde-41af-b5e7-3581c3f5928a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927083466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1927083466
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3961515876
Short name T154
Test name
Test status
Simulation time 8866532 ps
CPU time 0.71 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205276 kb
Host smart-95bf6b1c-0f12-4c13-85e2-bc1f6b2de1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961515876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3961515876
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3779759409
Short name T564
Test name
Test status
Simulation time 39917128 ps
CPU time 0.82 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205336 kb
Host smart-9e53fa4c-7c89-4ce5-89ff-a7718f64b76d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779759409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3779759409
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.737002789
Short name T454
Test name
Test status
Simulation time 25431955 ps
CPU time 0.91 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205268 kb
Host smart-5137e480-2d2a-429a-bcd0-a653c728b742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737002789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.737002789
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2581161502
Short name T199
Test name
Test status
Simulation time 38550267 ps
CPU time 0.71 seconds
Started May 11 03:32:40 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205300 kb
Host smart-3d53de48-9a09-4a3e-bc5c-c4e6c8118ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581161502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2581161502
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3885213389
Short name T502
Test name
Test status
Simulation time 12339924 ps
CPU time 0.89 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205288 kb
Host smart-05486814-b673-4da6-a842-c77536b2977f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885213389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3885213389
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3197344272
Short name T480
Test name
Test status
Simulation time 30027154 ps
CPU time 0.75 seconds
Started May 11 03:32:38 PM PDT 24
Finished May 11 03:32:40 PM PDT 24
Peak memory 205340 kb
Host smart-52b36f4a-4cd2-420a-9c85-16a4f634f116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197344272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3197344272
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2705148334
Short name T565
Test name
Test status
Simulation time 11649929 ps
CPU time 0.74 seconds
Started May 11 03:32:39 PM PDT 24
Finished May 11 03:32:41 PM PDT 24
Peak memory 205280 kb
Host smart-58e0b919-2c30-4895-aa6d-f614b312b896
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705148334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2705148334
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2079900553
Short name T519
Test name
Test status
Simulation time 531219166 ps
CPU time 9.37 seconds
Started May 11 03:32:17 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 205624 kb
Host smart-bef56462-e24d-48b9-aa08-1c9c09f93591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079900553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
079900553
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.472305862
Short name T571
Test name
Test status
Simulation time 6114302529 ps
CPU time 25.26 seconds
Started May 11 03:32:17 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205592 kb
Host smart-706854e4-bdbe-4fa1-9daa-781fbb07ba17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472305862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.472305862
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1562297417
Short name T545
Test name
Test status
Simulation time 17809992 ps
CPU time 1.02 seconds
Started May 11 03:32:11 PM PDT 24
Finished May 11 03:32:12 PM PDT 24
Peak memory 205568 kb
Host smart-f9bc52d3-7d47-4501-8e44-b6a777ab9094
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562297417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
562297417
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1607886309
Short name T529
Test name
Test status
Simulation time 20110394 ps
CPU time 1.5 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:17 PM PDT 24
Peak memory 213772 kb
Host smart-82d6002e-fe27-4f85-8bd6-8224d8801457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607886309 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1607886309
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2000642054
Short name T540
Test name
Test status
Simulation time 96014212 ps
CPU time 1.21 seconds
Started May 11 03:32:12 PM PDT 24
Finished May 11 03:32:13 PM PDT 24
Peak memory 205580 kb
Host smart-31515d79-25a2-4c03-813f-8944a3eca9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000642054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2000642054
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4065237495
Short name T472
Test name
Test status
Simulation time 35274142 ps
CPU time 0.83 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:12 PM PDT 24
Peak memory 205284 kb
Host smart-04d77fb8-f95f-45a8-b374-3892b973cc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065237495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4065237495
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.306020443
Short name T568
Test name
Test status
Simulation time 177763506 ps
CPU time 2.31 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:18 PM PDT 24
Peak memory 205568 kb
Host smart-5f196691-3a69-4df0-a540-4a3c58f2b28f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306020443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.306020443
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.376234637
Short name T475
Test name
Test status
Simulation time 119929094 ps
CPU time 2.64 seconds
Started May 11 03:32:12 PM PDT 24
Finished May 11 03:32:15 PM PDT 24
Peak memory 214040 kb
Host smart-b649fe29-abc1-4106-84ad-063cade540a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376234637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.376234637
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.799001552
Short name T126
Test name
Test status
Simulation time 641368771 ps
CPU time 18.1 seconds
Started May 11 03:32:10 PM PDT 24
Finished May 11 03:32:28 PM PDT 24
Peak memory 213952 kb
Host smart-cdb85268-307a-469a-9b46-3a72329d0a9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799001552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.799001552
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3153975934
Short name T525
Test name
Test status
Simulation time 18391253 ps
CPU time 1.43 seconds
Started May 11 03:32:16 PM PDT 24
Finished May 11 03:32:18 PM PDT 24
Peak memory 213752 kb
Host smart-eab90eca-e9be-436c-9a71-04a384c88033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153975934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3153975934
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3131422114
Short name T526
Test name
Test status
Simulation time 10360630 ps
CPU time 0.86 seconds
Started May 11 03:32:42 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205376 kb
Host smart-552aaf0e-cbee-46e4-97fa-8ad97f93f925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131422114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3131422114
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3598093538
Short name T447
Test name
Test status
Simulation time 13225022 ps
CPU time 0.74 seconds
Started May 11 03:32:41 PM PDT 24
Finished May 11 03:32:42 PM PDT 24
Peak memory 205364 kb
Host smart-4345aacb-774d-4abd-b17c-07d39dc03838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598093538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3598093538
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1479780434
Short name T542
Test name
Test status
Simulation time 110685173 ps
CPU time 0.8 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205364 kb
Host smart-f6e84e31-8839-4536-be4c-99575168d0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479780434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1479780434
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3057978537
Short name T494
Test name
Test status
Simulation time 142551872 ps
CPU time 0.92 seconds
Started May 11 03:32:42 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205364 kb
Host smart-1917598c-5b6a-40a5-b370-90a0ecc59899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057978537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3057978537
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1839431470
Short name T527
Test name
Test status
Simulation time 7742237 ps
CPU time 0.7 seconds
Started May 11 03:32:46 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 205372 kb
Host smart-10b7c695-f692-4260-a72c-447608719b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839431470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1839431470
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3496810668
Short name T152
Test name
Test status
Simulation time 12145559 ps
CPU time 0.73 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205364 kb
Host smart-7f90c0a8-afac-4c91-8b91-91c498ef94a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496810668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3496810668
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2424597062
Short name T457
Test name
Test status
Simulation time 33385448 ps
CPU time 0.72 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205268 kb
Host smart-61f6b20e-ee99-4d1a-86dd-2550531dce7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424597062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2424597062
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4149355171
Short name T513
Test name
Test status
Simulation time 12205172 ps
CPU time 0.75 seconds
Started May 11 03:32:45 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 205260 kb
Host smart-17ec84c8-7c0c-418e-856f-189daeab8c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149355171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4149355171
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4175739050
Short name T455
Test name
Test status
Simulation time 7459548 ps
CPU time 0.7 seconds
Started May 11 03:32:42 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 205328 kb
Host smart-9f47a29f-2c46-4437-bd7f-ae777491a4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175739050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4175739050
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.873819569
Short name T481
Test name
Test status
Simulation time 9119454 ps
CPU time 0.74 seconds
Started May 11 03:32:46 PM PDT 24
Finished May 11 03:32:47 PM PDT 24
Peak memory 205232 kb
Host smart-f5abd58c-8276-454f-adbd-1e033f7e2b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873819569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.873819569
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1652644580
Short name T528
Test name
Test status
Simulation time 81212320 ps
CPU time 4.42 seconds
Started May 11 03:32:17 PM PDT 24
Finished May 11 03:32:22 PM PDT 24
Peak memory 205576 kb
Host smart-72739daf-ef71-476f-9799-c347ba7b414f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652644580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
652644580
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1749735977
Short name T539
Test name
Test status
Simulation time 259051325 ps
CPU time 15.45 seconds
Started May 11 03:32:14 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 205584 kb
Host smart-68921fbf-960c-444c-bb63-931f21a5d47d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749735977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
749735977
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3527734060
Short name T186
Test name
Test status
Simulation time 101570012 ps
CPU time 1.83 seconds
Started May 11 03:32:16 PM PDT 24
Finished May 11 03:32:18 PM PDT 24
Peak memory 205564 kb
Host smart-c251c535-5cd6-42f8-a9f6-00d83f84d21d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527734060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
527734060
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3462864639
Short name T483
Test name
Test status
Simulation time 85480446 ps
CPU time 1.77 seconds
Started May 11 03:32:20 PM PDT 24
Finished May 11 03:32:23 PM PDT 24
Peak memory 213840 kb
Host smart-99a3b551-36b8-4d94-941e-6d9aed84062d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462864639 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3462864639
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3999455862
Short name T148
Test name
Test status
Simulation time 17182244 ps
CPU time 0.95 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:16 PM PDT 24
Peak memory 205096 kb
Host smart-7ce16a1c-9cf8-4b49-bff1-3359c554a771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999455862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3999455862
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1979784704
Short name T489
Test name
Test status
Simulation time 12073367 ps
CPU time 0.72 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:16 PM PDT 24
Peak memory 204972 kb
Host smart-ac4ed40f-f64d-4564-9ef4-51337fdb0c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979784704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1979784704
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3381922975
Short name T463
Test name
Test status
Simulation time 468480003 ps
CPU time 4.21 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:20 PM PDT 24
Peak memory 218668 kb
Host smart-cd27597d-6d03-4063-9ad9-775ec6b34b45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381922975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3381922975
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1452305077
Short name T518
Test name
Test status
Simulation time 283885281 ps
CPU time 2.6 seconds
Started May 11 03:32:18 PM PDT 24
Finished May 11 03:32:21 PM PDT 24
Peak memory 205616 kb
Host smart-01173cf7-f279-4099-a65c-c81b121d228e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452305077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1452305077
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4175721783
Short name T449
Test name
Test status
Simulation time 13098052 ps
CPU time 0.77 seconds
Started May 11 03:32:43 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205184 kb
Host smart-66b0c5e7-23e5-4ac1-9949-88b1ea01d473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175721783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4175721783
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1789137813
Short name T569
Test name
Test status
Simulation time 15570310 ps
CPU time 0.79 seconds
Started May 11 03:32:43 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205284 kb
Host smart-0da958de-ba4f-42bb-9fca-f24d6b176fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789137813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1789137813
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1622282339
Short name T572
Test name
Test status
Simulation time 23751516 ps
CPU time 0.78 seconds
Started May 11 03:32:43 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205376 kb
Host smart-f2d10db3-872c-42d7-8034-e2be146b9d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622282339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1622282339
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3339631026
Short name T200
Test name
Test status
Simulation time 25874938 ps
CPU time 0.88 seconds
Started May 11 03:32:45 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 205372 kb
Host smart-c7259472-3ddd-4fba-9a5a-00720ceea036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339631026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3339631026
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2763794417
Short name T470
Test name
Test status
Simulation time 35733425 ps
CPU time 0.68 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205256 kb
Host smart-7ba60d9e-e4ea-43a7-8196-bcfd7e3d69a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763794417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2763794417
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1525535828
Short name T570
Test name
Test status
Simulation time 10883819 ps
CPU time 0.72 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205364 kb
Host smart-f9bacb22-2469-4da9-9e48-7ea67790ab5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525535828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1525535828
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2706519084
Short name T524
Test name
Test status
Simulation time 23475543 ps
CPU time 0.72 seconds
Started May 11 03:32:44 PM PDT 24
Finished May 11 03:32:45 PM PDT 24
Peak memory 205260 kb
Host smart-8cdb5b4d-0f20-4f1e-88d2-c5ed377a328d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706519084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2706519084
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3593574014
Short name T515
Test name
Test status
Simulation time 11928370 ps
CPU time 0.92 seconds
Started May 11 03:32:43 PM PDT 24
Finished May 11 03:32:44 PM PDT 24
Peak memory 205376 kb
Host smart-6f4ff537-ad40-4c5c-81c7-2aaf5e1b3756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593574014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3593574014
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1594392980
Short name T452
Test name
Test status
Simulation time 16821811 ps
CPU time 0.74 seconds
Started May 11 03:32:42 PM PDT 24
Finished May 11 03:32:43 PM PDT 24
Peak memory 205300 kb
Host smart-79c83f28-12a7-44e1-8f09-15c74b4895f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594392980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1594392980
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1840716561
Short name T451
Test name
Test status
Simulation time 18674961 ps
CPU time 0.74 seconds
Started May 11 03:32:45 PM PDT 24
Finished May 11 03:32:46 PM PDT 24
Peak memory 205336 kb
Host smart-c5df4047-73a8-42f0-99a2-c8bdd7cfd14d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840716561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1840716561
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1898696228
Short name T511
Test name
Test status
Simulation time 20648640 ps
CPU time 1.3 seconds
Started May 11 03:32:19 PM PDT 24
Finished May 11 03:32:21 PM PDT 24
Peak memory 213836 kb
Host smart-0ffc0d09-94a4-4e00-a27e-dd1b920ddd48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898696228 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1898696228
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1603592169
Short name T155
Test name
Test status
Simulation time 49985657 ps
CPU time 0.89 seconds
Started May 11 03:32:19 PM PDT 24
Finished May 11 03:32:20 PM PDT 24
Peak memory 205268 kb
Host smart-f4e31445-33ee-47b1-9668-690c7c0e5634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603592169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1603592169
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.741379290
Short name T456
Test name
Test status
Simulation time 75657313 ps
CPU time 0.8 seconds
Started May 11 03:32:16 PM PDT 24
Finished May 11 03:32:18 PM PDT 24
Peak memory 205332 kb
Host smart-7eb6358e-11f0-4b27-a5ee-56f34f4b73dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741379290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.741379290
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.233130956
Short name T462
Test name
Test status
Simulation time 83958594 ps
CPU time 1.65 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 205580 kb
Host smart-a6743ff0-de62-45ba-9c65-eebb2892f4bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233130956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.233130956
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2975342861
Short name T185
Test name
Test status
Simulation time 416289658 ps
CPU time 2.4 seconds
Started May 11 03:32:14 PM PDT 24
Finished May 11 03:32:16 PM PDT 24
Peak memory 214108 kb
Host smart-babf7156-4185-4e77-a184-0f9f2f2a4102
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975342861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2975342861
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.577228338
Short name T501
Test name
Test status
Simulation time 501708244 ps
CPU time 12.03 seconds
Started May 11 03:32:18 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 214092 kb
Host smart-5d59896f-ed96-4878-b817-fa106c3db140
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577228338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.577228338
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1802328370
Short name T559
Test name
Test status
Simulation time 163790402 ps
CPU time 3.39 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:19 PM PDT 24
Peak memory 213816 kb
Host smart-56540685-c654-4531-998d-050ba65a78ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802328370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1802328370
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2122709009
Short name T169
Test name
Test status
Simulation time 466244720 ps
CPU time 5.48 seconds
Started May 11 03:32:15 PM PDT 24
Finished May 11 03:32:21 PM PDT 24
Peak memory 208888 kb
Host smart-65a22b80-dd77-4e89-a533-d1e8f54e2462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122709009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2122709009
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1777254544
Short name T535
Test name
Test status
Simulation time 205892895 ps
CPU time 1.31 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:25 PM PDT 24
Peak memory 213756 kb
Host smart-afa2f3ab-6ba8-49b2-9e44-2ba89f9fcd82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777254544 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1777254544
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3569172099
Short name T566
Test name
Test status
Simulation time 8224965 ps
CPU time 0.68 seconds
Started May 11 03:32:21 PM PDT 24
Finished May 11 03:32:22 PM PDT 24
Peak memory 205324 kb
Host smart-452eca3e-db09-4292-8c7f-b638dfed5ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569172099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3569172099
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2196559457
Short name T147
Test name
Test status
Simulation time 32393605 ps
CPU time 1.43 seconds
Started May 11 03:32:21 PM PDT 24
Finished May 11 03:32:23 PM PDT 24
Peak memory 205536 kb
Host smart-cf3b50bd-3f5c-46b0-9740-9f1dd9c3fb41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196559457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2196559457
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4242717001
Short name T127
Test name
Test status
Simulation time 169378229 ps
CPU time 3.75 seconds
Started May 11 03:32:23 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 213932 kb
Host smart-c32ece5f-ff65-45b3-9911-96795ae2268b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242717001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4242717001
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3696320521
Short name T120
Test name
Test status
Simulation time 1161417650 ps
CPU time 5.75 seconds
Started May 11 03:32:19 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 220012 kb
Host smart-383a670d-2414-40d5-875f-bc69fb4387bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696320521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3696320521
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2411842967
Short name T493
Test name
Test status
Simulation time 67806958 ps
CPU time 2.86 seconds
Started May 11 03:32:21 PM PDT 24
Finished May 11 03:32:24 PM PDT 24
Peak memory 213832 kb
Host smart-849d03d0-0ded-4954-ab06-de5d483050c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411842967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2411842967
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2762178485
Short name T474
Test name
Test status
Simulation time 36310716 ps
CPU time 1.91 seconds
Started May 11 03:32:22 PM PDT 24
Finished May 11 03:32:24 PM PDT 24
Peak memory 213788 kb
Host smart-64de3f1e-b766-4629-a784-3c5541b7dcf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762178485 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2762178485
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3756488113
Short name T156
Test name
Test status
Simulation time 94782193 ps
CPU time 1.31 seconds
Started May 11 03:32:25 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 205652 kb
Host smart-fb09fec8-d8cf-42e8-959d-42f2e51a8b88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756488113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3756488113
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3556556871
Short name T510
Test name
Test status
Simulation time 21744077 ps
CPU time 0.84 seconds
Started May 11 03:32:20 PM PDT 24
Finished May 11 03:32:21 PM PDT 24
Peak memory 205292 kb
Host smart-ebc99548-8269-483c-96e4-f07ece604e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556556871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3556556871
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3080926226
Short name T492
Test name
Test status
Simulation time 243184365 ps
CPU time 3.92 seconds
Started May 11 03:32:22 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 222040 kb
Host smart-4f3f52be-d3ca-418d-a288-879b0c95e86c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080926226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3080926226
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3777229277
Short name T485
Test name
Test status
Simulation time 827667623 ps
CPU time 8.77 seconds
Started May 11 03:32:20 PM PDT 24
Finished May 11 03:32:30 PM PDT 24
Peak memory 220176 kb
Host smart-252551fd-c056-4062-84ed-81106c3acb24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777229277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3777229277
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4046338174
Short name T495
Test name
Test status
Simulation time 51247994 ps
CPU time 3.73 seconds
Started May 11 03:32:22 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 217172 kb
Host smart-4ca419a6-9578-4230-90d2-0f668d2fb904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046338174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4046338174
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4104262073
Short name T143
Test name
Test status
Simulation time 5306734485 ps
CPU time 33.76 seconds
Started May 11 03:32:20 PM PDT 24
Finished May 11 03:32:54 PM PDT 24
Peak memory 211480 kb
Host smart-1f8dc619-aa0f-428f-8129-0ed698886288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104262073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4104262073
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2995752556
Short name T469
Test name
Test status
Simulation time 94728295 ps
CPU time 1.14 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 213972 kb
Host smart-e2f84a24-b4d2-46b4-89f8-478e50f4ed48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995752556 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2995752556
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3826431682
Short name T537
Test name
Test status
Simulation time 83008796 ps
CPU time 1.14 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 205556 kb
Host smart-aac9ac8f-3f7d-4fa7-a779-90084856f59b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826431682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3826431682
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3781849167
Short name T453
Test name
Test status
Simulation time 13359195 ps
CPU time 0.73 seconds
Started May 11 03:32:25 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 205336 kb
Host smart-da27c048-7e6e-4299-a3b3-278c9c5d74cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781849167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3781849167
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3140372615
Short name T532
Test name
Test status
Simulation time 71989016 ps
CPU time 2.55 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 205388 kb
Host smart-caa0754f-3e86-4c79-a067-0689abae47f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140372615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3140372615
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1952737414
Short name T181
Test name
Test status
Simulation time 471109079 ps
CPU time 4.72 seconds
Started May 11 03:32:23 PM PDT 24
Finished May 11 03:32:28 PM PDT 24
Peak memory 213956 kb
Host smart-6ac3686d-6d17-4f68-bce2-5c952628b2e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952737414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1952737414
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3422721691
Short name T520
Test name
Test status
Simulation time 1706512131 ps
CPU time 14.94 seconds
Started May 11 03:32:23 PM PDT 24
Finished May 11 03:32:38 PM PDT 24
Peak memory 220920 kb
Host smart-c9e28943-44f0-4792-9045-8067a9c8bd37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422721691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3422721691
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3936347157
Short name T134
Test name
Test status
Simulation time 51765623 ps
CPU time 1.62 seconds
Started May 11 03:32:26 PM PDT 24
Finished May 11 03:32:28 PM PDT 24
Peak memory 213820 kb
Host smart-376b1967-23e1-46b6-98f0-e1f957657c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936347157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3936347157
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2244336553
Short name T133
Test name
Test status
Simulation time 451306835 ps
CPU time 8.6 seconds
Started May 11 03:32:25 PM PDT 24
Finished May 11 03:32:34 PM PDT 24
Peak memory 208708 kb
Host smart-f2db61d8-4a58-448f-982d-547bc1ae514d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244336553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2244336553
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3397445309
Short name T196
Test name
Test status
Simulation time 142509129 ps
CPU time 1.34 seconds
Started May 11 03:32:24 PM PDT 24
Finished May 11 03:32:26 PM PDT 24
Peak memory 205608 kb
Host smart-c629de0b-017c-4dd8-aba0-a2dc09d8c8df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397445309 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3397445309
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2700630187
Short name T197
Test name
Test status
Simulation time 10734972 ps
CPU time 0.74 seconds
Started May 11 03:32:22 PM PDT 24
Finished May 11 03:32:23 PM PDT 24
Peak memory 205360 kb
Host smart-c19987cb-80ba-49f8-a487-f1888d136d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700630187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2700630187
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2972860322
Short name T531
Test name
Test status
Simulation time 133880200 ps
CPU time 2.09 seconds
Started May 11 03:32:25 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 205576 kb
Host smart-1d202a73-d904-4ea9-af51-25c8b51a5d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972860322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2972860322
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.495775891
Short name T523
Test name
Test status
Simulation time 119849727 ps
CPU time 4.31 seconds
Started May 11 03:32:26 PM PDT 24
Finished May 11 03:32:31 PM PDT 24
Peak memory 214004 kb
Host smart-807a5ead-a042-4d7c-9251-0761dd13df0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495775891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.495775891
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2740338265
Short name T574
Test name
Test status
Simulation time 331285723 ps
CPU time 4.14 seconds
Started May 11 03:32:23 PM PDT 24
Finished May 11 03:32:27 PM PDT 24
Peak memory 214024 kb
Host smart-fffd5ee6-686e-4d6c-91e8-fb4dc79459f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740338265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2740338265
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1343429934
Short name T178
Test name
Test status
Simulation time 117545096 ps
CPU time 4.29 seconds
Started May 11 03:32:26 PM PDT 24
Finished May 11 03:32:31 PM PDT 24
Peak memory 209044 kb
Host smart-bfe95d4f-0d43-4d4d-a529-4335cf7920e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343429934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1343429934
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3591877202
Short name T593
Test name
Test status
Simulation time 79832607 ps
CPU time 0.74 seconds
Started May 11 03:50:07 PM PDT 24
Finished May 11 03:50:08 PM PDT 24
Peak memory 206008 kb
Host smart-aa78476d-ec31-48fc-9e68-721f971c92bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591877202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3591877202
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1267218243
Short name T436
Test name
Test status
Simulation time 2157264449 ps
CPU time 106.86 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:51:54 PM PDT 24
Peak memory 214616 kb
Host smart-6704778d-5edf-432c-b135-32b12c0a8f6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267218243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1267218243
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3299220391
Short name T40
Test name
Test status
Simulation time 137691843 ps
CPU time 5.65 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:50:12 PM PDT 24
Peak memory 209944 kb
Host smart-bd57303e-2a7f-46e2-b748-97c446e18851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299220391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3299220391
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2087697427
Short name T929
Test name
Test status
Simulation time 870512413 ps
CPU time 21.6 seconds
Started May 11 03:50:07 PM PDT 24
Finished May 11 03:50:29 PM PDT 24
Peak memory 218368 kb
Host smart-973943ab-2d71-4252-86e4-878c942289b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087697427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2087697427
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3603365937
Short name T407
Test name
Test status
Simulation time 326864289 ps
CPU time 4.39 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:10 PM PDT 24
Peak memory 211428 kb
Host smart-1f21bc78-dd1e-407d-81ce-f2045ebd19b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603365937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3603365937
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3332905286
Short name T62
Test name
Test status
Simulation time 101664854 ps
CPU time 2.19 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:11 PM PDT 24
Peak memory 214504 kb
Host smart-4c57f810-db4b-41a8-a718-8798cc423fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332905286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3332905286
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2883456774
Short name T656
Test name
Test status
Simulation time 8707660856 ps
CPU time 49.21 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:50:56 PM PDT 24
Peak memory 220324 kb
Host smart-a5db7f80-aea5-46bd-9fc0-4c94e987f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883456774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2883456774
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.780819502
Short name T111
Test name
Test status
Simulation time 1234642560 ps
CPU time 10.46 seconds
Started May 11 03:50:04 PM PDT 24
Finished May 11 03:50:15 PM PDT 24
Peak memory 231436 kb
Host smart-126e7628-074f-4817-afaf-d099f5815f40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780819502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.780819502
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2803298938
Short name T769
Test name
Test status
Simulation time 73551286 ps
CPU time 3.87 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:12 PM PDT 24
Peak memory 208992 kb
Host smart-5765f7b7-e919-49ed-8747-e3a64d5ea0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803298938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2803298938
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.619407618
Short name T713
Test name
Test status
Simulation time 3719471836 ps
CPU time 40.78 seconds
Started May 11 03:50:03 PM PDT 24
Finished May 11 03:50:44 PM PDT 24
Peak memory 208828 kb
Host smart-944659cd-f0c2-4696-91dc-33d054ce3a99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619407618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.619407618
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.112891071
Short name T936
Test name
Test status
Simulation time 773933575 ps
CPU time 10.86 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:16 PM PDT 24
Peak memory 206972 kb
Host smart-f1f245b7-1f1a-464c-adbe-8c91e7f1b64a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112891071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.112891071
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1916651969
Short name T715
Test name
Test status
Simulation time 38273811 ps
CPU time 2.5 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:50:09 PM PDT 24
Peak memory 207052 kb
Host smart-71e9ea4f-53d8-4c91-8cbe-4fbeb8eadff7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916651969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1916651969
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.799188608
Short name T704
Test name
Test status
Simulation time 63771199 ps
CPU time 2.57 seconds
Started May 11 03:50:04 PM PDT 24
Finished May 11 03:50:07 PM PDT 24
Peak memory 209756 kb
Host smart-f75c7007-ffc2-4267-9ada-1734751ef9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799188608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.799188608
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1668325087
Short name T195
Test name
Test status
Simulation time 1428859363 ps
CPU time 39.66 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:45 PM PDT 24
Peak memory 208804 kb
Host smart-d3015cf3-8225-4f16-871b-ed5549aa3d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668325087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1668325087
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4045176235
Short name T344
Test name
Test status
Simulation time 8524453006 ps
CPU time 55.19 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:51:01 PM PDT 24
Peak memory 216168 kb
Host smart-52917682-4e44-4edb-ab20-bf77802dc24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045176235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4045176235
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2373304791
Short name T971
Test name
Test status
Simulation time 93559827 ps
CPU time 3.94 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:13 PM PDT 24
Peak memory 220504 kb
Host smart-0535e688-21e8-4a74-ac71-c63935ec2123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373304791 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2373304791
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2877695518
Short name T939
Test name
Test status
Simulation time 706557113 ps
CPU time 6.24 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:12 PM PDT 24
Peak memory 218520 kb
Host smart-024239e1-37f3-4d09-b15c-befd7a87b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877695518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2877695518
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1809423512
Short name T174
Test name
Test status
Simulation time 177395821 ps
CPU time 2.37 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:11 PM PDT 24
Peak memory 210492 kb
Host smart-8147c682-2193-4758-b438-b8280237d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809423512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1809423512
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2989489062
Short name T831
Test name
Test status
Simulation time 11077992 ps
CPU time 0.86 seconds
Started May 11 03:50:13 PM PDT 24
Finished May 11 03:50:14 PM PDT 24
Peak memory 205940 kb
Host smart-ba52c62c-2bf1-4ff4-aa0e-12b3b3c6de66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989489062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2989489062
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2990945956
Short name T442
Test name
Test status
Simulation time 112170540 ps
CPU time 4.62 seconds
Started May 11 03:50:14 PM PDT 24
Finished May 11 03:50:19 PM PDT 24
Peak memory 214508 kb
Host smart-0eb24d8b-695c-4a65-8d44-3c4a8648ba0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990945956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2990945956
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1521623607
Short name T834
Test name
Test status
Simulation time 48862673 ps
CPU time 2.92 seconds
Started May 11 03:50:10 PM PDT 24
Finished May 11 03:50:13 PM PDT 24
Peak memory 209468 kb
Host smart-2a80c350-b877-4908-9b21-50a903c64b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521623607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1521623607
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2090042731
Short name T76
Test name
Test status
Simulation time 73200490 ps
CPU time 3.2 seconds
Started May 11 03:50:10 PM PDT 24
Finished May 11 03:50:13 PM PDT 24
Peak memory 218388 kb
Host smart-19ae6f79-b06d-4f76-b679-cb58bd357737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090042731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2090042731
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1829077959
Short name T953
Test name
Test status
Simulation time 309845387 ps
CPU time 6.43 seconds
Started May 11 03:50:11 PM PDT 24
Finished May 11 03:50:18 PM PDT 24
Peak memory 219884 kb
Host smart-1cd16617-629d-44eb-8aec-0debafc7de57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829077959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1829077959
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4230309853
Short name T874
Test name
Test status
Simulation time 86773565 ps
CPU time 2.22 seconds
Started May 11 03:50:13 PM PDT 24
Finished May 11 03:50:16 PM PDT 24
Peak memory 215156 kb
Host smart-f3dddaa0-3f89-48d4-850a-f5afb693ae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230309853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4230309853
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1306837786
Short name T786
Test name
Test status
Simulation time 1537079158 ps
CPU time 10.08 seconds
Started May 11 03:50:12 PM PDT 24
Finished May 11 03:50:22 PM PDT 24
Peak memory 209564 kb
Host smart-f8585cfb-29de-49e3-bd66-d352c1e40038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306837786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1306837786
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1972236925
Short name T14
Test name
Test status
Simulation time 600996306 ps
CPU time 18.24 seconds
Started May 11 03:50:12 PM PDT 24
Finished May 11 03:50:31 PM PDT 24
Peak memory 230632 kb
Host smart-d2ea4b7d-b198-41f4-98a2-95699d3c74ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972236925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1972236925
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3685875997
Short name T762
Test name
Test status
Simulation time 1113623766 ps
CPU time 13.81 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:19 PM PDT 24
Peak memory 207980 kb
Host smart-a086d5c8-6169-4587-a4c6-b713740195f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685875997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3685875997
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2069174271
Short name T682
Test name
Test status
Simulation time 160263318 ps
CPU time 2.64 seconds
Started May 11 03:50:05 PM PDT 24
Finished May 11 03:50:08 PM PDT 24
Peak memory 207032 kb
Host smart-13d1da4a-b736-4718-b2f0-0312eee8bded
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069174271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2069174271
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1796626627
Short name T1022
Test name
Test status
Simulation time 106533485 ps
CPU time 3.17 seconds
Started May 11 03:50:08 PM PDT 24
Finished May 11 03:50:11 PM PDT 24
Peak memory 207012 kb
Host smart-a6c78e65-2d10-461a-bf2b-58163f1727ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796626627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1796626627
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3783667467
Short name T765
Test name
Test status
Simulation time 1471102151 ps
CPU time 18.86 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:50:25 PM PDT 24
Peak memory 208272 kb
Host smart-2b5ffd05-2490-4b2e-bb54-8325f536d88e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783667467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3783667467
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1688255773
Short name T423
Test name
Test status
Simulation time 23902152 ps
CPU time 1.64 seconds
Started May 11 03:50:10 PM PDT 24
Finished May 11 03:50:12 PM PDT 24
Peak memory 207164 kb
Host smart-56270ee1-fb60-41f9-a758-26669404e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688255773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1688255773
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.343671532
Short name T1073
Test name
Test status
Simulation time 147567242 ps
CPU time 4.49 seconds
Started May 11 03:50:06 PM PDT 24
Finished May 11 03:50:11 PM PDT 24
Peak memory 207028 kb
Host smart-1ec1ff0a-6ecc-4895-a4d1-e2967c0bfd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343671532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.343671532
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1738454606
Short name T86
Test name
Test status
Simulation time 208890209 ps
CPU time 11.72 seconds
Started May 11 03:50:13 PM PDT 24
Finished May 11 03:50:26 PM PDT 24
Peak memory 222700 kb
Host smart-227a26a3-d257-4538-8f53-a57b46b7bc71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738454606 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1738454606
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3951890304
Short name T950
Test name
Test status
Simulation time 771231223 ps
CPU time 5.49 seconds
Started May 11 03:50:13 PM PDT 24
Finished May 11 03:50:19 PM PDT 24
Peak memory 208708 kb
Host smart-ccaced01-9a22-4951-9512-161274037afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951890304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3951890304
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4179823477
Short name T577
Test name
Test status
Simulation time 79875159 ps
CPU time 1.38 seconds
Started May 11 03:50:11 PM PDT 24
Finished May 11 03:50:13 PM PDT 24
Peak memory 209988 kb
Host smart-b75165ba-6bfc-4618-a774-4855865505fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179823477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4179823477
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2590576856
Short name T429
Test name
Test status
Simulation time 315044877 ps
CPU time 15.96 seconds
Started May 11 03:50:47 PM PDT 24
Finished May 11 03:51:04 PM PDT 24
Peak memory 214524 kb
Host smart-9216be17-5231-4801-bc68-0487f5c42e3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590576856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2590576856
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3059638525
Short name T21
Test name
Test status
Simulation time 93829992 ps
CPU time 2.85 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:51:00 PM PDT 24
Peak memory 209576 kb
Host smart-6e9781cc-dfe7-4a9b-8033-7759498d7684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059638525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3059638525
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2008216652
Short name T59
Test name
Test status
Simulation time 339604434 ps
CPU time 4.35 seconds
Started May 11 03:50:52 PM PDT 24
Finished May 11 03:50:57 PM PDT 24
Peak memory 218496 kb
Host smart-bdc9b8ed-a79e-47ff-a9cc-afca31bec1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008216652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2008216652
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3806067418
Short name T104
Test name
Test status
Simulation time 190331303 ps
CPU time 3.34 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:50:59 PM PDT 24
Peak memory 219464 kb
Host smart-3a80fe9d-20ba-4357-a627-77bdb2b1ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806067418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3806067418
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1122603806
Short name T628
Test name
Test status
Simulation time 1567754413 ps
CPU time 5.14 seconds
Started May 11 03:50:48 PM PDT 24
Finished May 11 03:50:54 PM PDT 24
Peak memory 217832 kb
Host smart-92d13bec-a0ae-4e6d-859c-7051517871e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122603806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1122603806
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3494671745
Short name T930
Test name
Test status
Simulation time 362054923 ps
CPU time 5.54 seconds
Started May 11 03:50:49 PM PDT 24
Finished May 11 03:50:55 PM PDT 24
Peak memory 206856 kb
Host smart-462d79fb-6456-47a2-8293-8245092b2f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494671745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3494671745
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3073128420
Short name T587
Test name
Test status
Simulation time 129187691 ps
CPU time 3.59 seconds
Started May 11 03:50:49 PM PDT 24
Finished May 11 03:50:53 PM PDT 24
Peak memory 206932 kb
Host smart-cdb1eca5-716c-4feb-ab48-fa4ef15b00f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073128420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3073128420
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.749289244
Short name T659
Test name
Test status
Simulation time 79098381 ps
CPU time 2.36 seconds
Started May 11 03:50:51 PM PDT 24
Finished May 11 03:50:54 PM PDT 24
Peak memory 206876 kb
Host smart-86b09e86-c98a-47ed-b816-5f633eeafe7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749289244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.749289244
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1709146815
Short name T700
Test name
Test status
Simulation time 143519248 ps
CPU time 4.47 seconds
Started May 11 03:50:51 PM PDT 24
Finished May 11 03:50:56 PM PDT 24
Peak memory 206828 kb
Host smart-0034e247-0fa5-45dd-b698-0c64fa4d5d36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709146815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1709146815
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2022389690
Short name T378
Test name
Test status
Simulation time 15946857 ps
CPU time 1.4 seconds
Started May 11 03:50:53 PM PDT 24
Finished May 11 03:50:55 PM PDT 24
Peak memory 207880 kb
Host smart-8d3bf0ba-1a01-42b9-9bf5-120169577510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022389690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2022389690
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3470166868
Short name T1043
Test name
Test status
Simulation time 23539047 ps
CPU time 1.85 seconds
Started May 11 03:50:49 PM PDT 24
Finished May 11 03:50:51 PM PDT 24
Peak memory 206876 kb
Host smart-238c0ce7-c5ad-420a-adc0-62416c91dc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470166868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3470166868
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.171882090
Short name T1037
Test name
Test status
Simulation time 904442056 ps
CPU time 29.43 seconds
Started May 11 03:50:57 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 220356 kb
Host smart-307004eb-a3b4-4fed-852d-d096686defef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171882090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.171882090
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1241919196
Short name T684
Test name
Test status
Simulation time 3380577430 ps
CPU time 7.93 seconds
Started May 11 03:50:55 PM PDT 24
Finished May 11 03:51:04 PM PDT 24
Peak memory 222824 kb
Host smart-bc4f7964-49a7-4bbe-9dbd-164b035715e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241919196 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1241919196
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1830010393
Short name T844
Test name
Test status
Simulation time 180973965 ps
CPU time 7.46 seconds
Started May 11 03:50:51 PM PDT 24
Finished May 11 03:50:59 PM PDT 24
Peak memory 214444 kb
Host smart-f7739397-792a-4d32-a359-08b5ed10b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830010393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1830010393
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.715774749
Short name T890
Test name
Test status
Simulation time 153733984 ps
CPU time 3.08 seconds
Started May 11 03:50:54 PM PDT 24
Finished May 11 03:50:57 PM PDT 24
Peak memory 210052 kb
Host smart-eda85422-d179-413d-bb59-5005484dc63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715774749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.715774749
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2933793755
Short name T856
Test name
Test status
Simulation time 32921111 ps
CPU time 0.82 seconds
Started May 11 03:50:58 PM PDT 24
Finished May 11 03:51:00 PM PDT 24
Peak memory 206012 kb
Host smart-0a681d62-aebb-4c04-b23d-dc70551c91c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933793755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2933793755
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1554891967
Short name T309
Test name
Test status
Simulation time 425187664 ps
CPU time 4.93 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 215408 kb
Host smart-46adf761-8871-4b89-b230-f03461a93b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554891967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1554891967
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3527497943
Short name T805
Test name
Test status
Simulation time 144635549 ps
CPU time 5.75 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:06 PM PDT 24
Peak memory 210020 kb
Host smart-b65710a5-0c5f-4ac9-ae6c-df8e991ac9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527497943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3527497943
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.387298783
Short name T295
Test name
Test status
Simulation time 234551294 ps
CPU time 2.99 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:51:00 PM PDT 24
Peak memory 209724 kb
Host smart-530381ff-56a4-4423-bc77-71b0b8f43376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387298783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.387298783
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2165502175
Short name T955
Test name
Test status
Simulation time 278133981 ps
CPU time 3.95 seconds
Started May 11 03:51:01 PM PDT 24
Finished May 11 03:51:05 PM PDT 24
Peak memory 208752 kb
Host smart-48c6fb88-ac09-4263-8f6c-e220b0e64f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165502175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2165502175
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1152202862
Short name T618
Test name
Test status
Simulation time 128791275 ps
CPU time 5.52 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:51:02 PM PDT 24
Peak memory 219788 kb
Host smart-83c0b757-6c39-410f-b7c5-89ac25fbaa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152202862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1152202862
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2037029252
Short name T1034
Test name
Test status
Simulation time 373320578 ps
CPU time 5.25 seconds
Started May 11 03:50:55 PM PDT 24
Finished May 11 03:51:01 PM PDT 24
Peak memory 208932 kb
Host smart-24b63634-957f-4a9f-8b1b-c2e8c6bec1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037029252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2037029252
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.791049222
Short name T350
Test name
Test status
Simulation time 21025441 ps
CPU time 1.79 seconds
Started May 11 03:50:54 PM PDT 24
Finished May 11 03:50:56 PM PDT 24
Peak memory 206856 kb
Host smart-3aa120dc-fd61-4274-8fca-48a9a940d6d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791049222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.791049222
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2610065997
Short name T307
Test name
Test status
Simulation time 448851063 ps
CPU time 6.85 seconds
Started May 11 03:50:56 PM PDT 24
Finished May 11 03:51:04 PM PDT 24
Peak memory 208148 kb
Host smart-fd740a33-f42e-4714-80ce-29e27590859f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610065997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2610065997
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.435496135
Short name T617
Test name
Test status
Simulation time 76079906 ps
CPU time 2.17 seconds
Started May 11 03:50:58 PM PDT 24
Finished May 11 03:51:01 PM PDT 24
Peak memory 214312 kb
Host smart-dd87168f-dc2f-4040-ae28-162bf62a442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435496135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.435496135
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.982958430
Short name T1025
Test name
Test status
Simulation time 133319827 ps
CPU time 2.32 seconds
Started May 11 03:50:53 PM PDT 24
Finished May 11 03:50:56 PM PDT 24
Peak memory 207436 kb
Host smart-cf747c9a-1210-47c6-b1cc-96f1b03d2743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982958430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.982958430
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.966575041
Short name T280
Test name
Test status
Simulation time 35218742677 ps
CPU time 122.89 seconds
Started May 11 03:50:58 PM PDT 24
Finished May 11 03:53:01 PM PDT 24
Peak memory 218672 kb
Host smart-35e981a1-ce9c-41cd-92fc-f894cdac6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966575041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.966575041
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2494508777
Short name T941
Test name
Test status
Simulation time 120180294 ps
CPU time 2.87 seconds
Started May 11 03:50:58 PM PDT 24
Finished May 11 03:51:01 PM PDT 24
Peak memory 210164 kb
Host smart-883a36f8-b378-4c9f-98b1-7944f01145db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494508777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2494508777
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1968688540
Short name T108
Test name
Test status
Simulation time 8047702 ps
CPU time 0.7 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:05 PM PDT 24
Peak memory 206012 kb
Host smart-7e89cf8e-bc22-4533-9e74-cfa9eedbbc60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968688540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1968688540
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4153542104
Short name T917
Test name
Test status
Simulation time 82538053 ps
CPU time 2.87 seconds
Started May 11 03:50:57 PM PDT 24
Finished May 11 03:51:00 PM PDT 24
Peak memory 207768 kb
Host smart-3fd4122d-fab9-42fd-a485-765fd72bf392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153542104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4153542104
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1316513360
Short name T916
Test name
Test status
Simulation time 93136096 ps
CPU time 4.09 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:09 PM PDT 24
Peak memory 209240 kb
Host smart-86a2692c-f3f9-4904-ad45-5013de82ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316513360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1316513360
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3047294781
Short name T94
Test name
Test status
Simulation time 852746725 ps
CPU time 23.75 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 211692 kb
Host smart-f8eb5ce4-50d1-4792-a382-17df1f41686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047294781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3047294781
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2957506971
Short name T827
Test name
Test status
Simulation time 96554922 ps
CPU time 3.05 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:03 PM PDT 24
Peak memory 209324 kb
Host smart-5e22d546-74eb-4e77-8ba6-239577fe243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957506971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2957506971
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1957149393
Short name T891
Test name
Test status
Simulation time 1287962896 ps
CPU time 9.35 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:09 PM PDT 24
Peak memory 214596 kb
Host smart-305cf9c9-1986-4469-b9b5-cc172c1e6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957149393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1957149393
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3732176105
Short name T822
Test name
Test status
Simulation time 1448799715 ps
CPU time 42.98 seconds
Started May 11 03:50:57 PM PDT 24
Finished May 11 03:51:41 PM PDT 24
Peak memory 208884 kb
Host smart-6e0414d8-2ebd-4d58-8ee2-35d7b7c7ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732176105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3732176105
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4221116263
Short name T947
Test name
Test status
Simulation time 56448656 ps
CPU time 2.71 seconds
Started May 11 03:51:01 PM PDT 24
Finished May 11 03:51:04 PM PDT 24
Peak memory 207048 kb
Host smart-5d71b210-d343-4cb7-8ea3-dc0c6335d16d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221116263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4221116263
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1270048279
Short name T1031
Test name
Test status
Simulation time 715554853 ps
CPU time 19.25 seconds
Started May 11 03:50:58 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 208932 kb
Host smart-9e5318ff-a4f2-4077-b164-accd58f4a0d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270048279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1270048279
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4092785749
Short name T635
Test name
Test status
Simulation time 132756317 ps
CPU time 5.36 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:05 PM PDT 24
Peak memory 208084 kb
Host smart-ca1d1699-77de-4a66-8d56-3036bd7a7ce2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092785749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4092785749
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2007350380
Short name T798
Test name
Test status
Simulation time 160541402 ps
CPU time 3.48 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:09 PM PDT 24
Peak memory 214312 kb
Host smart-6e6b67cb-b1ba-46b5-80ad-3e4d3d631781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007350380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2007350380
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4176943930
Short name T680
Test name
Test status
Simulation time 1428790031 ps
CPU time 4.75 seconds
Started May 11 03:50:59 PM PDT 24
Finished May 11 03:51:04 PM PDT 24
Peak memory 206968 kb
Host smart-1e466edb-bd14-4767-b9ac-baa55152d2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176943930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4176943930
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3325162408
Short name T397
Test name
Test status
Simulation time 2879789603 ps
CPU time 55.96 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 216572 kb
Host smart-c48ac115-a03f-43ab-9c90-cb4f529c6fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325162408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3325162408
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.220936262
Short name T800
Test name
Test status
Simulation time 224980460 ps
CPU time 7.95 seconds
Started May 11 03:51:07 PM PDT 24
Finished May 11 03:51:15 PM PDT 24
Peak memory 222720 kb
Host smart-86cae252-6742-499e-b923-a062a91118a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220936262 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.220936262
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1655766450
Short name T1065
Test name
Test status
Simulation time 165994718 ps
CPU time 3.67 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:07 PM PDT 24
Peak memory 208816 kb
Host smart-46de783d-4b31-45cb-af75-71961b3dbcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655766450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1655766450
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3255225356
Short name T753
Test name
Test status
Simulation time 273886586 ps
CPU time 3.11 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 210176 kb
Host smart-27e5a9cd-7c68-4fba-8846-9067d24ed50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255225356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3255225356
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3999167102
Short name T1060
Test name
Test status
Simulation time 22072840 ps
CPU time 0.82 seconds
Started May 11 03:51:11 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 206004 kb
Host smart-3e318b04-b75c-44c5-98e8-005261a334e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999167102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3999167102
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3496062520
Short name T137
Test name
Test status
Simulation time 69285944 ps
CPU time 2.96 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:06 PM PDT 24
Peak memory 214872 kb
Host smart-505da2d5-5b5e-47a8-8a1f-246baec7fc53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496062520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3496062520
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.428021805
Short name T30
Test name
Test status
Simulation time 194398909 ps
CPU time 3.19 seconds
Started May 11 03:51:03 PM PDT 24
Finished May 11 03:51:07 PM PDT 24
Peak memory 221820 kb
Host smart-8efd10fb-be8d-40bb-9566-b0e040d8f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428021805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.428021805
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1727488645
Short name T79
Test name
Test status
Simulation time 517530421 ps
CPU time 3.22 seconds
Started May 11 03:51:06 PM PDT 24
Finished May 11 03:51:09 PM PDT 24
Peak memory 207736 kb
Host smart-1d560c17-d995-4061-9219-2803700c7783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727488645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1727488645
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3311730323
Short name T394
Test name
Test status
Simulation time 129066501 ps
CPU time 4.88 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 214388 kb
Host smart-a95c519c-8c48-4ca1-97ef-70daf19ef191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311730323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3311730323
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2231765657
Short name T106
Test name
Test status
Simulation time 118096491 ps
CPU time 2.73 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 210196 kb
Host smart-eec1822c-ab7d-41f2-b36d-e1ccbfe86161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231765657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2231765657
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2733498541
Short name T80
Test name
Test status
Simulation time 346423934 ps
CPU time 4.14 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:14 PM PDT 24
Peak memory 209328 kb
Host smart-d9ab375a-bb90-4bae-ab25-731d033aede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733498541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2733498541
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4271783767
Short name T640
Test name
Test status
Simulation time 201985937 ps
CPU time 2.98 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 207328 kb
Host smart-b5148ef5-2960-4c89-8585-c33ac093a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271783767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4271783767
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3365913087
Short name T647
Test name
Test status
Simulation time 62617336 ps
CPU time 3.12 seconds
Started May 11 03:51:02 PM PDT 24
Finished May 11 03:51:06 PM PDT 24
Peak memory 208644 kb
Host smart-33bcab04-fbef-4b87-9214-dc68808318b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365913087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3365913087
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1208006760
Short name T725
Test name
Test status
Simulation time 1130375085 ps
CPU time 12.43 seconds
Started May 11 03:51:03 PM PDT 24
Finished May 11 03:51:16 PM PDT 24
Peak memory 208692 kb
Host smart-e24baec8-6177-4d20-b607-56baf4800d0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208006760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1208006760
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2303578982
Short name T316
Test name
Test status
Simulation time 235511214 ps
CPU time 3.38 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 209132 kb
Host smart-22fd55c6-50e0-4d8c-996c-6474376ca35b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303578982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2303578982
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1245112705
Short name T873
Test name
Test status
Simulation time 56024235 ps
CPU time 3 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:14 PM PDT 24
Peak memory 208928 kb
Host smart-5346f41f-b1ab-4ac4-a374-03ec8005e648
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245112705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1245112705
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.580060133
Short name T1044
Test name
Test status
Simulation time 73217514 ps
CPU time 3.37 seconds
Started May 11 03:51:11 PM PDT 24
Finished May 11 03:51:14 PM PDT 24
Peak memory 210552 kb
Host smart-118f8511-32be-42d2-8bb9-d5e4b76f4547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580060133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.580060133
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2986201479
Short name T661
Test name
Test status
Simulation time 31561464 ps
CPU time 2.07 seconds
Started May 11 03:51:05 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 208664 kb
Host smart-5bb31b2c-f8aa-4511-89e7-0d5462854d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986201479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2986201479
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3850279163
Short name T886
Test name
Test status
Simulation time 137643680 ps
CPU time 7.73 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 222628 kb
Host smart-02189bb1-f3ed-400a-a2ee-bbf9126466a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850279163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3850279163
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3979707734
Short name T119
Test name
Test status
Simulation time 230638394 ps
CPU time 3.79 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 222628 kb
Host smart-83b54e0c-8b2e-4405-aba6-8c948f62840b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979707734 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3979707734
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2577641163
Short name T408
Test name
Test status
Simulation time 538546515 ps
CPU time 6.45 seconds
Started May 11 03:51:04 PM PDT 24
Finished May 11 03:51:12 PM PDT 24
Peak memory 214500 kb
Host smart-dd59b05d-206a-4e52-8913-7bbe15867b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577641163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2577641163
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3439554000
Short name T584
Test name
Test status
Simulation time 40697929 ps
CPU time 2.52 seconds
Started May 11 03:51:07 PM PDT 24
Finished May 11 03:51:10 PM PDT 24
Peak memory 210352 kb
Host smart-267f3abf-3e28-4bc9-b15c-0640fc13b276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439554000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3439554000
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3529541409
Short name T609
Test name
Test status
Simulation time 21301648 ps
CPU time 0.88 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:15 PM PDT 24
Peak memory 205984 kb
Host smart-cc73d3dd-1c41-40a5-bf83-fa806777e559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529541409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3529541409
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2047533540
Short name T1021
Test name
Test status
Simulation time 4889035523 ps
CPU time 6.81 seconds
Started May 11 03:51:13 PM PDT 24
Finished May 11 03:51:20 PM PDT 24
Peak memory 210444 kb
Host smart-f1a6a823-a6ce-45a9-9a05-239c1a7c03c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047533540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2047533540
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3031361190
Short name T1023
Test name
Test status
Simulation time 125628203 ps
CPU time 3.19 seconds
Started May 11 03:51:11 PM PDT 24
Finished May 11 03:51:15 PM PDT 24
Peak memory 218952 kb
Host smart-3ce0c860-876a-4b1e-9510-b5d2e7384458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031361190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3031361190
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.648949682
Short name T389
Test name
Test status
Simulation time 328831202 ps
CPU time 4.13 seconds
Started May 11 03:51:11 PM PDT 24
Finished May 11 03:51:16 PM PDT 24
Peak memory 222572 kb
Host smart-a581fe14-f9ef-4cce-9f98-0f5956681e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648949682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.648949682
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.10582220
Short name T272
Test name
Test status
Simulation time 67917561 ps
CPU time 3.99 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:14 PM PDT 24
Peak memory 220512 kb
Host smart-151a6bf4-4bdd-48a0-b750-b4adb88571a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10582220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.10582220
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3476783199
Short name T349
Test name
Test status
Simulation time 142267382 ps
CPU time 6.22 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:15 PM PDT 24
Peak memory 218380 kb
Host smart-2d46f89d-1f2a-4582-b410-4b2eb60bddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476783199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3476783199
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3532311328
Short name T395
Test name
Test status
Simulation time 56539438 ps
CPU time 2.79 seconds
Started May 11 03:51:07 PM PDT 24
Finished May 11 03:51:10 PM PDT 24
Peak memory 208536 kb
Host smart-66f4c775-0650-4e5a-9a45-f04ad6ef362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532311328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3532311328
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2067118128
Short name T644
Test name
Test status
Simulation time 206231857 ps
CPU time 2.84 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:13 PM PDT 24
Peak memory 207024 kb
Host smart-a80cba58-0391-4151-b073-f928862f281c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067118128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2067118128
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2208665516
Short name T740
Test name
Test status
Simulation time 3933978130 ps
CPU time 38.02 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:48 PM PDT 24
Peak memory 208132 kb
Host smart-dcb8ae86-e1e2-45d4-9e4b-38afb3d3bab0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208665516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2208665516
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.763773495
Short name T260
Test name
Test status
Simulation time 64344163 ps
CPU time 3.4 seconds
Started May 11 03:51:08 PM PDT 24
Finished May 11 03:51:12 PM PDT 24
Peak memory 208496 kb
Host smart-41db3862-2a1a-4990-affd-6bd02af3a5d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763773495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.763773495
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.529282822
Short name T248
Test name
Test status
Simulation time 423759866 ps
CPU time 8.9 seconds
Started May 11 03:51:12 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 209780 kb
Host smart-426358b7-1083-4066-ae24-47d3577fba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529282822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.529282822
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1946179031
Short name T419
Test name
Test status
Simulation time 121859124 ps
CPU time 2.27 seconds
Started May 11 03:51:10 PM PDT 24
Finished May 11 03:51:12 PM PDT 24
Peak memory 206704 kb
Host smart-12bf1030-08ab-4180-b01c-7c1a3b38a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946179031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1946179031
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.954793330
Short name T282
Test name
Test status
Simulation time 1350552394 ps
CPU time 49.22 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 221036 kb
Host smart-fd0c42d2-2576-4c81-8035-24b574c9704a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954793330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.954793330
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1191751899
Short name T809
Test name
Test status
Simulation time 404573610 ps
CPU time 2.87 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 215316 kb
Host smart-0ca88404-e823-472d-bc0b-e2e6c48c495e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191751899 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1191751899
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.666991713
Short name T813
Test name
Test status
Simulation time 243713579 ps
CPU time 7.62 seconds
Started May 11 03:51:09 PM PDT 24
Finished May 11 03:51:17 PM PDT 24
Peak memory 208692 kb
Host smart-482ec569-33e3-4297-a1c5-8ac94af88dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666991713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.666991713
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2408107373
Short name T687
Test name
Test status
Simulation time 127963982 ps
CPU time 1.67 seconds
Started May 11 03:51:16 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 210276 kb
Host smart-1c1da84f-72e1-484f-9690-48e3e5ab04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408107373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2408107373
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3633423906
Short name T842
Test name
Test status
Simulation time 27166669 ps
CPU time 0.76 seconds
Started May 11 03:51:20 PM PDT 24
Finished May 11 03:51:22 PM PDT 24
Peak memory 205916 kb
Host smart-bdc26a48-1481-4a83-a9aa-f51771da3837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633423906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3633423906
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1791228648
Short name T919
Test name
Test status
Simulation time 769884902 ps
CPU time 27.84 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 219252 kb
Host smart-1ed47ff4-8888-493c-aa43-4421bd813d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791228648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1791228648
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1661959296
Short name T807
Test name
Test status
Simulation time 134285046 ps
CPU time 2.35 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:17 PM PDT 24
Peak memory 207304 kb
Host smart-aae67775-62b6-4b14-8010-0faa78fa66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661959296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1661959296
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2742945184
Short name T907
Test name
Test status
Simulation time 897402457 ps
CPU time 10.79 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 209072 kb
Host smart-b824b8c7-22cf-4a46-bfeb-152356269121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742945184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2742945184
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3560151435
Short name T865
Test name
Test status
Simulation time 108739965 ps
CPU time 2.52 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:36 PM PDT 24
Peak memory 219248 kb
Host smart-9e96eff8-4ed5-45c9-b07e-de1c07db88b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560151435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3560151435
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3008951102
Short name T1036
Test name
Test status
Simulation time 965999054 ps
CPU time 20.64 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:36 PM PDT 24
Peak memory 208624 kb
Host smart-d1b2893b-01b0-46fb-995d-608fe9727d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008951102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3008951102
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1950368209
Short name T285
Test name
Test status
Simulation time 73476199 ps
CPU time 2.88 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 208568 kb
Host smart-3828be6a-50f6-450f-9cba-250e08948772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950368209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1950368209
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3212470990
Short name T913
Test name
Test status
Simulation time 837309163 ps
CPU time 3.66 seconds
Started May 11 03:51:13 PM PDT 24
Finished May 11 03:51:17 PM PDT 24
Peak memory 208936 kb
Host smart-67660c42-e99d-4ec5-8ff6-e0be67477460
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212470990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3212470990
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3981573801
Short name T884
Test name
Test status
Simulation time 202666088 ps
CPU time 5.12 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:20 PM PDT 24
Peak memory 208116 kb
Host smart-9c053425-0ec5-4131-bed7-e33bef3c87c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981573801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3981573801
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3460035439
Short name T18
Test name
Test status
Simulation time 60992596 ps
CPU time 3.2 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 208740 kb
Host smart-005b168e-464c-41a6-a5da-d0590f90c868
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460035439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3460035439
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3336955048
Short name T698
Test name
Test status
Simulation time 82252763 ps
CPU time 2.76 seconds
Started May 11 03:51:15 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 209900 kb
Host smart-2bf3d6ce-5481-42df-af8d-d64d71a3c561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336955048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3336955048
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3363690565
Short name T1
Test name
Test status
Simulation time 120140453 ps
CPU time 3.55 seconds
Started May 11 03:51:13 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 207968 kb
Host smart-3ba29c39-0dbb-419f-b3e7-6bca14455649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363690565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3363690565
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3001363223
Short name T343
Test name
Test status
Simulation time 1193581225 ps
CPU time 27.96 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 215904 kb
Host smart-b70d7206-8006-4223-82d3-a7c2df552c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001363223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3001363223
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.75854480
Short name T761
Test name
Test status
Simulation time 615666088 ps
CPU time 7.66 seconds
Started May 11 03:51:20 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 222760 kb
Host smart-3dfb1e77-73fe-4885-a0cf-bf5560c0a836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75854480 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.75854480
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.476127836
Short name T892
Test name
Test status
Simulation time 388882906 ps
CPU time 10.58 seconds
Started May 11 03:51:16 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 218428 kb
Host smart-8f88f635-00c2-430f-8ab7-d7b06b708139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476127836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.476127836
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1411607977
Short name T1020
Test name
Test status
Simulation time 43984543 ps
CPU time 1.79 seconds
Started May 11 03:51:13 PM PDT 24
Finished May 11 03:51:16 PM PDT 24
Peak memory 210004 kb
Host smart-371f4519-80ee-47ab-aa38-390966add9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411607977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1411607977
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.296328882
Short name T446
Test name
Test status
Simulation time 61400434 ps
CPU time 0.82 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:20 PM PDT 24
Peak memory 206008 kb
Host smart-9aa59fd3-a22a-4d5b-9b3e-cef48ce23a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296328882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.296328882
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4156195057
Short name T322
Test name
Test status
Simulation time 38213640 ps
CPU time 2.64 seconds
Started May 11 03:51:21 PM PDT 24
Finished May 11 03:51:24 PM PDT 24
Peak memory 214448 kb
Host smart-a9c620b1-d750-45d6-985a-8602af5054ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156195057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4156195057
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3289574993
Short name T11
Test name
Test status
Simulation time 85176868 ps
CPU time 2.55 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:36 PM PDT 24
Peak memory 214608 kb
Host smart-1ac5c1fb-4d58-4d6b-8c7c-bbe00c7de815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289574993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3289574993
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2184250181
Short name T981
Test name
Test status
Simulation time 39883612 ps
CPU time 2.64 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 209740 kb
Host smart-1cdebf81-5015-4422-90fe-693c456883ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184250181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2184250181
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4174507995
Short name T114
Test name
Test status
Simulation time 1172942310 ps
CPU time 8.26 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 214504 kb
Host smart-8963e22f-8ebe-4683-8d83-6be8e953d2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174507995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4174507995
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.225168313
Short name T614
Test name
Test status
Simulation time 148780420 ps
CPU time 2.42 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 209192 kb
Host smart-16f1f804-ed5c-4155-910d-07fde5a52c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225168313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.225168313
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3326419517
Short name T1010
Test name
Test status
Simulation time 52921684 ps
CPU time 3.33 seconds
Started May 11 03:51:17 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 218536 kb
Host smart-ecf03005-cf98-403c-bc55-6449e94f94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326419517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3326419517
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1853514493
Short name T1035
Test name
Test status
Simulation time 1315190281 ps
CPU time 31.14 seconds
Started May 11 03:51:16 PM PDT 24
Finished May 11 03:51:47 PM PDT 24
Peak memory 208596 kb
Host smart-96363427-fcde-4f85-91b0-4979d820429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853514493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1853514493
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1080801981
Short name T1041
Test name
Test status
Simulation time 38494997 ps
CPU time 2.38 seconds
Started May 11 03:51:21 PM PDT 24
Finished May 11 03:51:24 PM PDT 24
Peak memory 207112 kb
Host smart-986756f7-e29e-4e3b-98a7-620f32a980c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080801981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1080801981
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2160220563
Short name T751
Test name
Test status
Simulation time 1539984928 ps
CPU time 5.1 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:25 PM PDT 24
Peak memory 207016 kb
Host smart-57f6340b-c53b-4c8e-a658-6d7f0e4081fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160220563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2160220563
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.516546797
Short name T1055
Test name
Test status
Simulation time 126667111 ps
CPU time 2.12 seconds
Started May 11 03:51:21 PM PDT 24
Finished May 11 03:51:24 PM PDT 24
Peak memory 210160 kb
Host smart-8db43393-67d5-48fd-a730-cd0bf9859955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516546797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.516546797
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1015922825
Short name T845
Test name
Test status
Simulation time 104471662 ps
CPU time 2.78 seconds
Started May 11 03:51:14 PM PDT 24
Finished May 11 03:51:18 PM PDT 24
Peak memory 206868 kb
Host smart-22ac54cb-c0e9-4d73-92c0-8a4d08786a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015922825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1015922825
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3050712779
Short name T839
Test name
Test status
Simulation time 6639766210 ps
CPU time 126.46 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 221552 kb
Host smart-cc11af28-94d0-4c08-8299-d9f6e171f0e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050712779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3050712779
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.459942100
Short name T222
Test name
Test status
Simulation time 642532796 ps
CPU time 8.06 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:42 PM PDT 24
Peak memory 222932 kb
Host smart-d672af9e-eee1-409e-8a62-f396bd982594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459942100 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.459942100
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2781463380
Short name T855
Test name
Test status
Simulation time 74280879 ps
CPU time 3.19 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:22 PM PDT 24
Peak memory 208132 kb
Host smart-6f22c4f8-bdc4-4ccb-92e1-e89b565dffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781463380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2781463380
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1983345871
Short name T663
Test name
Test status
Simulation time 66349305 ps
CPU time 1.97 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 209904 kb
Host smart-dc9f7ca7-dd23-4fa1-a683-6d941f3c639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983345871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1983345871
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2047948856
Short name T3
Test name
Test status
Simulation time 15588007 ps
CPU time 0.82 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:25 PM PDT 24
Peak memory 205932 kb
Host smart-d8cf1aaa-4b9e-4df6-a132-ff646f704c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047948856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2047948856
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.90339611
Short name T427
Test name
Test status
Simulation time 30245182 ps
CPU time 2.64 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 214420 kb
Host smart-f6cdd246-5cd9-4f0d-911f-c81ca5ce165a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90339611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.90339611
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3211334337
Short name T666
Test name
Test status
Simulation time 149986261 ps
CPU time 5.32 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:29 PM PDT 24
Peak memory 222992 kb
Host smart-6792b2be-97b1-4135-a09c-dd9a0c027790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211334337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3211334337
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.364526347
Short name T1014
Test name
Test status
Simulation time 77350696 ps
CPU time 1.83 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:35 PM PDT 24
Peak memory 214220 kb
Host smart-6cf607a3-0dd9-4605-8f1c-3c6e9d254a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364526347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.364526347
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4185316677
Short name T403
Test name
Test status
Simulation time 4800308206 ps
CPU time 43.75 seconds
Started May 11 03:51:22 PM PDT 24
Finished May 11 03:52:07 PM PDT 24
Peak memory 222688 kb
Host smart-49619fb3-9cc0-41ed-85a1-5f5b83799906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185316677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4185316677
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1652535543
Short name T705
Test name
Test status
Simulation time 98447986 ps
CPU time 3.98 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 207976 kb
Host smart-301f51f2-5f36-4ebb-94c8-673808704874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652535543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1652535543
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1308468612
Short name T264
Test name
Test status
Simulation time 260460462 ps
CPU time 10.41 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:29 PM PDT 24
Peak memory 207740 kb
Host smart-08b4dedc-3d06-45ba-8a22-77000ac232be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308468612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1308468612
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1549202881
Short name T782
Test name
Test status
Simulation time 138946973 ps
CPU time 3.26 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:37 PM PDT 24
Peak memory 208620 kb
Host smart-dd617daf-8884-4358-91b1-25bfa3f48f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549202881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1549202881
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.397507260
Short name T710
Test name
Test status
Simulation time 58711400 ps
CPU time 2.3 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:22 PM PDT 24
Peak memory 207024 kb
Host smart-7511ab44-c68a-4349-b924-7b972c46d095
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397507260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.397507260
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3674066052
Short name T730
Test name
Test status
Simulation time 24426287 ps
CPU time 1.9 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:20 PM PDT 24
Peak memory 207072 kb
Host smart-172aebe0-73d0-4dfc-a6e5-6e54de4ad18e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674066052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3674066052
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.932838931
Short name T770
Test name
Test status
Simulation time 631479260 ps
CPU time 3.5 seconds
Started May 11 03:51:19 PM PDT 24
Finished May 11 03:51:23 PM PDT 24
Peak memory 208536 kb
Host smart-4d16991b-99c9-4a6c-b8c5-79935bae7959
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932838931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.932838931
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3381000319
Short name T688
Test name
Test status
Simulation time 191687088 ps
CPU time 2.72 seconds
Started May 11 03:51:23 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 208904 kb
Host smart-77f231f5-d3ef-4437-b64f-f2be40aa214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381000319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3381000319
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1144219256
Short name T795
Test name
Test status
Simulation time 48740175 ps
CPU time 2.61 seconds
Started May 11 03:51:18 PM PDT 24
Finished May 11 03:51:21 PM PDT 24
Peak memory 206748 kb
Host smart-6569a1d3-18b9-494d-b0da-393cb5e89143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144219256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1144219256
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1846896536
Short name T73
Test name
Test status
Simulation time 647445628 ps
CPU time 23.78 seconds
Started May 11 03:51:29 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 215104 kb
Host smart-2af34c96-3dc2-4bb5-aefb-41a8fb754047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846896536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1846896536
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2091243843
Short name T422
Test name
Test status
Simulation time 137662012 ps
CPU time 5.57 seconds
Started May 11 03:51:31 PM PDT 24
Finished May 11 03:51:37 PM PDT 24
Peak memory 222636 kb
Host smart-d3481221-4ee5-476e-a66d-ebdd91aebba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091243843 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2091243843
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2748377203
Short name T28
Test name
Test status
Simulation time 984481330 ps
CPU time 7.56 seconds
Started May 11 03:51:20 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 208416 kb
Host smart-c719fc7a-2d5e-4bd0-bdbf-6675bc9a4aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748377203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2748377203
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3109093228
Short name T758
Test name
Test status
Simulation time 280062195 ps
CPU time 2.55 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 210336 kb
Host smart-4dd662c1-32ee-49b0-83a4-354414ad0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109093228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3109093228
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2570412290
Short name T583
Test name
Test status
Simulation time 16389192 ps
CPU time 0.83 seconds
Started May 11 03:51:32 PM PDT 24
Finished May 11 03:51:33 PM PDT 24
Peak memory 205920 kb
Host smart-db37aea8-5c9f-4b79-8228-41b6680db5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570412290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2570412290
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1082175621
Short name T876
Test name
Test status
Simulation time 852799290 ps
CPU time 5.94 seconds
Started May 11 03:51:30 PM PDT 24
Finished May 11 03:51:36 PM PDT 24
Peak memory 218056 kb
Host smart-a1e45554-6442-4944-aec1-eb3a2b186b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082175621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1082175621
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.24932996
Short name T1029
Test name
Test status
Simulation time 284606258 ps
CPU time 2.61 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 218384 kb
Host smart-b1920ba4-ef88-4e52-bcf0-9cdc34af4a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24932996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.24932996
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2570928777
Short name T99
Test name
Test status
Simulation time 781140834 ps
CPU time 6.2 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:30 PM PDT 24
Peak memory 219196 kb
Host smart-487a6c2c-d3e0-4e28-a08f-615bdf62e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570928777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2570928777
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3347337391
Short name T276
Test name
Test status
Simulation time 2200889499 ps
CPU time 16.25 seconds
Started May 11 03:51:23 PM PDT 24
Finished May 11 03:51:40 PM PDT 24
Peak memory 214432 kb
Host smart-163aeee2-cb50-4d81-971a-c751d021f141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347337391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3347337391
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.177108416
Short name T231
Test name
Test status
Simulation time 218494702 ps
CPU time 4.55 seconds
Started May 11 03:51:24 PM PDT 24
Finished May 11 03:51:29 PM PDT 24
Peak memory 216492 kb
Host smart-db45c3b7-c11b-44b2-9fb6-7cbe98cea643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177108416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.177108416
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1182569161
Short name T965
Test name
Test status
Simulation time 106032399 ps
CPU time 4.89 seconds
Started May 11 03:51:23 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 218428 kb
Host smart-7390158a-086b-47d6-abe2-bb3814852f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182569161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1182569161
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1873804240
Short name T212
Test name
Test status
Simulation time 202652373 ps
CPU time 2.92 seconds
Started May 11 03:51:23 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 206984 kb
Host smart-9b281439-c289-4986-b3bc-75a1c127d415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873804240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1873804240
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1581641508
Short name T319
Test name
Test status
Simulation time 1610818711 ps
CPU time 4.53 seconds
Started May 11 03:51:22 PM PDT 24
Finished May 11 03:51:27 PM PDT 24
Peak memory 208884 kb
Host smart-4e28b53d-c6fa-4bbc-9f33-640edc443e21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581641508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1581641508
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3421516880
Short name T657
Test name
Test status
Simulation time 476942152 ps
CPU time 4.85 seconds
Started May 11 03:51:29 PM PDT 24
Finished May 11 03:51:35 PM PDT 24
Peak memory 208504 kb
Host smart-bab19fff-edb1-423d-a146-a94ac5698cce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421516880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3421516880
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.259382169
Short name T1039
Test name
Test status
Simulation time 223838430 ps
CPU time 3.16 seconds
Started May 11 03:51:25 PM PDT 24
Finished May 11 03:51:28 PM PDT 24
Peak memory 208284 kb
Host smart-e03c4fd3-7980-430e-82a0-a9e327223ea0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259382169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.259382169
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3068943132
Short name T377
Test name
Test status
Simulation time 92280003 ps
CPU time 3.1 seconds
Started May 11 03:51:28 PM PDT 24
Finished May 11 03:51:32 PM PDT 24
Peak memory 210080 kb
Host smart-6d49f057-9052-4101-98a9-ebc2b1c7bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068943132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3068943132
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4253122644
Short name T1046
Test name
Test status
Simulation time 118968315 ps
CPU time 2.43 seconds
Started May 11 03:51:31 PM PDT 24
Finished May 11 03:51:34 PM PDT 24
Peak memory 208448 kb
Host smart-f0f94e89-868d-4941-bdb6-144d2d4d94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253122644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4253122644
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3516780118
Short name T995
Test name
Test status
Simulation time 3006084783 ps
CPU time 74.52 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:52:48 PM PDT 24
Peak memory 222732 kb
Host smart-f7d64abc-8ef6-4a0d-b0ad-74077dbaf176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516780118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3516780118
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1427906280
Short name T744
Test name
Test status
Simulation time 241599481 ps
CPU time 8.1 seconds
Started May 11 03:51:35 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 220700 kb
Host smart-01023f32-6e48-47ce-b188-2ee868e06a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427906280 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1427906280
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3022191694
Short name T206
Test name
Test status
Simulation time 1022554318 ps
CPU time 7.27 seconds
Started May 11 03:51:22 PM PDT 24
Finished May 11 03:51:30 PM PDT 24
Peak memory 210196 kb
Host smart-8c600183-1f58-40ad-b9ea-ae9cb1621358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022191694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3022191694
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1287058878
Short name T177
Test name
Test status
Simulation time 78792536 ps
CPU time 1.46 seconds
Started May 11 03:51:34 PM PDT 24
Finished May 11 03:51:35 PM PDT 24
Peak memory 209936 kb
Host smart-4001405e-5701-4298-8086-a5906b814ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287058878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1287058878
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2648116662
Short name T714
Test name
Test status
Simulation time 10178516 ps
CPU time 0.84 seconds
Started May 11 03:51:31 PM PDT 24
Finished May 11 03:51:32 PM PDT 24
Peak memory 205928 kb
Host smart-3c6b82ea-39c0-4738-92b7-71632c76870d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648116662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2648116662
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3490824361
Short name T67
Test name
Test status
Simulation time 72750860 ps
CPU time 2.39 seconds
Started May 11 03:51:29 PM PDT 24
Finished May 11 03:51:32 PM PDT 24
Peak memory 218356 kb
Host smart-3216c36e-a15e-433c-86b5-a039b8e005ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490824361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3490824361
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3899189129
Short name T97
Test name
Test status
Simulation time 74723080 ps
CPU time 4.54 seconds
Started May 11 03:51:35 PM PDT 24
Finished May 11 03:51:40 PM PDT 24
Peak memory 220912 kb
Host smart-b4bbde15-1a19-4ed5-8c89-92c059662399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899189129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3899189129
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3157947815
Short name T914
Test name
Test status
Simulation time 2707618639 ps
CPU time 8.54 seconds
Started May 11 03:51:35 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 212100 kb
Host smart-162eee52-4353-4ee1-b65c-d83b6c7855aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157947815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3157947815
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3780225501
Short name T118
Test name
Test status
Simulation time 1530408681 ps
CPU time 3.36 seconds
Started May 11 03:51:34 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 209060 kb
Host smart-a06ac9f0-da1c-4ffa-9ff5-9ef71a5112e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780225501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3780225501
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.766721655
Short name T747
Test name
Test status
Simulation time 115350338 ps
CPU time 5.13 seconds
Started May 11 03:51:31 PM PDT 24
Finished May 11 03:51:37 PM PDT 24
Peak memory 208356 kb
Host smart-09316a42-46b1-411e-be89-0facc50a7246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766721655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.766721655
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3959764152
Short name T779
Test name
Test status
Simulation time 30880783 ps
CPU time 2.14 seconds
Started May 11 03:51:28 PM PDT 24
Finished May 11 03:51:31 PM PDT 24
Peak memory 206804 kb
Host smart-dc079b99-6cf5-43f1-ac56-83325fc91902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959764152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3959764152
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4294126097
Short name T752
Test name
Test status
Simulation time 512644276 ps
CPU time 6.34 seconds
Started May 11 03:51:31 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 207936 kb
Host smart-aceefe9d-ea38-435d-bf77-31f9db38fbdc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294126097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4294126097
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3484000880
Short name T803
Test name
Test status
Simulation time 206042973 ps
CPU time 2.81 seconds
Started May 11 03:51:29 PM PDT 24
Finished May 11 03:51:33 PM PDT 24
Peak memory 207024 kb
Host smart-c4196a22-eb5a-40c1-9a8b-7d3aac548275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484000880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3484000880
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2669615933
Short name T345
Test name
Test status
Simulation time 186085683 ps
CPU time 4.9 seconds
Started May 11 03:51:30 PM PDT 24
Finished May 11 03:51:35 PM PDT 24
Peak memory 209052 kb
Host smart-eb813c0a-4b4f-4111-b1c9-15028781b126
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669615933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2669615933
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1681826808
Short name T608
Test name
Test status
Simulation time 177032217 ps
CPU time 4.74 seconds
Started May 11 03:51:32 PM PDT 24
Finished May 11 03:51:37 PM PDT 24
Peak memory 209952 kb
Host smart-e6bc2d42-ccba-4511-9055-4a03fbc49884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681826808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1681826808
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.159319277
Short name T980
Test name
Test status
Simulation time 74413070 ps
CPU time 3.21 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:36 PM PDT 24
Peak memory 208612 kb
Host smart-8585e22e-ce3d-4975-8c93-e400fba38642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159319277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.159319277
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3439500201
Short name T257
Test name
Test status
Simulation time 493401753 ps
CPU time 5.4 seconds
Started May 11 03:51:32 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 210492 kb
Host smart-7bff2124-e8b3-4df5-bb66-d682031ef500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439500201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3439500201
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2054652433
Short name T417
Test name
Test status
Simulation time 356406750 ps
CPU time 4.73 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 222664 kb
Host smart-07986b67-c1c2-42a2-8796-42a4536015f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054652433 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2054652433
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3044585217
Short name T894
Test name
Test status
Simulation time 455624896 ps
CPU time 12.3 seconds
Started May 11 03:51:30 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 209176 kb
Host smart-41bdc737-6b89-419b-9153-ebbe55d7db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044585217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3044585217
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.965524557
Short name T946
Test name
Test status
Simulation time 201101935 ps
CPU time 3.63 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:42 PM PDT 24
Peak memory 209836 kb
Host smart-5969f18d-9ba0-4dd0-8efa-145086ec0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965524557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.965524557
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1029055515
Short name T707
Test name
Test status
Simulation time 43658268 ps
CPU time 0.82 seconds
Started May 11 03:50:18 PM PDT 24
Finished May 11 03:50:19 PM PDT 24
Peak memory 205940 kb
Host smart-53f1be34-32fb-4a62-9b45-e46fff8eada4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029055515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1029055515
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3453906864
Short name T750
Test name
Test status
Simulation time 471921162 ps
CPU time 3.34 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:20 PM PDT 24
Peak memory 210568 kb
Host smart-8a83c65e-b8f6-4c94-8a50-6adafce6c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453906864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3453906864
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3318019824
Short name T733
Test name
Test status
Simulation time 3702947216 ps
CPU time 19.83 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:36 PM PDT 24
Peak memory 218720 kb
Host smart-821b154b-d29b-4c13-a33a-8ffd876bcb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318019824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3318019824
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1841596006
Short name T102
Test name
Test status
Simulation time 779526372 ps
CPU time 3.77 seconds
Started May 11 03:50:17 PM PDT 24
Finished May 11 03:50:21 PM PDT 24
Peak memory 219252 kb
Host smart-249b8937-6e55-4e30-b83a-0252ec119774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841596006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1841596006
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.137737519
Short name T296
Test name
Test status
Simulation time 90839292 ps
CPU time 4.68 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:21 PM PDT 24
Peak memory 211416 kb
Host smart-3b5c6ce0-97c2-4d61-b196-4e3eb720721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137737519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.137737519
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.369132778
Short name T1009
Test name
Test status
Simulation time 548496611 ps
CPU time 3.22 seconds
Started May 11 03:50:17 PM PDT 24
Finished May 11 03:50:20 PM PDT 24
Peak memory 214508 kb
Host smart-d046d565-debb-4bb2-b85e-ea148985102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369132778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.369132778
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1199868470
Short name T885
Test name
Test status
Simulation time 246006552 ps
CPU time 4.16 seconds
Started May 11 03:50:18 PM PDT 24
Finished May 11 03:50:23 PM PDT 24
Peak memory 208112 kb
Host smart-1a0cec0d-d127-46fd-8cd9-bbd817733572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199868470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1199868470
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.298725611
Short name T12
Test name
Test status
Simulation time 2681680363 ps
CPU time 55.18 seconds
Started May 11 03:50:15 PM PDT 24
Finished May 11 03:51:11 PM PDT 24
Peak memory 252428 kb
Host smart-0bc0d4bc-9f2a-4840-ad7e-805200e953ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298725611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.298725611
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3501214266
Short name T135
Test name
Test status
Simulation time 203192168 ps
CPU time 2.79 seconds
Started May 11 03:50:13 PM PDT 24
Finished May 11 03:50:16 PM PDT 24
Peak memory 206820 kb
Host smart-b3743299-e94a-4261-8c6e-0d947bb116b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501214266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3501214266
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1911612769
Short name T729
Test name
Test status
Simulation time 154485098 ps
CPU time 3.65 seconds
Started May 11 03:50:11 PM PDT 24
Finished May 11 03:50:15 PM PDT 24
Peak memory 208708 kb
Host smart-a0472ed3-a35e-4cf4-825d-70f7bb3e6452
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911612769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1911612769
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1756295230
Short name T749
Test name
Test status
Simulation time 76911391 ps
CPU time 1.86 seconds
Started May 11 03:50:10 PM PDT 24
Finished May 11 03:50:13 PM PDT 24
Peak memory 206972 kb
Host smart-aa6616bc-ae31-4ff2-b18b-c0a0f4889165
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756295230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1756295230
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1894809132
Short name T1069
Test name
Test status
Simulation time 363613059 ps
CPU time 8.56 seconds
Started May 11 03:50:17 PM PDT 24
Finished May 11 03:50:26 PM PDT 24
Peak memory 208528 kb
Host smart-b6d4600d-b77e-4458-988b-c46929968835
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894809132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1894809132
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.791645108
Short name T742
Test name
Test status
Simulation time 86206075 ps
CPU time 2.76 seconds
Started May 11 03:50:19 PM PDT 24
Finished May 11 03:50:22 PM PDT 24
Peak memory 216016 kb
Host smart-a8a6ed35-9531-4b43-8d94-70c3d63776c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791645108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.791645108
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2812922180
Short name T88
Test name
Test status
Simulation time 2455147680 ps
CPU time 38.43 seconds
Started May 11 03:50:11 PM PDT 24
Finished May 11 03:50:50 PM PDT 24
Peak memory 208156 kb
Host smart-fbf71508-c86d-497f-be72-807b0ee8cb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812922180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2812922180
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2879039104
Short name T323
Test name
Test status
Simulation time 20712129985 ps
CPU time 342.1 seconds
Started May 11 03:50:18 PM PDT 24
Finished May 11 03:56:01 PM PDT 24
Peak memory 217608 kb
Host smart-2236a1ab-cf30-4122-93ac-23f058daf560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879039104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2879039104
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1464796040
Short name T732
Test name
Test status
Simulation time 177422740 ps
CPU time 3.18 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:20 PM PDT 24
Peak memory 222244 kb
Host smart-0f19cd72-80b4-42dd-9e52-b1c678e43f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464796040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1464796040
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.167500707
Short name T962
Test name
Test status
Simulation time 72770018 ps
CPU time 3.34 seconds
Started May 11 03:50:17 PM PDT 24
Finished May 11 03:50:21 PM PDT 24
Peak memory 207896 kb
Host smart-335767df-644c-4a16-a01d-763860fa3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167500707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.167500707
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3269147413
Short name T685
Test name
Test status
Simulation time 60776147 ps
CPU time 2.58 seconds
Started May 11 03:50:15 PM PDT 24
Finished May 11 03:50:18 PM PDT 24
Peak memory 209912 kb
Host smart-0c33e93c-7113-4571-8529-065e164d4943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269147413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3269147413
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1407218257
Short name T596
Test name
Test status
Simulation time 45219654 ps
CPU time 0.87 seconds
Started May 11 03:51:36 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 205904 kb
Host smart-8a7b715b-7645-4788-9a0d-d7017ebafb16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407218257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1407218257
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.467105097
Short name T979
Test name
Test status
Simulation time 364729303 ps
CPU time 10.79 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 214428 kb
Host smart-1a43f06f-e1fe-40be-ad40-b4c686bde5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467105097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.467105097
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.940815244
Short name T32
Test name
Test status
Simulation time 79039719 ps
CPU time 2.46 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:41 PM PDT 24
Peak memory 208140 kb
Host smart-a8908310-d57f-4eec-9508-faa16eb94e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940815244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.940815244
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.575788880
Short name T622
Test name
Test status
Simulation time 102302884 ps
CPU time 2.61 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:40 PM PDT 24
Peak memory 208292 kb
Host smart-e1e0f528-a4a9-4f15-aebe-dc7a67447f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575788880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.575788880
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1672550317
Short name T799
Test name
Test status
Simulation time 8962835192 ps
CPU time 54.03 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 214488 kb
Host smart-6c1a7516-97a5-47f0-b0ac-690f87d2c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672550317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1672550317
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2683516280
Short name T113
Test name
Test status
Simulation time 140692280 ps
CPU time 6.08 seconds
Started May 11 03:51:33 PM PDT 24
Finished May 11 03:51:40 PM PDT 24
Peak memory 211112 kb
Host smart-c834e14c-f501-43fd-bfc4-4f195ebd73ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683516280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2683516280
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1289720875
Short name T43
Test name
Test status
Simulation time 257791315 ps
CPU time 3.26 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:42 PM PDT 24
Peak memory 220012 kb
Host smart-0c6aa238-bd95-44cd-879d-86a0995c3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289720875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1289720875
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.510003408
Short name T90
Test name
Test status
Simulation time 374838977 ps
CPU time 3.94 seconds
Started May 11 03:51:34 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 207392 kb
Host smart-f16f5078-7b67-46dc-9b44-dcfd8ad77e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510003408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.510003408
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2916687911
Short name T832
Test name
Test status
Simulation time 146661023 ps
CPU time 3.52 seconds
Started May 11 03:51:34 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 206760 kb
Host smart-22cfb176-8abd-46b6-9a9d-4f17be68367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916687911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2916687911
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1256914589
Short name T877
Test name
Test status
Simulation time 121686797 ps
CPU time 2.39 seconds
Started May 11 03:51:36 PM PDT 24
Finished May 11 03:51:39 PM PDT 24
Peak memory 206964 kb
Host smart-a82e4cec-9571-4d16-bed5-8858bf0c0477
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256914589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1256914589
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.651596157
Short name T416
Test name
Test status
Simulation time 1154436126 ps
CPU time 8.2 seconds
Started May 11 03:51:32 PM PDT 24
Finished May 11 03:51:41 PM PDT 24
Peak memory 208940 kb
Host smart-1213d5a4-abf8-4c7d-b07c-c0897c01f7f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651596157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.651596157
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2245151885
Short name T138
Test name
Test status
Simulation time 8187135763 ps
CPU time 80.9 seconds
Started May 11 03:51:32 PM PDT 24
Finished May 11 03:52:53 PM PDT 24
Peak memory 208620 kb
Host smart-193a508c-65af-42fa-92f5-99a8b4fc0509
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245151885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2245151885
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2960116613
Short name T139
Test name
Test status
Simulation time 764412001 ps
CPU time 2.33 seconds
Started May 11 03:51:40 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 218336 kb
Host smart-b63fb9b9-be6b-4c77-a88d-eaf551bc8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960116613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2960116613
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2623897173
Short name T589
Test name
Test status
Simulation time 84371394 ps
CPU time 3.53 seconds
Started May 11 03:51:36 PM PDT 24
Finished May 11 03:51:40 PM PDT 24
Peak memory 208336 kb
Host smart-535f23f7-ab65-47e5-a81e-47865dddb523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623897173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2623897173
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2283798860
Short name T862
Test name
Test status
Simulation time 570206680 ps
CPU time 23.17 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 222688 kb
Host smart-df698d2b-a862-43b9-b361-fa654188de05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283798860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2283798860
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1480356163
Short name T227
Test name
Test status
Simulation time 137247085 ps
CPU time 7.48 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 222748 kb
Host smart-303db80c-df2a-45b7-8043-332b152df739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480356163 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1480356163
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3340205341
Short name T616
Test name
Test status
Simulation time 643567371 ps
CPU time 5.2 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 208184 kb
Host smart-f9994e3a-4dcc-4686-a4a5-821485821322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340205341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3340205341
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1736211557
Short name T56
Test name
Test status
Simulation time 538295188 ps
CPU time 11.12 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 210552 kb
Host smart-ea9fcf67-d914-40f7-a5f1-2f7ff3494a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736211557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1736211557
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4013328901
Short name T837
Test name
Test status
Simulation time 31972576 ps
CPU time 0.94 seconds
Started May 11 03:51:44 PM PDT 24
Finished May 11 03:51:45 PM PDT 24
Peak memory 206192 kb
Host smart-50630554-19c9-49a5-99ee-3cff6042cdad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013328901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4013328901
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3924487434
Short name T352
Test name
Test status
Simulation time 106709459 ps
CPU time 2.42 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:41 PM PDT 24
Peak memory 214484 kb
Host smart-3c1062ed-2b73-4d1f-b1c8-83f46dae74d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924487434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3924487434
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.451138904
Short name T858
Test name
Test status
Simulation time 266107980 ps
CPU time 4.08 seconds
Started May 11 03:51:39 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 221648 kb
Host smart-b3c4448a-a6e6-462f-b760-745d2749ea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451138904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.451138904
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1553106484
Short name T204
Test name
Test status
Simulation time 107462112 ps
CPU time 2.07 seconds
Started May 11 03:51:44 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 214396 kb
Host smart-13c74e3c-364b-4493-8eeb-3b9f42020322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553106484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1553106484
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3431625090
Short name T98
Test name
Test status
Simulation time 816694360 ps
CPU time 14.52 seconds
Started May 11 03:51:39 PM PDT 24
Finished May 11 03:51:54 PM PDT 24
Peak memory 209232 kb
Host smart-6995d66a-db4c-4bb2-80ad-ec8e60666b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431625090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3431625090
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2638603911
Short name T275
Test name
Test status
Simulation time 577296097 ps
CPU time 6.59 seconds
Started May 11 03:51:37 PM PDT 24
Finished May 11 03:51:45 PM PDT 24
Peak memory 222596 kb
Host smart-ce877a1a-bea4-49f3-bff4-39c48ca3c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638603911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2638603911
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1649259656
Short name T382
Test name
Test status
Simulation time 84073776 ps
CPU time 4.65 seconds
Started May 11 03:51:39 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 209700 kb
Host smart-3cf83c17-9d36-4d37-b4db-b255ea52441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649259656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1649259656
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1859154744
Short name T652
Test name
Test status
Simulation time 1370482527 ps
CPU time 9.41 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:51 PM PDT 24
Peak memory 208808 kb
Host smart-253124a4-fbd0-440b-9383-c3104bcdd927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859154744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1859154744
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3321634794
Short name T649
Test name
Test status
Simulation time 679674978 ps
CPU time 4.84 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 206200 kb
Host smart-c8fcbc1f-daf9-466e-a125-b40a66d1aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321634794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3321634794
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1219100856
Short name T964
Test name
Test status
Simulation time 20824989 ps
CPU time 1.82 seconds
Started May 11 03:51:35 PM PDT 24
Finished May 11 03:51:37 PM PDT 24
Peak memory 206976 kb
Host smart-d2832072-9fe4-43bb-8009-7f49ed594595
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219100856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1219100856
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3870830570
Short name T757
Test name
Test status
Simulation time 353039757 ps
CPU time 4.89 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 208648 kb
Host smart-a11227c3-eb92-45e4-a195-b927c08fd201
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870830570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3870830570
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3586527939
Short name T867
Test name
Test status
Simulation time 146541658 ps
CPU time 3.61 seconds
Started May 11 03:51:40 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 208512 kb
Host smart-f5b7a813-01ab-4734-84d3-6505e6014976
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586527939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3586527939
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.170515752
Short name T982
Test name
Test status
Simulation time 1277831695 ps
CPU time 8.83 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 218492 kb
Host smart-61a56fc2-e02e-42ae-b9a4-e34bf9bf8dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170515752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.170515752
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2808761121
Short name T215
Test name
Test status
Simulation time 252088320 ps
CPU time 7.37 seconds
Started May 11 03:51:38 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 207048 kb
Host smart-b697f2e2-211a-495e-98e4-f07057fc8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808761121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2808761121
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4122995884
Short name T321
Test name
Test status
Simulation time 833847155 ps
CPU time 21.65 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:52:03 PM PDT 24
Peak memory 222732 kb
Host smart-2d9b0722-1a6d-48de-aa14-95c4de3ebc79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122995884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4122995884
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3790102542
Short name T387
Test name
Test status
Simulation time 167057358 ps
CPU time 5.06 seconds
Started May 11 03:51:39 PM PDT 24
Finished May 11 03:51:45 PM PDT 24
Peak memory 209492 kb
Host smart-52d821c6-a202-4d75-8fe1-2f8e777bde26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790102542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3790102542
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2582299635
Short name T686
Test name
Test status
Simulation time 716595247 ps
CPU time 6.14 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:55 PM PDT 24
Peak memory 210380 kb
Host smart-b39d1e1e-7adc-4c33-908a-96aebdfd9652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582299635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2582299635
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.107776149
Short name T785
Test name
Test status
Simulation time 11684916 ps
CPU time 0.73 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:49 PM PDT 24
Peak memory 206008 kb
Host smart-9649e232-ba74-4f60-9b6f-98e800ab926d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107776149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.107776149
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1402436973
Short name T308
Test name
Test status
Simulation time 64370407 ps
CPU time 4.69 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:51:48 PM PDT 24
Peak memory 214656 kb
Host smart-45c1dd7c-c370-4527-b0c1-62aed270292e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402436973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1402436973
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1291981705
Short name T836
Test name
Test status
Simulation time 297872346 ps
CPU time 2.9 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:51:47 PM PDT 24
Peak memory 209768 kb
Host smart-c98a0a9c-2133-4e74-9d26-9954b63c4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291981705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1291981705
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3199956490
Short name T96
Test name
Test status
Simulation time 254314293 ps
CPU time 2.96 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:44 PM PDT 24
Peak memory 208604 kb
Host smart-2742209e-7e85-402d-8de1-a8def8c9af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199956490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3199956490
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.908380765
Short name T665
Test name
Test status
Simulation time 136778638 ps
CPU time 3.03 seconds
Started May 11 03:51:42 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 220508 kb
Host smart-ab117b17-ed2b-42d3-b239-ca4661a48c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908380765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.908380765
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3670886121
Short name T793
Test name
Test status
Simulation time 2947727289 ps
CPU time 19.85 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 208996 kb
Host smart-d5788abc-ce59-4e9b-9ac4-9ca9651223f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670886121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3670886121
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2409625109
Short name T804
Test name
Test status
Simulation time 236297988 ps
CPU time 3.95 seconds
Started May 11 03:51:42 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 208424 kb
Host smart-d6085bbb-a777-49d5-b2cc-41d8803c8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409625109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2409625109
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3563468666
Short name T637
Test name
Test status
Simulation time 71464291 ps
CPU time 2.49 seconds
Started May 11 03:51:43 PM PDT 24
Finished May 11 03:51:46 PM PDT 24
Peak memory 208764 kb
Host smart-2f971223-d306-4998-abe0-dbf8eaaa86d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563468666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3563468666
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1457310390
Short name T671
Test name
Test status
Simulation time 324620128 ps
CPU time 6.08 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:54 PM PDT 24
Peak memory 208600 kb
Host smart-39c21eaf-dae1-400b-a067-81a048b22509
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457310390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1457310390
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3582197105
Short name T717
Test name
Test status
Simulation time 42248975 ps
CPU time 1.58 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 207016 kb
Host smart-a641990f-140b-4d48-800a-a7b0650ba371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582197105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3582197105
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1668137025
Short name T203
Test name
Test status
Simulation time 657604493 ps
CPU time 4.84 seconds
Started May 11 03:51:42 PM PDT 24
Finished May 11 03:51:47 PM PDT 24
Peak memory 208220 kb
Host smart-22e040ac-7219-4c16-83c2-4d82a9d76d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668137025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1668137025
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3672796078
Short name T240
Test name
Test status
Simulation time 876923023 ps
CPU time 34.71 seconds
Started May 11 03:51:42 PM PDT 24
Finished May 11 03:52:17 PM PDT 24
Peak memory 222604 kb
Host smart-889343fe-9b82-4708-8c5f-bd63acba5a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672796078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3672796078
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2879202346
Short name T821
Test name
Test status
Simulation time 139399736 ps
CPU time 4.85 seconds
Started May 11 03:51:41 PM PDT 24
Finished May 11 03:51:47 PM PDT 24
Peak memory 222728 kb
Host smart-423b91d0-a658-4bad-800c-cb5746986625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879202346 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2879202346
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4252392357
Short name T748
Test name
Test status
Simulation time 302860234 ps
CPU time 4.47 seconds
Started May 11 03:51:49 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 207624 kb
Host smart-42a160c8-5761-4ee4-babe-da2f91684c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252392357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4252392357
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3948984605
Short name T776
Test name
Test status
Simulation time 217004338 ps
CPU time 5.44 seconds
Started May 11 03:51:42 PM PDT 24
Finished May 11 03:51:48 PM PDT 24
Peak memory 210736 kb
Host smart-09476ef2-48e7-4993-a40f-ac9c5fc1bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948984605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3948984605
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1086757330
Short name T580
Test name
Test status
Simulation time 19194195 ps
CPU time 0.68 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:48 PM PDT 24
Peak memory 205852 kb
Host smart-900cd214-4a7a-4e5b-a228-fd6a8da75f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086757330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1086757330
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.970406129
Short name T214
Test name
Test status
Simulation time 171740065 ps
CPU time 3.39 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 214424 kb
Host smart-543c54ae-dd61-42eb-ab23-e6f4590f840e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970406129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.970406129
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.838446604
Short name T41
Test name
Test status
Simulation time 239240761 ps
CPU time 2.02 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 214520 kb
Host smart-96a7d638-4d2d-4724-a296-d768d8aa123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838446604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.838446604
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1619605211
Short name T678
Test name
Test status
Simulation time 269378650 ps
CPU time 5.7 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 208260 kb
Host smart-120a041c-01d2-4d34-b619-5a59e1a097da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619605211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1619605211
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1896382435
Short name T906
Test name
Test status
Simulation time 1150367660 ps
CPU time 10.52 seconds
Started May 11 03:51:49 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 209492 kb
Host smart-be63763f-4ff3-4428-ae84-15ddd8b861c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896382435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1896382435
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3457801911
Short name T254
Test name
Test status
Simulation time 94023113 ps
CPU time 4.87 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 222504 kb
Host smart-0e921171-75da-441a-a7fa-8e9eb15fa77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457801911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3457801911
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2572532424
Short name T650
Test name
Test status
Simulation time 243595266 ps
CPU time 3.44 seconds
Started May 11 03:51:49 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 220048 kb
Host smart-850fb5cd-bfd8-4d51-9527-8a9cd10f4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572532424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2572532424
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2588360911
Short name T1051
Test name
Test status
Simulation time 238691600 ps
CPU time 4.81 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 206932 kb
Host smart-65d09382-f709-4f2b-9e50-097afecf01e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588360911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2588360911
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2550198703
Short name T787
Test name
Test status
Simulation time 77915660 ps
CPU time 1.78 seconds
Started May 11 03:51:46 PM PDT 24
Finished May 11 03:51:49 PM PDT 24
Peak memory 206784 kb
Host smart-1a673fcc-eaca-446a-b3bf-9e716e598bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550198703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2550198703
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2124994208
Short name T1038
Test name
Test status
Simulation time 153507481 ps
CPU time 2.43 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 207552 kb
Host smart-7bafc565-0ebc-459f-b096-c78b9a13e149
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124994208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2124994208
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.665641084
Short name T866
Test name
Test status
Simulation time 386996237 ps
CPU time 3.86 seconds
Started May 11 03:51:49 PM PDT 24
Finished May 11 03:51:54 PM PDT 24
Peak memory 208732 kb
Host smart-caff2fcd-8bd7-4bba-a2fa-cfd496cccdfc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665641084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.665641084
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3699722307
Short name T91
Test name
Test status
Simulation time 4118908160 ps
CPU time 28.26 seconds
Started May 11 03:51:46 PM PDT 24
Finished May 11 03:52:15 PM PDT 24
Peak memory 208088 kb
Host smart-29a92379-13b0-4e5b-87a8-0de1225bdd39
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699722307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3699722307
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3952266466
Short name T211
Test name
Test status
Simulation time 7023039335 ps
CPU time 21.99 seconds
Started May 11 03:51:51 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 209744 kb
Host smart-324faf1d-0255-40d2-963a-4d24a981f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952266466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3952266466
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2964402170
Short name T415
Test name
Test status
Simulation time 81827014 ps
CPU time 1.86 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:50 PM PDT 24
Peak memory 206920 kb
Host smart-03b8e686-0e55-43d2-ac52-853e2e26f257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964402170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2964402170
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2426310744
Short name T44
Test name
Test status
Simulation time 1373731563 ps
CPU time 6.35 seconds
Started May 11 03:51:50 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 222544 kb
Host smart-baaecb9f-e3e9-4de2-8755-fb76ff77d8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426310744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2426310744
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2397148877
Short name T228
Test name
Test status
Simulation time 179030027 ps
CPU time 5.14 seconds
Started May 11 03:51:47 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 220452 kb
Host smart-1264ec93-af4a-459a-bdd6-a63847f2722f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397148877 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2397148877
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2360561758
Short name T346
Test name
Test status
Simulation time 104452818 ps
CPU time 3.5 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 208064 kb
Host smart-24f12696-5ac3-4a6c-9103-eeedc50f84ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360561758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2360561758
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1830402620
Short name T50
Test name
Test status
Simulation time 42994108 ps
CPU time 1.98 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:51 PM PDT 24
Peak memory 210420 kb
Host smart-e7ea2e96-a235-4a5b-8aac-f6edae730e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830402620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1830402620
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1017031516
Short name T578
Test name
Test status
Simulation time 22060518 ps
CPU time 1.05 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 206180 kb
Host smart-f66bb539-69b6-4e07-b097-6c53eabd0b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017031516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1017031516
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3176742920
Short name T881
Test name
Test status
Simulation time 106687128 ps
CPU time 3.26 seconds
Started May 11 03:51:53 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 207324 kb
Host smart-a140978b-baa1-4a9b-afd1-ef9fd2b07073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176742920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3176742920
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.246299704
Short name T89
Test name
Test status
Simulation time 160515610 ps
CPU time 2.82 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:51:56 PM PDT 24
Peak memory 217380 kb
Host smart-620c28c3-a938-4ce9-9666-77299d36cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246299704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.246299704
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4283670864
Short name T301
Test name
Test status
Simulation time 365272962 ps
CPU time 5.11 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:51:58 PM PDT 24
Peak memory 211740 kb
Host smart-b584b3b2-3d0e-4055-a8f4-0f96445d0bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283670864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4283670864
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2758082691
Short name T875
Test name
Test status
Simulation time 175535670 ps
CPU time 2.88 seconds
Started May 11 03:51:51 PM PDT 24
Finished May 11 03:51:54 PM PDT 24
Peak memory 206244 kb
Host smart-92089835-e6cc-4207-89c5-e02e60d75112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758082691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2758082691
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3064986031
Short name T1074
Test name
Test status
Simulation time 56266599 ps
CPU time 3.76 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 218192 kb
Host smart-637fa8f4-1342-4e4c-85f8-fd17fe02997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064986031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3064986031
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1901625094
Short name T355
Test name
Test status
Simulation time 918083617 ps
CPU time 17.87 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 208028 kb
Host smart-79d976fc-9c94-41f7-bc0d-216b93f52a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901625094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1901625094
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.361335254
Short name T738
Test name
Test status
Simulation time 3217524017 ps
CPU time 8.02 seconds
Started May 11 03:51:53 PM PDT 24
Finished May 11 03:52:01 PM PDT 24
Peak memory 208028 kb
Host smart-7f45b7db-07f3-4d51-be26-122a6e283790
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361335254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.361335254
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3663059928
Short name T641
Test name
Test status
Simulation time 54319321 ps
CPU time 2.98 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:51:56 PM PDT 24
Peak memory 206980 kb
Host smart-25d50b7f-d3e6-4dd5-b693-14bbee9f0261
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663059928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3663059928
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1082686553
Short name T399
Test name
Test status
Simulation time 521101820 ps
CPU time 7.95 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 208728 kb
Host smart-c572abb4-5777-4cc9-8087-e648ce607f3f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082686553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1082686553
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.721163255
Short name T784
Test name
Test status
Simulation time 70714479 ps
CPU time 2.6 seconds
Started May 11 03:51:50 PM PDT 24
Finished May 11 03:51:53 PM PDT 24
Peak memory 216388 kb
Host smart-cecce05a-4235-44d2-89c2-fbb34f0eb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721163255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.721163255
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2314051824
Short name T726
Test name
Test status
Simulation time 221131991 ps
CPU time 3.01 seconds
Started May 11 03:51:48 PM PDT 24
Finished May 11 03:51:52 PM PDT 24
Peak memory 208628 kb
Host smart-23225c69-fcc0-4667-9177-a56e484cd42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314051824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2314051824
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1855975707
Short name T592
Test name
Test status
Simulation time 1561571620 ps
CPU time 16.21 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 209268 kb
Host smart-76f4bfb8-df6a-44e4-a494-23a91d49c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855975707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1855975707
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1800157267
Short name T1045
Test name
Test status
Simulation time 476757019 ps
CPU time 4.44 seconds
Started May 11 03:51:51 PM PDT 24
Finished May 11 03:51:56 PM PDT 24
Peak memory 210608 kb
Host smart-36491a56-3b33-4c8e-9ae2-8ff028eb0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800157267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1800157267
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2639896072
Short name T445
Test name
Test status
Simulation time 16847463 ps
CPU time 0.94 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 206160 kb
Host smart-98859c4f-6e0a-429a-b08a-bc1afea37f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639896072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2639896072
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3316279993
Short name T287
Test name
Test status
Simulation time 661854278 ps
CPU time 4.44 seconds
Started May 11 03:51:50 PM PDT 24
Finished May 11 03:51:55 PM PDT 24
Peak memory 214612 kb
Host smart-3baaa842-e5c1-4c4b-896f-738efe8e30d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316279993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3316279993
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3091264241
Short name T956
Test name
Test status
Simulation time 70889549 ps
CPU time 2.61 seconds
Started May 11 03:51:54 PM PDT 24
Finished May 11 03:51:57 PM PDT 24
Peak memory 209628 kb
Host smart-fd6f81ef-dfb9-4b1a-92d3-60a64f9d9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091264241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3091264241
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1226397985
Short name T334
Test name
Test status
Simulation time 48385187 ps
CPU time 3.03 seconds
Started May 11 03:51:52 PM PDT 24
Finished May 11 03:51:56 PM PDT 24
Peak memory 218228 kb
Host smart-c43aafa3-8536-4819-afc6-00e0c6042b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226397985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1226397985
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3584719931
Short name T696
Test name
Test status
Simulation time 184730971 ps
CPU time 4.94 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 209148 kb
Host smart-e5488acb-d6b5-497e-991f-6949f632a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584719931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3584719931
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.549297915
Short name T263
Test name
Test status
Simulation time 204127250 ps
CPU time 3.81 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 214524 kb
Host smart-333efec8-6080-4b5f-a2d6-b7a66e71acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549297915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.549297915
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1871186466
Short name T949
Test name
Test status
Simulation time 899424944 ps
CPU time 9.61 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:07 PM PDT 24
Peak memory 207156 kb
Host smart-ffc71cca-eaf7-4b98-934c-b2c4e5e929a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871186466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1871186466
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.849880034
Short name T594
Test name
Test status
Simulation time 1921644012 ps
CPU time 51.44 seconds
Started May 11 03:51:51 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 208528 kb
Host smart-75d1fbf1-4f0a-44a8-8222-3bc45961a7a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849880034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.849880034
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2518341184
Short name T675
Test name
Test status
Simulation time 39347942 ps
CPU time 2.71 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 208568 kb
Host smart-545bbca1-e2ca-44ce-a12a-7b728793c120
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518341184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2518341184
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4280680767
Short name T610
Test name
Test status
Simulation time 7121803109 ps
CPU time 76.4 seconds
Started May 11 03:51:50 PM PDT 24
Finished May 11 03:53:07 PM PDT 24
Peak memory 208804 kb
Host smart-1effe24e-5a7c-4e2a-9a7d-3f36aa9ee936
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280680767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4280680767
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1041655025
Short name T973
Test name
Test status
Simulation time 38048035 ps
CPU time 1.63 seconds
Started May 11 03:51:58 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 206996 kb
Host smart-ba1d1711-3803-4ea6-88bc-a598fab106fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041655025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1041655025
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2224927228
Short name T1015
Test name
Test status
Simulation time 219698280 ps
CPU time 5.71 seconds
Started May 11 03:51:53 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 206716 kb
Host smart-7a46d840-1a6a-426d-81e5-17f43eeefb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224927228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2224927228
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3462177048
Short name T901
Test name
Test status
Simulation time 680028451 ps
CPU time 4.61 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 222696 kb
Host smart-a8553ea9-fc48-4082-8791-92eeea29fa28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462177048 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3462177048
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2125803935
Short name T857
Test name
Test status
Simulation time 528098109 ps
CPU time 10.08 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:08 PM PDT 24
Peak memory 208308 kb
Host smart-9e59ff73-002b-4ef8-83b5-5fea7bced066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125803935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2125803935
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.571966816
Short name T37
Test name
Test status
Simulation time 65000528 ps
CPU time 2.03 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 210244 kb
Host smart-347d12c2-4eea-496f-a2a2-da75ddd7b01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571966816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.571966816
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1074475755
Short name T634
Test name
Test status
Simulation time 14240734 ps
CPU time 0.75 seconds
Started May 11 03:52:03 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 205872 kb
Host smart-4ff08381-acda-4708-8a13-35bb4b6c242a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074475755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1074475755
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1747714674
Short name T266
Test name
Test status
Simulation time 242181339 ps
CPU time 3.86 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:01 PM PDT 24
Peak memory 215340 kb
Host smart-4e58857f-65dc-4986-a3eb-8d0196b4a862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747714674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1747714674
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1843654739
Short name T1063
Test name
Test status
Simulation time 72489706 ps
CPU time 3.32 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 218552 kb
Host smart-7bc714e3-bb08-4944-bde2-8563a28096a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843654739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1843654739
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.41883250
Short name T83
Test name
Test status
Simulation time 65790002 ps
CPU time 2.6 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 221492 kb
Host smart-b22abe8c-2693-4009-bf07-31aece445f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41883250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.41883250
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1410508075
Short name T960
Test name
Test status
Simulation time 67943403 ps
CPU time 4.51 seconds
Started May 11 03:52:01 PM PDT 24
Finished May 11 03:52:06 PM PDT 24
Peak memory 210300 kb
Host smart-307ccb2e-35a1-4a6d-9835-ae576251ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410508075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1410508075
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1039412550
Short name T720
Test name
Test status
Simulation time 162465120 ps
CPU time 4.35 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:01 PM PDT 24
Peak memory 222556 kb
Host smart-acd24b55-67e7-4658-a976-4c9747418a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039412550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1039412550
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1071907435
Short name T796
Test name
Test status
Simulation time 236859149 ps
CPU time 5.49 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:52:01 PM PDT 24
Peak memory 209904 kb
Host smart-2ac55e14-71a4-4b57-a7b5-658edafb6067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071907435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1071907435
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2339099781
Short name T251
Test name
Test status
Simulation time 302653071 ps
CPU time 2.82 seconds
Started May 11 03:51:53 PM PDT 24
Finished May 11 03:51:56 PM PDT 24
Peak memory 206856 kb
Host smart-2b78bc7d-834b-43ea-bda6-b35d7ace4040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339099781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2339099781
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1111175998
Short name T1016
Test name
Test status
Simulation time 1065265717 ps
CPU time 25.96 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 208052 kb
Host smart-fe7d5bc2-d77c-4c9f-8f47-7ba31ea90825
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111175998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1111175998
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2473330816
Short name T789
Test name
Test status
Simulation time 3187546706 ps
CPU time 34.54 seconds
Started May 11 03:51:55 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 208608 kb
Host smart-cfa72a3f-136e-4f42-89d9-2ced8a8fd4fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473330816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2473330816
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4194383580
Short name T1018
Test name
Test status
Simulation time 79876734 ps
CPU time 3.07 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:52:00 PM PDT 24
Peak memory 209024 kb
Host smart-f7b0534e-cb5e-49e5-a18d-2b0b836a6b0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194383580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4194383580
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2588886583
Short name T1052
Test name
Test status
Simulation time 152793208 ps
CPU time 4.53 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 215616 kb
Host smart-23ea089e-73ce-43bf-896b-b5d1dbdf2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588886583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2588886583
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3584410368
Short name T741
Test name
Test status
Simulation time 55178624 ps
CPU time 2.89 seconds
Started May 11 03:51:56 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 206900 kb
Host smart-cf3e94c0-e9ed-491c-b8ce-20ee13a42300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584410368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3584410368
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2914816193
Short name T232
Test name
Test status
Simulation time 2205035292 ps
CPU time 22.67 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 219872 kb
Host smart-ce7787b1-16d6-4785-9add-6f31e1a311c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914816193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2914816193
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2235547044
Short name T45
Test name
Test status
Simulation time 1010349640 ps
CPU time 9.41 seconds
Started May 11 03:52:03 PM PDT 24
Finished May 11 03:52:13 PM PDT 24
Peak memory 222748 kb
Host smart-dd2f6bf5-22b4-4a93-989f-cbce5362691a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235547044 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2235547044
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4012971181
Short name T306
Test name
Test status
Simulation time 86369176 ps
CPU time 4.44 seconds
Started May 11 03:51:57 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 208448 kb
Host smart-ab34589d-6eae-43c6-a498-e0fda91ddc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012971181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4012971181
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3685894805
Short name T820
Test name
Test status
Simulation time 821301453 ps
CPU time 4.2 seconds
Started May 11 03:52:02 PM PDT 24
Finished May 11 03:52:06 PM PDT 24
Peak memory 210628 kb
Host smart-dcb33951-6b1b-4b1c-b2b5-2e3888eca0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685894805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3685894805
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1718855163
Short name T1061
Test name
Test status
Simulation time 12595490 ps
CPU time 0.93 seconds
Started May 11 03:52:05 PM PDT 24
Finished May 11 03:52:06 PM PDT 24
Peak memory 205956 kb
Host smart-73d408a2-1c82-41d1-8913-88d83ca71070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718855163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1718855163
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4220209032
Short name T311
Test name
Test status
Simulation time 203435371 ps
CPU time 10.82 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 214436 kb
Host smart-d2e291e6-3fd8-46b5-9529-f8846fd145d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220209032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4220209032
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.388321424
Short name T961
Test name
Test status
Simulation time 659601915 ps
CPU time 5.76 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:06 PM PDT 24
Peak memory 217512 kb
Host smart-01679365-a222-42f2-a911-3c9e9c40e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388321424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.388321424
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3475108452
Short name T1048
Test name
Test status
Simulation time 902531163 ps
CPU time 17.89 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 208396 kb
Host smart-79365885-3fc7-4732-9351-61e75da8e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475108452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3475108452
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3544253712
Short name T331
Test name
Test status
Simulation time 298895000 ps
CPU time 3.53 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 208556 kb
Host smart-e3cd3f89-21bc-4aec-a6f6-896a527bedda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544253712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3544253712
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.656710028
Short name T297
Test name
Test status
Simulation time 183869591 ps
CPU time 7.38 seconds
Started May 11 03:52:03 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 222564 kb
Host smart-2b4d25a3-fc98-4f3e-99d3-99bfa2fbb970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656710028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.656710028
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1758427562
Short name T702
Test name
Test status
Simulation time 112602656 ps
CPU time 2.98 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:03 PM PDT 24
Peak memory 216736 kb
Host smart-96df9c3f-fdd6-4d79-aa68-0eb3fc5e34f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758427562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1758427562
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.894766346
Short name T869
Test name
Test status
Simulation time 344304484 ps
CPU time 4.7 seconds
Started May 11 03:51:59 PM PDT 24
Finished May 11 03:52:04 PM PDT 24
Peak memory 207584 kb
Host smart-fe1576f5-e17c-4bd3-a7f8-8d9b94a60d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894766346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.894766346
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4273851799
Short name T213
Test name
Test status
Simulation time 189498543 ps
CPU time 7.27 seconds
Started May 11 03:52:02 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 208532 kb
Host smart-5d6798f3-6035-4dad-ac49-02849f6c0356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273851799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4273851799
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2802978099
Short name T883
Test name
Test status
Simulation time 125462298 ps
CPU time 4.92 seconds
Started May 11 03:52:03 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 208696 kb
Host smart-a2b09dff-937f-4897-9210-a677de953019
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802978099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2802978099
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1680078721
Short name T792
Test name
Test status
Simulation time 119466883 ps
CPU time 2.38 seconds
Started May 11 03:52:01 PM PDT 24
Finished May 11 03:52:03 PM PDT 24
Peak memory 206920 kb
Host smart-8627605c-023d-4b40-8fae-05f308678a0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680078721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1680078721
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3335332046
Short name T830
Test name
Test status
Simulation time 32959806 ps
CPU time 2.47 seconds
Started May 11 03:52:00 PM PDT 24
Finished May 11 03:52:03 PM PDT 24
Peak memory 206968 kb
Host smart-5863f611-d97c-460f-989c-7d18b11c1adb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335332046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3335332046
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1355430959
Short name T708
Test name
Test status
Simulation time 176050383 ps
CPU time 3.62 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 209836 kb
Host smart-2ef8d966-7204-4dd1-8887-d2090ff23ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355430959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1355430959
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1347290744
Short name T636
Test name
Test status
Simulation time 61110349 ps
CPU time 2.27 seconds
Started May 11 03:51:59 PM PDT 24
Finished May 11 03:52:02 PM PDT 24
Peak memory 206908 kb
Host smart-06b6023b-de3a-4fb8-8e47-d755ccc6eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347290744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1347290744
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2812141496
Short name T706
Test name
Test status
Simulation time 318394216 ps
CPU time 6.39 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 220152 kb
Host smart-aa2face1-55cd-454e-8c0f-5d0878160c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812141496 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2812141496
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.451787519
Short name T626
Test name
Test status
Simulation time 374055842 ps
CPU time 5.08 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 218496 kb
Host smart-61f6366d-7588-461b-99d9-b6a52b98ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451787519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.451787519
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3970800884
Short name T598
Test name
Test status
Simulation time 45623334 ps
CPU time 2.38 seconds
Started May 11 03:52:03 PM PDT 24
Finished May 11 03:52:06 PM PDT 24
Peak memory 209972 kb
Host smart-b67208bb-0842-4b6a-a6d3-09b1f03f7f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970800884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3970800884
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1946994813
Short name T646
Test name
Test status
Simulation time 14233783 ps
CPU time 0.85 seconds
Started May 11 03:52:08 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 206012 kb
Host smart-5ee05561-37be-4911-aecf-05bc3808c509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946994813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1946994813
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3321920035
Short name T430
Test name
Test status
Simulation time 108942394 ps
CPU time 2.54 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:07 PM PDT 24
Peak memory 215416 kb
Host smart-6d6a3557-4ea5-416f-999b-cf4032c36bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321920035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3321920035
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3857300592
Short name T1072
Test name
Test status
Simulation time 676458194 ps
CPU time 19.39 seconds
Started May 11 03:52:07 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 222912 kb
Host smart-5474e83d-4b79-433b-8783-bf8f8ac78118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857300592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3857300592
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.298248578
Short name T117
Test name
Test status
Simulation time 28934132 ps
CPU time 2.01 seconds
Started May 11 03:52:07 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 214508 kb
Host smart-d4800c22-b65c-49a4-91e4-eddfc8d0be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298248578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.298248578
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.98897099
Short name T853
Test name
Test status
Simulation time 1393566366 ps
CPU time 32.26 seconds
Started May 11 03:52:05 PM PDT 24
Finished May 11 03:52:38 PM PDT 24
Peak memory 214480 kb
Host smart-94f8de2b-3dda-4596-8a46-5a9b1ec14b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98897099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.98897099
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3697809864
Short name T699
Test name
Test status
Simulation time 89344211 ps
CPU time 2.89 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:08 PM PDT 24
Peak memory 208776 kb
Host smart-89e9a018-42e5-4f64-9452-dfce08349907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697809864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3697809864
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.371598149
Short name T957
Test name
Test status
Simulation time 187271413 ps
CPU time 4.43 seconds
Started May 11 03:52:05 PM PDT 24
Finished May 11 03:52:10 PM PDT 24
Peak memory 218368 kb
Host smart-5b8caa76-a430-4c39-bf8f-6b714da3da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371598149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.371598149
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1028313794
Short name T305
Test name
Test status
Simulation time 351804997 ps
CPU time 4.46 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 206888 kb
Host smart-8a794345-4240-4bb9-bbe6-a95fce528c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028313794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1028313794
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1691464061
Short name T780
Test name
Test status
Simulation time 928251998 ps
CPU time 5.49 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 208748 kb
Host smart-ce45cb9e-24ba-4a70-a9d5-4a46d8cf984a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691464061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1691464061
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2808673091
Short name T624
Test name
Test status
Simulation time 1149934552 ps
CPU time 6.63 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 208732 kb
Host smart-0dca21eb-fb21-4a71-aa77-809381e34b63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808673091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2808673091
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4234474256
Short name T693
Test name
Test status
Simulation time 23569282 ps
CPU time 1.92 seconds
Started May 11 03:52:06 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 208740 kb
Host smart-81c3375c-e1e8-4b67-88f9-8ce055a68cc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234474256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4234474256
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2869238564
Short name T942
Test name
Test status
Simulation time 27920686 ps
CPU time 2.17 seconds
Started May 11 03:52:09 PM PDT 24
Finished May 11 03:52:11 PM PDT 24
Peak memory 214456 kb
Host smart-4b040f32-d85b-4196-9252-9b6623343d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869238564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2869238564
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.161894692
Short name T772
Test name
Test status
Simulation time 435207563 ps
CPU time 3.02 seconds
Started May 11 03:52:05 PM PDT 24
Finished May 11 03:52:09 PM PDT 24
Peak memory 208464 kb
Host smart-aa567a63-4862-4f8e-8869-2343e615ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161894692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.161894692
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1729919296
Short name T424
Test name
Test status
Simulation time 61039637 ps
CPU time 3.92 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:52:15 PM PDT 24
Peak memory 220068 kb
Host smart-fe806bfa-10eb-482c-bb9a-01dc9beeb77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729919296 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1729919296
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3818207858
Short name T788
Test name
Test status
Simulation time 585238795 ps
CPU time 19.4 seconds
Started May 11 03:52:04 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 214472 kb
Host smart-d63a6e97-1177-4a9e-be0b-0122f199f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818207858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3818207858
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3655107568
Short name T683
Test name
Test status
Simulation time 123299149 ps
CPU time 2.6 seconds
Started May 11 03:52:11 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 210000 kb
Host smart-b1634336-2f45-4a09-9e83-c118dcc03c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655107568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3655107568
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3048551954
Short name T755
Test name
Test status
Simulation time 31709757 ps
CPU time 0.72 seconds
Started May 11 03:52:13 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 205976 kb
Host smart-b2a7dec9-a3f8-435d-9fd0-d9286f9c9207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048551954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3048551954
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1292609163
Short name T356
Test name
Test status
Simulation time 837588005 ps
CPU time 3.99 seconds
Started May 11 03:52:09 PM PDT 24
Finished May 11 03:52:13 PM PDT 24
Peak memory 214568 kb
Host smart-f5ddc7f6-1452-4a7c-af5d-9af634b8e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292609163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1292609163
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1067014310
Short name T910
Test name
Test status
Simulation time 67104315 ps
CPU time 2.84 seconds
Started May 11 03:52:09 PM PDT 24
Finished May 11 03:52:12 PM PDT 24
Peak memory 209540 kb
Host smart-23406610-b0e9-4afa-8acc-3ddd141dcb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067014310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1067014310
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2016633501
Short name T668
Test name
Test status
Simulation time 77682398 ps
CPU time 3.56 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 207916 kb
Host smart-15359af9-2cfc-4601-b5b2-6f30ff54fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016633501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2016633501
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2120762808
Short name T383
Test name
Test status
Simulation time 32175533 ps
CPU time 2.14 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:52:13 PM PDT 24
Peak memory 208436 kb
Host smart-0184f89e-ee59-46ef-be22-7c94967df196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120762808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2120762808
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2136961265
Short name T937
Test name
Test status
Simulation time 60054062 ps
CPU time 3.33 seconds
Started May 11 03:52:08 PM PDT 24
Finished May 11 03:52:12 PM PDT 24
Peak memory 207052 kb
Host smart-27a33fad-fee7-4e3e-b5c8-de30e2732aae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136961265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2136961265
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3434370025
Short name T737
Test name
Test status
Simulation time 454977854 ps
CPU time 8.9 seconds
Started May 11 03:52:08 PM PDT 24
Finished May 11 03:52:17 PM PDT 24
Peak memory 208592 kb
Host smart-3e41697e-2778-4d04-9905-3d6e455cb4d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434370025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3434370025
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.320229029
Short name T681
Test name
Test status
Simulation time 613963690 ps
CPU time 6.2 seconds
Started May 11 03:52:09 PM PDT 24
Finished May 11 03:52:16 PM PDT 24
Peak memory 208720 kb
Host smart-b08f14c3-8b70-41e8-932a-70a9715019d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320229029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.320229029
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2742362565
Short name T878
Test name
Test status
Simulation time 78876032 ps
CPU time 3.29 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 209096 kb
Host smart-dd4a5875-6b63-470c-ad5c-0e537767c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742362565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2742362565
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1575144503
Short name T579
Test name
Test status
Simulation time 306944389 ps
CPU time 3.55 seconds
Started May 11 03:52:08 PM PDT 24
Finished May 11 03:52:12 PM PDT 24
Peak memory 206932 kb
Host smart-cd77f069-9f75-433c-960a-64c3678a8bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575144503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1575144503
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1729224002
Short name T711
Test name
Test status
Simulation time 237181705 ps
CPU time 6.3 seconds
Started May 11 03:52:13 PM PDT 24
Finished May 11 03:52:20 PM PDT 24
Peak memory 214528 kb
Host smart-3737c7cb-0b57-4a4e-816e-91075844219f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729224002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1729224002
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2446926171
Short name T801
Test name
Test status
Simulation time 376982633 ps
CPU time 4.36 seconds
Started May 11 03:52:10 PM PDT 24
Finished May 11 03:52:14 PM PDT 24
Peak memory 207308 kb
Host smart-45fb4982-01c4-4248-aa30-143c8eac2d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446926171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2446926171
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4106120922
Short name T643
Test name
Test status
Simulation time 611770092 ps
CPU time 2.27 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:20 PM PDT 24
Peak memory 210232 kb
Host smart-97831249-ac4c-41ef-af53-7eb336aae1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106120922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.4106120922
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.525974768
Short name T818
Test name
Test status
Simulation time 43658550 ps
CPU time 0.76 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:23 PM PDT 24
Peak memory 205960 kb
Host smart-2f419b61-f33a-4112-b2e8-420500cb1b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525974768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.525974768
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1897637729
Short name T245
Test name
Test status
Simulation time 35043722 ps
CPU time 2.85 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:25 PM PDT 24
Peak memory 214504 kb
Host smart-9265ae41-5fcb-40db-a0b5-dd9b921f2200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1897637729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1897637729
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1221686247
Short name T935
Test name
Test status
Simulation time 817425267 ps
CPU time 4.34 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:27 PM PDT 24
Peak memory 218648 kb
Host smart-2519a525-28c6-4b0b-bca7-462db3cd7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221686247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1221686247
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4019861092
Short name T255
Test name
Test status
Simulation time 137784560 ps
CPU time 4.24 seconds
Started May 11 03:50:23 PM PDT 24
Finished May 11 03:50:27 PM PDT 24
Peak memory 210876 kb
Host smart-253db67d-b630-417d-a19b-443c12c9b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019861092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4019861092
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.3136263363
Short name T756
Test name
Test status
Simulation time 176144582 ps
CPU time 5.6 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:28 PM PDT 24
Peak memory 207048 kb
Host smart-e4fb7d9c-d919-4aed-866a-248d646bb341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136263363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3136263363
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.948007181
Short name T42
Test name
Test status
Simulation time 3958511055 ps
CPU time 72.01 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:51:38 PM PDT 24
Peak memory 234872 kb
Host smart-4389e4ca-782f-4be0-8929-dff46c361db1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948007181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.948007181
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1165868091
Short name T193
Test name
Test status
Simulation time 144260761 ps
CPU time 3.45 seconds
Started May 11 03:50:18 PM PDT 24
Finished May 11 03:50:22 PM PDT 24
Peak memory 208916 kb
Host smart-470c7689-d143-4c7e-9900-a1a7895c83de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165868091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1165868091
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.497832179
Short name T606
Test name
Test status
Simulation time 197910122 ps
CPU time 2.69 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:19 PM PDT 24
Peak memory 207028 kb
Host smart-09099f80-a242-4b78-b022-a060a0b911d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497832179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.497832179
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1320911996
Short name T841
Test name
Test status
Simulation time 2067238311 ps
CPU time 4.13 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:21 PM PDT 24
Peak memory 206860 kb
Host smart-3d84deb6-d616-4bf7-8e7a-9a527ac95ce4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320911996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1320911996
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.406591809
Short name T210
Test name
Test status
Simulation time 81088779 ps
CPU time 3.53 seconds
Started May 11 03:50:25 PM PDT 24
Finished May 11 03:50:28 PM PDT 24
Peak memory 208828 kb
Host smart-c4442581-ddc8-4a7b-aa42-71e97de1bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406591809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.406591809
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1685521308
Short name T728
Test name
Test status
Simulation time 60464251 ps
CPU time 2.86 seconds
Started May 11 03:50:16 PM PDT 24
Finished May 11 03:50:20 PM PDT 24
Peak memory 206884 kb
Host smart-52df0ebc-a12d-4206-af8a-7a30a60e24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685521308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1685521308
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1347264834
Short name T943
Test name
Test status
Simulation time 3577087938 ps
CPU time 33.86 seconds
Started May 11 03:50:21 PM PDT 24
Finished May 11 03:50:55 PM PDT 24
Peak memory 222716 kb
Host smart-951a58f4-d73b-4789-a706-93d9bbab513b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347264834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1347264834
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1829347748
Short name T304
Test name
Test status
Simulation time 1326857979 ps
CPU time 14.39 seconds
Started May 11 03:50:23 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 218536 kb
Host smart-14a79103-444e-4a5b-befd-bbd68ee0d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829347748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1829347748
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1576574031
Short name T53
Test name
Test status
Simulation time 60934336 ps
CPU time 2.62 seconds
Started May 11 03:50:21 PM PDT 24
Finished May 11 03:50:24 PM PDT 24
Peak memory 210028 kb
Host smart-0b821ccd-8053-4cfa-a6ad-9f69d6540694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576574031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1576574031
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2835601552
Short name T724
Test name
Test status
Simulation time 43268278 ps
CPU time 0.73 seconds
Started May 11 03:52:18 PM PDT 24
Finished May 11 03:52:19 PM PDT 24
Peak memory 206004 kb
Host smart-145e7826-0952-429c-9eb0-04c5cc3488f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835601552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2835601552
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.893143331
Short name T396
Test name
Test status
Simulation time 382858175 ps
CPU time 4.59 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 215564 kb
Host smart-9de7c52a-386c-46c5-977e-1ecd24b7ed15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893143331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.893143331
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1096230804
Short name T988
Test name
Test status
Simulation time 217399833 ps
CPU time 1.9 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 208096 kb
Host smart-72190711-ff28-41fb-b4a4-3a2495e78171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096230804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1096230804
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3752186228
Short name T405
Test name
Test status
Simulation time 331023206 ps
CPU time 3.78 seconds
Started May 11 03:52:15 PM PDT 24
Finished May 11 03:52:19 PM PDT 24
Peak memory 209236 kb
Host smart-dc82e56e-23c2-4ff3-a595-a50a97b69a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752186228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3752186228
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.838833071
Short name T390
Test name
Test status
Simulation time 8818754226 ps
CPU time 60.89 seconds
Started May 11 03:52:14 PM PDT 24
Finished May 11 03:53:15 PM PDT 24
Peak memory 225592 kb
Host smart-86b83579-2b2d-4b88-aa97-bdbb2ef38e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838833071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.838833071
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4103899033
Short name T57
Test name
Test status
Simulation time 77175518 ps
CPU time 2.68 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:21 PM PDT 24
Peak memory 216688 kb
Host smart-5896f3b2-3156-4d6a-a239-3cfff5fcd7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103899033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4103899033
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3603389212
Short name T771
Test name
Test status
Simulation time 408643974 ps
CPU time 13.81 seconds
Started May 11 03:52:13 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 214524 kb
Host smart-78791084-665b-441f-9b06-d00994523797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603389212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3603389212
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3971425036
Short name T833
Test name
Test status
Simulation time 224698552 ps
CPU time 5.63 seconds
Started May 11 03:52:16 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 208728 kb
Host smart-27253c99-d17b-43f0-898e-9c14f241ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971425036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3971425036
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1467284819
Short name T764
Test name
Test status
Simulation time 71655726 ps
CPU time 2.44 seconds
Started May 11 03:52:15 PM PDT 24
Finished May 11 03:52:18 PM PDT 24
Peak memory 206932 kb
Host smart-e0edb6b3-b0f2-406f-a7b8-0ee3dbaa3531
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467284819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1467284819
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3337530705
Short name T607
Test name
Test status
Simulation time 83679038 ps
CPU time 1.9 seconds
Started May 11 03:52:14 PM PDT 24
Finished May 11 03:52:16 PM PDT 24
Peak memory 207080 kb
Host smart-6c7de1f5-81cf-4296-8cae-806dc45955b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337530705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3337530705
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.379410270
Short name T625
Test name
Test status
Simulation time 458929135 ps
CPU time 5.65 seconds
Started May 11 03:52:13 PM PDT 24
Finished May 11 03:52:20 PM PDT 24
Peak memory 207004 kb
Host smart-4e2fdc77-1ce0-48d9-80b1-c914564b0eab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379410270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.379410270
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1259995202
Short name T412
Test name
Test status
Simulation time 498928211 ps
CPU time 5.11 seconds
Started May 11 03:52:12 PM PDT 24
Finished May 11 03:52:17 PM PDT 24
Peak memory 209904 kb
Host smart-cb3a98b7-9218-4668-b9f2-cf1360d294c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259995202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1259995202
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.892634791
Short name T1042
Test name
Test status
Simulation time 676882443 ps
CPU time 14.26 seconds
Started May 11 03:52:12 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 207860 kb
Host smart-2c248e94-c385-4d60-930d-5faa8cf7df22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892634791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.892634791
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1563114815
Short name T292
Test name
Test status
Simulation time 210084985 ps
CPU time 5.91 seconds
Started May 11 03:52:16 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 209960 kb
Host smart-bb48cb33-d4cd-47db-a950-f13e0563d4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563114815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1563114815
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1137370027
Short name T882
Test name
Test status
Simulation time 58492951 ps
CPU time 1.29 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:18 PM PDT 24
Peak memory 209580 kb
Host smart-c2e765f2-08a5-421a-81ba-564075cad0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137370027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1137370027
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2055512536
Short name T727
Test name
Test status
Simulation time 13469334 ps
CPU time 0.8 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:21 PM PDT 24
Peak memory 205864 kb
Host smart-4af6aad8-fdaa-4d7a-a2d8-c0ff4e93eb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055512536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2055512536
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2103163449
Short name T851
Test name
Test status
Simulation time 428718700 ps
CPU time 2.27 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:19 PM PDT 24
Peak memory 221448 kb
Host smart-22549438-7cdb-4199-b33b-0fa81f0d25d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103163449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2103163449
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.827939399
Short name T986
Test name
Test status
Simulation time 39386870 ps
CPU time 1.61 seconds
Started May 11 03:52:16 PM PDT 24
Finished May 11 03:52:18 PM PDT 24
Peak memory 207808 kb
Host smart-a60639ab-62cd-4572-848d-b6fc7ec0d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827939399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.827939399
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3823579677
Short name T959
Test name
Test status
Simulation time 611356964 ps
CPU time 8.4 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 214568 kb
Host smart-f6779c16-6c46-4727-bf85-e92ba703e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823579677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3823579677
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1566103409
Short name T277
Test name
Test status
Simulation time 593595027 ps
CPU time 5.5 seconds
Started May 11 03:52:23 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 214420 kb
Host smart-6bac1f42-41d8-482c-b29c-9fb7573d6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566103409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1566103409
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.476376759
Short name T998
Test name
Test status
Simulation time 799665177 ps
CPU time 4.72 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 215140 kb
Host smart-7f6ba759-afbc-4c2f-bc34-de804b5ed7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476376759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.476376759
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2019387269
Short name T893
Test name
Test status
Simulation time 145586055 ps
CPU time 2.98 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 208052 kb
Host smart-b286d370-fd05-466e-a456-fbe3f01cf1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019387269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2019387269
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.547331895
Short name T921
Test name
Test status
Simulation time 22986721 ps
CPU time 1.99 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:21 PM PDT 24
Peak memory 207408 kb
Host smart-99e05f9b-e841-43ab-9d7f-f82969bce242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547331895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.547331895
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3476126206
Short name T994
Test name
Test status
Simulation time 2551296274 ps
CPU time 17.82 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:37 PM PDT 24
Peak memory 208668 kb
Host smart-a4c9cafc-e262-4a63-bbc8-03b9b0f45cd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476126206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3476126206
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2839203939
Short name T754
Test name
Test status
Simulation time 21959758 ps
CPU time 1.87 seconds
Started May 11 03:52:20 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 206864 kb
Host smart-87b6a0fb-ac1a-4437-9a2b-a38ebbcb2736
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839203939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2839203939
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4251572919
Short name T633
Test name
Test status
Simulation time 286175920 ps
CPU time 7.15 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 207912 kb
Host smart-e943c735-ede7-4777-9ac9-b519ce483b96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251572919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4251572919
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3801609994
Short name T847
Test name
Test status
Simulation time 57290172 ps
CPU time 2.91 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 210128 kb
Host smart-8993280f-1d72-4291-a7f5-de08e072e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801609994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3801609994
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3374121722
Short name T651
Test name
Test status
Simulation time 130614389 ps
CPU time 2.41 seconds
Started May 11 03:52:19 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 206764 kb
Host smart-13204063-56f1-4c5c-9d81-78f91a5b142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374121722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3374121722
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2858409645
Short name T992
Test name
Test status
Simulation time 208714161 ps
CPU time 4.67 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 210572 kb
Host smart-f27258e5-ea91-43bd-a40c-9e1d3682af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858409645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2858409645
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3293866500
Short name T585
Test name
Test status
Simulation time 63623147 ps
CPU time 1.31 seconds
Started May 11 03:52:16 PM PDT 24
Finished May 11 03:52:18 PM PDT 24
Peak memory 210056 kb
Host smart-80393b98-ae59-4ca1-8bfd-94aae5346911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293866500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3293866500
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3566760138
Short name T107
Test name
Test status
Simulation time 65762182 ps
CPU time 0.82 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 205976 kb
Host smart-7d93a546-ddf8-47b1-83c0-c75b0d37cac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566760138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3566760138
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.163638718
Short name T441
Test name
Test status
Simulation time 82013290 ps
CPU time 4.04 seconds
Started May 11 03:52:25 PM PDT 24
Finished May 11 03:52:30 PM PDT 24
Peak memory 214464 kb
Host smart-eeff74a0-37f8-4ba0-8103-f998753f9587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163638718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.163638718
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4232531683
Short name T20
Test name
Test status
Simulation time 32072230 ps
CPU time 2.06 seconds
Started May 11 03:52:23 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 215864 kb
Host smart-55bbb38a-021e-4b87-90dc-d68b1d78e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232531683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4232531683
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2216118178
Short name T690
Test name
Test status
Simulation time 58822371 ps
CPU time 1.66 seconds
Started May 11 03:52:20 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 209324 kb
Host smart-76d0a948-728f-446e-891a-5be71a7f99c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216118178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2216118178
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1453492623
Short name T983
Test name
Test status
Simulation time 148707780 ps
CPU time 3.08 seconds
Started May 11 03:52:23 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 209152 kb
Host smart-8793c062-bd51-4fda-a8a1-00a3283c0763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453492623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1453492623
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1172634176
Short name T51
Test name
Test status
Simulation time 2400616304 ps
CPU time 78.59 seconds
Started May 11 03:52:23 PM PDT 24
Finished May 11 03:53:42 PM PDT 24
Peak memory 222596 kb
Host smart-e9ca3e44-2a4e-4ba5-9d62-11e6bad1810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172634176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1172634176
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.179526316
Short name T697
Test name
Test status
Simulation time 103420125 ps
CPU time 3.23 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:25 PM PDT 24
Peak memory 214912 kb
Host smart-2f9f3eee-6ad6-4f63-8098-de8a76be8118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179526316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.179526316
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4098624902
Short name T912
Test name
Test status
Simulation time 3140945251 ps
CPU time 7.58 seconds
Started May 11 03:52:23 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 207252 kb
Host smart-3f439c7e-a6f2-4c02-ae69-5b2fd2156af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098624902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4098624902
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2041197720
Short name T291
Test name
Test status
Simulation time 983308118 ps
CPU time 10.58 seconds
Started May 11 03:52:18 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 208468 kb
Host smart-f95f6596-ad9b-46f2-b85d-9913f5200308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041197720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2041197720
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1075435601
Short name T815
Test name
Test status
Simulation time 844449482 ps
CPU time 5.65 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 208268 kb
Host smart-36296b76-c231-4bbc-86f1-08ce916a6b3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075435601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1075435601
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3498729960
Short name T642
Test name
Test status
Simulation time 32484612 ps
CPU time 2.44 seconds
Started May 11 03:52:20 PM PDT 24
Finished May 11 03:52:23 PM PDT 24
Peak memory 207640 kb
Host smart-eb733321-63f4-4ba4-87da-96baac0d0aad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498729960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3498729960
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3983673797
Short name T294
Test name
Test status
Simulation time 159201461 ps
CPU time 3.2 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 208732 kb
Host smart-e17cc9fe-8acd-4d83-8912-2410ca30a6a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983673797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3983673797
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2771279019
Short name T375
Test name
Test status
Simulation time 740195669 ps
CPU time 5.94 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 220332 kb
Host smart-87c2c39a-7c3c-41de-8ad0-9bfc955a0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771279019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2771279019
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2218035191
Short name T888
Test name
Test status
Simulation time 85996824 ps
CPU time 3.56 seconds
Started May 11 03:52:17 PM PDT 24
Finished May 11 03:52:22 PM PDT 24
Peak memory 208900 kb
Host smart-897b0500-a40b-42df-8565-f348d6006b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218035191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2218035191
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.292433890
Short name T1050
Test name
Test status
Simulation time 198766931 ps
CPU time 6.6 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:37 PM PDT 24
Peak memory 223132 kb
Host smart-c514ca2d-75ce-440d-aaee-85ab081c2bba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292433890 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.292433890
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.363115559
Short name T372
Test name
Test status
Simulation time 645171000 ps
CPU time 6.47 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:28 PM PDT 24
Peak memory 218612 kb
Host smart-7072c4aa-3e5a-448e-ab50-172640963d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363115559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.363115559
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1339555903
Short name T602
Test name
Test status
Simulation time 30086723 ps
CPU time 1.85 seconds
Started May 11 03:52:21 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 210000 kb
Host smart-15d381fb-ab41-459b-ae86-5e3d1a9c8719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339555903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1339555903
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.652020511
Short name T940
Test name
Test status
Simulation time 28894543 ps
CPU time 0.77 seconds
Started May 11 03:52:28 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 206000 kb
Host smart-11d8ae92-e345-4076-b212-ba320158014a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652020511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.652020511
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4217383280
Short name T183
Test name
Test status
Simulation time 46667991 ps
CPU time 2.34 seconds
Started May 11 03:52:26 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 217600 kb
Host smart-9a8e1faf-f5c8-4394-9d50-26af135f08ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217383280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4217383280
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4054822001
Short name T46
Test name
Test status
Simulation time 1796187456 ps
CPU time 10.87 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:33 PM PDT 24
Peak memory 219760 kb
Host smart-30e5ed32-787b-4371-ae40-037adfd827bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054822001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4054822001
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2109939019
Short name T826
Test name
Test status
Simulation time 144313536 ps
CPU time 4.96 seconds
Started May 11 03:52:26 PM PDT 24
Finished May 11 03:52:32 PM PDT 24
Peak memory 214448 kb
Host smart-632d4d16-2ba8-4e13-8d8f-8ed7df2dc51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109939019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2109939019
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.769606550
Short name T367
Test name
Test status
Simulation time 124970724 ps
CPU time 6.46 seconds
Started May 11 03:52:26 PM PDT 24
Finished May 11 03:52:33 PM PDT 24
Peak memory 222612 kb
Host smart-9167d9c6-4b0e-4725-b6f3-fd634ac11ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769606550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.769606550
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1194325008
Short name T332
Test name
Test status
Simulation time 205057947 ps
CPU time 3.05 seconds
Started May 11 03:52:25 PM PDT 24
Finished May 11 03:52:29 PM PDT 24
Peak memory 207908 kb
Host smart-a77a5534-48ac-4c14-b158-b8f57ff695c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194325008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1194325008
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1063831225
Short name T924
Test name
Test status
Simulation time 50787882 ps
CPU time 3.37 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:27 PM PDT 24
Peak memory 218392 kb
Host smart-5e3beb12-693c-4703-9c0d-9a01cdcc0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063831225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1063831225
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3150686162
Short name T371
Test name
Test status
Simulation time 52982848 ps
CPU time 2.93 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:26 PM PDT 24
Peak memory 208644 kb
Host smart-5e3e1699-d6e9-4485-9078-03142f3f9a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150686162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3150686162
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3762726253
Short name T140
Test name
Test status
Simulation time 36852518 ps
CPU time 2.57 seconds
Started May 11 03:52:22 PM PDT 24
Finished May 11 03:52:25 PM PDT 24
Peak memory 207048 kb
Host smart-44d03cd8-304e-405f-9dc8-20f12ae5c438
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762726253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3762726253
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2529036045
Short name T638
Test name
Test status
Simulation time 51234656 ps
CPU time 2.04 seconds
Started May 11 03:52:25 PM PDT 24
Finished May 11 03:52:28 PM PDT 24
Peak memory 208884 kb
Host smart-642bcff6-5814-452e-a8e4-1f99dc975a4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529036045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2529036045
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3462468642
Short name T597
Test name
Test status
Simulation time 62017561 ps
CPU time 3.17 seconds
Started May 11 03:52:20 PM PDT 24
Finished May 11 03:52:24 PM PDT 24
Peak memory 209048 kb
Host smart-62f843a5-143d-4f87-9d14-01b94231f556
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462468642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3462468642
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1902315502
Short name T1027
Test name
Test status
Simulation time 773853947 ps
CPU time 2.24 seconds
Started May 11 03:52:28 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 208736 kb
Host smart-09ff9899-785d-44de-a3f8-dd8785b646a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902315502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1902315502
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2597494967
Short name T932
Test name
Test status
Simulation time 274820193 ps
CPU time 5.22 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 208924 kb
Host smart-7bd3f9fd-d067-4761-99b5-6728d666ce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597494967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2597494967
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1747851463
Short name T77
Test name
Test status
Simulation time 1013186809 ps
CPU time 36.16 seconds
Started May 11 03:52:26 PM PDT 24
Finished May 11 03:53:02 PM PDT 24
Peak memory 216524 kb
Host smart-42e733dd-59a1-4167-a6ef-17a198b9d0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747851463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1747851463
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.930205788
Short name T621
Test name
Test status
Simulation time 154130214 ps
CPU time 5.43 seconds
Started May 11 03:52:27 PM PDT 24
Finished May 11 03:52:33 PM PDT 24
Peak memory 208104 kb
Host smart-76565c9a-2de1-456a-bfdf-53f8b0386947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930205788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.930205788
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4118394342
Short name T768
Test name
Test status
Simulation time 47310917 ps
CPU time 0.86 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 205924 kb
Host smart-b326bb44-6ec7-4d97-93a2-12747f4ced26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118394342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4118394342
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1929264016
Short name T361
Test name
Test status
Simulation time 206547537 ps
CPU time 3.82 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:35 PM PDT 24
Peak memory 214516 kb
Host smart-83b868ab-0107-46cb-89f7-453bdc8f9e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929264016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1929264016
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4044848301
Short name T10
Test name
Test status
Simulation time 69025346 ps
CPU time 2.46 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:34 PM PDT 24
Peak memory 222788 kb
Host smart-2640864d-6698-4ee2-b11a-d8c1d9a81c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044848301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4044848301
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3106226808
Short name T325
Test name
Test status
Simulation time 62778913 ps
CPU time 2.68 seconds
Started May 11 03:52:27 PM PDT 24
Finished May 11 03:52:30 PM PDT 24
Peak memory 222664 kb
Host smart-bf3e2453-faf6-41fb-a9ad-2e46f43c3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106226808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3106226808
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3741123601
Short name T406
Test name
Test status
Simulation time 82209264 ps
CPU time 3.86 seconds
Started May 11 03:52:32 PM PDT 24
Finished May 11 03:52:37 PM PDT 24
Peak memory 220720 kb
Host smart-1379c108-b1e0-4dcc-b461-193ea1c62107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741123601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3741123601
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3265197250
Short name T314
Test name
Test status
Simulation time 259104160 ps
CPU time 7.71 seconds
Started May 11 03:52:32 PM PDT 24
Finished May 11 03:52:40 PM PDT 24
Peak memory 222664 kb
Host smart-d4acd2ff-4765-4363-b2de-b67c2a3d0611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265197250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3265197250
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.549836270
Short name T258
Test name
Test status
Simulation time 184565671 ps
CPU time 3.69 seconds
Started May 11 03:52:27 PM PDT 24
Finished May 11 03:52:31 PM PDT 24
Peak memory 210228 kb
Host smart-2119e653-7aae-4b42-8d99-a0edf5adebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549836270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.549836270
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1485122805
Short name T911
Test name
Test status
Simulation time 220656042 ps
CPU time 6.56 seconds
Started May 11 03:52:26 PM PDT 24
Finished May 11 03:52:34 PM PDT 24
Peak memory 207996 kb
Host smart-a851e8ba-19d3-4712-a19f-2c84b9dd06f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485122805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1485122805
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2112522677
Short name T300
Test name
Test status
Simulation time 906221699 ps
CPU time 6.95 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 208932 kb
Host smart-22a6f1e8-2cb9-4e7c-af01-9614fe1cd82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112522677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2112522677
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.171228177
Short name T989
Test name
Test status
Simulation time 823802838 ps
CPU time 30.89 seconds
Started May 11 03:52:28 PM PDT 24
Finished May 11 03:52:59 PM PDT 24
Peak memory 208184 kb
Host smart-382c7516-c517-4e96-b897-0e50dd65c4c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171228177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.171228177
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1953207157
Short name T999
Test name
Test status
Simulation time 36551899 ps
CPU time 2.52 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:34 PM PDT 24
Peak memory 208808 kb
Host smart-a6646512-5652-4b04-963f-903b543e9838
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953207157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1953207157
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2022628702
Short name T190
Test name
Test status
Simulation time 1326896932 ps
CPU time 5.84 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:37 PM PDT 24
Peak memory 208608 kb
Host smart-369002d9-3607-443c-9664-7f0b5f52d80b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022628702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2022628702
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3736989929
Short name T838
Test name
Test status
Simulation time 591128439 ps
CPU time 1.85 seconds
Started May 11 03:52:34 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 208904 kb
Host smart-5cb7addf-c763-4eb3-9303-54a30c3af663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736989929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3736989929
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4053389661
Short name T582
Test name
Test status
Simulation time 34362541 ps
CPU time 2.27 seconds
Started May 11 03:52:27 PM PDT 24
Finished May 11 03:52:30 PM PDT 24
Peak memory 206892 kb
Host smart-f852381c-ac6b-49ed-9300-206386eeb742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053389661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4053389661
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3706833431
Short name T1030
Test name
Test status
Simulation time 147847730 ps
CPU time 5.26 seconds
Started May 11 03:52:30 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 219604 kb
Host smart-489cdfce-7a9f-42c1-9ea9-58559a5005f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706833431 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3706833431
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3374581603
Short name T348
Test name
Test status
Simulation time 76811225 ps
CPU time 2.58 seconds
Started May 11 03:52:29 PM PDT 24
Finished May 11 03:52:32 PM PDT 24
Peak memory 210392 kb
Host smart-0cb8f517-e09a-4eca-98e4-d6e5580de063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374581603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3374581603
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4153453715
Short name T595
Test name
Test status
Simulation time 113528891 ps
CPU time 1.65 seconds
Started May 11 03:52:34 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 209844 kb
Host smart-a2d733f7-bc94-4c3e-87dd-7890c8e7bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153453715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4153453715
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4205266626
Short name T677
Test name
Test status
Simulation time 19432037 ps
CPU time 0.7 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 205932 kb
Host smart-fe5a62e9-7447-4275-9d2d-88c0cae4b5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205266626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4205266626
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4020394568
Short name T843
Test name
Test status
Simulation time 252744340 ps
CPU time 2 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 208044 kb
Host smart-20fedc88-fe1c-4351-a99e-6a9025789972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020394568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4020394568
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.981636957
Short name T908
Test name
Test status
Simulation time 113009796 ps
CPU time 4.73 seconds
Started May 11 03:52:33 PM PDT 24
Finished May 11 03:52:38 PM PDT 24
Peak memory 214500 kb
Host smart-cdc537d1-5c96-4cf1-be60-3edd98b8f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981636957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.981636957
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.377210237
Short name T931
Test name
Test status
Simulation time 219494342 ps
CPU time 3.32 seconds
Started May 11 03:52:33 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 211968 kb
Host smart-f51d8758-4456-4593-8ec8-b9d3a8c2b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377210237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.377210237
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3314607505
Short name T723
Test name
Test status
Simulation time 184298609 ps
CPU time 4.37 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 215300 kb
Host smart-9ec2af78-e5bc-49c3-b2a4-8a7e11304ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314607505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3314607505
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2886670876
Short name T327
Test name
Test status
Simulation time 200567288 ps
CPU time 4.99 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:37 PM PDT 24
Peak memory 219668 kb
Host smart-057db1a3-d04c-417a-9ca2-5a4e96da19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886670876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2886670876
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2596590394
Short name T952
Test name
Test status
Simulation time 3851258328 ps
CPU time 53.28 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 208588 kb
Host smart-f0825929-756e-4fb1-bb7a-512cbd9eff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596590394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2596590394
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3126288551
Short name T718
Test name
Test status
Simulation time 39588542 ps
CPU time 2.41 seconds
Started May 11 03:52:31 PM PDT 24
Finished May 11 03:52:34 PM PDT 24
Peak memory 206860 kb
Host smart-ddf515fb-2d28-4d06-8e98-3545700b9b49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126288551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3126288551
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3064755007
Short name T1049
Test name
Test status
Simulation time 299101425 ps
CPU time 7.95 seconds
Started May 11 03:52:32 PM PDT 24
Finished May 11 03:52:40 PM PDT 24
Peak memory 208040 kb
Host smart-bfb9e18b-b0db-422b-83c9-c29f01f49403
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064755007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3064755007
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.295860634
Short name T189
Test name
Test status
Simulation time 557572709 ps
CPU time 2.6 seconds
Started May 11 03:52:32 PM PDT 24
Finished May 11 03:52:35 PM PDT 24
Peak memory 208164 kb
Host smart-afd0d1ac-8eab-473f-a631-ebbf310f9f95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295860634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.295860634
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2415828849
Short name T658
Test name
Test status
Simulation time 102350878 ps
CPU time 2.08 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:40 PM PDT 24
Peak memory 215716 kb
Host smart-4d18d0a6-94d1-4da1-bf42-c35ed2fd0886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415828849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2415828849
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2004579717
Short name T1011
Test name
Test status
Simulation time 249219772 ps
CPU time 3.88 seconds
Started May 11 03:52:28 PM PDT 24
Finished May 11 03:52:33 PM PDT 24
Peak memory 208632 kb
Host smart-f34e1544-b967-457e-9716-a5ac56636225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004579717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2004579717
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3422493047
Short name T75
Test name
Test status
Simulation time 1326933596 ps
CPU time 13.54 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:52 PM PDT 24
Peak memory 222684 kb
Host smart-ab72ab22-bc1b-445b-9cf8-23e0a4be8780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422493047 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3422493047
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3265974112
Short name T970
Test name
Test status
Simulation time 142738476 ps
CPU time 6.29 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 208844 kb
Host smart-39052a9a-0d0b-46b6-8877-3cfb39fc25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265974112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3265974112
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.208016756
Short name T2
Test name
Test status
Simulation time 43930703 ps
CPU time 1.97 seconds
Started May 11 03:52:33 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 210072 kb
Host smart-6ca95c69-d365-44be-b71d-1836f9ce3ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208016756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.208016756
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2038686566
Short name T993
Test name
Test status
Simulation time 57238531 ps
CPU time 0.79 seconds
Started May 11 03:52:35 PM PDT 24
Finished May 11 03:52:36 PM PDT 24
Peak memory 205944 kb
Host smart-cd124663-adfa-42cb-90a5-ee9b7c49b61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038686566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2038686566
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3009188512
Short name T401
Test name
Test status
Simulation time 692486221 ps
CPU time 18.44 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:53:00 PM PDT 24
Peak memory 214436 kb
Host smart-6d94fb76-16d0-48af-b005-992569c362de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009188512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3009188512
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3479865093
Short name T29
Test name
Test status
Simulation time 503492606 ps
CPU time 5.71 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:47 PM PDT 24
Peak memory 210256 kb
Host smart-c6d38f6b-64c3-4820-8994-90a5b4c9df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479865093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3479865093
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1461172505
Short name T653
Test name
Test status
Simulation time 48073571 ps
CPU time 2.55 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:40 PM PDT 24
Peak memory 222696 kb
Host smart-f8409a64-da25-482d-be2a-1aff25aa98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461172505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1461172505
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1166738682
Short name T969
Test name
Test status
Simulation time 13062502258 ps
CPU time 59.07 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:53:39 PM PDT 24
Peak memory 214548 kb
Host smart-4bdaac62-d5b0-46ef-aefd-41272151a702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166738682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1166738682
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2328512098
Short name T298
Test name
Test status
Simulation time 106695749 ps
CPU time 5.19 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:42 PM PDT 24
Peak memory 222600 kb
Host smart-4b7dce13-2806-47e7-8b23-501379adf2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328512098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2328512098
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.939644259
Short name T660
Test name
Test status
Simulation time 359780041 ps
CPU time 3.54 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:41 PM PDT 24
Peak memory 220152 kb
Host smart-9fc3bda2-7f8a-46cf-9eee-417e87f47928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939644259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.939644259
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1911220684
Short name T388
Test name
Test status
Simulation time 632482768 ps
CPU time 5.18 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 214488 kb
Host smart-5b0e1950-ff7f-4c05-a38e-c36d5217915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911220684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1911220684
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1600569773
Short name T814
Test name
Test status
Simulation time 192812462 ps
CPU time 5.5 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:46 PM PDT 24
Peak memory 208084 kb
Host smart-24e78fef-67bc-4280-862b-999637c03170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600569773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1600569773
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4285521525
Short name T716
Test name
Test status
Simulation time 124085555 ps
CPU time 3.88 seconds
Started May 11 03:52:35 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 208816 kb
Host smart-1303cc04-ad4d-4cad-84d2-b7e7abc9a3e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285521525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4285521525
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3851162140
Short name T363
Test name
Test status
Simulation time 1346393225 ps
CPU time 3.67 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:45 PM PDT 24
Peak memory 208992 kb
Host smart-bbbaeb2c-7507-4abd-82da-891c1cee5725
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851162140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3851162140
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3300829118
Short name T922
Test name
Test status
Simulation time 109649934 ps
CPU time 4.82 seconds
Started May 11 03:52:43 PM PDT 24
Finished May 11 03:52:48 PM PDT 24
Peak memory 208472 kb
Host smart-e7e44465-5494-4f19-bbea-83433b8de333
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300829118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3300829118
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3999652842
Short name T360
Test name
Test status
Simulation time 223573572 ps
CPU time 3.22 seconds
Started May 11 03:52:43 PM PDT 24
Finished May 11 03:52:46 PM PDT 24
Peak memory 207808 kb
Host smart-e0437dda-8fa8-4953-ba26-f63aa1b2a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999652842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3999652842
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3138646993
Short name T630
Test name
Test status
Simulation time 94973041 ps
CPU time 3.58 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:40 PM PDT 24
Peak memory 208596 kb
Host smart-6ec19a4a-3c95-4019-b10e-66a7bd3c59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138646993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3138646993
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4214567529
Short name T691
Test name
Test status
Simulation time 75634571 ps
CPU time 3.19 seconds
Started May 11 03:52:35 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 208320 kb
Host smart-6a81ccb6-2107-43c9-880f-3a34d8ec5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214567529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4214567529
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1450215988
Short name T229
Test name
Test status
Simulation time 194568162 ps
CPU time 2.03 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:39 PM PDT 24
Peak memory 222656 kb
Host smart-041e31bd-c2ea-4f7d-ad41-52c1a209f7b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450215988 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1450215988
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1163083706
Short name T1002
Test name
Test status
Simulation time 96813035 ps
CPU time 4.62 seconds
Started May 11 03:52:36 PM PDT 24
Finished May 11 03:52:42 PM PDT 24
Peak memory 209460 kb
Host smart-0097b087-0f31-46e6-8cd0-c4af1f54f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163083706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1163083706
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3803337545
Short name T918
Test name
Test status
Simulation time 90272707 ps
CPU time 2.35 seconds
Started May 11 03:52:37 PM PDT 24
Finished May 11 03:52:41 PM PDT 24
Peak memory 210112 kb
Host smart-65bee90d-209d-4b69-a91c-f77f791d58ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803337545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3803337545
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4094951736
Short name T846
Test name
Test status
Simulation time 26794496 ps
CPU time 0.71 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:42 PM PDT 24
Peak memory 205800 kb
Host smart-ea0b2ac6-d969-4b94-a64c-2529d533477b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094951736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4094951736
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1774341403
Short name T432
Test name
Test status
Simulation time 227015126 ps
CPU time 4.27 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 214612 kb
Host smart-462feb93-196a-4486-8ae0-c94fae9b1174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774341403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1774341403
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1292465156
Short name T1033
Test name
Test status
Simulation time 88391891 ps
CPU time 2.98 seconds
Started May 11 03:52:38 PM PDT 24
Finished May 11 03:52:42 PM PDT 24
Peak memory 220900 kb
Host smart-477e84d1-fbc9-4873-8074-d679d984f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292465156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1292465156
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.594994154
Short name T78
Test name
Test status
Simulation time 99222621 ps
CPU time 2.28 seconds
Started May 11 03:52:41 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 210436 kb
Host smart-2ed963a6-3d32-43fa-a5a4-552742a4e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594994154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.594994154
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4148491868
Short name T393
Test name
Test status
Simulation time 4314002905 ps
CPU time 21.26 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:53:02 PM PDT 24
Peak memory 220128 kb
Host smart-f9ce25c0-02dc-42fe-b72b-c392a9704a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148491868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4148491868
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2926575249
Short name T92
Test name
Test status
Simulation time 897993470 ps
CPU time 5.18 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:46 PM PDT 24
Peak memory 214388 kb
Host smart-eaacf3ce-3064-49f9-8cef-69b7736c5272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926575249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2926575249
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2941782443
Short name T233
Test name
Test status
Simulation time 112916286 ps
CPU time 4 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 209732 kb
Host smart-53cd8423-b939-44bb-b66b-3ff9ad850c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941782443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2941782443
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1020449441
Short name T968
Test name
Test status
Simulation time 1258347073 ps
CPU time 8.05 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:49 PM PDT 24
Peak memory 209292 kb
Host smart-c3cd2527-26a9-42c5-97df-49d10e4d70cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020449441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1020449441
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1551285363
Short name T860
Test name
Test status
Simulation time 3045489134 ps
CPU time 32.19 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:53:13 PM PDT 24
Peak memory 209020 kb
Host smart-591b349a-b562-4a88-b6b5-1c6e80e790a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551285363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1551285363
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3117521352
Short name T954
Test name
Test status
Simulation time 1373115537 ps
CPU time 7.19 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:52:47 PM PDT 24
Peak memory 208712 kb
Host smart-ff00ee11-fece-43dc-ac00-a15ede0a3e97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117521352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3117521352
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.54863269
Short name T760
Test name
Test status
Simulation time 2680231627 ps
CPU time 11.23 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:52 PM PDT 24
Peak memory 208740 kb
Host smart-ff50af6f-4ae3-4811-9390-16808040c58c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54863269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.54863269
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3918823545
Short name T262
Test name
Test status
Simulation time 1601388191 ps
CPU time 15.08 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:52:55 PM PDT 24
Peak memory 208284 kb
Host smart-cad2d989-21dc-4d1e-8f19-219cc8c6789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918823545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3918823545
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.876098971
Short name T1071
Test name
Test status
Simulation time 4553621508 ps
CPU time 25.89 seconds
Started May 11 03:52:42 PM PDT 24
Finished May 11 03:53:08 PM PDT 24
Peak memory 208092 kb
Host smart-a4f67d5b-8c25-4e83-a1ea-5c4c3d2cb9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876098971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.876098971
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2660928729
Short name T234
Test name
Test status
Simulation time 4990200586 ps
CPU time 52.3 seconds
Started May 11 03:52:38 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 222648 kb
Host smart-c567b12c-d4ba-47be-a682-c37b2dae3a1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660928729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2660928729
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.893366329
Short name T905
Test name
Test status
Simulation time 405401785 ps
CPU time 3.97 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:45 PM PDT 24
Peak memory 208220 kb
Host smart-e6e6e80f-3a5e-41b8-bb53-7f2be4577217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893366329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.893366329
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.121267520
Short name T1057
Test name
Test status
Simulation time 57959145 ps
CPU time 2.75 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:43 PM PDT 24
Peak memory 210288 kb
Host smart-a9ebbc6f-0ed7-48f8-b76c-e9317fd01a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121267520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.121267520
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.326531521
Short name T722
Test name
Test status
Simulation time 17431843 ps
CPU time 0.98 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:51 PM PDT 24
Peak memory 206180 kb
Host smart-1611c88b-73e3-433d-837a-df0943834a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326531521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.326531521
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3210334954
Short name T438
Test name
Test status
Simulation time 128749327 ps
CPU time 2.35 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:52:56 PM PDT 24
Peak memory 214512 kb
Host smart-bc645066-fa62-4bf3-bfc1-669884d1a6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210334954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3210334954
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1588927160
Short name T66
Test name
Test status
Simulation time 534531946 ps
CPU time 7.38 seconds
Started May 11 03:52:49 PM PDT 24
Finished May 11 03:52:57 PM PDT 24
Peak memory 209924 kb
Host smart-3c4da7c6-004d-4c09-9600-c9ea5a39cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588927160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1588927160
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.262112908
Short name T274
Test name
Test status
Simulation time 99264685 ps
CPU time 4.6 seconds
Started May 11 03:52:47 PM PDT 24
Finished May 11 03:52:52 PM PDT 24
Peak memory 210880 kb
Host smart-1d8af45b-e2b4-4dc8-a6cf-afb70f528098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262112908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.262112908
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.636377750
Short name T55
Test name
Test status
Simulation time 286035844 ps
CPU time 4.89 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:52:58 PM PDT 24
Peak memory 220232 kb
Host smart-338d3eaa-a12d-4541-ad12-c7f32c487815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636377750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.636377750
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1951331548
Short name T265
Test name
Test status
Simulation time 39095048 ps
CPU time 2.8 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 207684 kb
Host smart-fec2e1a1-abdf-4ccd-a859-f210f52d6736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951331548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1951331548
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3295585354
Short name T863
Test name
Test status
Simulation time 298801599 ps
CPU time 3.29 seconds
Started May 11 03:52:40 PM PDT 24
Finished May 11 03:52:44 PM PDT 24
Peak memory 206896 kb
Host smart-39dcf340-3818-4045-8bb3-ae0ce799c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295585354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3295585354
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3093177556
Short name T778
Test name
Test status
Simulation time 33397978 ps
CPU time 2.32 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:52:42 PM PDT 24
Peak memory 207020 kb
Host smart-64c43c78-f40e-4575-8449-29fedcfc6d2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093177556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3093177556
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3403010673
Short name T611
Test name
Test status
Simulation time 2259541397 ps
CPU time 49.73 seconds
Started May 11 03:52:39 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208552 kb
Host smart-392075f4-d641-414a-9f0d-742e534c496c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403010673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3403010673
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.479522820
Short name T976
Test name
Test status
Simulation time 63854699 ps
CPU time 2.39 seconds
Started May 11 03:52:38 PM PDT 24
Finished May 11 03:52:41 PM PDT 24
Peak memory 206908 kb
Host smart-72f446a1-2fe5-4ab8-9120-9b5e13d77c88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479522820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.479522820
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3699819687
Short name T783
Test name
Test status
Simulation time 882678543 ps
CPU time 2.63 seconds
Started May 11 03:52:47 PM PDT 24
Finished May 11 03:52:50 PM PDT 24
Peak memory 209736 kb
Host smart-1afac0b1-381b-4523-b869-976a2eb76bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699819687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3699819687
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2250399057
Short name T581
Test name
Test status
Simulation time 261914762 ps
CPU time 2.65 seconds
Started May 11 03:52:38 PM PDT 24
Finished May 11 03:52:41 PM PDT 24
Peak memory 208652 kb
Host smart-e1decb06-bb38-4e07-9e58-745e8308c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250399057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2250399057
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.114762731
Short name T674
Test name
Test status
Simulation time 5122676343 ps
CPU time 20.38 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:53:09 PM PDT 24
Peak memory 215320 kb
Host smart-ed47df19-704a-4e79-aaa5-6431b70812da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114762731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.114762731
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4190939652
Short name T1004
Test name
Test status
Simulation time 487026089 ps
CPU time 3.93 seconds
Started May 11 03:52:49 PM PDT 24
Finished May 11 03:52:53 PM PDT 24
Peak memory 218172 kb
Host smart-eb4437fb-e983-4157-b925-61218a0766b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190939652 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4190939652
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.816585416
Short name T1003
Test name
Test status
Simulation time 1677892202 ps
CPU time 5.36 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:52:54 PM PDT 24
Peak memory 207632 kb
Host smart-0d1b7e23-9a49-4bc4-872c-e4221c168c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816585416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.816585416
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1882236512
Short name T975
Test name
Test status
Simulation time 80414573 ps
CPU time 2.29 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:54 PM PDT 24
Peak memory 210324 kb
Host smart-65cbcf0b-23ea-49c1-ab18-4ee2d6309813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882236512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1882236512
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1704835182
Short name T588
Test name
Test status
Simulation time 17415982 ps
CPU time 0.73 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:02 PM PDT 24
Peak memory 205936 kb
Host smart-473f8dae-9fd6-4dcf-94bf-edd0e7788084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704835182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1704835182
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2752984465
Short name T64
Test name
Test status
Simulation time 61326058 ps
CPU time 2.34 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:53 PM PDT 24
Peak memory 214428 kb
Host smart-0b16f7bc-5fc6-4d12-9566-9d85dbca5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752984465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2752984465
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4033544521
Short name T313
Test name
Test status
Simulation time 85351332 ps
CPU time 4.81 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:56 PM PDT 24
Peak memory 210496 kb
Host smart-a0476685-e05d-436d-bf34-f6bcef0361f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033544521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4033544521
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1836216813
Short name T241
Test name
Test status
Simulation time 65785348 ps
CPU time 4.35 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:55 PM PDT 24
Peak memory 222736 kb
Host smart-322c37f7-631d-4651-a200-076c1add8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836216813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1836216813
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.311127962
Short name T267
Test name
Test status
Simulation time 194143829 ps
CPU time 5.86 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:53:00 PM PDT 24
Peak memory 208204 kb
Host smart-502c63a0-3eed-485a-8550-5c96193c63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311127962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.311127962
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1725619256
Short name T87
Test name
Test status
Simulation time 133840927 ps
CPU time 2.73 seconds
Started May 11 03:52:48 PM PDT 24
Finished May 11 03:52:51 PM PDT 24
Peak memory 208624 kb
Host smart-d46bd9a9-f110-434a-9a5f-cb2f45a36662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725619256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1725619256
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2208882471
Short name T810
Test name
Test status
Simulation time 84004746 ps
CPU time 1.83 seconds
Started May 11 03:52:49 PM PDT 24
Finished May 11 03:52:52 PM PDT 24
Peak memory 207000 kb
Host smart-26d74c37-da2e-4302-a05b-a7afde64d26b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208882471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2208882471
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3334135709
Short name T775
Test name
Test status
Simulation time 527461072 ps
CPU time 13.73 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:53:06 PM PDT 24
Peak memory 207936 kb
Host smart-29a9f577-2dfd-4507-8c22-60c5d76ea339
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334135709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3334135709
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2397136878
Short name T669
Test name
Test status
Simulation time 135901176 ps
CPU time 5.06 seconds
Started May 11 03:52:50 PM PDT 24
Finished May 11 03:52:55 PM PDT 24
Peak memory 206924 kb
Host smart-03a88294-2b9a-42f7-add5-4e279f32e8f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397136878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2397136878
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2295879184
Short name T208
Test name
Test status
Simulation time 228723762 ps
CPU time 5.46 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 209244 kb
Host smart-468b0451-c569-419e-b157-ff26ed91ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295879184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2295879184
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1897825830
Short name T1012
Test name
Test status
Simulation time 90332309 ps
CPU time 2.55 seconds
Started May 11 03:52:46 PM PDT 24
Finished May 11 03:52:49 PM PDT 24
Peak memory 206904 kb
Host smart-4e777ade-a2c7-492a-b9e3-b3b5bde61b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897825830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1897825830
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1554538631
Short name T972
Test name
Test status
Simulation time 392903923 ps
CPU time 3.5 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:03 PM PDT 24
Peak memory 222756 kb
Host smart-cc9af46c-2003-4627-83ba-f45261ffa7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554538631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1554538631
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1188516320
Short name T175
Test name
Test status
Simulation time 218461652 ps
CPU time 2.43 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:52:58 PM PDT 24
Peak memory 210052 kb
Host smart-4158e57e-f370-4be7-9431-92f324e6a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188516320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1188516320
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2536301065
Short name T816
Test name
Test status
Simulation time 64529913 ps
CPU time 0.81 seconds
Started May 11 03:50:29 PM PDT 24
Finished May 11 03:50:30 PM PDT 24
Peak memory 205960 kb
Host smart-86f79751-bc33-419a-bd3b-e01c613054f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536301065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2536301065
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1283602708
Short name T1056
Test name
Test status
Simulation time 31313361 ps
CPU time 2.55 seconds
Started May 11 03:50:28 PM PDT 24
Finished May 11 03:50:31 PM PDT 24
Peak memory 214616 kb
Host smart-bd08a17f-a678-4de6-a675-1f40936174e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283602708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1283602708
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3938310095
Short name T60
Test name
Test status
Simulation time 238715751 ps
CPU time 3.6 seconds
Started May 11 03:50:29 PM PDT 24
Finished May 11 03:50:33 PM PDT 24
Peak memory 209276 kb
Host smart-c054c000-edc1-4e95-9d28-9e569e52c80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938310095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3938310095
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2262844594
Short name T991
Test name
Test status
Simulation time 379010874 ps
CPU time 2.73 seconds
Started May 11 03:50:27 PM PDT 24
Finished May 11 03:50:30 PM PDT 24
Peak memory 208808 kb
Host smart-c916ee11-d177-45df-9bbc-5811f04c399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262844594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2262844594
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.512654919
Short name T249
Test name
Test status
Simulation time 3952050830 ps
CPU time 35.71 seconds
Started May 11 03:50:29 PM PDT 24
Finished May 11 03:51:05 PM PDT 24
Peak memory 214516 kb
Host smart-67c6a31b-f824-4cb7-83fa-0f502cb71aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512654919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.512654919
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2022370005
Short name T69
Test name
Test status
Simulation time 58798361 ps
CPU time 3.57 seconds
Started May 11 03:50:27 PM PDT 24
Finished May 11 03:50:31 PM PDT 24
Peak memory 209352 kb
Host smart-5d122031-6439-47dc-b646-be0ea5985f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022370005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2022370005
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2054130320
Short name T897
Test name
Test status
Simulation time 143227505 ps
CPU time 3.45 seconds
Started May 11 03:50:28 PM PDT 24
Finished May 11 03:50:32 PM PDT 24
Peak memory 215160 kb
Host smart-419593ca-bb8a-42c1-b6e8-7c776d58116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054130320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2054130320
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2608866474
Short name T967
Test name
Test status
Simulation time 270865896 ps
CPU time 5.72 seconds
Started May 11 03:50:20 PM PDT 24
Finished May 11 03:50:26 PM PDT 24
Peak memory 210376 kb
Host smart-7a7c912c-1f7d-4f35-bb71-04d785347344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608866474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2608866474
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2477690671
Short name T601
Test name
Test status
Simulation time 114741546 ps
CPU time 4.71 seconds
Started May 11 03:50:20 PM PDT 24
Finished May 11 03:50:26 PM PDT 24
Peak memory 206912 kb
Host smart-5e1aa72e-b533-4d63-9e75-ba6451d69d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477690671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2477690671
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.49854493
Short name T286
Test name
Test status
Simulation time 4296574656 ps
CPU time 9.2 seconds
Started May 11 03:50:20 PM PDT 24
Finished May 11 03:50:30 PM PDT 24
Peak memory 208604 kb
Host smart-705eff44-82df-4857-81e0-feaa4d7bf5bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49854493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.49854493
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1968729862
Short name T870
Test name
Test status
Simulation time 151122056 ps
CPU time 6.28 seconds
Started May 11 03:50:22 PM PDT 24
Finished May 11 03:50:29 PM PDT 24
Peak memory 208664 kb
Host smart-34c6adef-66a7-4055-ba8b-83163e318e31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968729862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1968729862
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1930729461
Short name T790
Test name
Test status
Simulation time 487641918 ps
CPU time 5.63 seconds
Started May 11 03:50:23 PM PDT 24
Finished May 11 03:50:29 PM PDT 24
Peak memory 207128 kb
Host smart-2ec9668b-324f-4a46-840b-af19b805e587
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930729461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1930729461
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2423050908
Short name T944
Test name
Test status
Simulation time 67881317 ps
CPU time 3.52 seconds
Started May 11 03:50:28 PM PDT 24
Finished May 11 03:50:32 PM PDT 24
Peak memory 208756 kb
Host smart-d054cdec-f054-4551-9a18-9b8e66b13639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423050908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2423050908
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3103712341
Short name T958
Test name
Test status
Simulation time 310385405 ps
CPU time 3.02 seconds
Started May 11 03:50:25 PM PDT 24
Finished May 11 03:50:29 PM PDT 24
Peak memory 208476 kb
Host smart-65fecf97-2d16-44c9-8310-a1bfabd8b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103712341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3103712341
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3716109001
Short name T736
Test name
Test status
Simulation time 3113921380 ps
CPU time 43.32 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:51:10 PM PDT 24
Peak memory 220496 kb
Host smart-51bde022-6c59-4957-b9ac-4bdd83bd7b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716109001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3716109001
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4237242465
Short name T835
Test name
Test status
Simulation time 54464395 ps
CPU time 2.68 seconds
Started May 11 03:50:30 PM PDT 24
Finished May 11 03:50:33 PM PDT 24
Peak memory 214436 kb
Host smart-90791295-a259-4fd1-a331-7568c2bf6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237242465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4237242465
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.688273805
Short name T1054
Test name
Test status
Simulation time 67735338 ps
CPU time 2.77 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:50:30 PM PDT 24
Peak memory 210260 kb
Host smart-1e60f308-799c-4271-8f3d-6a1b32535251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688273805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.688273805
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3032237164
Short name T928
Test name
Test status
Simulation time 18180674 ps
CPU time 0.99 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:14 PM PDT 24
Peak memory 206176 kb
Host smart-24491cbc-7c06-4653-b491-9c25876b91cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032237164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3032237164
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3022006444
Short name T443
Test name
Test status
Simulation time 2515678810 ps
CPU time 65.01 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:53:58 PM PDT 24
Peak memory 215760 kb
Host smart-57534988-0c73-4894-8216-c1d8c7ce57ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022006444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3022006444
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1986605878
Short name T670
Test name
Test status
Simulation time 436268671 ps
CPU time 3.47 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:13 PM PDT 24
Peak memory 209088 kb
Host smart-6ffe19aa-0ede-40ab-a967-834401b0b958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986605878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1986605878
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.422405354
Short name T58
Test name
Test status
Simulation time 497698835 ps
CPU time 3.2 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 209276 kb
Host smart-a135ef19-825d-4f7d-ae0f-4ca47c25ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422405354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.422405354
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.820094088
Short name T281
Test name
Test status
Simulation time 2293186915 ps
CPU time 15.12 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:53:09 PM PDT 24
Peak memory 214608 kb
Host smart-707a672a-fd61-4973-873b-3eddd883a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820094088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.820094088
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2925629248
Short name T974
Test name
Test status
Simulation time 121829032 ps
CPU time 5.17 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:52:58 PM PDT 24
Peak memory 220360 kb
Host smart-b1550c3b-48e3-444e-95e4-dbbd4a60bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925629248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2925629248
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.4118695569
Short name T664
Test name
Test status
Simulation time 794908387 ps
CPU time 6.5 seconds
Started May 11 03:52:52 PM PDT 24
Finished May 11 03:53:02 PM PDT 24
Peak memory 214520 kb
Host smart-eb03ced7-393d-4024-9f74-75b4e2bb087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118695569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.4118695569
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.155216619
Short name T612
Test name
Test status
Simulation time 3134075980 ps
CPU time 10.98 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:17 PM PDT 24
Peak memory 209876 kb
Host smart-c416c577-feaa-414c-8034-0c86c3433030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155216619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.155216619
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.730763295
Short name T978
Test name
Test status
Simulation time 35927812 ps
CPU time 2.36 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:12 PM PDT 24
Peak memory 207000 kb
Host smart-e681d5a8-fab6-4c39-ac2b-cb6047374a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730763295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.730763295
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4113679195
Short name T695
Test name
Test status
Simulation time 76349081 ps
CPU time 2.38 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:00 PM PDT 24
Peak memory 206988 kb
Host smart-4f2107e1-ed18-44cd-bc45-a676ab51edb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113679195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4113679195
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1412703975
Short name T868
Test name
Test status
Simulation time 45602708 ps
CPU time 1.88 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:15 PM PDT 24
Peak memory 206972 kb
Host smart-3d169780-d956-4c41-a320-b452f34fcd83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412703975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1412703975
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4076510636
Short name T191
Test name
Test status
Simulation time 257431180 ps
CPU time 3.22 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:07 PM PDT 24
Peak memory 208580 kb
Host smart-05f1f97f-f4f7-4fac-9dd9-bd1391ce12fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076510636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4076510636
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3825595848
Short name T734
Test name
Test status
Simulation time 2761527018 ps
CPU time 7.5 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 210572 kb
Host smart-a5d06618-8531-43c1-9e22-f28336e48b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825595848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3825595848
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2223030518
Short name T1019
Test name
Test status
Simulation time 609144710 ps
CPU time 6.62 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 208280 kb
Host smart-9730d7d7-939c-4624-815e-97cb25cdae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223030518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2223030518
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.90117230
Short name T767
Test name
Test status
Simulation time 75031481 ps
CPU time 0.88 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:52:54 PM PDT 24
Peak memory 205976 kb
Host smart-af05132b-208c-4144-bc57-04924acf1ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90117230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.90117230
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3006863074
Short name T951
Test name
Test status
Simulation time 176142191 ps
CPU time 3.4 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:52:56 PM PDT 24
Peak memory 218452 kb
Host smart-48710846-02c4-4938-a9f5-eb2a082b515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006863074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3006863074
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2615405990
Short name T38
Test name
Test status
Simulation time 202417062 ps
CPU time 6.38 seconds
Started May 11 03:52:51 PM PDT 24
Finished May 11 03:53:00 PM PDT 24
Peak memory 210988 kb
Host smart-3566f7e8-ac8d-4311-839d-2bee118a07f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615405990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2615405990
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2957489009
Short name T613
Test name
Test status
Simulation time 32585678 ps
CPU time 0.94 seconds
Started May 11 03:52:59 PM PDT 24
Finished May 11 03:53:19 PM PDT 24
Peak memory 206116 kb
Host smart-496ca2e0-b205-49d0-bee2-3c6d39fbb062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957489009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2957489009
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2882606531
Short name T902
Test name
Test status
Simulation time 57996567 ps
CPU time 3 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:04 PM PDT 24
Peak memory 210900 kb
Host smart-eb5fe993-04c4-4929-ac96-805281f72830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882606531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2882606531
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.502688594
Short name T603
Test name
Test status
Simulation time 360238826 ps
CPU time 8.89 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:14 PM PDT 24
Peak memory 209312 kb
Host smart-122d1681-4d78-4ff7-9aa7-0bc397f86714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502688594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.502688594
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3913832947
Short name T920
Test name
Test status
Simulation time 718225314 ps
CPU time 5.44 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:15 PM PDT 24
Peak memory 214464 kb
Host smart-68e87c19-65f5-4487-938f-c35f8d7a9210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913832947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3913832947
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1968086710
Short name T392
Test name
Test status
Simulation time 2572409410 ps
CPU time 7.14 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:18 PM PDT 24
Peak memory 211896 kb
Host smart-956e14fa-59ae-4bc8-8b66-d23b1baea79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968086710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1968086710
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3550270720
Short name T398
Test name
Test status
Simulation time 136155701 ps
CPU time 2.66 seconds
Started May 11 03:52:53 PM PDT 24
Finished May 11 03:53:02 PM PDT 24
Peak memory 220260 kb
Host smart-a25305b4-1624-4d71-988d-37c4bac27734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550270720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3550270720
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.156019991
Short name T689
Test name
Test status
Simulation time 110836061 ps
CPU time 4.51 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:05 PM PDT 24
Peak memory 214408 kb
Host smart-5da31316-59ec-47cd-b39b-9e3fc316ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156019991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.156019991
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3266506463
Short name T354
Test name
Test status
Simulation time 233901553 ps
CPU time 2.72 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:16 PM PDT 24
Peak memory 207472 kb
Host smart-c9a9642b-2502-4fab-8d7f-b0b4338b43a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266506463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3266506463
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2356697144
Short name T362
Test name
Test status
Simulation time 245888663 ps
CPU time 3.12 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:12 PM PDT 24
Peak memory 209004 kb
Host smart-3ba2b984-3c9b-4bb8-8076-24047fc608f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356697144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2356697144
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2808052431
Short name T763
Test name
Test status
Simulation time 314332184 ps
CPU time 2.86 seconds
Started May 11 03:52:57 PM PDT 24
Finished May 11 03:53:16 PM PDT 24
Peak memory 207032 kb
Host smart-80be704f-6ef1-4350-8da4-2b982ce53fa0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808052431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2808052431
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3608782379
Short name T351
Test name
Test status
Simulation time 337817391 ps
CPU time 3.29 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:14 PM PDT 24
Peak memory 207124 kb
Host smart-1226c1d3-19f0-417f-b4de-7ee922161e68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608782379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3608782379
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4033691678
Short name T1062
Test name
Test status
Simulation time 52682148 ps
CPU time 1.94 seconds
Started May 11 03:53:01 PM PDT 24
Finished May 11 03:53:21 PM PDT 24
Peak memory 207224 kb
Host smart-d5ccbc4a-c267-4203-a075-23ea4f56473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033691678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4033691678
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2650053197
Short name T209
Test name
Test status
Simulation time 47376243 ps
CPU time 2.44 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:13 PM PDT 24
Peak memory 206980 kb
Host smart-7fd52677-ced3-4dd7-b3ff-3d041539ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650053197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2650053197
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.328979429
Short name T52
Test name
Test status
Simulation time 2381521976 ps
CPU time 27.02 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:39 PM PDT 24
Peak memory 215516 kb
Host smart-00b38687-f0c8-4ab8-8f11-a0990d61ead1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328979429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.328979429
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.864751270
Short name T1005
Test name
Test status
Simulation time 752233742 ps
CPU time 2.53 seconds
Started May 11 03:53:01 PM PDT 24
Finished May 11 03:53:22 PM PDT 24
Peak memory 217336 kb
Host smart-2e5cf7df-fdff-48c0-bcbb-81ee0c64066d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864751270 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.864751270
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3971346704
Short name T115
Test name
Test status
Simulation time 519701135 ps
CPU time 10.06 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:17 PM PDT 24
Peak memory 207496 kb
Host smart-8bddcc1f-9890-45e5-8334-dfe4e3533672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971346704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3971346704
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1383068992
Short name T1006
Test name
Test status
Simulation time 64139372 ps
CPU time 1.7 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:10 PM PDT 24
Peak memory 209992 kb
Host smart-d459e4e6-13aa-4854-9fd5-b83a790fd1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383068992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1383068992
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1705246664
Short name T759
Test name
Test status
Simulation time 8605964 ps
CPU time 0.83 seconds
Started May 11 03:52:58 PM PDT 24
Finished May 11 03:53:17 PM PDT 24
Peak memory 206008 kb
Host smart-e54a5878-facb-4a18-91da-18b688d394c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705246664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1705246664
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1439522584
Short name T328
Test name
Test status
Simulation time 1857146115 ps
CPU time 88.77 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:54:49 PM PDT 24
Peak memory 214272 kb
Host smart-e7f30828-990a-437f-82ef-ed8518b94024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439522584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1439522584
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3547346818
Short name T116
Test name
Test status
Simulation time 493696346 ps
CPU time 3.21 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 209080 kb
Host smart-ed44250d-f8b7-4667-a2cb-313c66670f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547346818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3547346818
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.786615041
Short name T444
Test name
Test status
Simulation time 35509848 ps
CPU time 1.69 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:11 PM PDT 24
Peak memory 207764 kb
Host smart-2de5cffe-6fa5-43f7-a1fa-6c5640f5f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786615041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.786615041
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.146115516
Short name T315
Test name
Test status
Simulation time 495395107 ps
CPU time 7.62 seconds
Started May 11 03:52:58 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 222636 kb
Host smart-47dc91c9-fdd4-4058-8ead-7fd35763356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146115516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.146115516
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2487451251
Short name T410
Test name
Test status
Simulation time 101534734 ps
CPU time 3.02 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:08 PM PDT 24
Peak memory 209060 kb
Host smart-b7cb1ec3-389d-45b4-9d3c-5bffb805e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487451251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2487451251
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1872533451
Short name T364
Test name
Test status
Simulation time 384134517 ps
CPU time 5.62 seconds
Started May 11 03:53:00 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 207448 kb
Host smart-5147e5f2-72c9-42bd-9b67-e3a96b59e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872533451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1872533451
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3784295924
Short name T985
Test name
Test status
Simulation time 170518260 ps
CPU time 4.92 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 207708 kb
Host smart-ca3d747c-d750-4299-bb6f-b4aaacd94607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784295924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3784295924
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3354944857
Short name T268
Test name
Test status
Simulation time 41456424 ps
CPU time 2.4 seconds
Started May 11 03:52:56 PM PDT 24
Finished May 11 03:53:13 PM PDT 24
Peak memory 206748 kb
Host smart-28dd2797-da40-4d68-ba0c-285c2387050c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354944857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3354944857
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2262994887
Short name T599
Test name
Test status
Simulation time 1263389357 ps
CPU time 3.9 seconds
Started May 11 03:52:55 PM PDT 24
Finished May 11 03:53:10 PM PDT 24
Peak memory 208908 kb
Host smart-e702123f-c6d0-4e58-9039-287b56ab8915
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262994887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2262994887
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1180385084
Short name T859
Test name
Test status
Simulation time 105547174 ps
CPU time 2.97 seconds
Started May 11 03:53:01 PM PDT 24
Finished May 11 03:53:22 PM PDT 24
Peak memory 206996 kb
Host smart-09a2d61a-a461-4660-875e-845fbcbc28ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180385084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1180385084
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1641161701
Short name T1040
Test name
Test status
Simulation time 126757639 ps
CPU time 2.02 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 215696 kb
Host smart-a450137a-6b03-4512-bc28-5bc4e0f9752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641161701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1641161701
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2404374186
Short name T219
Test name
Test status
Simulation time 161288486 ps
CPU time 2.52 seconds
Started May 11 03:53:01 PM PDT 24
Finished May 11 03:53:22 PM PDT 24
Peak memory 206924 kb
Host smart-2d967412-fcfc-4420-bfa8-23e99eff490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404374186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2404374186
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1106237476
Short name T777
Test name
Test status
Simulation time 2928887066 ps
CPU time 11.01 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:15 PM PDT 24
Peak memory 214568 kb
Host smart-0bb339c5-6ab5-4b37-8854-302a44bd8ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106237476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1106237476
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4105863051
Short name T600
Test name
Test status
Simulation time 116735875 ps
CPU time 4.73 seconds
Started May 11 03:52:58 PM PDT 24
Finished May 11 03:53:22 PM PDT 24
Peak memory 222768 kb
Host smart-dad19cb2-ce61-4cce-a998-cc061af888c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105863051 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4105863051
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2401613780
Short name T270
Test name
Test status
Simulation time 96182188 ps
CPU time 4.68 seconds
Started May 11 03:53:00 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 210040 kb
Host smart-8ba2c090-1b7c-49f5-9093-7b9e9d223d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401613780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2401613780
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2371974947
Short name T4
Test name
Test status
Simulation time 726817676 ps
CPU time 13.31 seconds
Started May 11 03:52:58 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 211200 kb
Host smart-c7ee0e57-bdbf-4103-b920-bb21b0de63e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371974947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2371974947
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.249780441
Short name T1000
Test name
Test status
Simulation time 18845343 ps
CPU time 0.81 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:22 PM PDT 24
Peak memory 205964 kb
Host smart-78d790d4-431d-4579-87b6-cc80f5b6ed58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249780441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.249780441
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3963752021
Short name T63
Test name
Test status
Simulation time 828835855 ps
CPU time 10.68 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 221968 kb
Host smart-90391f69-30d7-4ba8-b4ab-bb00dccef97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963752021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3963752021
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2458682065
Short name T990
Test name
Test status
Simulation time 1277535714 ps
CPU time 7.12 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 208916 kb
Host smart-60566021-c1a5-4966-863e-8f37881e41ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458682065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2458682065
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.527476005
Short name T369
Test name
Test status
Simulation time 234465072 ps
CPU time 4.84 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 211204 kb
Host smart-18091b82-e804-42a6-aaaa-feac8c45fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527476005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.527476005
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.948884384
Short name T235
Test name
Test status
Simulation time 65987675 ps
CPU time 2.66 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 214504 kb
Host smart-791f88f0-9287-42df-a1fe-eaea16ed8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948884384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.948884384
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2885374971
Short name T205
Test name
Test status
Simulation time 290812201 ps
CPU time 3.7 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 210296 kb
Host smart-f9c902e8-a4f3-4ba2-9e97-cd59d7e48361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885374971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2885374971
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2560254053
Short name T848
Test name
Test status
Simulation time 1148075342 ps
CPU time 3.47 seconds
Started May 11 03:52:57 PM PDT 24
Finished May 11 03:53:19 PM PDT 24
Peak memory 206824 kb
Host smart-a3863b6e-c00b-4386-a9b7-1cf505b102fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560254053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2560254053
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2267659619
Short name T819
Test name
Test status
Simulation time 376664305 ps
CPU time 2.9 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 206796 kb
Host smart-ad64152c-0b5f-45b3-906e-c99f94bfb828
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267659619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2267659619
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1265957054
Short name T823
Test name
Test status
Simulation time 59855394 ps
CPU time 2.84 seconds
Started May 11 03:52:58 PM PDT 24
Finished May 11 03:53:19 PM PDT 24
Peak memory 209064 kb
Host smart-b3beaf34-cf70-402d-b286-6f881984eff7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265957054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1265957054
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1821593059
Short name T774
Test name
Test status
Simulation time 89717496 ps
CPU time 4.27 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 208836 kb
Host smart-3b9b304c-e7d6-4842-ac17-d33415f7c9ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821593059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1821593059
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1890374316
Short name T852
Test name
Test status
Simulation time 71348326 ps
CPU time 2.62 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 215840 kb
Host smart-545abf9b-fcd8-4b0f-824f-470028f699d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890374316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1890374316
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.192803587
Short name T735
Test name
Test status
Simulation time 591522789 ps
CPU time 4.49 seconds
Started May 11 03:52:54 PM PDT 24
Finished May 11 03:53:10 PM PDT 24
Peak memory 206736 kb
Host smart-d9f14af4-931f-4414-89b7-e87264d8f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192803587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.192803587
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1181417180
Short name T376
Test name
Test status
Simulation time 805307018 ps
CPU time 9.14 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:32 PM PDT 24
Peak memory 214464 kb
Host smart-73df68fc-6ac5-4aa3-9ba0-469bac8d8561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181417180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1181417180
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4132276346
Short name T440
Test name
Test status
Simulation time 251914437 ps
CPU time 5.65 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 220132 kb
Host smart-9287c8e2-333a-48e2-99b1-5deef831a6a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132276346 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4132276346
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.333170634
Short name T694
Test name
Test status
Simulation time 1086161662 ps
CPU time 21.13 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:42 PM PDT 24
Peak memory 209408 kb
Host smart-e22a1fe8-ac31-467d-a171-570eadb94725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333170634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.333170634
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1589604205
Short name T864
Test name
Test status
Simulation time 1002637555 ps
CPU time 8.66 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 211156 kb
Host smart-94dcea49-0fd2-4b1c-bcc0-385a1baad6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589604205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1589604205
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.256809571
Short name T880
Test name
Test status
Simulation time 38027014 ps
CPU time 0.8 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 205988 kb
Host smart-dfdaedf4-bdb4-4091-812e-07e8d5da5d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256809571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.256809571
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3504446429
Short name T1047
Test name
Test status
Simulation time 231729144 ps
CPU time 4.41 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 215320 kb
Host smart-2d7f6cd0-185f-4efb-9c4f-6091d579c99b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504446429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3504446429
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3702089654
Short name T35
Test name
Test status
Simulation time 114710447 ps
CPU time 4.79 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 214472 kb
Host smart-d91e8f42-7fe7-4b65-90b7-656346921d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702089654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3702089654
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2077018158
Short name T1013
Test name
Test status
Simulation time 333066974 ps
CPU time 8.03 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208892 kb
Host smart-31c88e02-e671-4982-82f2-fbbab1f35ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077018158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2077018158
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4132724141
Short name T900
Test name
Test status
Simulation time 448848517 ps
CPU time 5.2 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 208988 kb
Host smart-d8f72ca9-9d52-47f8-b322-130b17f05aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132724141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4132724141
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1830038118
Short name T95
Test name
Test status
Simulation time 86255060 ps
CPU time 2.17 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 208932 kb
Host smart-32eeddb7-ad5a-420f-8574-2b672cb91c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830038118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1830038118
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2431552659
Short name T435
Test name
Test status
Simulation time 189355518 ps
CPU time 2.59 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 219976 kb
Host smart-9bbf277b-31bc-4bfd-9471-7627423a366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431552659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2431552659
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.131779733
Short name T872
Test name
Test status
Simulation time 107918530 ps
CPU time 5.2 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 207400 kb
Host smart-9c3800f3-15af-43b5-a9c9-b8bcf6155427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131779733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.131779733
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3105131390
Short name T326
Test name
Test status
Simulation time 124156070 ps
CPU time 3.29 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 206940 kb
Host smart-4996ec53-2b7e-4a1a-a8b2-55e5f1be41d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105131390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3105131390
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1220175178
Short name T879
Test name
Test status
Simulation time 3545379849 ps
CPU time 70.17 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:54:31 PM PDT 24
Peak memory 208236 kb
Host smart-3689ecd9-f492-42be-9480-9dcafacf2378
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220175178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1220175178
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.696707368
Short name T221
Test name
Test status
Simulation time 598678364 ps
CPU time 5.33 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208760 kb
Host smart-cd3dabd3-5ec1-4f13-95cf-38a47f85e2ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696707368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.696707368
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3696083424
Short name T746
Test name
Test status
Simulation time 380634898 ps
CPU time 2.75 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 206872 kb
Host smart-1f0b9d34-e35a-4781-9467-df7f10ca3bc9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696083424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3696083424
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2298605773
Short name T977
Test name
Test status
Simulation time 49802720 ps
CPU time 2.49 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 207020 kb
Host smart-edd46074-7bfe-4d41-8cc1-982cea048db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298605773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2298605773
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2933360661
Short name T420
Test name
Test status
Simulation time 124329339 ps
CPU time 3.71 seconds
Started May 11 03:53:03 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 206824 kb
Host smart-cf364117-3b68-4543-b259-1354d18b4387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933360661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2933360661
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2973775816
Short name T337
Test name
Test status
Simulation time 6640422156 ps
CPU time 29.94 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:52 PM PDT 24
Peak memory 217228 kb
Host smart-bdfd3936-a85f-4984-bb36-648bef6abfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973775816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2973775816
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4236148061
Short name T854
Test name
Test status
Simulation time 76753982 ps
CPU time 3.71 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 222768 kb
Host smart-e5c61fd9-9068-4455-8d28-c3980f557ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236148061 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4236148061
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1446924697
Short name T629
Test name
Test status
Simulation time 361214770 ps
CPU time 9.32 seconds
Started May 11 03:53:04 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 208256 kb
Host smart-504c4451-bfbc-4c62-882c-e54b475ff774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446924697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1446924697
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4066760577
Short name T639
Test name
Test status
Simulation time 103806150 ps
CPU time 1.68 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 210012 kb
Host smart-a5e048c6-387e-4a6d-ae7a-9e4ac98a7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066760577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4066760577
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2308739845
Short name T904
Test name
Test status
Simulation time 24475370 ps
CPU time 0.87 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 206004 kb
Host smart-41ad4565-2cf6-4509-b90a-989f7ebd4a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308739845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2308739845
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2195133906
Short name T425
Test name
Test status
Simulation time 131815748 ps
CPU time 5.07 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 214840 kb
Host smart-6d65c3ad-90b8-4bd9-9992-79c4fab4d2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195133906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2195133906
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.384397149
Short name T33
Test name
Test status
Simulation time 680773040 ps
CPU time 6.66 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 209448 kb
Host smart-b25f3c35-6d77-46c0-bbfa-5c6475c14e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384397149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.384397149
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3021437555
Short name T402
Test name
Test status
Simulation time 142021914 ps
CPU time 2.51 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 218400 kb
Host smart-645b9125-f257-4b14-a1ad-f1321e427ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021437555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3021437555
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1262600062
Short name T373
Test name
Test status
Simulation time 177160701 ps
CPU time 4.16 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 209144 kb
Host smart-d5566806-4864-4aac-99f3-fa1750bc13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262600062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1262600062
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3839252288
Short name T945
Test name
Test status
Simulation time 326958381 ps
CPU time 4.24 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 210568 kb
Host smart-45683c91-1b25-4386-87f5-d75266979954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839252288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3839252288
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.805415987
Short name T709
Test name
Test status
Simulation time 52669647 ps
CPU time 2.92 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 208408 kb
Host smart-6c330644-b5f9-4e84-bcbb-f302b4b1be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805415987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.805415987
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.71103186
Short name T218
Test name
Test status
Simulation time 290688974 ps
CPU time 7.82 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 208732 kb
Host smart-deb840c8-26ff-499f-92f9-cb0d9091f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71103186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.71103186
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3978035777
Short name T411
Test name
Test status
Simulation time 1043887155 ps
CPU time 7.73 seconds
Started May 11 03:53:06 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 207740 kb
Host smart-45095dea-9e17-464d-a1a1-e40918081874
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978035777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3978035777
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.169656885
Short name T335
Test name
Test status
Simulation time 290335626 ps
CPU time 6.77 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 208884 kb
Host smart-a08474bd-b2cd-4a55-8466-fc7c92d5f0b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169656885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.169656885
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2923121733
Short name T386
Test name
Test status
Simulation time 113007221 ps
CPU time 2.32 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 206996 kb
Host smart-21a2b8a2-abaf-4e24-ac20-8c9ca480f26f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923121733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2923121733
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2696854105
Short name T903
Test name
Test status
Simulation time 378497182 ps
CPU time 3.46 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 218592 kb
Host smart-d26fd0a9-43b7-40b2-a5e0-c4f4ce4e522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696854105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2696854105
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1521842221
Short name T811
Test name
Test status
Simulation time 289092697 ps
CPU time 3.13 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 208588 kb
Host smart-bb0941b6-e5d8-419e-8801-e99760528456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521842221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1521842221
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1987003684
Short name T341
Test name
Test status
Simulation time 2805151990 ps
CPU time 47.02 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:54:10 PM PDT 24
Peak memory 215956 kb
Host smart-ccd69eff-972e-4628-8c61-3618aa9537c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987003684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1987003684
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2975028856
Short name T434
Test name
Test status
Simulation time 250650442 ps
CPU time 10.21 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:33 PM PDT 24
Peak memory 220524 kb
Host smart-f59a4042-76c8-47ca-84d4-d14f20e62553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975028856 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2975028856
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2465265171
Short name T829
Test name
Test status
Simulation time 57303602 ps
CPU time 3.85 seconds
Started May 11 03:53:07 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 214612 kb
Host smart-57309d4d-d7a4-4792-bbfd-e4bdd72059ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465265171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2465265171
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2980558867
Short name T899
Test name
Test status
Simulation time 98607397 ps
CPU time 1.83 seconds
Started May 11 03:53:05 PM PDT 24
Finished May 11 03:53:23 PM PDT 24
Peak memory 209836 kb
Host smart-7110183b-37d5-441b-9108-a94de60bef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980558867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2980558867
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3455596759
Short name T825
Test name
Test status
Simulation time 31181936 ps
CPU time 0.74 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 205964 kb
Host smart-9bea56fe-8131-408a-91bf-359a58b77a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455596759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3455596759
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3852977135
Short name T244
Test name
Test status
Simulation time 66991132 ps
CPU time 2.76 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 214488 kb
Host smart-90614b93-c5b8-486a-b18f-aa8e4fd0afb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852977135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3852977135
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.271697343
Short name T16
Test name
Test status
Simulation time 27277487 ps
CPU time 2.07 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 218400 kb
Host smart-b60f15be-de62-44b6-a631-a55e5f4d73a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271697343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.271697343
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4159234256
Short name T103
Test name
Test status
Simulation time 456933229 ps
CPU time 4.97 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 209620 kb
Host smart-24d9a3f4-e10f-4c8a-86cf-7bcded1bae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159234256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4159234256
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1334713777
Short name T253
Test name
Test status
Simulation time 126486529 ps
CPU time 3.42 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 214440 kb
Host smart-d0912c22-be41-4235-a433-42d108133d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334713777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1334713777
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2773559812
Short name T48
Test name
Test status
Simulation time 63791849 ps
CPU time 3.37 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 214396 kb
Host smart-d0b2cc3a-0f7e-4923-92f4-841d83544da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773559812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2773559812
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3941841156
Short name T324
Test name
Test status
Simulation time 74509966 ps
CPU time 3.66 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 218460 kb
Host smart-e8be2d9a-e6da-45ac-81e5-aa49bdf2f454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941841156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3941841156
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.257138464
Short name T824
Test name
Test status
Simulation time 92673766 ps
CPU time 2.92 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 206800 kb
Host smart-72f53502-6664-4143-9d8f-b4e66c36cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257138464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.257138464
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.353154808
Short name T655
Test name
Test status
Simulation time 1175514787 ps
CPU time 5.53 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208852 kb
Host smart-51675af1-290a-4b35-bf3d-14555e8214b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353154808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.353154808
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1411009547
Short name T745
Test name
Test status
Simulation time 2523554116 ps
CPU time 6.48 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 208404 kb
Host smart-b68f36c7-194c-43cc-a6b2-ce3411e6983c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411009547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1411009547
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1270448228
Short name T259
Test name
Test status
Simulation time 24451814 ps
CPU time 1.92 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 207392 kb
Host smart-e799772f-e18c-40d3-a8e3-69ebfbe4bba6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270448228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1270448228
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2552333888
Short name T439
Test name
Test status
Simulation time 2307102099 ps
CPU time 14.97 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:39 PM PDT 24
Peak memory 209344 kb
Host smart-81ba1dd9-46ed-41b1-bd38-a309ac8dd3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552333888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2552333888
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2771130865
Short name T615
Test name
Test status
Simulation time 328339133 ps
CPU time 3.79 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208876 kb
Host smart-975797a1-aeb3-4a90-a5f2-33a5e5dbd7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771130865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2771130865
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3834540801
Short name T374
Test name
Test status
Simulation time 93931429 ps
CPU time 6.52 seconds
Started May 11 03:53:08 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 220092 kb
Host smart-0a89244e-902d-4842-a4f1-41da070ef6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834540801 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3834540801
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.913266528
Short name T247
Test name
Test status
Simulation time 62654070 ps
CPU time 4.09 seconds
Started May 11 03:53:10 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 222540 kb
Host smart-4e089526-97cc-4473-8b02-ee0112589cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913266528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.913266528
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.983029279
Short name T1066
Test name
Test status
Simulation time 11161237 ps
CPU time 0.73 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:24 PM PDT 24
Peak memory 205896 kb
Host smart-9e8fd207-aa60-48ab-92f0-5286b42e7547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983029279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.983029279
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3260775254
Short name T437
Test name
Test status
Simulation time 38575836 ps
CPU time 3.13 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 214508 kb
Host smart-688cdc5d-64dd-4038-bd37-604311cc8860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260775254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3260775254
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4110331631
Short name T8
Test name
Test status
Simulation time 1033234792 ps
CPU time 35.09 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:59 PM PDT 24
Peak memory 223044 kb
Host smart-2f219c73-d7e1-40c2-91f2-08270f689361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110331631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4110331631
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.735050896
Short name T808
Test name
Test status
Simulation time 463694612 ps
CPU time 2.55 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 210016 kb
Host smart-ff080a34-41d7-4726-b5d4-c6bb87fd2d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735050896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.735050896
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3700399563
Short name T101
Test name
Test status
Simulation time 269121485 ps
CPU time 6.24 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 221576 kb
Host smart-b3e9c390-674e-4883-a564-f1c84bee7ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700399563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3700399563
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4118897552
Short name T703
Test name
Test status
Simulation time 81795575 ps
CPU time 2.43 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 220380 kb
Host smart-dce79000-7712-45bd-b0be-bb967f1a6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118897552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4118897552
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4070628806
Short name T739
Test name
Test status
Simulation time 69682119 ps
CPU time 3.85 seconds
Started May 11 03:53:13 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208800 kb
Host smart-40c91693-1516-41ac-826a-84bfd4eb1926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070628806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4070628806
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.225037527
Short name T672
Test name
Test status
Simulation time 47089842 ps
CPU time 1.92 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:25 PM PDT 24
Peak memory 206960 kb
Host smart-94ecf8be-1d10-4c05-9da2-a41989f34720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225037527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.225037527
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2824704125
Short name T605
Test name
Test status
Simulation time 197443792 ps
CPU time 2.76 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 207024 kb
Host smart-f324307d-2e71-4394-8cab-338f003c4049
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824704125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2824704125
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3843861436
Short name T938
Test name
Test status
Simulation time 767415864 ps
CPU time 5.67 seconds
Started May 11 03:53:11 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208960 kb
Host smart-f22c73de-33d3-4f7c-ac23-753383e751e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843861436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3843861436
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.505541252
Short name T1076
Test name
Test status
Simulation time 719557299 ps
CPU time 8.16 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:33 PM PDT 24
Peak memory 208976 kb
Host smart-127e0da1-0a5d-428e-b912-45759eedcac4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505541252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.505541252
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1698227575
Short name T850
Test name
Test status
Simulation time 443088246 ps
CPU time 2.22 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 209912 kb
Host smart-31de5065-8dd4-4b3b-b8e8-37f19cf9d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698227575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1698227575
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4001289764
Short name T828
Test name
Test status
Simulation time 213978089 ps
CPU time 4.6 seconds
Started May 11 03:53:09 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 208556 kb
Host smart-14353b0d-7d20-40cd-a990-584ac8e89094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001289764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4001289764
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3390146033
Short name T1053
Test name
Test status
Simulation time 183475094 ps
CPU time 3.4 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 222832 kb
Host smart-68b34f3a-0502-43e1-bad9-a9c87edd5dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390146033 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3390146033
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2334007492
Short name T871
Test name
Test status
Simulation time 711067692 ps
CPU time 7.82 seconds
Started May 11 03:53:12 PM PDT 24
Finished May 11 03:53:32 PM PDT 24
Peak memory 218536 kb
Host smart-23dac6bf-2684-4980-80ec-0ee83a4522c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334007492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2334007492
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2358664235
Short name T802
Test name
Test status
Simulation time 12792437 ps
CPU time 0.74 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:26 PM PDT 24
Peak memory 205984 kb
Host smart-d8a6db69-4605-4062-9c0f-50ad050061d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358664235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2358664235
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.539057574
Short name T414
Test name
Test status
Simulation time 273411781 ps
CPU time 15.24 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:53:40 PM PDT 24
Peak memory 214500 kb
Host smart-6ae5db73-875c-42fb-94af-886150b927a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539057574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.539057574
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.977763879
Short name T34
Test name
Test status
Simulation time 190171958 ps
CPU time 3.39 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 208664 kb
Host smart-a79a1063-19cc-4a69-9c83-01551a525cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977763879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.977763879
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1547880303
Short name T74
Test name
Test status
Simulation time 1958483384 ps
CPU time 18.29 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:43 PM PDT 24
Peak memory 209820 kb
Host smart-d6b84176-3625-4849-8398-fd010ed897a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547880303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1547880303
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1168150833
Short name T1058
Test name
Test status
Simulation time 4973753615 ps
CPU time 54.56 seconds
Started May 11 03:53:17 PM PDT 24
Finished May 11 03:54:20 PM PDT 24
Peak memory 214364 kb
Host smart-c70802c3-5dca-4e29-8357-bce3eb79b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168150833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1168150833
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.111637351
Short name T368
Test name
Test status
Simulation time 130553016 ps
CPU time 4.33 seconds
Started May 11 03:53:21 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 222592 kb
Host smart-4a994218-f112-4dec-8bf9-359fdd0a42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111637351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.111637351
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4119771605
Short name T320
Test name
Test status
Simulation time 258876589 ps
CPU time 4.26 seconds
Started May 11 03:53:17 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 222684 kb
Host smart-e20f4bb6-4360-40aa-a823-8550748bffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119771605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4119771605
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.644123431
Short name T923
Test name
Test status
Simulation time 23638957916 ps
CPU time 48.14 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:54:13 PM PDT 24
Peak memory 209448 kb
Host smart-f940b061-e6a5-46d2-94b4-79c744b6ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644123431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.644123431
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3001030420
Short name T997
Test name
Test status
Simulation time 1141641793 ps
CPU time 37.94 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:54:05 PM PDT 24
Peak memory 208224 kb
Host smart-1ae31d74-4be0-4a25-94d3-648286cbef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001030420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3001030420
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1572086116
Short name T112
Test name
Test status
Simulation time 1362547277 ps
CPU time 17.39 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:43 PM PDT 24
Peak memory 208376 kb
Host smart-7a5e6bd9-44b1-4f09-8e1f-12912f577fc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572086116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1572086116
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3079558662
Short name T357
Test name
Test status
Simulation time 178224735 ps
CPU time 3.73 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 206972 kb
Host smart-422c813c-016a-4ec3-950e-4f59c0a584c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079558662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3079558662
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3712626247
Short name T623
Test name
Test status
Simulation time 124103081 ps
CPU time 3.13 seconds
Started May 11 03:53:15 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208488 kb
Host smart-aa6ffc21-195e-45c4-ab92-b470e605e004
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712626247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3712626247
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2491666685
Short name T1067
Test name
Test status
Simulation time 263781218 ps
CPU time 4.08 seconds
Started May 11 03:53:17 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 218440 kb
Host smart-919e2063-77fd-4462-8d0c-bec9ac5ec341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491666685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2491666685
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2879704700
Short name T645
Test name
Test status
Simulation time 132622255 ps
CPU time 3.82 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 206576 kb
Host smart-79c887f8-53cb-465a-81fa-2a42ac148c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879704700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2879704700
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.411850008
Short name T330
Test name
Test status
Simulation time 254082343 ps
CPU time 10.13 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:53:36 PM PDT 24
Peak memory 218984 kb
Host smart-d049f0db-c8df-4f98-8ff6-a766d97f28cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411850008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.411850008
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.931659002
Short name T413
Test name
Test status
Simulation time 122103582 ps
CPU time 2.53 seconds
Started May 11 03:53:19 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 222224 kb
Host smart-07ee9607-928c-4ccd-b647-a615a148b83c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931659002 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.931659002
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.182968086
Short name T926
Test name
Test status
Simulation time 269472107 ps
CPU time 4.13 seconds
Started May 11 03:53:19 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 210032 kb
Host smart-7818ccc1-d12c-4c13-924b-069f0435d153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182968086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.182968086
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3721505022
Short name T849
Test name
Test status
Simulation time 50376754 ps
CPU time 1.96 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 210092 kb
Host smart-e771beb0-acfc-41db-86c3-de38231f5565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721505022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3721505022
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1075446184
Short name T692
Test name
Test status
Simulation time 9089680 ps
CPU time 0.79 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 205928 kb
Host smart-7230a9c1-800e-470f-9e6f-0901471a3ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075446184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1075446184
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3352666747
Short name T288
Test name
Test status
Simulation time 155681747 ps
CPU time 4.82 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:53:32 PM PDT 24
Peak memory 214516 kb
Host smart-26c17411-49dd-4e91-91d5-a74594ba8dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352666747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3352666747
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.910810235
Short name T925
Test name
Test status
Simulation time 526526700 ps
CPU time 9.37 seconds
Started May 11 03:53:22 PM PDT 24
Finished May 11 03:53:36 PM PDT 24
Peak memory 218624 kb
Host smart-907424ad-c052-4ab3-9ab7-32b5621ca1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910810235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.910810235
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1331844297
Short name T70
Test name
Test status
Simulation time 55466229 ps
CPU time 2.35 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208512 kb
Host smart-a64d752b-6438-4abb-8942-96ef52e36da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331844297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1331844297
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4292419293
Short name T100
Test name
Test status
Simulation time 32659392 ps
CPU time 2.38 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208664 kb
Host smart-d5895793-83e7-4dda-ad80-69cfa4909801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292419293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4292419293
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2033770965
Short name T299
Test name
Test status
Simulation time 435009702 ps
CPU time 5.5 seconds
Started May 11 03:53:21 PM PDT 24
Finished May 11 03:53:32 PM PDT 24
Peak memory 214528 kb
Host smart-f488b573-c5d9-410e-a332-fba4486678a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033770965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2033770965
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.3147772072
Short name T996
Test name
Test status
Simulation time 164648331 ps
CPU time 2.46 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:28 PM PDT 24
Peak memory 208308 kb
Host smart-d8f6a6dd-fca5-499c-abb4-5f14fcd96e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147772072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3147772072
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3767112677
Short name T620
Test name
Test status
Simulation time 122599301 ps
CPU time 3.1 seconds
Started May 11 03:53:18 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 208164 kb
Host smart-b32fe763-9d27-4117-8417-0d166eadf8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767112677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3767112677
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3337952535
Short name T409
Test name
Test status
Simulation time 341032709 ps
CPU time 4.33 seconds
Started May 11 03:53:23 PM PDT 24
Finished May 11 03:53:32 PM PDT 24
Peak memory 207204 kb
Host smart-dcba0b74-8133-4ffa-8f92-c7957bb95adb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337952535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3337952535
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4185482538
Short name T662
Test name
Test status
Simulation time 271131301 ps
CPU time 8.45 seconds
Started May 11 03:53:17 PM PDT 24
Finished May 11 03:53:34 PM PDT 24
Peak memory 208332 kb
Host smart-a79e8f87-aa86-4d7e-86cc-9d8e1f20c0e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185482538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4185482538
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.158321117
Short name T1075
Test name
Test status
Simulation time 203703748 ps
CPU time 3.02 seconds
Started May 11 03:53:24 PM PDT 24
Finished May 11 03:53:31 PM PDT 24
Peak memory 207012 kb
Host smart-bf74b04d-4f5d-43db-be4e-3b119ccf0e21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158321117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.158321117
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4280718814
Short name T889
Test name
Test status
Simulation time 50518176 ps
CPU time 2.29 seconds
Started May 11 03:53:21 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 215764 kb
Host smart-c5f83f96-eaa6-4964-a4fc-0da9367c7e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280718814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4280718814
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3985577770
Short name T676
Test name
Test status
Simulation time 103478583 ps
CPU time 2.07 seconds
Started May 11 03:53:16 PM PDT 24
Finished May 11 03:53:27 PM PDT 24
Peak memory 208584 kb
Host smart-3d81189a-c99f-42fe-81f0-a74d6fb4038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985577770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3985577770
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1664289509
Short name T654
Test name
Test status
Simulation time 503495385 ps
CPU time 9.2 seconds
Started May 11 03:53:22 PM PDT 24
Finished May 11 03:53:36 PM PDT 24
Peak memory 222696 kb
Host smart-a943c7df-85f7-4dba-9607-26655adf0fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664289509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1664289509
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3098294386
Short name T329
Test name
Test status
Simulation time 93328053 ps
CPU time 4.01 seconds
Started May 11 03:53:20 PM PDT 24
Finished May 11 03:53:30 PM PDT 24
Peak memory 208672 kb
Host smart-ef1ee8e7-d0cb-431e-92b2-ea0f1ad2a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098294386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3098294386
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1489287217
Short name T586
Test name
Test status
Simulation time 41462419 ps
CPU time 2.16 seconds
Started May 11 03:53:22 PM PDT 24
Finished May 11 03:53:29 PM PDT 24
Peak memory 210316 kb
Host smart-626c39bc-5865-4aa6-8e20-9083534eb41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489287217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1489287217
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3002051459
Short name T673
Test name
Test status
Simulation time 41725889 ps
CPU time 0.74 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:35 PM PDT 24
Peak memory 205996 kb
Host smart-13366db0-ec21-43e0-8d89-c4ee8049cfb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002051459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3002051459
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3229429868
Short name T948
Test name
Test status
Simulation time 63911726 ps
CPU time 3.33 seconds
Started May 11 03:50:36 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 208972 kb
Host smart-4bae23e4-787a-4841-a14f-4b548f77e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229429868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3229429868
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3915626679
Short name T65
Test name
Test status
Simulation time 16725053 ps
CPU time 1.41 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:50:28 PM PDT 24
Peak memory 207804 kb
Host smart-1f1fa739-d361-4b42-87d9-020a859171c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915626679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3915626679
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2706947943
Short name T619
Test name
Test status
Simulation time 145178276 ps
CPU time 6.18 seconds
Started May 11 03:50:26 PM PDT 24
Finished May 11 03:50:32 PM PDT 24
Peak memory 220644 kb
Host smart-b5d95898-a958-4c95-9354-70565f6bba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706947943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2706947943
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3003090217
Short name T984
Test name
Test status
Simulation time 278209325 ps
CPU time 7.65 seconds
Started May 11 03:50:28 PM PDT 24
Finished May 11 03:50:36 PM PDT 24
Peak memory 218064 kb
Host smart-5b23f3ec-797c-4529-a381-5ee46b866e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003090217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3003090217
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3907113511
Short name T627
Test name
Test status
Simulation time 230433898 ps
CPU time 2.64 seconds
Started May 11 03:50:29 PM PDT 24
Finished May 11 03:50:32 PM PDT 24
Peak memory 206876 kb
Host smart-db958f17-b420-415f-9fa6-6fcc1b18d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907113511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3907113511
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2896866175
Short name T895
Test name
Test status
Simulation time 253835576 ps
CPU time 5.07 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 206956 kb
Host smart-7b600ea6-7105-45f5-a894-01f96e23b00f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896866175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2896866175
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2756112915
Short name T743
Test name
Test status
Simulation time 333637717 ps
CPU time 4.52 seconds
Started May 11 03:50:30 PM PDT 24
Finished May 11 03:50:34 PM PDT 24
Peak memory 206856 kb
Host smart-a8bd6e0b-ebd2-4524-84e8-9627efb8b29f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756112915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2756112915
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3852724803
Short name T339
Test name
Test status
Simulation time 72805168 ps
CPU time 2.75 seconds
Started May 11 03:50:29 PM PDT 24
Finished May 11 03:50:32 PM PDT 24
Peak memory 207448 kb
Host smart-00afd69d-e423-4dd4-b51f-8f716deb6599
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852724803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3852724803
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3032070472
Short name T1028
Test name
Test status
Simulation time 71565710 ps
CPU time 2.85 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 215640 kb
Host smart-3bca1ab6-b590-4d60-ad59-104fe921a6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032070472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3032070472
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3235074440
Short name T887
Test name
Test status
Simulation time 199727209 ps
CPU time 5.45 seconds
Started May 11 03:50:27 PM PDT 24
Finished May 11 03:50:33 PM PDT 24
Peak memory 207864 kb
Host smart-95cf109f-2fbb-41d2-a896-e5640a0f9056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235074440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3235074440
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3202329897
Short name T72
Test name
Test status
Simulation time 506652198 ps
CPU time 13.3 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:48 PM PDT 24
Peak memory 216748 kb
Host smart-ed71e60d-4e7e-4172-99fc-d55d7b59762b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202329897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3202329897
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.435299658
Short name T667
Test name
Test status
Simulation time 600795521 ps
CPU time 8.12 seconds
Started May 11 03:50:36 PM PDT 24
Finished May 11 03:50:44 PM PDT 24
Peak memory 208764 kb
Host smart-071030dc-c534-4ea8-9de5-5bb57557f706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435299658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.435299658
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.146680129
Short name T1024
Test name
Test status
Simulation time 75123372 ps
CPU time 2.15 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:36 PM PDT 24
Peak memory 210024 kb
Host smart-57b8c862-f90b-4b72-8cf9-d0cd02e80b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146680129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.146680129
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1292721338
Short name T604
Test name
Test status
Simulation time 48872593 ps
CPU time 0.86 seconds
Started May 11 03:50:31 PM PDT 24
Finished May 11 03:50:33 PM PDT 24
Peak memory 206008 kb
Host smart-cb25b89f-4d9f-4f19-a52d-fa016a796082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292721338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1292721338
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1721144367
Short name T840
Test name
Test status
Simulation time 1347250226 ps
CPU time 3.8 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 218952 kb
Host smart-021418ff-6dd1-4b47-a008-245a86f4ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721144367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1721144367
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2662260231
Short name T861
Test name
Test status
Simulation time 215495944 ps
CPU time 3.29 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 214436 kb
Host smart-5a0e5ec8-ed4d-4e2f-89b4-26b29abff212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662260231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2662260231
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2657180200
Short name T85
Test name
Test status
Simulation time 125794998 ps
CPU time 5.46 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 209604 kb
Host smart-33634fed-94b9-4313-9a8f-ac06e463d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657180200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2657180200
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.820193827
Short name T338
Test name
Test status
Simulation time 253971693 ps
CPU time 3.96 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 222504 kb
Host smart-48814500-f349-4922-b2a1-cc2690288e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820193827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.820193827
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3632358840
Short name T927
Test name
Test status
Simulation time 92357405 ps
CPU time 4.14 seconds
Started May 11 03:50:36 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 220200 kb
Host smart-965d3bbe-0fd5-4bbd-a12a-40a0a9a58c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632358840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3632358840
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.942954878
Short name T933
Test name
Test status
Simulation time 36543485 ps
CPU time 2.65 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 208056 kb
Host smart-56ced49a-c760-4be3-a7de-9aa34847a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942954878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.942954878
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1266323910
Short name T290
Test name
Test status
Simulation time 317703411 ps
CPU time 7.69 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:42 PM PDT 24
Peak memory 208032 kb
Host smart-e4c19537-6ff1-48ba-a255-0da7ad2a5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266323910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1266323910
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2191459453
Short name T712
Test name
Test status
Simulation time 66839711 ps
CPU time 2.57 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 208680 kb
Host smart-4abb2cd0-7fde-44f4-852d-650d4ef209a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191459453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2191459453
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4256383144
Short name T1059
Test name
Test status
Simulation time 23542118 ps
CPU time 1.92 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:34 PM PDT 24
Peak memory 206800 kb
Host smart-0dcf50f0-520d-4eae-a39a-9899730240d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256383144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4256383144
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.881659788
Short name T1032
Test name
Test status
Simulation time 22653660 ps
CPU time 1.83 seconds
Started May 11 03:50:32 PM PDT 24
Finished May 11 03:50:35 PM PDT 24
Peak memory 206836 kb
Host smart-16a07ab0-642a-4a45-85a1-76d65154b5ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881659788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.881659788
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2785549571
Short name T84
Test name
Test status
Simulation time 54602229 ps
CPU time 1.98 seconds
Started May 11 03:50:36 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 207600 kb
Host smart-4b901e59-e313-4939-9a02-da25dd49b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785549571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2785549571
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1010284441
Short name T1017
Test name
Test status
Simulation time 1037029602 ps
CPU time 6.3 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 207752 kb
Host smart-736a4d19-a323-4c88-87e4-3c172b97281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010284441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1010284441
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3704444141
Short name T271
Test name
Test status
Simulation time 240951801 ps
CPU time 5.28 seconds
Started May 11 03:50:35 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 206840 kb
Host smart-8fb0c338-1b68-48c9-92dd-62a497fe5e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704444141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3704444141
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1517103135
Short name T217
Test name
Test status
Simulation time 244043912 ps
CPU time 8.92 seconds
Started May 11 03:50:31 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 220852 kb
Host smart-379f9aed-3d16-4d1b-8fa2-841822b7d1b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517103135 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1517103135
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1814643957
Short name T721
Test name
Test status
Simulation time 555302679 ps
CPU time 6.2 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 210428 kb
Host smart-db95636b-5d44-420e-a436-0e0b5b101693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814643957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1814643957
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3180766936
Short name T648
Test name
Test status
Simulation time 307048912 ps
CPU time 3.39 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 210476 kb
Host smart-c4123ed1-ef1e-4422-9164-5c1bd6bfa793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180766936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3180766936
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4089503008
Short name T1070
Test name
Test status
Simulation time 20838238 ps
CPU time 0.86 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:50:45 PM PDT 24
Peak memory 205988 kb
Host smart-35f08302-39df-417f-8f64-6845d1dc7711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089503008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4089503008
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1507053057
Short name T731
Test name
Test status
Simulation time 36956201 ps
CPU time 2.29 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:44 PM PDT 24
Peak memory 218712 kb
Host smart-39420768-7e3c-4f03-8632-2f248359feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507053057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1507053057
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1030694210
Short name T915
Test name
Test status
Simulation time 286232464 ps
CPU time 4.47 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 214512 kb
Host smart-68de07f8-3329-41e2-8b56-865c8612c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030694210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1030694210
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.357374587
Short name T404
Test name
Test status
Simulation time 407616867 ps
CPU time 11.21 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:53 PM PDT 24
Peak memory 214460 kb
Host smart-4a013560-2ac9-48d0-b928-319188d8cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357374587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.357374587
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3206381915
Short name T54
Test name
Test status
Simulation time 204999687 ps
CPU time 3.73 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:45 PM PDT 24
Peak memory 210272 kb
Host smart-5f047211-0f39-4684-8a72-2421e890e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206381915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3206381915
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3822094764
Short name T794
Test name
Test status
Simulation time 85488084 ps
CPU time 4.16 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 218448 kb
Host smart-c7a8e6f8-a62b-4ff4-9b8e-0e5c73bebb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822094764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3822094764
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1247092817
Short name T1068
Test name
Test status
Simulation time 3579174467 ps
CPU time 39.67 seconds
Started May 11 03:50:34 PM PDT 24
Finished May 11 03:51:15 PM PDT 24
Peak memory 208096 kb
Host smart-1e23fc88-4a9c-4272-b55f-145470c64ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247092817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1247092817
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.641914846
Short name T773
Test name
Test status
Simulation time 75244547 ps
CPU time 2.67 seconds
Started May 11 03:50:35 PM PDT 24
Finished May 11 03:50:38 PM PDT 24
Peak memory 208828 kb
Host smart-61ad5206-dd78-45bb-bb34-1df2c22f44d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641914846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.641914846
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2457102874
Short name T223
Test name
Test status
Simulation time 45709657313 ps
CPU time 82.45 seconds
Started May 11 03:50:35 PM PDT 24
Finished May 11 03:51:59 PM PDT 24
Peak memory 208692 kb
Host smart-eb79ce76-d87d-41b8-bc07-1c73d0e02a38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457102874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2457102874
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.845810679
Short name T701
Test name
Test status
Simulation time 984366600 ps
CPU time 8.03 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:49 PM PDT 24
Peak memory 208076 kb
Host smart-9d533827-641b-4fd5-a975-ed2a10289593
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845810679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.845810679
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1916681324
Short name T269
Test name
Test status
Simulation time 168318071 ps
CPU time 5.25 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:49 PM PDT 24
Peak memory 208824 kb
Host smart-8dc74e87-23ee-4bb7-b191-471b130176fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916681324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1916681324
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3655166715
Short name T934
Test name
Test status
Simulation time 67711563 ps
CPU time 3.05 seconds
Started May 11 03:50:33 PM PDT 24
Finished May 11 03:50:37 PM PDT 24
Peak memory 207088 kb
Host smart-5c97161a-b255-4a3d-bca1-62f3cfa1c7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655166715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3655166715
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2214391260
Short name T289
Test name
Test status
Simulation time 1394647072 ps
CPU time 10.7 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:54 PM PDT 24
Peak memory 218460 kb
Host smart-103feffb-23d3-4965-8b31-a8c92ceeabb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214391260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2214391260
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3925008354
Short name T433
Test name
Test status
Simulation time 2042606378 ps
CPU time 7.72 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:51 PM PDT 24
Peak memory 223716 kb
Host smart-d46bff77-d108-43e5-b5fb-4b6748968590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925008354 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3925008354
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2140682490
Short name T400
Test name
Test status
Simulation time 191702251 ps
CPU time 3.63 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 207164 kb
Host smart-8013450c-4890-44fc-b02c-0d50ae9123f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140682490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2140682490
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.344498361
Short name T631
Test name
Test status
Simulation time 198813768 ps
CPU time 1.59 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:50:46 PM PDT 24
Peak memory 209988 kb
Host smart-19bf171f-e735-461d-a091-b50bdd2a99cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344498361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.344498361
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3312553152
Short name T909
Test name
Test status
Simulation time 35640939 ps
CPU time 0.74 seconds
Started May 11 03:50:39 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 205948 kb
Host smart-0456a6f2-8699-4dc9-bedc-cc26fd368f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312553152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3312553152
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2761191097
Short name T797
Test name
Test status
Simulation time 193875996 ps
CPU time 2.38 seconds
Started May 11 03:50:38 PM PDT 24
Finished May 11 03:50:40 PM PDT 24
Peak memory 209932 kb
Host smart-2c435039-a9e3-41d4-b57f-9b03de4947e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761191097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2761191097
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3384038675
Short name T898
Test name
Test status
Simulation time 630820249 ps
CPU time 3.41 seconds
Started May 11 03:50:40 PM PDT 24
Finished May 11 03:50:44 PM PDT 24
Peak memory 214496 kb
Host smart-0075edb6-bdd8-429b-8183-ca5415c31a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384038675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3384038675
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3930819138
Short name T340
Test name
Test status
Simulation time 332338058 ps
CPU time 9.65 seconds
Started May 11 03:50:47 PM PDT 24
Finished May 11 03:50:57 PM PDT 24
Peak memory 214500 kb
Host smart-9beb1936-3fd6-4611-aa3d-161851d7ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930819138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3930819138
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.28543031
Short name T5
Test name
Test status
Simulation time 68756809 ps
CPU time 3.52 seconds
Started May 11 03:50:39 PM PDT 24
Finished May 11 03:50:43 PM PDT 24
Peak memory 207372 kb
Host smart-6dd62062-a069-4c31-8a0c-995a27a0d331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28543031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.28543031
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1995613978
Short name T336
Test name
Test status
Simulation time 252338842 ps
CPU time 6.28 seconds
Started May 11 03:50:40 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 214516 kb
Host smart-beee5838-efbc-4723-bb17-9a06f5745e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995613978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1995613978
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1007322315
Short name T381
Test name
Test status
Simulation time 139692547 ps
CPU time 3.87 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 208732 kb
Host smart-9344e170-93fc-426c-8e72-442f68d92da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007322315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1007322315
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2199909341
Short name T987
Test name
Test status
Simulation time 799808010 ps
CPU time 4.97 seconds
Started May 11 03:50:39 PM PDT 24
Finished May 11 03:50:45 PM PDT 24
Peak memory 208024 kb
Host smart-f55a9ecf-273a-4170-9a9a-96d7c1623150
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199909341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2199909341
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1027881915
Short name T719
Test name
Test status
Simulation time 87465912 ps
CPU time 3.47 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:46 PM PDT 24
Peak memory 208636 kb
Host smart-e969bfec-6c87-468b-8afe-fc135a9a8842
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027881915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1027881915
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.221612888
Short name T1001
Test name
Test status
Simulation time 155616231 ps
CPU time 2.34 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:43 PM PDT 24
Peak memory 207012 kb
Host smart-8d7df5e5-1ea8-4c51-9291-597336c54112
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221612888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.221612888
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3649079914
Short name T418
Test name
Test status
Simulation time 152549391 ps
CPU time 4.57 seconds
Started May 11 03:50:41 PM PDT 24
Finished May 11 03:50:46 PM PDT 24
Peak memory 207940 kb
Host smart-fa4518d8-0e69-4f85-a4aa-31e1ac5250f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649079914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3649079914
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3091737691
Short name T1007
Test name
Test status
Simulation time 158447585 ps
CPU time 2.96 seconds
Started May 11 03:50:40 PM PDT 24
Finished May 11 03:50:43 PM PDT 24
Peak memory 208264 kb
Host smart-d169b16c-e758-4e9d-a5f6-d92de0df11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091737691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3091737691
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2124291849
Short name T347
Test name
Test status
Simulation time 1096684271 ps
CPU time 36.64 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:51:19 PM PDT 24
Peak memory 220772 kb
Host smart-a1684355-04b0-4da5-aa50-be6a4f674bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124291849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2124291849
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2225425047
Short name T359
Test name
Test status
Simulation time 1521913194 ps
CPU time 9.1 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:50:51 PM PDT 24
Peak memory 222784 kb
Host smart-e6a2dc82-74c3-42e8-8073-8e61c86eecbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225425047 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2225425047
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2296112642
Short name T1064
Test name
Test status
Simulation time 1242727083 ps
CPU time 43.61 seconds
Started May 11 03:50:42 PM PDT 24
Finished May 11 03:51:26 PM PDT 24
Peak memory 210764 kb
Host smart-f9e99db8-c6ab-42eb-a8b0-5ee88899e891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296112642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2296112642
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1744437896
Short name T806
Test name
Test status
Simulation time 1483627157 ps
CPU time 3.7 seconds
Started May 11 03:50:39 PM PDT 24
Finished May 11 03:50:43 PM PDT 24
Peak memory 209948 kb
Host smart-ad67f4fc-a167-479e-835b-59b1f6da1c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744437896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1744437896
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.462304554
Short name T963
Test name
Test status
Simulation time 53558528 ps
CPU time 0.94 seconds
Started May 11 03:50:46 PM PDT 24
Finished May 11 03:50:48 PM PDT 24
Peak memory 206104 kb
Host smart-026dee2d-58f1-442b-8b91-92927cedf131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462304554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.462304554
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.331580792
Short name T431
Test name
Test status
Simulation time 223679130 ps
CPU time 4.45 seconds
Started May 11 03:50:45 PM PDT 24
Finished May 11 03:50:50 PM PDT 24
Peak memory 214384 kb
Host smart-7e094754-407d-4b7e-ae8b-ab169043845c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331580792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.331580792
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1984392182
Short name T19
Test name
Test status
Simulation time 420355250 ps
CPU time 4.14 seconds
Started May 11 03:50:50 PM PDT 24
Finished May 11 03:50:55 PM PDT 24
Peak memory 210632 kb
Host smart-526a490a-c9cb-400c-85eb-08fc684cf721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984392182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1984392182
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1010301143
Short name T896
Test name
Test status
Simulation time 2347241190 ps
CPU time 23.37 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:51:08 PM PDT 24
Peak memory 209496 kb
Host smart-667320f0-f3d2-43f2-936b-7d1fcc2850e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010301143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1010301143
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1328672243
Short name T25
Test name
Test status
Simulation time 11394228411 ps
CPU time 109.06 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:52:33 PM PDT 24
Peak memory 214476 kb
Host smart-b71f4278-ab0d-495f-b170-ab48b71359db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328672243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1328672243
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3624260971
Short name T791
Test name
Test status
Simulation time 371915089 ps
CPU time 5.93 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:50:50 PM PDT 24
Peak memory 214440 kb
Host smart-3d45b2bd-688f-4644-aa92-5c9a0a13a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624260971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3624260971
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1017300942
Short name T252
Test name
Test status
Simulation time 64438491 ps
CPU time 4.05 seconds
Started May 11 03:50:43 PM PDT 24
Finished May 11 03:50:48 PM PDT 24
Peak memory 214484 kb
Host smart-acab55dd-14da-4113-aee2-dffdfbd4314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017300942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1017300942
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.202972984
Short name T679
Test name
Test status
Simulation time 503642321 ps
CPU time 13.68 seconds
Started May 11 03:50:45 PM PDT 24
Finished May 11 03:50:59 PM PDT 24
Peak memory 208876 kb
Host smart-02e6f54e-cc4e-44c7-a154-674c5f89cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202972984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.202972984
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2914697149
Short name T246
Test name
Test status
Simulation time 52077122 ps
CPU time 2.95 seconds
Started May 11 03:50:46 PM PDT 24
Finished May 11 03:50:49 PM PDT 24
Peak memory 208812 kb
Host smart-9ca44992-a5b5-4cc0-88c8-b8ef2728982a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914697149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2914697149
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.949148597
Short name T781
Test name
Test status
Simulation time 232806827 ps
CPU time 7.61 seconds
Started May 11 03:50:45 PM PDT 24
Finished May 11 03:50:53 PM PDT 24
Peak memory 208108 kb
Host smart-12adbf15-d92f-4a02-b547-198988de2d63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949148597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.949148597
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3468676392
Short name T591
Test name
Test status
Simulation time 2717209367 ps
CPU time 26.3 seconds
Started May 11 03:50:45 PM PDT 24
Finished May 11 03:51:11 PM PDT 24
Peak memory 209104 kb
Host smart-0fbaaeec-ce18-4b66-a249-bc4b1919185e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468676392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3468676392
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.647879277
Short name T812
Test name
Test status
Simulation time 768251052 ps
CPU time 4.69 seconds
Started May 11 03:50:50 PM PDT 24
Finished May 11 03:50:55 PM PDT 24
Peak memory 209392 kb
Host smart-0eb01bc3-0722-479b-b357-b1c9fbe4ee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647879277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.647879277
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2627316128
Short name T590
Test name
Test status
Simulation time 126463142 ps
CPU time 2.37 seconds
Started May 11 03:50:44 PM PDT 24
Finished May 11 03:50:47 PM PDT 24
Peak memory 206940 kb
Host smart-7fc09f8f-63c8-4ffa-9a61-c3d60a59527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627316128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2627316128
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2268321172
Short name T817
Test name
Test status
Simulation time 36780047 ps
CPU time 0.97 seconds
Started May 11 03:50:47 PM PDT 24
Finished May 11 03:50:49 PM PDT 24
Peak memory 206100 kb
Host smart-47222b25-c428-458e-981b-8b85475ef6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268321172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2268321172
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2190627530
Short name T109
Test name
Test status
Simulation time 238821489 ps
CPU time 2.53 seconds
Started May 11 03:50:48 PM PDT 24
Finished May 11 03:50:51 PM PDT 24
Peak memory 218172 kb
Host smart-151cbbac-517e-455a-b19f-9ad4cc5c292f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190627530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2190627530
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2453249112
Short name T136
Test name
Test status
Simulation time 9144359215 ps
CPU time 54.94 seconds
Started May 11 03:50:48 PM PDT 24
Finished May 11 03:51:43 PM PDT 24
Peak memory 208660 kb
Host smart-cdc1f135-cd3e-4af1-8c86-e45ef3d6e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453249112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2453249112
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2403152370
Short name T1026
Test name
Test status
Simulation time 2086495492 ps
CPU time 33.04 seconds
Started May 11 03:50:49 PM PDT 24
Finished May 11 03:51:23 PM PDT 24
Peak memory 211192 kb
Host smart-2caea31a-9523-4f93-8ff9-1c8eea8888e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403152370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2403152370
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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