Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
50747 |
1 |
|
|
T1 |
39 |
|
T2 |
15 |
|
T3 |
45 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
30423 |
1 |
|
|
T1 |
39 |
|
T2 |
2 |
|
T3 |
45 |
auto[1] |
20324 |
1 |
|
|
T2 |
13 |
|
T4 |
33 |
|
T15 |
271 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
25155 |
1 |
|
|
T1 |
20 |
|
T2 |
2 |
|
T3 |
23 |
auto[1] |
25592 |
1 |
|
|
T1 |
19 |
|
T2 |
13 |
|
T3 |
22 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
| | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
15043 |
1 |
|
|
T1 |
20 |
|
T2 |
2 |
|
T3 |
23 |
all_values[0] |
auto[0] |
auto[1] |
15380 |
1 |
|
|
T1 |
19 |
|
T3 |
22 |
|
T4 |
1 |
all_values[0] |
auto[1] |
auto[0] |
10112 |
1 |
|
|
T4 |
17 |
|
T15 |
169 |
|
T6 |
179 |
all_values[0] |
auto[1] |
auto[1] |
10212 |
1 |
|
|
T2 |
13 |
|
T4 |
16 |
|
T15 |
102 |