Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
76.19 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 0 14 100.00
Crosses 49 15 34 69.39


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 0 5 100.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 14 21 60.00 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 77 1 T2 1 T15 2 T17 1
auto[OpGenId] 21 1 T107 2 T157 1 T158 1
auto[OpGenSwOut] 25 1 T15 1 T125 1 T198 1
auto[OpGenHwOut] 29 1 T6 1 T7 1 T8 1
auto[OpDisable] 1 1 T199 1 - - - -


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1751 1 T15 4 T6 2 T17 1
auto[StInit] 139 1 T15 2 T6 1 T46 1
auto[StCreatorRootKey] 65 1 T32 1 T47 1 T39 2
auto[StOwnerIntKey] 34 1 T2 1 T15 1 T7 1
auto[StOwnerKey] 32 1 T41 1 T52 1 T33 1
auto[StDisabled] 305 1 T15 8 T6 8 T41 6
auto[StInvalid] 45 1 T22 1 T31 1 T95 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3280 1 T1 1 T2 1 T3 1
auto[1] 153 1 T2 1 T15 3 T6 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1732 1 T15 3 T6 2 T82 4
auto[StReset] auto[1] 19 1 T15 1 T17 1 T82 1
auto[StInit] auto[0] 56 1 T46 1 T108 1 T61 1
auto[StInit] auto[1] 83 1 T15 2 T6 1 T39 1
auto[StCreatorRootKey] auto[0] 40 1 T32 1 T47 1 T39 1
auto[StCreatorRootKey] auto[1] 25 1 T39 1 T107 3 T40 2
auto[StOwnerIntKey] auto[0] 25 1 T15 1 T106 1 T51 1
auto[StOwnerIntKey] auto[1] 9 1 T2 1 T7 1 T8 1
auto[StOwnerKey] auto[0] 28 1 T41 1 T52 1 T33 1
auto[StOwnerKey] auto[1] 4 1 T200 1 T201 1 T202 1
auto[StDisabled] auto[0] 292 1 T15 8 T6 8 T41 6
auto[StDisabled] auto[1] 13 1 T182 1 T183 1 T125 1
auto[StInvalid] auto[0] 45 1 T22 1 T31 1 T95 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 14 21 60.00 14


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 3
[auto[StInit]] [auto[OpDisable]] 0 1 1
[auto[StOwnerIntKey]] [auto[OpGenId]] 0 1 1
[auto[StOwnerIntKey]] [auto[OpDisable]] 0 1 1
[auto[StOwnerKey]] [auto[OpGenSwOut]] 0 1 1
[auto[StOwnerKey]] [auto[OpDisable]] 0 1 1
[auto[StDisabled]] [auto[OpDisable]] 0 1 1


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 18 1 T15 1 T17 1 T82 1
auto[StReset] auto[OpGenId] 1 1 T28 1 - - - -
auto[StInit] auto[OpAdvance] 34 1 T15 1 T39 1 T61 1
auto[StInit] auto[OpGenId] 12 1 T107 1 T157 1 T203 1
auto[StInit] auto[OpGenSwOut] 20 1 T15 1 T204 1 T205 1
auto[StInit] auto[OpGenHwOut] 17 1 T6 1 T61 2 T204 1
auto[StCreatorRootKey] auto[OpAdvance] 15 1 T39 1 T107 1 T40 1
auto[StCreatorRootKey] auto[OpGenId] 5 1 T107 1 T158 1 T206 1
auto[StCreatorRootKey] auto[OpGenSwOut] 1 1 T207 1 - - - -
auto[StCreatorRootKey] auto[OpGenHwOut] 3 1 T107 1 T40 1 T208 1
auto[StCreatorRootKey] auto[OpDisable] 1 1 T199 1 - - - -
auto[StOwnerIntKey] auto[OpAdvance] 4 1 T2 1 T61 1 T209 1
auto[StOwnerIntKey] auto[OpGenSwOut] 1 1 T210 1 - - - -
auto[StOwnerIntKey] auto[OpGenHwOut] 4 1 T7 1 T8 1 T211 1
auto[StOwnerKey] auto[OpAdvance] 2 1 T200 1 T212 1 - -
auto[StOwnerKey] auto[OpGenId] 1 1 T202 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T201 1 - - - -
auto[StDisabled] auto[OpAdvance] 4 1 T201 1 T213 1 T214 1
auto[StDisabled] auto[OpGenId] 2 1 T215 1 T216 1 - -
auto[StDisabled] auto[OpGenSwOut] 3 1 T125 1 T198 1 T217 1
auto[StDisabled] auto[OpGenHwOut] 4 1 T182 1 T183 1 T218 1