Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10695

1

T1

4

T2

5

T3

12

auto[Attestation]

7241

1

T1

7

T2

5

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2569	1			T2	3		T3	1		T4	1
auto[Aes]	3367	1			T1	2		T2	2		T3	1
auto[Kmac]	3230	1			T1	3		T2	2		T3	4
auto[Otbn]	3280	1			T1	1		T2	3		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7099	1			T1	8		T2	3		T3	8
auto[OpGenId]	5490	1			T1	5		T3	7		T4	4
auto[OpGenSwOut]	5596	1			T1	6		T2	6		T3	7
auto[OpGenHwOut]	6850	1			T2	4		T4	1		T5	3
auto[OpDisable]	111	1			T6	2		T41	1		T42	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9256

1

T1

8

T2

12

T3

8

auto[OpDoneFail]

15890

1

T1

11

T2

1

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5876	1			T1	4		T2	1		T3	7
auto[StInit]	4122	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	2750	1			T1	2		T2	5		T3	2
auto[StOwnerIntKey]	2365	1			T1	2		T2	5		T3	2
auto[StOwnerKey]	2171	1			T1	2		T3	2		T4	2
auto[StDisabled]	6821	1			T1	7		T3	7		T4	7
auto[StInvalid]	1041	1			T22	25		T31	15		T95	21

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	295	1			T15	11		T18	2		T41	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	131	1			T3	1		T16	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T6	1		T41	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T2	1		T15	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T33	1		T39	2		T177	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	145	1			T5	1		T15	2		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	41	1			T22	3		T178	1		T179	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T15	3		T6	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T5	1		T15	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	70	1			T30	1		T38	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	56	1			T4	1		T15	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	42	1			T6	1		T39	2		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	209	1			T4	2		T6	2		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	30	1			T31	2		T95	3		T179	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	295	1			T1	1		T3	3		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T15	1		T22	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T15	2		T33	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T2	1		T15	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	48	1			T3	1		T30	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	198	1			T15	2		T6	2		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T22	1		T31	1		T179	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	306	1			T3	1		T15	3		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	113	1			T15	1		T30	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T15	1		T38	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	49	1			T6	1		T51	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T38	1		T121	1		T41	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	201	1			T15	5		T6	2		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T178	3		T100	2		T180	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T41	1		T39	2		T40	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	124	1			T16	2		T6	2		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	65	1			T2	1		T4	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T2	1		T15	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T15	1		T6	3		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	193	1			T15	4		T6	3		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	22	1			T22	1		T95	3		T179	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T39	2		T61	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T16	2		T6	2		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T1	1		T15	2		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	54	1			T6	1		T39	3		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	51	1			T15	3		T6	3		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	177	1			T1	1		T3	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	19	1			T95	1		T178	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T39	1		T40	5		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T15	1		T16	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T5	1		T6	3		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	57	1			T2	1		T124	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T1	1		T15	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	179	1			T1	1		T15	2		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T22	1		T178	3		T179	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T41	1		T39	2		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T15	2		T16	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T23	1		T48	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	55	1			T2	1		T6	3		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	57	1			T5	1		T15	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	188	1			T1	1		T15	3		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T22	1		T178	4		T99	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	267	1			T15	4		T6	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	117	1			T15	2		T16	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	52	1			T15	1		T54	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	49	1			T6	1		T18	1		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T15	1		T39	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	155	1			T15	5		T6	1		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	40	1			T22	3		T95	2		T185	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	488	1			T15	3		T6	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	145	1			T2	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	113	1			T6	2		T7	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	102	1			T15	2		T6	2		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T39	1		T187	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	246	1			T15	2		T6	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	40	1			T22	1		T178	3		T179	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	454	1			T15	2		T6	3		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T7	1		T121	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T15	2		T41	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T15	1		T18	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	82	1			T41	1		T188	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	227	1			T15	1		T18	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T22	1		T95	1		T178	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	395	1			T15	2		T18	1		T22	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T15	1		T22	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T2	2		T190	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T190	1		T33	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T39	1		T191	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	268	1			T4	1		T15	4		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	31	1			T22	1		T31	1		T178	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	46	1			T41	2		T39	3		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	93	1			T16	1		T6	1		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	56	1			T41	1		T53	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	49	1			T15	3		T193	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T18	1		T41	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	139	1			T15	2		T6	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T99	2		T181	3		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	46	1			T41	1		T39	3		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	143	1			T22	1		T39	4		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	106	1			T2	1		T6	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T41	1		T39	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	81	1			T39	2		T194	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	263	1			T5	1		T15	1		T121	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	34	1			T178	2		T179	1		T99	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	50	1			T39	4		T40	1		T182	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T6	1		T41	1		T39	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T5	1		T15	2		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T15	1		T189	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	89	1			T15	1		T39	2		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	261	1			T15	2		T6	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T178	3		T179	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T39	2		T107	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	152	1			T15	1		T6	3		T121	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T6	1		T41	1		T186	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T15	1		T18	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	100	1			T38	1		T41	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	249	1			T5	1		T15	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T31	1		T99	1		T181	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T2	1		T15	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	626	1			T3	1		T5	1		T15	13
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	159	1			T4	1		T15	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	681	1			T4	2		T5	1		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T2	1		T3	1		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	638	1			T1	1		T3	3		T15	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	168	1			T15	1		T6	1		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	673	1			T3	1		T15	9		T6	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	161	1			T2	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	420	1			T15	5		T16	2		T6	8
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	173	1			T1	1		T15	5		T6	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	379	1			T1	1		T3	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T1	1		T2	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	393	1			T1	1		T15	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	184	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	409	1			T1	1		T15	5		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	148	1			T15	1		T6	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	587	1			T15	12		T16	2		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	290	1			T15	2		T6	4		T7	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	932	1			T2	1		T15	7		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	248	1			T15	3		T18	1		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	854	1			T15	3		T6	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	256	1			T2	2		T190	2		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	823	1			T4	1		T15	7		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	142	1			T15	1		T18	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	322	1			T15	4		T16	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	254	1			T2	1		T6	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	499	1			T5	1		T15	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	248	1			T5	1		T15	3		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	480	1			T15	3		T6	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T15	1		T18	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	495	1			T5	1		T15	3		T6	5