Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28875

1

T1

21

T2

16

T3

26

auto[1]

303

1

T18

10

T38

14

T124

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	28885	1			T1	21		T2	16		T3	26
auto[134217728:268435455]	8	1			T18	1		T38	1		T75	1
auto[268435456:402653183]	8	1			T38	1		T75	1		T360	1
auto[402653184:536870911]	9	1			T124	1		T371	1		T396	1
auto[536870912:671088639]	9	1			T265	1		T277	1		T397	1
auto[671088640:805306367]	13	1			T38	1		T219	1		T360	1
auto[805306368:939524095]	7	1			T38	1		T219	1		T362	1
auto[939524096:1073741823]	8	1			T18	1		T371	1		T398	1
auto[1073741824:1207959551]	16	1			T18	2		T75	1		T240	1
auto[1207959552:1342177279]	10	1			T301	3		T371	1		T398	1
auto[1342177280:1476395007]	11	1			T75	1		T362	1		T396	1
auto[1476395008:1610612735]	8	1			T18	1		T124	2		T219	1
auto[1610612736:1744830463]	8	1			T220	1		T267	1		T278	1
auto[1744830464:1879048191]	12	1			T124	1		T360	1		T362	1
auto[1879048192:2013265919]	5	1			T371	2		T268	1		T267	1
auto[2013265920:2147483647]	10	1			T18	1		T124	1		T75	1
auto[2147483648:2281701375]	4	1			T124	1		T371	1		T277	1
auto[2281701376:2415919103]	8	1			T38	1		T265	1		T325	1
auto[2415919104:2550136831]	8	1			T38	3		T75	1		T79	1
auto[2550136832:2684354559]	11	1			T18	1		T75	1		T219	1
auto[2684354560:2818572287]	12	1			T38	1		T75	1		T240	1
auto[2818572288:2952790015]	12	1			T38	2		T360	1		T398	1
auto[2952790016:3087007743]	11	1			T38	1		T124	1		T253	1
auto[3087007744:3221225471]	9	1			T277	1		T267	1		T399	2
auto[3221225472:3355443199]	11	1			T75	1		T79	1		T301	1
auto[3355443200:3489660927]	13	1			T124	1		T75	2		T79	1
auto[3489660928:3623878655]	10	1			T75	2		T400	1		T220	1
auto[3623878656:3758096383]	4	1			T360	1		T240	1		T401	1
auto[3758096384:3892314111]	5	1			T38	1		T265	1		T398	1
auto[3892314112:4026531839]	9	1			T18	2		T38	1		T75	1
auto[4026531840:4160749567]	16	1			T18	1		T75	1		T360	2
auto[4160749568:4294967295]	8	1			T219	1		T371	2		T255	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	28875	1			T1	21		T2	16		T3	26
auto[0:134217727]	auto[1]	10	1			T265	1		T360	2		T277	1
auto[134217728:268435455]	auto[1]	8	1			T18	1		T38	1		T75	1
auto[268435456:402653183]	auto[1]	8	1			T38	1		T75	1		T360	1
auto[402653184:536870911]	auto[1]	9	1			T124	1		T371	1		T396	1
auto[536870912:671088639]	auto[1]	9	1			T265	1		T277	1		T397	1
auto[671088640:805306367]	auto[1]	13	1			T38	1		T219	1		T360	1
auto[805306368:939524095]	auto[1]	7	1			T38	1		T219	1		T362	1
auto[939524096:1073741823]	auto[1]	8	1			T18	1		T371	1		T398	1
auto[1073741824:1207959551]	auto[1]	16	1			T18	2		T75	1		T240	1
auto[1207959552:1342177279]	auto[1]	10	1			T301	3		T371	1		T398	1
auto[1342177280:1476395007]	auto[1]	11	1			T75	1		T362	1		T396	1
auto[1476395008:1610612735]	auto[1]	8	1			T18	1		T124	2		T219	1
auto[1610612736:1744830463]	auto[1]	8	1			T220	1		T267	1		T278	1
auto[1744830464:1879048191]	auto[1]	12	1			T124	1		T360	1		T362	1
auto[1879048192:2013265919]	auto[1]	5	1			T371	2		T268	1		T267	1
auto[2013265920:2147483647]	auto[1]	10	1			T18	1		T124	1		T75	1
auto[2147483648:2281701375]	auto[1]	4	1			T124	1		T371	1		T277	1
auto[2281701376:2415919103]	auto[1]	8	1			T38	1		T265	1		T325	1
auto[2415919104:2550136831]	auto[1]	8	1			T38	3		T75	1		T79	1
auto[2550136832:2684354559]	auto[1]	11	1			T18	1		T75	1		T219	1
auto[2684354560:2818572287]	auto[1]	12	1			T38	1		T75	1		T240	1
auto[2818572288:2952790015]	auto[1]	12	1			T38	2		T360	1		T398	1
auto[2952790016:3087007743]	auto[1]	11	1			T38	1		T124	1		T253	1
auto[3087007744:3221225471]	auto[1]	9	1			T277	1		T267	1		T399	2
auto[3221225472:3355443199]	auto[1]	11	1			T75	1		T79	1		T301	1
auto[3355443200:3489660927]	auto[1]	13	1			T124	1		T75	2		T79	1
auto[3489660928:3623878655]	auto[1]	10	1			T75	2		T400	1		T220	1
auto[3623878656:3758096383]	auto[1]	4	1			T360	1		T240	1		T401	1
auto[3758096384:3892314111]	auto[1]	5	1			T38	1		T265	1		T398	1
auto[3892314112:4026531839]	auto[1]	9	1			T18	2		T38	1		T75	1
auto[4026531840:4160749567]	auto[1]	16	1			T18	1		T75	1		T360	2
auto[4160749568:4294967295]	auto[1]	8	1			T219	1		T371	2		T255	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1490

1

T2

1

T5

1

T15

21

auto[1]

1648

1

T2

2

T5

1

T15

20

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T15	2		T38	1		T23	1
auto[134217728:268435455]	92	1			T15	1		T41	3		T39	2
auto[268435456:402653183]	106	1			T15	1		T18	1		T41	2
auto[402653184:536870911]	112	1			T15	1		T18	1		T22	2
auto[536870912:671088639]	108	1			T15	2		T18	1		T22	1
auto[671088640:805306367]	102	1			T2	1		T5	1		T15	1
auto[805306368:939524095]	105	1			T15	3		T32	1		T41	1
auto[939524096:1073741823]	102	1			T2	1		T15	3		T16	1
auto[1073741824:1207959551]	103	1			T15	2		T16	1		T22	1
auto[1207959552:1342177279]	112	1			T6	2		T46	1		T23	1
auto[1342177280:1476395007]	104	1			T15	2		T32	1		T22	1
auto[1476395008:1610612735]	98	1			T15	1		T6	1		T38	1
auto[1610612736:1744830463]	108	1			T2	1		T22	1		T41	1
auto[1744830464:1879048191]	90	1			T22	1		T41	1		T31	1
auto[1879048192:2013265919]	90	1			T5	1		T15	3		T6	1
auto[2013265920:2147483647]	96	1			T15	1		T6	1		T82	1
auto[2147483648:2281701375]	102	1			T15	2		T6	2		T18	2
auto[2281701376:2415919103]	91	1			T6	1		T41	2		T23	1
auto[2415919104:2550136831]	103	1			T15	1		T16	1		T6	2
auto[2550136832:2684354559]	90	1			T6	1		T18	1		T7	2
auto[2684354560:2818572287]	85	1			T6	1		T121	2		T58	1
auto[2818572288:2952790015]	86	1			T15	3		T6	2		T124	2
auto[2952790016:3087007743]	101	1			T15	1		T6	1		T121	1
auto[3087007744:3221225471]	91	1			T6	1		T17	1		T189	1
auto[3221225472:3355443199]	94	1			T15	1		T7	1		T121	1
auto[3355443200:3489660927]	94	1			T15	2		T16	1		T23	1
auto[3489660928:3623878655]	105	1			T41	2		T124	1		T39	1
auto[3623878656:3758096383]	89	1			T15	2		T7	1		T52	1
auto[3758096384:3892314111]	92	1			T15	1		T22	1		T47	2
auto[3892314112:4026531839]	110	1			T15	2		T6	1		T22	1
auto[4026531840:4160749567]	96	1			T15	2		T6	1		T38	1
auto[4160749568:4294967295]	77	1			T15	1		T39	1		T283	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T23	1		T39	2		T63	1
auto[0:134217727]	auto[1]	57	1			T15	2		T38	1		T39	4
auto[134217728:268435455]	auto[0]	41	1			T15	1		T39	1		T283	1
auto[134217728:268435455]	auto[1]	51	1			T41	3		T39	1		T40	1
auto[268435456:402653183]	auto[0]	51	1			T18	1		T41	1		T184	1
auto[268435456:402653183]	auto[1]	55	1			T15	1		T41	1		T50	2
auto[402653184:536870911]	auto[0]	48	1			T15	1		T18	1		T22	2
auto[402653184:536870911]	auto[1]	64	1			T39	2		T96	1		T57	1
auto[536870912:671088639]	auto[0]	58	1			T15	1		T18	1		T22	1
auto[536870912:671088639]	auto[1]	50	1			T15	1		T121	1		T41	1
auto[671088640:805306367]	auto[0]	45	1			T2	1		T15	1		T39	3
auto[671088640:805306367]	auto[1]	57	1			T5	1		T18	1		T52	1
auto[805306368:939524095]	auto[0]	54	1			T15	2		T31	1		T96	1
auto[805306368:939524095]	auto[1]	51	1			T15	1		T32	1		T41	1
auto[939524096:1073741823]	auto[0]	47	1			T15	2		T16	1		T18	1
auto[939524096:1073741823]	auto[1]	55	1			T2	1		T15	1		T41	1
auto[1073741824:1207959551]	auto[0]	46	1			T15	1		T16	1		T41	1
auto[1073741824:1207959551]	auto[1]	57	1			T15	1		T22	1		T47	1
auto[1207959552:1342177279]	auto[0]	47	1			T46	1		T23	1		T124	1
auto[1207959552:1342177279]	auto[1]	65	1			T6	2		T189	1		T39	1
auto[1342177280:1476395007]	auto[0]	59	1			T32	1		T22	1		T39	1
auto[1342177280:1476395007]	auto[1]	45	1			T15	2		T42	1		T57	1
auto[1476395008:1610612735]	auto[0]	40	1			T6	1		T38	1		T233	1
auto[1476395008:1610612735]	auto[1]	58	1			T15	1		T95	1		T40	2
auto[1610612736:1744830463]	auto[0]	54	1			T22	1		T41	1		T23	1
auto[1610612736:1744830463]	auto[1]	54	1			T2	1		T192	1		T106	1
auto[1744830464:1879048191]	auto[0]	45	1			T22	1		T31	1		T59	1
auto[1744830464:1879048191]	auto[1]	45	1			T41	1		T39	1		T351	1
auto[1879048192:2013265919]	auto[0]	43	1			T5	1		T15	2		T6	1
auto[1879048192:2013265919]	auto[1]	47	1			T15	1		T38	1		T184	1
auto[2013265920:2147483647]	auto[0]	46	1			T15	1		T6	1		T41	1
auto[2013265920:2147483647]	auto[1]	50	1			T82	1		T7	1		T23	1
auto[2147483648:2281701375]	auto[0]	50	1			T6	1		T39	2		T59	1
auto[2147483648:2281701375]	auto[1]	52	1			T15	2		T6	1		T18	2
auto[2281701376:2415919103]	auto[0]	46	1			T41	2		T23	1		T95	1
auto[2281701376:2415919103]	auto[1]	45	1			T6	1		T42	1		T39	1
auto[2415919104:2550136831]	auto[0]	47	1			T16	1		T41	2		T31	1
auto[2415919104:2550136831]	auto[1]	56	1			T15	1		T6	2		T41	1
auto[2550136832:2684354559]	auto[0]	49	1			T18	1		T7	2		T41	2
auto[2550136832:2684354559]	auto[1]	41	1			T6	1		T23	1		T42	1
auto[2684354560:2818572287]	auto[0]	42	1			T6	1		T39	1		T192	1
auto[2684354560:2818572287]	auto[1]	43	1			T121	2		T58	1		T39	2
auto[2818572288:2952790015]	auto[0]	39	1			T15	2		T39	1		T107	1
auto[2818572288:2952790015]	auto[1]	47	1			T15	1		T6	2		T124	2
auto[2952790016:3087007743]	auto[0]	42	1			T121	1		T40	1		T125	2
auto[2952790016:3087007743]	auto[1]	59	1			T15	1		T6	1		T39	1
auto[3087007744:3221225471]	auto[0]	35	1			T54	1		T107	1		T275	1
auto[3087007744:3221225471]	auto[1]	56	1			T6	1		T17	1		T189	1
auto[3221225472:3355443199]	auto[0]	51	1			T15	1		T7	1		T121	1
auto[3221225472:3355443199]	auto[1]	43	1			T89	1		T56	1		T40	1
auto[3355443200:3489660927]	auto[0]	50	1			T15	2		T16	1		T23	1
auto[3355443200:3489660927]	auto[1]	44	1			T39	1		T89	1		T388	1
auto[3489660928:3623878655]	auto[0]	52	1			T41	1		T59	1		T56	1
auto[3489660928:3623878655]	auto[1]	53	1			T41	1		T124	1		T39	1
auto[3623878656:3758096383]	auto[0]	41	1			T15	1		T52	1		T46	1
auto[3623878656:3758096383]	auto[1]	48	1			T15	1		T7	1		T39	2
auto[3758096384:3892314111]	auto[0]	43	1			T47	2		T39	2		T183	1
auto[3758096384:3892314111]	auto[1]	49	1			T15	1		T22	1		T39	1
auto[3892314112:4026531839]	auto[0]	58	1			T15	1		T6	1		T7	1
auto[3892314112:4026531839]	auto[1]	52	1			T15	1		T22	1		T41	1
auto[4026531840:4160749567]	auto[0]	46	1			T15	1		T41	1		T46	1
auto[4026531840:4160749567]	auto[1]	50	1			T15	1		T6	1		T38	1
auto[4160749568:4294967295]	auto[0]	28	1			T15	1		T283	1		T89	1
auto[4160749568:4294967295]	auto[1]	49	1			T39	1		T183	1		T125	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1475

1

T2

2

T5

1

T15

23

auto[1]

1654

1

T2

1

T5

1

T15

18

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T15	3		T18	1		T7	1
auto[134217728:268435455]	95	1			T16	2		T6	2		T18	2
auto[268435456:402653183]	102	1			T15	1		T38	1		T52	1
auto[402653184:536870911]	102	1			T15	2		T6	2		T41	1
auto[536870912:671088639]	119	1			T2	1		T15	2		T41	1
auto[671088640:805306367]	100	1			T22	1		T39	2		T63	1
auto[805306368:939524095]	97	1			T2	1		T15	1		T6	1
auto[939524096:1073741823]	77	1			T15	2		T121	1		T47	1
auto[1073741824:1207959551]	94	1			T15	2		T7	1		T41	2
auto[1207959552:1342177279]	97	1			T2	1		T15	2		T41	1
auto[1342177280:1476395007]	85	1			T5	1		T22	1		T41	1
auto[1476395008:1610612735]	96	1			T15	2		T39	2		T62	1
auto[1610612736:1744830463]	112	1			T6	1		T41	1		T46	2
auto[1744830464:1879048191]	89	1			T15	4		T6	1		T121	2
auto[1879048192:2013265919]	93	1			T6	1		T41	1		T47	1
auto[2013265920:2147483647]	120	1			T15	1		T6	1		T7	1
auto[2147483648:2281701375]	94	1			T5	1		T15	1		T6	3
auto[2281701376:2415919103]	83	1			T6	1		T41	1		T23	1
auto[2415919104:2550136831]	87	1			T15	1		T39	2		T95	1
auto[2550136832:2684354559]	117	1			T15	1		T6	1		T18	1
auto[2684354560:2818572287]	105	1			T15	3		T18	2		T22	1
auto[2818572288:2952790015]	96	1			T15	1		T41	1		T42	1
auto[2952790016:3087007743]	99	1			T15	4		T22	1		T41	1
auto[3087007744:3221225471]	103	1			T15	2		T18	1		T38	1
auto[3221225472:3355443199]	88	1			T15	1		T22	1		T7	1
auto[3355443200:3489660927]	92	1			T15	1		T16	1		T7	1
auto[3489660928:3623878655]	86	1			T15	1		T32	1		T121	1
auto[3623878656:3758096383]	111	1			T15	1		T6	1		T18	1
auto[3758096384:3892314111]	111	1			T16	1		T38	1		T41	1
auto[3892314112:4026531839]	94	1			T22	1		T41	2		T23	1
auto[4026531840:4160749567]	97	1			T15	1		T6	3		T41	2
auto[4160749568:4294967295]	100	1			T15	1		T7	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T15	1		T7	1		T63	1
auto[0:134217727]	auto[1]	46	1			T15	2		T18	1		T41	1
auto[134217728:268435455]	auto[0]	50	1			T16	2		T6	1		T18	1
auto[134217728:268435455]	auto[1]	45	1			T6	1		T18	1		T39	2
auto[268435456:402653183]	auto[0]	42	1			T52	1		T95	1		T192	1
auto[268435456:402653183]	auto[1]	60	1			T15	1		T38	1		T42	1
auto[402653184:536870911]	auto[0]	42	1			T15	1		T41	1		T40	1
auto[402653184:536870911]	auto[1]	60	1			T15	1		T6	2		T183	1
auto[536870912:671088639]	auto[0]	52	1			T15	2		T31	1		T96	1
auto[536870912:671088639]	auto[1]	67	1			T2	1		T41	1		T124	1
auto[671088640:805306367]	auto[0]	44	1			T39	1		T63	1		T283	1
auto[671088640:805306367]	auto[1]	56	1			T22	1		T39	1		T96	1
auto[805306368:939524095]	auto[0]	52	1			T2	1		T15	1		T6	1
auto[805306368:939524095]	auto[1]	45	1			T39	1		T192	1		T50	1
auto[939524096:1073741823]	auto[0]	42	1			T121	1		T47	1		T59	1
auto[939524096:1073741823]	auto[1]	35	1			T15	2		T351	1		T57	1
auto[1073741824:1207959551]	auto[0]	40	1			T7	1		T41	2		T46	1
auto[1073741824:1207959551]	auto[1]	54	1			T15	2		T95	1		T8	1
auto[1207959552:1342177279]	auto[0]	41	1			T2	1		T15	1		T95	1
auto[1207959552:1342177279]	auto[1]	56	1			T15	1		T41	1		T39	2
auto[1342177280:1476395007]	auto[0]	46	1			T41	1		T39	3		T19	1
auto[1342177280:1476395007]	auto[1]	39	1			T5	1		T22	1		T39	1
auto[1476395008:1610612735]	auto[0]	42	1			T15	2		T62	1		T89	1
auto[1476395008:1610612735]	auto[1]	54	1			T39	2		T184	1		T40	1
auto[1610612736:1744830463]	auto[0]	49	1			T6	1		T41	1		T46	1
auto[1610612736:1744830463]	auto[1]	63	1			T46	1		T189	1		T58	1
auto[1744830464:1879048191]	auto[0]	48	1			T15	3		T121	1		T46	1
auto[1744830464:1879048191]	auto[1]	41	1			T15	1		T6	1		T121	1
auto[1879048192:2013265919]	auto[0]	42	1			T47	1		T39	1		T95	1
auto[1879048192:2013265919]	auto[1]	51	1			T6	1		T41	1		T39	1
auto[2013265920:2147483647]	auto[0]	60	1			T15	1		T41	1		T40	2
auto[2013265920:2147483647]	auto[1]	60	1			T6	1		T7	1		T121	1
auto[2147483648:2281701375]	auto[0]	48	1			T5	1		T15	1		T6	2
auto[2147483648:2281701375]	auto[1]	46	1			T6	1		T41	1		T23	1
auto[2281701376:2415919103]	auto[0]	39	1			T23	1		T59	1		T54	1
auto[2281701376:2415919103]	auto[1]	44	1			T6	1		T41	1		T47	1
auto[2415919104:2550136831]	auto[0]	35	1			T39	1		T50	1		T183	1
auto[2415919104:2550136831]	auto[1]	52	1			T15	1		T39	1		T95	1
auto[2550136832:2684354559]	auto[0]	60	1			T15	1		T18	1		T46	1
auto[2550136832:2684354559]	auto[1]	57	1			T6	1		T22	1		T57	1
auto[2684354560:2818572287]	auto[0]	45	1			T15	3		T18	1		T22	1
auto[2684354560:2818572287]	auto[1]	60	1			T18	1		T39	1		T96	1
auto[2818572288:2952790015]	auto[0]	47	1			T42	1		T47	1		T39	1
auto[2818572288:2952790015]	auto[1]	49	1			T15	1		T41	1		T179	1
auto[2952790016:3087007743]	auto[0]	51	1			T15	2		T22	1		T41	1
auto[2952790016:3087007743]	auto[1]	48	1			T15	2		T39	3		T89	1
auto[3087007744:3221225471]	auto[0]	45	1			T15	2		T18	1		T38	1
auto[3087007744:3221225471]	auto[1]	58	1			T47	1		T124	1		T39	1
auto[3221225472:3355443199]	auto[0]	47	1			T22	1		T7	1		T31	1
auto[3221225472:3355443199]	auto[1]	41	1			T15	1		T192	1		T89	1
auto[3355443200:3489660927]	auto[0]	47	1			T16	1		T41	1		T59	1
auto[3355443200:3489660927]	auto[1]	45	1			T15	1		T7	1		T189	1
auto[3489660928:3623878655]	auto[0]	43	1			T15	1		T32	1		T31	1
auto[3489660928:3623878655]	auto[1]	43	1			T121	1		T41	1		T23	1
auto[3623878656:3758096383]	auto[0]	56	1			T6	1		T32	1		T47	1
auto[3623878656:3758096383]	auto[1]	55	1			T15	1		T18	1		T41	1
auto[3758096384:3892314111]	auto[0]	58	1			T16	1		T41	1		T31	1
auto[3758096384:3892314111]	auto[1]	53	1			T38	1		T39	2		T182	1
auto[3892314112:4026531839]	auto[0]	33	1			T22	1		T23	1		T184	1
auto[3892314112:4026531839]	auto[1]	61	1			T41	2		T58	1		T39	1
auto[4026531840:4160749567]	auto[0]	46	1			T6	2		T41	2		T23	1
auto[4026531840:4160749567]	auto[1]	51	1			T15	1		T6	1		T42	1
auto[4160749568:4294967295]	auto[0]	41	1			T15	1		T275	1		T265	1
auto[4160749568:4294967295]	auto[1]	59	1			T7	1		T42	1		T124	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1457

1

T2

2

T5

1

T15

22

auto[1]

1676

1

T2

1

T5

1

T15

19

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T18	1		T41	2		T189	1
auto[134217728:268435455]	97	1			T6	2		T38	2		T41	2
auto[268435456:402653183]	88	1			T6	1		T7	1		T23	1
auto[402653184:536870911]	89	1			T15	2		T6	1		T41	1
auto[536870912:671088639]	102	1			T15	1		T7	1		T31	1
auto[671088640:805306367]	112	1			T15	2		T82	1		T7	1
auto[805306368:939524095]	92	1			T32	1		T52	1		T124	1
auto[939524096:1073741823]	98	1			T15	3		T6	1		T18	1
auto[1073741824:1207959551]	116	1			T2	1		T5	1		T15	2
auto[1207959552:1342177279]	107	1			T15	1		T18	1		T41	1
auto[1342177280:1476395007]	105	1			T15	1		T18	1		T121	1
auto[1476395008:1610612735]	91	1			T6	1		T46	1		T23	1
auto[1610612736:1744830463]	101	1			T5	1		T15	1		T6	1
auto[1744830464:1879048191]	97	1			T15	1		T6	1		T17	1
auto[1879048192:2013265919]	106	1			T15	1		T22	1		T121	1
auto[2013265920:2147483647]	85	1			T6	1		T22	1		T351	1
auto[2147483648:2281701375]	94	1			T2	1		T15	4		T16	1
auto[2281701376:2415919103]	90	1			T2	1		T15	2		T18	1
auto[2415919104:2550136831]	91	1			T52	1		T124	1		T39	2
auto[2550136832:2684354559]	97	1			T15	1		T6	1		T38	1
auto[2684354560:2818572287]	86	1			T16	1		T7	1		T41	1
auto[2818572288:2952790015]	104	1			T15	2		T121	1		T41	2
auto[2952790016:3087007743]	92	1			T18	1		T41	2		T42	1
auto[3087007744:3221225471]	108	1			T15	2		T16	1		T18	1
auto[3221225472:3355443199]	91	1			T6	1		T39	3		T59	1
auto[3355443200:3489660927]	82	1			T15	1		T6	1		T42	1
auto[3489660928:3623878655]	101	1			T15	1		T58	1		T39	1
auto[3623878656:3758096383]	124	1			T15	2		T6	2		T41	2
auto[3758096384:3892314111]	91	1			T15	3		T16	1		T46	1
auto[3892314112:4026531839]	89	1			T15	3		T6	2		T22	1
auto[4026531840:4160749567]	103	1			T15	1		T22	1		T41	2
auto[4160749568:4294967295]	110	1			T15	4		T22	1		T121	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T41	1		T8	1		T62	1
auto[0:134217727]	auto[1]	47	1			T18	1		T41	1		T189	1
auto[134217728:268435455]	auto[0]	42	1			T41	2		T46	1		T39	1
auto[134217728:268435455]	auto[1]	55	1			T6	2		T38	2		T183	1
auto[268435456:402653183]	auto[0]	42	1			T6	1		T23	1		T39	2
auto[268435456:402653183]	auto[1]	46	1			T7	1		T39	1		T182	2
auto[402653184:536870911]	auto[0]	49	1			T41	1		T39	1		T95	1
auto[402653184:536870911]	auto[1]	40	1			T15	2		T6	1		T39	4
auto[536870912:671088639]	auto[0]	49	1			T7	1		T31	1		T39	1
auto[536870912:671088639]	auto[1]	53	1			T15	1		T56	1		T57	1
auto[671088640:805306367]	auto[0]	47	1			T15	2		T7	1		T89	1
auto[671088640:805306367]	auto[1]	65	1			T82	1		T42	1		T95	1
auto[805306368:939524095]	auto[0]	46	1			T32	1		T52	1		T124	1
auto[805306368:939524095]	auto[1]	46	1			T39	2		T106	1		T50	1
auto[939524096:1073741823]	auto[0]	38	1			T15	2		T32	1		T7	1
auto[939524096:1073741823]	auto[1]	60	1			T15	1		T6	1		T18	1
auto[1073741824:1207959551]	auto[0]	52	1			T2	1		T5	1		T15	1
auto[1073741824:1207959551]	auto[1]	64	1			T15	1		T6	1		T124	1
auto[1207959552:1342177279]	auto[0]	57	1			T18	1		T41	1		T39	2
auto[1207959552:1342177279]	auto[1]	50	1			T15	1		T39	1		T40	1
auto[1342177280:1476395007]	auto[0]	43	1			T18	1		T41	1		T23	1
auto[1342177280:1476395007]	auto[1]	62	1			T15	1		T121	1		T41	1
auto[1476395008:1610612735]	auto[0]	37	1			T46	1		T23	1		T124	1
auto[1476395008:1610612735]	auto[1]	54	1			T6	1		T40	2		T182	1
auto[1610612736:1744830463]	auto[0]	39	1			T22	1		T40	2		T182	1
auto[1610612736:1744830463]	auto[1]	62	1			T5	1		T15	1		T6	1
auto[1744830464:1879048191]	auto[0]	42	1			T15	1		T6	1		T18	1
auto[1744830464:1879048191]	auto[1]	55	1			T17	1		T41	1		T61	1
auto[1879048192:2013265919]	auto[0]	46	1			T15	1		T22	1		T41	2
auto[1879048192:2013265919]	auto[1]	60	1			T121	1		T41	1		T23	1
auto[2013265920:2147483647]	auto[0]	44	1			T6	1		T22	1		T8	1
auto[2013265920:2147483647]	auto[1]	41	1			T351	1		T57	1		T40	2
auto[2147483648:2281701375]	auto[0]	46	1			T15	3		T16	1		T6	1
auto[2147483648:2281701375]	auto[1]	48	1			T2	1		T15	1		T23	1
auto[2281701376:2415919103]	auto[0]	35	1			T2	1		T47	2		T8	1
auto[2281701376:2415919103]	auto[1]	55	1			T15	2		T18	1		T22	1
auto[2415919104:2550136831]	auto[0]	38	1			T39	1		T95	2		T40	2
auto[2415919104:2550136831]	auto[1]	53	1			T52	1		T124	1		T39	1
auto[2550136832:2684354559]	auto[0]	50	1			T15	1		T6	1		T38	1
auto[2550136832:2684354559]	auto[1]	47	1			T7	1		T47	1		T39	2
auto[2684354560:2818572287]	auto[0]	38	1			T16	1		T7	1		T107	2
auto[2684354560:2818572287]	auto[1]	48	1			T41	1		T40	1		T183	2
auto[2818572288:2952790015]	auto[0]	54	1			T46	1		T23	1		T47	1
auto[2818572288:2952790015]	auto[1]	50	1			T15	2		T121	1		T41	2
auto[2952790016:3087007743]	auto[0]	43	1			T41	1		T39	2		T283	1
auto[2952790016:3087007743]	auto[1]	49	1			T18	1		T41	1		T42	1
auto[3087007744:3221225471]	auto[0]	49	1			T15	2		T16	1		T18	1
auto[3087007744:3221225471]	auto[1]	59	1			T39	1		T96	1		T89	1
auto[3221225472:3355443199]	auto[0]	45	1			T39	1		T59	1		T91	1
auto[3221225472:3355443199]	auto[1]	46	1			T6	1		T39	2		T56	1
auto[3355443200:3489660927]	auto[0]	33	1			T15	1		T40	1		T241	1
auto[3355443200:3489660927]	auto[1]	49	1			T6	1		T42	1		T183	1
auto[3489660928:3623878655]	auto[0]	54	1			T15	1		T39	1		T95	1
auto[3489660928:3623878655]	auto[1]	47	1			T58	1		T96	1		T57	1
auto[3623878656:3758096383]	auto[0]	57	1			T15	2		T41	1		T46	1
auto[3623878656:3758096383]	auto[1]	67	1			T6	2		T41	1		T189	1
auto[3758096384:3892314111]	auto[0]	46	1			T15	1		T16	1		T46	1
auto[3758096384:3892314111]	auto[1]	45	1			T15	2		T23	1		T42	1
auto[3892314112:4026531839]	auto[0]	46	1			T15	2		T6	1		T22	1
auto[3892314112:4026531839]	auto[1]	43	1			T15	1		T6	1		T39	2
auto[4026531840:4160749567]	auto[0]	54	1			T41	1		T192	1		T184	1
auto[4026531840:4160749567]	auto[1]	49	1			T15	1		T22	1		T41	1
auto[4160749568:4294967295]	auto[0]	49	1			T15	2		T47	1		T39	2
auto[4160749568:4294967295]	auto[1]	61	1			T15	2		T22	1		T121	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1483

1

T2

1

T5

1

T15

21

auto[1]

1650

1

T2

2

T5

1

T15

20

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T38	1		T31	1		T47	1
auto[134217728:268435455]	91	1			T15	1		T18	1		T32	1
auto[268435456:402653183]	96	1			T15	2		T6	1		T17	1
auto[402653184:536870911]	103	1			T6	1		T7	1		T189	1
auto[536870912:671088639]	98	1			T2	1		T15	3		T16	2
auto[671088640:805306367]	107	1			T15	1		T41	3		T46	1
auto[805306368:939524095]	85	1			T41	1		T189	1		T39	4
auto[939524096:1073741823]	104	1			T15	1		T6	1		T22	1
auto[1073741824:1207959551]	99	1			T15	1		T46	1		T39	4
auto[1207959552:1342177279]	88	1			T15	2		T18	2		T22	1
auto[1342177280:1476395007]	97	1			T15	1		T6	2		T22	1
auto[1476395008:1610612735]	96	1			T15	1		T6	1		T41	1
auto[1610612736:1744830463]	105	1			T15	4		T41	1		T46	1
auto[1744830464:1879048191]	101	1			T15	2		T39	2		T59	1
auto[1879048192:2013265919]	83	1			T2	1		T15	1		T18	1
auto[2013265920:2147483647]	105	1			T18	1		T22	1		T23	1
auto[2147483648:2281701375]	83	1			T15	3		T18	1		T41	1
auto[2281701376:2415919103]	111	1			T15	2		T6	2		T18	1
auto[2415919104:2550136831]	94	1			T15	1		T6	2		T38	2
auto[2550136832:2684354559]	92	1			T22	1		T121	1		T41	1
auto[2684354560:2818572287]	101	1			T15	2		T23	1		T42	1
auto[2818572288:2952790015]	92	1			T15	2		T16	1		T52	1
auto[2952790016:3087007743]	110	1			T2	1		T15	1		T121	1
auto[3087007744:3221225471]	90	1			T15	1		T41	2		T47	1
auto[3221225472:3355443199]	99	1			T6	1		T32	1		T22	1
auto[3355443200:3489660927]	103	1			T15	2		T7	1		T41	2
auto[3489660928:3623878655]	100	1			T6	1		T41	1		T42	1
auto[3623878656:3758096383]	94	1			T5	1		T15	1		T6	1
auto[3758096384:3892314111]	103	1			T22	1		T41	1		T39	1
auto[3892314112:4026531839]	107	1			T15	2		T6	3		T22	1
auto[4026531840:4160749567]	85	1			T5	1		T15	3		T16	1
auto[4160749568:4294967295]	112	1			T15	1		T41	2		T58	1