dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4120 1 T2 4 T5 4 T15 48
auto[1] 2144 1 T2 2 T15 34 T6 10



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 170 1 T15 2 T18 2 T38 2
auto[134217728:268435455] 212 1 T121 2 T23 2 T31 2
auto[268435456:402653183] 172 1 T15 2 T47 2 T39 2
auto[402653184:536870911] 192 1 T15 4 T18 2 T22 4
auto[536870912:671088639] 196 1 T15 4 T6 4 T41 2
auto[671088640:805306367] 202 1 T15 2 T6 2 T41 2
auto[805306368:939524095] 154 1 T17 2 T38 2 T22 2
auto[939524096:1073741823] 222 1 T6 2 T38 2 T7 2
auto[1073741824:1207959551] 214 1 T15 2 T16 2 T41 2
auto[1207959552:1342177279] 186 1 T15 4 T6 4 T18 2
auto[1342177280:1476395007] 218 1 T15 4 T6 2 T18 2
auto[1476395008:1610612735] 206 1 T5 2 T15 2 T6 4
auto[1610612736:1744830463] 198 1 T121 2 T41 2 T47 2
auto[1744830464:1879048191] 188 1 T15 8 T18 2 T41 2
auto[1879048192:2013265919] 216 1 T15 2 T16 2 T7 2
auto[2013265920:2147483647] 188 1 T15 4 T22 2 T7 2
auto[2147483648:2281701375] 206 1 T15 6 T16 2 T6 4
auto[2281701376:2415919103] 240 1 T15 2 T6 2 T7 2
auto[2415919104:2550136831] 160 1 T6 2 T32 2 T39 4
auto[2550136832:2684354559] 176 1 T15 2 T52 2 T23 2
auto[2684354560:2818572287] 154 1 T2 2 T15 2 T22 2
auto[2818572288:2952790015] 216 1 T15 4 T7 2 T23 4
auto[2952790016:3087007743] 178 1 T5 2 T41 2 T39 2
auto[3087007744:3221225471] 194 1 T15 2 T6 4 T41 4
auto[3221225472:3355443199] 214 1 T6 2 T41 6 T23 2
auto[3355443200:3489660927] 202 1 T2 2 T15 2 T121 2
auto[3489660928:3623878655] 198 1 T15 2 T18 2 T32 2
auto[3623878656:3758096383] 194 1 T15 4 T18 2 T7 2
auto[3758096384:3892314111] 176 1 T15 6 T41 2 T46 2
auto[3892314112:4026531839] 200 1 T15 2 T6 4 T41 2
auto[4026531840:4160749567] 226 1 T2 2 T15 2 T16 2
auto[4160749568:4294967295] 196 1 T15 6 T22 2 T52 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 122 1 T15 2 T18 2 T38 2
auto[0:134217727] auto[1] 48 1 T224 2 T43 2 T24 2
auto[134217728:268435455] auto[0] 146 1 T121 2 T23 2 T31 2
auto[134217728:268435455] auto[1] 66 1 T192 2 T106 2 T40 2
auto[268435456:402653183] auto[0] 104 1 T47 2 T39 2 T182 2
auto[268435456:402653183] auto[1] 68 1 T15 2 T409 2 T209 4
auto[402653184:536870911] auto[0] 136 1 T15 4 T18 2 T41 6
auto[402653184:536870911] auto[1] 56 1 T22 4 T39 2 T182 2
auto[536870912:671088639] auto[0] 122 1 T15 4 T6 2 T41 2
auto[536870912:671088639] auto[1] 74 1 T6 2 T46 2 T189 2
auto[671088640:805306367] auto[0] 124 1 T6 2 T41 2 T95 2
auto[671088640:805306367] auto[1] 78 1 T15 2 T47 2 T54 2
auto[805306368:939524095] auto[0] 90 1 T22 2 T95 2 T96 2
auto[805306368:939524095] auto[1] 64 1 T17 2 T38 2 T95 2
auto[939524096:1073741823] auto[0] 142 1 T6 2 T38 2 T7 2
auto[939524096:1073741823] auto[1] 80 1 T124 2 T40 4 T64 2
auto[1073741824:1207959551] auto[0] 146 1 T16 2 T41 2 T39 2
auto[1073741824:1207959551] auto[1] 68 1 T15 2 T39 2 T8 2
auto[1207959552:1342177279] auto[0] 120 1 T15 2 T6 4 T18 2
auto[1207959552:1342177279] auto[1] 66 1 T15 2 T39 2 T60 2
auto[1342177280:1476395007] auto[0] 148 1 T15 2 T18 2 T41 2
auto[1342177280:1476395007] auto[1] 70 1 T15 2 T6 2 T58 2
auto[1476395008:1610612735] auto[0] 140 1 T5 2 T15 2 T6 4
auto[1476395008:1610612735] auto[1] 66 1 T41 2 T39 2 T107 2
auto[1610612736:1744830463] auto[0] 118 1 T121 2 T47 2 T39 10
auto[1610612736:1744830463] auto[1] 80 1 T41 2 T39 2 T219 2
auto[1744830464:1879048191] auto[0] 120 1 T15 8 T41 2 T50 2
auto[1744830464:1879048191] auto[1] 68 1 T18 2 T42 2 T39 4
auto[1879048192:2013265919] auto[0] 138 1 T16 2 T7 2 T42 2
auto[1879048192:2013265919] auto[1] 78 1 T15 2 T39 2 T106 2
auto[2013265920:2147483647] auto[0] 136 1 T15 4 T22 2 T7 2
auto[2013265920:2147483647] auto[1] 52 1 T39 2 T40 2 T183 2
auto[2147483648:2281701375] auto[0] 134 1 T15 2 T16 2 T6 2
auto[2147483648:2281701375] auto[1] 72 1 T15 4 T6 2 T408 2
auto[2281701376:2415919103] auto[0] 150 1 T15 2 T39 6 T192 2
auto[2281701376:2415919103] auto[1] 90 1 T6 2 T7 2 T46 2
auto[2415919104:2550136831] auto[0] 114 1 T6 2 T39 4 T57 2
auto[2415919104:2550136831] auto[1] 46 1 T32 2 T125 2 T265 2
auto[2550136832:2684354559] auto[0] 122 1 T15 2 T23 2 T39 2
auto[2550136832:2684354559] auto[1] 54 1 T52 2 T40 4 T281 2
auto[2684354560:2818572287] auto[0] 102 1 T22 2 T41 2 T46 2
auto[2684354560:2818572287] auto[1] 52 1 T2 2 T15 2 T39 2
auto[2818572288:2952790015] auto[0] 148 1 T7 2 T23 4 T42 2
auto[2818572288:2952790015] auto[1] 68 1 T15 4 T58 2 T39 2
auto[2952790016:3087007743] auto[0] 112 1 T5 2 T283 2 T89 2
auto[2952790016:3087007743] auto[1] 66 1 T41 2 T39 2 T283 2
auto[3087007744:3221225471] auto[0] 128 1 T6 4 T41 4 T31 2
auto[3087007744:3221225471] auto[1] 66 1 T15 2 T23 2 T39 4
auto[3221225472:3355443199] auto[0] 138 1 T6 2 T41 6 T23 2
auto[3221225472:3355443199] auto[1] 76 1 T182 2 T43 2 T256 2
auto[3355443200:3489660927] auto[0] 128 1 T2 2 T50 2 T183 2
auto[3355443200:3489660927] auto[1] 74 1 T15 2 T121 2 T41 2
auto[3489660928:3623878655] auto[0] 120 1 T18 2 T41 2 T47 2
auto[3489660928:3623878655] auto[1] 78 1 T15 2 T32 2 T39 2
auto[3623878656:3758096383] auto[0] 128 1 T15 2 T18 2 T7 2
auto[3623878656:3758096383] auto[1] 66 1 T15 2 T63 2 T96 2
auto[3758096384:3892314111] auto[0] 110 1 T15 4 T46 2 T47 2
auto[3758096384:3892314111] auto[1] 66 1 T15 2 T41 2 T189 2
auto[3892314112:4026531839] auto[0] 132 1 T6 2 T41 2 T46 2
auto[3892314112:4026531839] auto[1] 68 1 T15 2 T6 2 T189 2
auto[4026531840:4160749567] auto[0] 174 1 T2 2 T15 2 T16 2
auto[4026531840:4160749567] auto[1] 52 1 T22 2 T351 2 T50 2
auto[4160749568:4294967295] auto[0] 128 1 T15 6 T22 2 T91 2
auto[4160749568:4294967295] auto[1] 68 1 T52 2 T39 2 T256 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%