Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
843 |
1 |
|
|
T15 |
21 |
|
T6 |
11 |
|
T82 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
450 |
1 |
|
|
T15 |
13 |
|
T6 |
8 |
|
T82 |
4 |
auto[1] |
393 |
1 |
|
|
T15 |
8 |
|
T6 |
3 |
|
T82 |
3 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
290 |
1 |
|
|
T15 |
3 |
|
T6 |
2 |
|
T82 |
3 |
auto[1] |
553 |
1 |
|
|
T15 |
18 |
|
T6 |
9 |
|
T82 |
4 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
| | | | | | | | | | | | |
auto[0] |
474 |
1 |
|
|
T15 |
11 |
|
T6 |
6 |
|
T82 |
4 |
auto[1] |
369 |
1 |
|
|
T15 |
10 |
|
T6 |
5 |
|
T82 |
3 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
| | | | | |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
| | | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
158 |
1 |
|
|
T15 |
3 |
|
T6 |
1 |
|
T82 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
85 |
1 |
|
|
T15 |
5 |
|
T6 |
2 |
|
T82 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
132 |
1 |
|
|
T6 |
1 |
|
T39 |
5 |
|
T172 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
99 |
1 |
|
|
T15 |
3 |
|
T6 |
2 |
|
T39 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
207 |
1 |
|
|
T15 |
5 |
|
T6 |
5 |
|
T39 |
4 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
162 |
1 |
|
|
T15 |
5 |
|
T82 |
3 |
|
T39 |
3 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |