Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.87 99.10 97.91 98.88 100.00 99.12 98.41 91.68


Total test records in report: 1062
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1007 /workspace/coverage/default/36.keymgr_cfg_regwen.1182240481 May 18 04:12:33 PM PDT 24 May 18 04:12:38 PM PDT 24 34498076 ps
T1008 /workspace/coverage/default/19.keymgr_stress_all.2313551137 May 18 04:11:22 PM PDT 24 May 18 04:11:27 PM PDT 24 27138778 ps
T1009 /workspace/coverage/default/46.keymgr_smoke.3547791835 May 18 04:13:05 PM PDT 24 May 18 04:13:11 PM PDT 24 449789199 ps
T258 /workspace/coverage/default/33.keymgr_stress_all.931490235 May 18 04:12:31 PM PDT 24 May 18 04:13:12 PM PDT 24 1520773659 ps
T1010 /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2333087936 May 18 04:11:05 PM PDT 24 May 18 04:11:15 PM PDT 24 741118989 ps
T1011 /workspace/coverage/default/16.keymgr_random.1060042849 May 18 04:11:02 PM PDT 24 May 18 04:12:39 PM PDT 24 10474916145 ps
T1012 /workspace/coverage/default/29.keymgr_direct_to_disabled.3659429100 May 18 04:11:59 PM PDT 24 May 18 04:12:03 PM PDT 24 43426831 ps
T1013 /workspace/coverage/default/17.keymgr_sideload_otbn.3576678172 May 18 04:11:10 PM PDT 24 May 18 04:11:55 PM PDT 24 4598455583 ps
T1014 /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2391716978 May 18 04:12:10 PM PDT 24 May 18 04:12:15 PM PDT 24 360346853 ps
T1015 /workspace/coverage/default/3.keymgr_sideload_protect.2626217292 May 18 04:10:05 PM PDT 24 May 18 04:10:09 PM PDT 24 98253302 ps
T1016 /workspace/coverage/default/2.keymgr_sideload.2901538054 May 18 04:10:02 PM PDT 24 May 18 04:10:05 PM PDT 24 32276515 ps
T1017 /workspace/coverage/default/10.keymgr_random.4255664668 May 18 04:10:40 PM PDT 24 May 18 04:10:46 PM PDT 24 152699359 ps
T1018 /workspace/coverage/default/38.keymgr_sideload.1769615978 May 18 04:12:35 PM PDT 24 May 18 04:12:41 PM PDT 24 64846706 ps
T373 /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3157348710 May 18 04:12:28 PM PDT 24 May 18 04:12:32 PM PDT 24 352334047 ps
T1019 /workspace/coverage/default/2.keymgr_direct_to_disabled.948553921 May 18 04:09:59 PM PDT 24 May 18 04:10:04 PM PDT 24 257187227 ps
T1020 /workspace/coverage/default/5.keymgr_direct_to_disabled.3351923622 May 18 04:10:16 PM PDT 24 May 18 04:10:19 PM PDT 24 27162293 ps
T1021 /workspace/coverage/default/3.keymgr_alert_test.1255506781 May 18 04:10:07 PM PDT 24 May 18 04:10:09 PM PDT 24 17149161 ps
T259 /workspace/coverage/default/10.keymgr_stress_all.3437144458 May 18 04:10:41 PM PDT 24 May 18 04:10:47 PM PDT 24 241630685 ps
T1022 /workspace/coverage/default/20.keymgr_random.138451578 May 18 04:11:25 PM PDT 24 May 18 04:11:33 PM PDT 24 463742999 ps
T1023 /workspace/coverage/default/2.keymgr_sideload_protect.4020492720 May 18 04:09:59 PM PDT 24 May 18 04:10:03 PM PDT 24 106303158 ps
T1024 /workspace/coverage/default/13.keymgr_kmac_rsp_err.1214905910 May 18 04:10:55 PM PDT 24 May 18 04:11:05 PM PDT 24 763647784 ps
T1025 /workspace/coverage/default/48.keymgr_sideload.3419351312 May 18 04:13:18 PM PDT 24 May 18 04:13:22 PM PDT 24 107619552 ps
T1026 /workspace/coverage/default/43.keymgr_alert_test.68454735 May 18 04:12:56 PM PDT 24 May 18 04:12:59 PM PDT 24 78206085 ps
T1027 /workspace/coverage/default/44.keymgr_direct_to_disabled.3144522164 May 18 04:12:57 PM PDT 24 May 18 04:13:07 PM PDT 24 465728996 ps
T1028 /workspace/coverage/default/42.keymgr_sideload_otbn.4236719793 May 18 04:12:47 PM PDT 24 May 18 04:12:52 PM PDT 24 34488429 ps
T1029 /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1975883775 May 18 04:10:28 PM PDT 24 May 18 04:10:35 PM PDT 24 2263487183 ps
T1030 /workspace/coverage/default/45.keymgr_random.997858480 May 18 04:13:16 PM PDT 24 May 18 04:13:22 PM PDT 24 288878585 ps
T1031 /workspace/coverage/default/35.keymgr_sideload_aes.3891544492 May 18 04:12:29 PM PDT 24 May 18 04:12:35 PM PDT 24 92691953 ps
T1032 /workspace/coverage/default/17.keymgr_sync_async_fault_cross.660735087 May 18 04:11:11 PM PDT 24 May 18 04:11:16 PM PDT 24 111383125 ps
T1033 /workspace/coverage/default/10.keymgr_sw_invalid_input.274832400 May 18 04:10:34 PM PDT 24 May 18 04:10:41 PM PDT 24 415942657 ps
T1034 /workspace/coverage/default/41.keymgr_sideload.3052456895 May 18 04:12:45 PM PDT 24 May 18 04:13:18 PM PDT 24 1129559988 ps
T1035 /workspace/coverage/default/27.keymgr_custom_cm.1899143293 May 18 04:11:51 PM PDT 24 May 18 04:11:57 PM PDT 24 78230615 ps
T1036 /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3598686350 May 18 04:12:15 PM PDT 24 May 18 04:12:24 PM PDT 24 411476897 ps
T1037 /workspace/coverage/default/16.keymgr_sideload_protect.2282517874 May 18 04:11:12 PM PDT 24 May 18 04:11:16 PM PDT 24 98952740 ps
T1038 /workspace/coverage/default/1.keymgr_sideload_aes.4158123243 May 18 04:09:52 PM PDT 24 May 18 04:09:57 PM PDT 24 114573962 ps
T1039 /workspace/coverage/default/6.keymgr_sideload_kmac.2354150056 May 18 04:10:19 PM PDT 24 May 18 04:10:23 PM PDT 24 42038006 ps
T1040 /workspace/coverage/default/0.keymgr_lc_disable.892944808 May 18 04:09:45 PM PDT 24 May 18 04:09:50 PM PDT 24 336843203 ps
T1041 /workspace/coverage/default/43.keymgr_random.136457934 May 18 04:12:56 PM PDT 24 May 18 04:13:03 PM PDT 24 166777895 ps
T208 /workspace/coverage/default/30.keymgr_lc_disable.3091134184 May 18 04:12:06 PM PDT 24 May 18 04:12:13 PM PDT 24 442234472 ps
T1042 /workspace/coverage/default/17.keymgr_smoke.206849830 May 18 04:11:09 PM PDT 24 May 18 04:11:16 PM PDT 24 238131743 ps
T1043 /workspace/coverage/default/26.keymgr_sideload.3290748826 May 18 04:11:45 PM PDT 24 May 18 04:12:04 PM PDT 24 3949073438 ps
T1044 /workspace/coverage/default/38.keymgr_smoke.3941267693 May 18 04:12:37 PM PDT 24 May 18 04:12:43 PM PDT 24 68481849 ps
T1045 /workspace/coverage/default/36.keymgr_sideload_protect.2428671387 May 18 04:12:37 PM PDT 24 May 18 04:12:42 PM PDT 24 47256410 ps
T1046 /workspace/coverage/default/23.keymgr_smoke.1668561367 May 18 04:11:37 PM PDT 24 May 18 04:11:44 PM PDT 24 164314284 ps
T1047 /workspace/coverage/default/37.keymgr_sideload_aes.2885697932 May 18 04:12:33 PM PDT 24 May 18 04:12:41 PM PDT 24 528876493 ps
T1048 /workspace/coverage/default/9.keymgr_smoke.2004184132 May 18 04:10:34 PM PDT 24 May 18 04:10:56 PM PDT 24 760101070 ps
T1049 /workspace/coverage/default/17.keymgr_stress_all.281611420 May 18 04:11:09 PM PDT 24 May 18 04:11:39 PM PDT 24 2733136861 ps
T1050 /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1909795128 May 18 04:09:51 PM PDT 24 May 18 04:09:57 PM PDT 24 118943141 ps
T1051 /workspace/coverage/default/21.keymgr_random.1235272656 May 18 04:11:25 PM PDT 24 May 18 04:11:37 PM PDT 24 371026661 ps
T1052 /workspace/coverage/default/7.keymgr_sw_invalid_input.1439842906 May 18 04:10:27 PM PDT 24 May 18 04:10:33 PM PDT 24 154087149 ps
T330 /workspace/coverage/default/49.keymgr_kmac_rsp_err.3198854597 May 18 04:13:17 PM PDT 24 May 18 04:13:31 PM PDT 24 426650941 ps
T1053 /workspace/coverage/default/24.keymgr_smoke.3720313514 May 18 04:11:39 PM PDT 24 May 18 04:11:43 PM PDT 24 63743148 ps
T1054 /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2931589864 May 18 04:12:46 PM PDT 24 May 18 04:12:51 PM PDT 24 57559316 ps
T1055 /workspace/coverage/default/27.keymgr_smoke.494687946 May 18 04:11:52 PM PDT 24 May 18 04:11:58 PM PDT 24 144411830 ps
T221 /workspace/coverage/default/27.keymgr_cfg_regwen.1255129698 May 18 04:11:53 PM PDT 24 May 18 04:12:04 PM PDT 24 487944355 ps
T1056 /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4165981370 May 18 04:10:14 PM PDT 24 May 18 04:10:27 PM PDT 24 1162659497 ps
T1057 /workspace/coverage/default/4.keymgr_custom_cm.1335632791 May 18 04:10:16 PM PDT 24 May 18 04:10:24 PM PDT 24 1114132309 ps
T1058 /workspace/coverage/default/32.keymgr_sideload_kmac.20951552 May 18 04:12:18 PM PDT 24 May 18 04:12:22 PM PDT 24 342654191 ps
T1059 /workspace/coverage/default/48.keymgr_sw_invalid_input.2229907022 May 18 04:13:25 PM PDT 24 May 18 04:13:34 PM PDT 24 292937924 ps
T1060 /workspace/coverage/default/43.keymgr_sw_invalid_input.4249334484 May 18 04:13:04 PM PDT 24 May 18 04:13:10 PM PDT 24 184037411 ps
T1061 /workspace/coverage/default/16.keymgr_sideload_aes.3470505438 May 18 04:11:04 PM PDT 24 May 18 04:11:12 PM PDT 24 2205457153 ps
T1062 /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3438120116 May 18 04:12:59 PM PDT 24 May 18 04:13:09 PM PDT 24 120406119 ps

Test location /workspace/coverage/default/15.keymgr_stress_all.578047847
Short name T15
Test name
Test status
Simulation time 5922734439 ps
CPU time 57.46 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:12:01 PM PDT 24
Peak memory 215988 kb
Host smart-b5162ab1-f6e0-49cd-8eda-f77d90053990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578047847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.578047847
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1977183729
Short name T40
Test name
Test status
Simulation time 593929957 ps
CPU time 26.23 seconds
Started May 18 04:12:00 PM PDT 24
Finished May 18 04:12:27 PM PDT 24
Peak memory 214480 kb
Host smart-91d796bc-c061-4d60-86a3-ca18a2f22382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977183729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1977183729
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3992781148
Short name T82
Test name
Test status
Simulation time 133189026 ps
CPU time 2.38 seconds
Started May 18 04:10:06 PM PDT 24
Finished May 18 04:10:09 PM PDT 24
Peak memory 222356 kb
Host smart-650441f5-5a5c-4374-87c0-c1063d24e165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992781148 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3992781148
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3723551231
Short name T12
Test name
Test status
Simulation time 1569649146 ps
CPU time 29.49 seconds
Started May 18 04:09:51 PM PDT 24
Finished May 18 04:10:22 PM PDT 24
Peak memory 235560 kb
Host smart-5e2de78e-aaca-4606-a1c0-7f87f10b4aca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723551231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3723551231
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.454658437
Short name T41
Test name
Test status
Simulation time 2384629981 ps
CPU time 23.78 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:43 PM PDT 24
Peak memory 222208 kb
Host smart-812496d8-0b3b-4530-bd21-ea40fe485330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454658437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.454658437
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4196568528
Short name T39
Test name
Test status
Simulation time 4180726866 ps
CPU time 90.42 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:12:28 PM PDT 24
Peak memory 216216 kb
Host smart-afa8daca-ff7f-4487-a1ff-ae7fc5eef8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196568528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4196568528
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.448474497
Short name T38
Test name
Test status
Simulation time 6009362313 ps
CPU time 73.65 seconds
Started May 18 04:13:17 PM PDT 24
Finished May 18 04:14:32 PM PDT 24
Peak memory 215876 kb
Host smart-0c4a7f8f-be05-4fdd-ad27-48e0e5039c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448474497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.448474497
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.82100960
Short name T110
Test name
Test status
Simulation time 483290778 ps
CPU time 9.65 seconds
Started May 18 04:03:00 PM PDT 24
Finished May 18 04:03:10 PM PDT 24
Peak memory 214108 kb
Host smart-7931a26f-93da-49b1-aba3-fe383ade8afa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82100960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_shadow_reg_errors_with_csr_rw.82100960
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2645872497
Short name T9
Test name
Test status
Simulation time 297691742 ps
CPU time 4.96 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:12:48 PM PDT 24
Peak memory 222460 kb
Host smart-180352cf-fbd7-443b-b33f-d7d496cd9042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645872497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2645872497
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1254637488
Short name T43
Test name
Test status
Simulation time 4544656109 ps
CPU time 105.36 seconds
Started May 18 04:11:54 PM PDT 24
Finished May 18 04:13:42 PM PDT 24
Peak memory 215048 kb
Host smart-56e7790c-9b83-45c6-b7b8-308cb969e4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254637488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1254637488
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1396037377
Short name T22
Test name
Test status
Simulation time 566711918 ps
CPU time 6.86 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:20 PM PDT 24
Peak memory 222224 kb
Host smart-d0e83504-af55-449a-bda1-cce61b6c912f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396037377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1396037377
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2331177236
Short name T75
Test name
Test status
Simulation time 2754038192 ps
CPU time 37.06 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:51 PM PDT 24
Peak memory 215284 kb
Host smart-4183b420-70c1-4a30-a18b-f43ce911bd10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331177236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2331177236
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3109561776
Short name T61
Test name
Test status
Simulation time 888626541 ps
CPU time 12.65 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:08 PM PDT 24
Peak memory 222332 kb
Host smart-866da889-011e-4b32-bfc4-b13a5ce262ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109561776 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3109561776
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1150486178
Short name T277
Test name
Test status
Simulation time 10418479886 ps
CPU time 57.29 seconds
Started May 18 04:12:51 PM PDT 24
Finished May 18 04:13:50 PM PDT 24
Peak memory 216340 kb
Host smart-19af34cb-a9a7-435e-9cf1-37cace6df767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150486178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1150486178
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2116292251
Short name T77
Test name
Test status
Simulation time 347598977 ps
CPU time 6.38 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:18 PM PDT 24
Peak memory 213976 kb
Host smart-374097b7-0c82-44f4-9104-a9a9a39a4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116292251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2116292251
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3825818567
Short name T123
Test name
Test status
Simulation time 480837690 ps
CPU time 12.42 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:03:07 PM PDT 24
Peak memory 209016 kb
Host smart-55067c8e-df8f-48a0-b975-bbb6ea1ebbda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825818567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3825818567
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1950986477
Short name T183
Test name
Test status
Simulation time 525847276 ps
CPU time 25.38 seconds
Started May 18 04:11:23 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 222124 kb
Host smart-6d948555-9abb-45c6-a00a-c14e33394aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950986477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1950986477
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4166552527
Short name T18
Test name
Test status
Simulation time 1552600916 ps
CPU time 19.43 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:59 PM PDT 24
Peak memory 222104 kb
Host smart-df251ef3-a5c6-4356-a5a0-874aae1e1117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166552527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4166552527
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1798995685
Short name T114
Test name
Test status
Simulation time 1120555796 ps
CPU time 20.04 seconds
Started May 18 04:02:49 PM PDT 24
Finished May 18 04:03:10 PM PDT 24
Peak memory 222156 kb
Host smart-2e5a9d60-5a7a-4455-b08a-2a7b4724188b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798995685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1798995685
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.799662020
Short name T404
Test name
Test status
Simulation time 655156538 ps
CPU time 16.75 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:17 PM PDT 24
Peak memory 214112 kb
Host smart-1556987b-c354-48a7-aebc-664c554da8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799662020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.799662020
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2481593466
Short name T215
Test name
Test status
Simulation time 3167885436 ps
CPU time 31.05 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:42 PM PDT 24
Peak memory 215036 kb
Host smart-77490fd5-43f9-49b0-90fb-f9032ee90ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481593466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2481593466
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1556232758
Short name T32
Test name
Test status
Simulation time 203613153 ps
CPU time 3.5 seconds
Started May 18 04:10:10 PM PDT 24
Finished May 18 04:10:14 PM PDT 24
Peak memory 208592 kb
Host smart-7a7efc61-f260-4863-aa53-396b3c6bfbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556232758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1556232758
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1631085750
Short name T86
Test name
Test status
Simulation time 88086934 ps
CPU time 3.31 seconds
Started May 18 04:10:42 PM PDT 24
Finished May 18 04:10:48 PM PDT 24
Peak memory 208356 kb
Host smart-258c3b71-ca66-4027-8f5d-b009c979c3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631085750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1631085750
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.480519724
Short name T267
Test name
Test status
Simulation time 293669862 ps
CPU time 15.8 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 215188 kb
Host smart-d2484c05-8f20-429a-94d1-f2e36b5a8413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480519724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.480519724
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2292320476
Short name T125
Test name
Test status
Simulation time 86296993894 ps
CPU time 550.93 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:21:43 PM PDT 24
Peak memory 230484 kb
Host smart-fcd7857b-3f62-4d44-850a-f323b3945e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292320476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2292320476
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1281018552
Short name T69
Test name
Test status
Simulation time 19396578301 ps
CPU time 238.7 seconds
Started May 18 04:13:19 PM PDT 24
Finished May 18 04:17:19 PM PDT 24
Peak memory 217916 kb
Host smart-3ef1339c-1c60-4bd3-943a-49ad5a798c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281018552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1281018552
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2574089950
Short name T19
Test name
Test status
Simulation time 289438389 ps
CPU time 5.06 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 220112 kb
Host smart-e132b40a-244f-4e61-9ac8-404c83b156fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574089950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2574089950
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3547196371
Short name T26
Test name
Test status
Simulation time 710167216 ps
CPU time 8.92 seconds
Started May 18 04:11:07 PM PDT 24
Finished May 18 04:11:17 PM PDT 24
Peak memory 209380 kb
Host smart-5ae6e3f0-cad0-44e1-9e39-7de1531a6c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547196371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3547196371
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1644948826
Short name T158
Test name
Test status
Simulation time 1059956627 ps
CPU time 12.72 seconds
Started May 18 04:10:48 PM PDT 24
Finished May 18 04:11:01 PM PDT 24
Peak memory 217672 kb
Host smart-2cb6d182-84ab-4faa-ab08-32b7fbe01590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644948826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1644948826
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.846158385
Short name T403
Test name
Test status
Simulation time 5848301921 ps
CPU time 72.52 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:13:45 PM PDT 24
Peak memory 214108 kb
Host smart-3a9645c3-9de4-486d-84bb-c834ece84bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846158385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.846158385
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.380115525
Short name T85
Test name
Test status
Simulation time 346312326 ps
CPU time 8.03 seconds
Started May 18 04:12:11 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 222104 kb
Host smart-a801916f-7542-4d9e-8bce-609181a2adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380115525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.380115525
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2972200262
Short name T107
Test name
Test status
Simulation time 351398080 ps
CPU time 8.4 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:59 PM PDT 24
Peak memory 220292 kb
Host smart-5ac83595-ea20-4b5e-8039-f309f7a20929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972200262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2972200262
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.923288095
Short name T92
Test name
Test status
Simulation time 28602474 ps
CPU time 1.17 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:10:43 PM PDT 24
Peak memory 205652 kb
Host smart-f725c900-1308-436e-9418-6bf334c0469a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923288095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.923288095
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4284566117
Short name T363
Test name
Test status
Simulation time 231107850 ps
CPU time 10.03 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 213968 kb
Host smart-064c4fde-57aa-40cf-8b5a-8407559adceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284566117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4284566117
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3274298688
Short name T244
Test name
Test status
Simulation time 1173450504 ps
CPU time 9.91 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:25 PM PDT 24
Peak memory 214504 kb
Host smart-7b11a947-11b3-4eb0-b69c-095c195a1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274298688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3274298688
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3462655413
Short name T217
Test name
Test status
Simulation time 420008141 ps
CPU time 16.47 seconds
Started May 18 04:12:48 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 215692 kb
Host smart-2bc36160-9a31-439d-92cd-533a7d810e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462655413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3462655413
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2687903936
Short name T209
Test name
Test status
Simulation time 730417578 ps
CPU time 20.28 seconds
Started May 18 04:10:20 PM PDT 24
Finished May 18 04:10:41 PM PDT 24
Peak memory 214752 kb
Host smart-5e7110c3-a177-4513-bfcc-edd8c4253169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687903936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2687903936
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4141514785
Short name T28
Test name
Test status
Simulation time 65391539 ps
CPU time 1.83 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 216000 kb
Host smart-83482f74-5e3e-4229-a0e4-e21f3ce65250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141514785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4141514785
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.787541372
Short name T90
Test name
Test status
Simulation time 141015528 ps
CPU time 3.72 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:19 PM PDT 24
Peak memory 218792 kb
Host smart-1346d8b0-da37-4e7c-9826-8ce43f0fc410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787541372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.787541372
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3696389668
Short name T161
Test name
Test status
Simulation time 111087362 ps
CPU time 4.24 seconds
Started May 18 04:13:08 PM PDT 24
Finished May 18 04:13:13 PM PDT 24
Peak memory 222316 kb
Host smart-df9f583f-f16b-429d-b051-ae4721bb746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696389668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3696389668
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1293951304
Short name T159
Test name
Test status
Simulation time 52561514 ps
CPU time 1.83 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:17 PM PDT 24
Peak memory 214576 kb
Host smart-95d00d1f-143d-47e1-a8b2-30c4c7c1a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293951304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1293951304
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3835335997
Short name T160
Test name
Test status
Simulation time 67875542 ps
CPU time 4.42 seconds
Started May 18 04:10:17 PM PDT 24
Finished May 18 04:10:23 PM PDT 24
Peak memory 217588 kb
Host smart-034afc8e-e4b4-4087-a871-d98a6c7df392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835335997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3835335997
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.871833833
Short name T256
Test name
Test status
Simulation time 582562486 ps
CPU time 22.42 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:21 PM PDT 24
Peak memory 221472 kb
Host smart-2dc3f0d9-ae08-45e1-97be-d2acdb9653f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871833833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.871833833
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1255129698
Short name T221
Test name
Test status
Simulation time 487944355 ps
CPU time 8.25 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 214332 kb
Host smart-ba2e338d-c5d0-427a-96be-683988a02817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255129698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1255129698
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3287993674
Short name T364
Test name
Test status
Simulation time 590834797 ps
CPU time 26.82 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 215800 kb
Host smart-8daa3f3a-30ae-4aa5-ba45-888ee6a2f5fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287993674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3287993674
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2927397104
Short name T145
Test name
Test status
Simulation time 818882715 ps
CPU time 8.92 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 213800 kb
Host smart-bd28ad83-7ccc-4ef2-a1db-7df02026de2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927397104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2927397104
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.188044947
Short name T165
Test name
Test status
Simulation time 71830384 ps
CPU time 1.96 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:14 PM PDT 24
Peak memory 217096 kb
Host smart-c935e6af-69f4-434e-859d-8c0b4adddfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188044947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.188044947
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.435576845
Short name T180
Test name
Test status
Simulation time 66573856 ps
CPU time 2.81 seconds
Started May 18 04:11:11 PM PDT 24
Finished May 18 04:11:15 PM PDT 24
Peak memory 211056 kb
Host smart-e301f38e-b0f7-4ffd-8b34-0c0b8a24d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435576845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.435576845
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3973142390
Short name T266
Test name
Test status
Simulation time 145666604 ps
CPU time 5.04 seconds
Started May 18 04:09:59 PM PDT 24
Finished May 18 04:10:05 PM PDT 24
Peak memory 214092 kb
Host smart-aea7a96e-f9c3-43c0-9641-bed0e1b2badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973142390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3973142390
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1167216646
Short name T202
Test name
Test status
Simulation time 5755873000 ps
CPU time 59.04 seconds
Started May 18 04:11:41 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 217312 kb
Host smart-25c2d9a2-1870-4ca4-b5c9-63215be24afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167216646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1167216646
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2427647938
Short name T264
Test name
Test status
Simulation time 5851287172 ps
CPU time 54.84 seconds
Started May 18 04:10:39 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 214756 kb
Host smart-58e169ea-f85b-4a83-99ae-3d7fc9504b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427647938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2427647938
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3872475472
Short name T138
Test name
Test status
Simulation time 252206118 ps
CPU time 7.61 seconds
Started May 18 04:03:00 PM PDT 24
Finished May 18 04:03:08 PM PDT 24
Peak memory 208068 kb
Host smart-0d8c30c5-24ae-4171-a04d-1d39cd4e4303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872475472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3872475472
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4206807750
Short name T142
Test name
Test status
Simulation time 55141148 ps
CPU time 2.76 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 209652 kb
Host smart-4a0dac53-8ca9-4772-9e5d-1ee01dfec4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206807750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4206807750
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.756111263
Short name T166
Test name
Test status
Simulation time 127552641 ps
CPU time 3.58 seconds
Started May 18 04:11:38 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 215784 kb
Host smart-28850372-769b-4b2f-bbef-c2d60cadcc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756111263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.756111263
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2918555802
Short name T55
Test name
Test status
Simulation time 208366672 ps
CPU time 3.16 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 222216 kb
Host smart-d00f7e36-cabd-4820-895f-078cba4e3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918555802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2918555802
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.425174510
Short name T2
Test name
Test status
Simulation time 139520261 ps
CPU time 6.16 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:29 PM PDT 24
Peak memory 217480 kb
Host smart-247b56df-57c5-4f16-a303-bc24dc94d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425174510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.425174510
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3573706426
Short name T973
Test name
Test status
Simulation time 1795569709 ps
CPU time 37.6 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:47 PM PDT 24
Peak memory 222208 kb
Host smart-77bfdcb4-72e3-424f-92d7-3a5492b1534b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573706426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3573706426
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3816380059
Short name T897
Test name
Test status
Simulation time 165278552 ps
CPU time 8.03 seconds
Started May 18 04:11:33 PM PDT 24
Finished May 18 04:11:44 PM PDT 24
Peak memory 213940 kb
Host smart-58c12eea-16a9-4942-b915-c91eb20db018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816380059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3816380059
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2594622320
Short name T324
Test name
Test status
Simulation time 227963808 ps
CPU time 6.66 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:12:02 PM PDT 24
Peak memory 208148 kb
Host smart-31d2992f-806b-4da5-b3b3-6c2cc1c8634e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594622320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2594622320
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2451053719
Short name T187
Test name
Test status
Simulation time 105332464 ps
CPU time 3.63 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:23 PM PDT 24
Peak memory 208308 kb
Host smart-b5f64b30-4c40-4204-a8a7-fd2c021034fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451053719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2451053719
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4016469622
Short name T84
Test name
Test status
Simulation time 386887839 ps
CPU time 12.11 seconds
Started May 18 04:12:22 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 222020 kb
Host smart-e0d84d8e-27b0-4232-a9eb-3c6e6d4a421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016469622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4016469622
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.626893831
Short name T112
Test name
Test status
Simulation time 1352206347 ps
CPU time 40.99 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:43 PM PDT 24
Peak memory 213744 kb
Host smart-f7f52a0b-4e67-4de8-9b4c-e97c1b859014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626893831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.626893831
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2861148412
Short name T149
Test name
Test status
Simulation time 39462345 ps
CPU time 1.49 seconds
Started May 18 04:12:42 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 209752 kb
Host smart-fb28091d-f3b3-4dff-a960-8875f67c584a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861148412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2861148412
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.655885716
Short name T154
Test name
Test status
Simulation time 316713311 ps
CPU time 2.24 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:16 PM PDT 24
Peak memory 209612 kb
Host smart-b94b9410-387a-4741-8ced-4bd0eb8594fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655885716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.655885716
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2598893785
Short name T162
Test name
Test status
Simulation time 1424199016 ps
CPU time 6.67 seconds
Started May 18 04:11:56 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 217152 kb
Host smart-4089f627-384a-4b00-8ae2-5fac24723445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598893785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2598893785
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1503028323
Short name T949
Test name
Test status
Simulation time 423108437 ps
CPU time 7.79 seconds
Started May 18 04:11:12 PM PDT 24
Finished May 18 04:11:21 PM PDT 24
Peak memory 210808 kb
Host smart-8946baea-c8fe-4bb3-afb3-8fdf377f8288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503028323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1503028323
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.643021643
Short name T306
Test name
Test status
Simulation time 550247948 ps
CPU time 4.42 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 209828 kb
Host smart-a2e70a94-a19b-488d-9bf3-5876b0459498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643021643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.643021643
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1037277724
Short name T309
Test name
Test status
Simulation time 84884945 ps
CPU time 4.56 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 210220 kb
Host smart-fe293120-1077-401d-9e46-474e8a760e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037277724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1037277724
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1012555581
Short name T356
Test name
Test status
Simulation time 178231288 ps
CPU time 4.44 seconds
Started May 18 04:11:28 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 214016 kb
Host smart-325d395b-80fc-4b12-b911-b7f8dd780c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012555581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1012555581
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2317887714
Short name T212
Test name
Test status
Simulation time 1200470436 ps
CPU time 44.81 seconds
Started May 18 04:12:08 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 222412 kb
Host smart-9f18229c-3495-4846-a9e7-cfbe1aafbfc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317887714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2317887714
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1210356648
Short name T6
Test name
Test status
Simulation time 2100046072 ps
CPU time 49.58 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:13:08 PM PDT 24
Peak memory 220772 kb
Host smart-0f20eb69-9fc9-4064-bd10-635c8a022ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210356648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1210356648
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.931490235
Short name T258
Test name
Test status
Simulation time 1520773659 ps
CPU time 39.37 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 215512 kb
Host smart-ce890c36-aab8-4bb3-ac16-c8c9eb8ce198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931490235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.931490235
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.260641883
Short name T201
Test name
Test status
Simulation time 295759664 ps
CPU time 14.62 seconds
Started May 18 04:12:34 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 222340 kb
Host smart-4b35ae8b-51ea-4521-9a91-cb8ff432241b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260641883 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.260641883
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.247860514
Short name T211
Test name
Test status
Simulation time 289796884 ps
CPU time 8.65 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 214052 kb
Host smart-50d559ff-e34e-4305-9a4c-65b78140886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247860514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.247860514
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1068390383
Short name T199
Test name
Test status
Simulation time 309159164 ps
CPU time 4.5 seconds
Started May 18 04:13:22 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 222292 kb
Host smart-f1ae3914-d611-4493-8e39-aa06f861349e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068390383 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1068390383
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1498780333
Short name T445
Test name
Test status
Simulation time 116408780 ps
CPU time 1.68 seconds
Started May 18 04:02:13 PM PDT 24
Finished May 18 04:02:16 PM PDT 24
Peak memory 214004 kb
Host smart-fb12aab9-90d9-4360-97ee-16a5f4ceb3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498780333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1498780333
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.949254177
Short name T118
Test name
Test status
Simulation time 415787672 ps
CPU time 5.63 seconds
Started May 18 04:02:40 PM PDT 24
Finished May 18 04:02:46 PM PDT 24
Peak memory 208880 kb
Host smart-1c0b3a65-51f4-4d86-8ff4-41caa2ef8616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949254177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
949254177
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1254581782
Short name T148
Test name
Test status
Simulation time 44411068 ps
CPU time 1.59 seconds
Started May 18 04:09:51 PM PDT 24
Finished May 18 04:09:55 PM PDT 24
Peak memory 209556 kb
Host smart-05d800a0-0176-4014-a6bf-347aa58cbbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254581782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1254581782
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3248543793
Short name T164
Test name
Test status
Simulation time 468369827 ps
CPU time 5.61 seconds
Started May 18 04:12:55 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 217672 kb
Host smart-7728d0c8-a56c-47a5-9526-904d4c348927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248543793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3248543793
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3592962975
Short name T249
Test name
Test status
Simulation time 18214493421 ps
CPU time 32.33 seconds
Started May 18 04:09:43 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 222236 kb
Host smart-c621952c-2965-46e5-ba52-666616b9a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592962975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3592962975
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1591569599
Short name T342
Test name
Test status
Simulation time 203838065 ps
CPU time 8.64 seconds
Started May 18 04:09:52 PM PDT 24
Finished May 18 04:10:02 PM PDT 24
Peak memory 215224 kb
Host smart-b523be67-8ff2-4ab1-b694-d7a3e96980b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591569599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1591569599
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3634790030
Short name T414
Test name
Test status
Simulation time 2831606620 ps
CPU time 123.26 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 214020 kb
Host smart-763d6948-0cc5-41fa-82c1-a991e01cd67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634790030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3634790030
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4221728107
Short name T178
Test name
Test status
Simulation time 600102062 ps
CPU time 6.85 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:10:49 PM PDT 24
Peak memory 222068 kb
Host smart-a08616d5-40f4-4b6e-a602-8248d94fe038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221728107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4221728107
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.911644205
Short name T240
Test name
Test status
Simulation time 253099371 ps
CPU time 14.03 seconds
Started May 18 04:10:47 PM PDT 24
Finished May 18 04:11:02 PM PDT 24
Peak memory 214120 kb
Host smart-325a6039-63d6-44b3-a0bb-8363181d0120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911644205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.911644205
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3349201441
Short name T247
Test name
Test status
Simulation time 311036297 ps
CPU time 7.48 seconds
Started May 18 04:10:47 PM PDT 24
Finished May 18 04:10:56 PM PDT 24
Peak memory 210476 kb
Host smart-acef2436-5d68-4a4f-b4de-5bc095bc536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349201441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3349201441
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2386095362
Short name T314
Test name
Test status
Simulation time 388251177 ps
CPU time 12.9 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 208732 kb
Host smart-8e1c17b0-2bf2-4186-9985-1f7f334c9217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386095362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2386095362
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4159817650
Short name T31
Test name
Test status
Simulation time 1349174716 ps
CPU time 9.69 seconds
Started May 18 04:11:05 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 213956 kb
Host smart-b0bece54-0b07-4c49-8113-7b1d80b780d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159817650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4159817650
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1637431694
Short name T317
Test name
Test status
Simulation time 950793713 ps
CPU time 6.74 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 214188 kb
Host smart-7192745b-2296-4920-bdb3-17394d92ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637431694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1637431694
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2919192851
Short name T255
Test name
Test status
Simulation time 66824370 ps
CPU time 3.7 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 215456 kb
Host smart-37875dc9-e586-4c60-8597-e3390c05edc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919192851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2919192851
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4111258083
Short name T79
Test name
Test status
Simulation time 440921194 ps
CPU time 7.37 seconds
Started May 18 04:11:15 PM PDT 24
Finished May 18 04:11:24 PM PDT 24
Peak memory 222180 kb
Host smart-0e6485d2-bdca-4114-a73c-766eed5bdd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111258083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4111258083
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3872137984
Short name T280
Test name
Test status
Simulation time 948078106 ps
CPU time 10.19 seconds
Started May 18 04:11:31 PM PDT 24
Finished May 18 04:11:44 PM PDT 24
Peak memory 222108 kb
Host smart-7b89ef9a-07a4-4506-af2e-25aaead4b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872137984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3872137984
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2364077232
Short name T207
Test name
Test status
Simulation time 58913279 ps
CPU time 2.83 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:11:50 PM PDT 24
Peak memory 216276 kb
Host smart-9349c919-6f39-4024-97ea-78d29eb3c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364077232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2364077232
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.53693822
Short name T284
Test name
Test status
Simulation time 203739498 ps
CPU time 6.27 seconds
Started May 18 04:10:08 PM PDT 24
Finished May 18 04:10:15 PM PDT 24
Peak memory 213948 kb
Host smart-9fcf5549-6a97-40cf-85cb-d637bb2e133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53693822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.53693822
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1626811866
Short name T360
Test name
Test status
Simulation time 693117231 ps
CPU time 10.39 seconds
Started May 18 04:12:05 PM PDT 24
Finished May 18 04:12:16 PM PDT 24
Peak memory 213980 kb
Host smart-6d4a65ec-2a85-4515-aa8e-87aa7937dcdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626811866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1626811866
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3003602192
Short name T300
Test name
Test status
Simulation time 3754679648 ps
CPU time 61.97 seconds
Started May 18 04:12:30 PM PDT 24
Finished May 18 04:13:34 PM PDT 24
Peak memory 217008 kb
Host smart-f1c732da-3823-4ce7-b23d-003462b53c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003602192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3003602192
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1182240481
Short name T1007
Test name
Test status
Simulation time 34498076 ps
CPU time 2.56 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:38 PM PDT 24
Peak memory 214040 kb
Host smart-28d0105b-0c02-4680-a999-f8a8d24842fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182240481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1182240481
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3384173065
Short name T415
Test name
Test status
Simulation time 67721747 ps
CPU time 4.36 seconds
Started May 18 04:12:39 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 215032 kb
Host smart-d51b28a5-26d2-476f-b4cc-eb2e9660b8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384173065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3384173065
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1161025620
Short name T340
Test name
Test status
Simulation time 80945171 ps
CPU time 2.93 seconds
Started May 18 04:12:34 PM PDT 24
Finished May 18 04:12:40 PM PDT 24
Peak memory 209416 kb
Host smart-7474abbf-7437-426e-a052-f1c2095cfd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161025620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1161025620
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1378657175
Short name T298
Test name
Test status
Simulation time 525470555 ps
CPU time 5.65 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:21 PM PDT 24
Peak memory 219108 kb
Host smart-470931e1-55ff-40e0-a151-7f3b84c87672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378657175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1378657175
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3267675316
Short name T210
Test name
Test status
Simulation time 293244261 ps
CPU time 6.44 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:26 PM PDT 24
Peak memory 222456 kb
Host smart-662c67f6-c1e3-4283-b2de-6dc673d657ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267675316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3267675316
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4053682731
Short name T163
Test name
Test status
Simulation time 76237899 ps
CPU time 2.84 seconds
Started May 18 04:10:42 PM PDT 24
Finished May 18 04:10:47 PM PDT 24
Peak memory 217380 kb
Host smart-2908db4f-5222-4899-803f-f372a91aefb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053682731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4053682731
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1248904828
Short name T157
Test name
Test status
Simulation time 941437597 ps
CPU time 6.91 seconds
Started May 18 04:11:43 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 222356 kb
Host smart-4285dc73-beb0-4b5d-b73a-10ee61e2b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248904828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1248904828
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1756580341
Short name T524
Test name
Test status
Simulation time 71931829 ps
CPU time 4.6 seconds
Started May 18 04:02:11 PM PDT 24
Finished May 18 04:02:18 PM PDT 24
Peak memory 205660 kb
Host smart-f1aec5fd-0318-46ba-b44f-5ce70ca1679b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756580341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
756580341
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3928990811
Short name T497
Test name
Test status
Simulation time 522763140 ps
CPU time 7.65 seconds
Started May 18 04:02:11 PM PDT 24
Finished May 18 04:02:20 PM PDT 24
Peak memory 205540 kb
Host smart-00d3a11f-a24f-47b9-b698-60fad9382e81
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928990811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
928990811
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1649148811
Short name T469
Test name
Test status
Simulation time 18282537 ps
CPU time 0.95 seconds
Started May 18 04:02:13 PM PDT 24
Finished May 18 04:02:16 PM PDT 24
Peak memory 205568 kb
Host smart-527cafb7-fdc5-4adf-a681-db776d7d5068
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649148811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
649148811
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3991194182
Short name T131
Test name
Test status
Simulation time 43754441 ps
CPU time 1.18 seconds
Started May 18 04:02:12 PM PDT 24
Finished May 18 04:02:15 PM PDT 24
Peak memory 213796 kb
Host smart-be5a3637-749b-46aa-9b05-910203f306b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991194182 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3991194182
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2823566822
Short name T136
Test name
Test status
Simulation time 14197228 ps
CPU time 1.11 seconds
Started May 18 04:02:13 PM PDT 24
Finished May 18 04:02:15 PM PDT 24
Peak memory 205728 kb
Host smart-38a2cedf-fd64-4e76-a15e-38b41954f59e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823566822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2823566822
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.277589103
Short name T450
Test name
Test status
Simulation time 86307131 ps
CPU time 0.81 seconds
Started May 18 04:02:10 PM PDT 24
Finished May 18 04:02:12 PM PDT 24
Peak memory 205340 kb
Host smart-3104bb4e-3820-4c35-81e6-b8afc1bc3904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277589103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.277589103
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1886569069
Short name T493
Test name
Test status
Simulation time 74423774 ps
CPU time 2.17 seconds
Started May 18 04:02:11 PM PDT 24
Finished May 18 04:02:14 PM PDT 24
Peak memory 222088 kb
Host smart-77b51baf-9d46-4428-afaa-1fdc99a44831
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886569069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1886569069
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1603720724
Short name T440
Test name
Test status
Simulation time 716886655 ps
CPU time 4.34 seconds
Started May 18 04:02:19 PM PDT 24
Finished May 18 04:02:24 PM PDT 24
Peak memory 205560 kb
Host smart-3a0036ed-2786-4724-975d-9ed85a826595
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603720724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
603720724
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1452377993
Short name T137
Test name
Test status
Simulation time 41512449 ps
CPU time 0.89 seconds
Started May 18 04:02:19 PM PDT 24
Finished May 18 04:02:21 PM PDT 24
Peak memory 205416 kb
Host smart-67402563-9ebc-4a24-bbe4-deea5e6806d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452377993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
452377993
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2502257943
Short name T505
Test name
Test status
Simulation time 20447975 ps
CPU time 1.24 seconds
Started May 18 04:02:20 PM PDT 24
Finished May 18 04:02:22 PM PDT 24
Peak memory 205652 kb
Host smart-3d9cee3e-4cbe-4a21-94fe-c985234c87b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502257943 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2502257943
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.719387133
Short name T536
Test name
Test status
Simulation time 94458944 ps
CPU time 1.1 seconds
Started May 18 04:02:20 PM PDT 24
Finished May 18 04:02:22 PM PDT 24
Peak memory 205640 kb
Host smart-9b4b908d-8e8b-4289-bfbb-488640f278ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719387133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.719387133
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3708287578
Short name T420
Test name
Test status
Simulation time 13676636 ps
CPU time 0.73 seconds
Started May 18 04:02:23 PM PDT 24
Finished May 18 04:02:24 PM PDT 24
Peak memory 205332 kb
Host smart-9809badb-42b7-43b7-9a7b-ec0857346206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708287578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3708287578
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2359567305
Short name T537
Test name
Test status
Simulation time 1172098420 ps
CPU time 5.31 seconds
Started May 18 04:02:12 PM PDT 24
Finished May 18 04:02:19 PM PDT 24
Peak memory 214092 kb
Host smart-9cb35a82-7661-413b-bb0c-fc3475dd474d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359567305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2359567305
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.79360018
Short name T500
Test name
Test status
Simulation time 1599037458 ps
CPU time 7.83 seconds
Started May 18 04:02:18 PM PDT 24
Finished May 18 04:02:27 PM PDT 24
Peak memory 219800 kb
Host smart-8f7c75a7-d8a0-4688-a44f-987924428ab6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79360018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_shadow_reg_errors_with_csr_rw.79360018
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1131553803
Short name T522
Test name
Test status
Simulation time 25292023 ps
CPU time 1.59 seconds
Started May 18 04:02:21 PM PDT 24
Finished May 18 04:02:24 PM PDT 24
Peak memory 205684 kb
Host smart-1eb38965-bdc3-4607-9138-eaec8dda38e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131553803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1131553803
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3745061566
Short name T527
Test name
Test status
Simulation time 42806530 ps
CPU time 1.29 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:03 PM PDT 24
Peak memory 205712 kb
Host smart-9e71aa50-db54-4676-a81c-72675369546f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745061566 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3745061566
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2921904124
Short name T447
Test name
Test status
Simulation time 15943692 ps
CPU time 1 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:05 PM PDT 24
Peak memory 205416 kb
Host smart-9e648dcd-07c4-4e91-8ee5-6620cb40b1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921904124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2921904124
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2339836108
Short name T468
Test name
Test status
Simulation time 40059627 ps
CPU time 0.72 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:02 PM PDT 24
Peak memory 205336 kb
Host smart-eafda6a8-f5ae-49cf-9064-6dfa2750e1c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339836108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2339836108
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4225555330
Short name T520
Test name
Test status
Simulation time 178526501 ps
CPU time 2.21 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:06 PM PDT 24
Peak memory 205452 kb
Host smart-0ed48253-e2b0-41a6-abca-ebe0e2d651fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225555330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4225555330
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3154644608
Short name T490
Test name
Test status
Simulation time 714600194 ps
CPU time 14.86 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:19 PM PDT 24
Peak memory 214404 kb
Host smart-d76c2607-9b65-4f8b-9889-2dc07bcf9fa9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154644608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3154644608
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.476411472
Short name T452
Test name
Test status
Simulation time 294280143 ps
CPU time 2.45 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:04 PM PDT 24
Peak memory 216080 kb
Host smart-f8f8fd2d-255d-4679-a392-bf376e8d7b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476411472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.476411472
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.59520217
Short name T504
Test name
Test status
Simulation time 74168332 ps
CPU time 1.18 seconds
Started May 18 04:03:10 PM PDT 24
Finished May 18 04:03:12 PM PDT 24
Peak memory 213888 kb
Host smart-5d7fb1c8-f479-4afc-b1c7-974b86eeca06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59520217 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.59520217
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1578255527
Short name T498
Test name
Test status
Simulation time 11877284 ps
CPU time 0.72 seconds
Started May 18 04:03:08 PM PDT 24
Finished May 18 04:03:10 PM PDT 24
Peak memory 205356 kb
Host smart-c63ce770-20ac-48e3-93f5-b07cbad5e5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578255527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1578255527
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1238588533
Short name T171
Test name
Test status
Simulation time 96645650 ps
CPU time 3.27 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:07 PM PDT 24
Peak memory 222072 kb
Host smart-a22e08c7-1150-4dbf-907f-713d4fa401dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238588533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1238588533
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2003096191
Short name T543
Test name
Test status
Simulation time 236181412 ps
CPU time 8.84 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:10 PM PDT 24
Peak memory 214028 kb
Host smart-c0d71bc8-428f-4093-a896-0f3f086cdd7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003096191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2003096191
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2335100392
Short name T515
Test name
Test status
Simulation time 65086350 ps
CPU time 1.88 seconds
Started May 18 04:03:01 PM PDT 24
Finished May 18 04:03:03 PM PDT 24
Peak memory 205624 kb
Host smart-114c8172-e548-48d4-a9a7-99d63cb58f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335100392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2335100392
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.259459459
Short name T471
Test name
Test status
Simulation time 34784360 ps
CPU time 1.46 seconds
Started May 18 04:03:12 PM PDT 24
Finished May 18 04:03:14 PM PDT 24
Peak memory 213836 kb
Host smart-67753cbf-1a1e-47b9-bfe5-2533a5f8ec45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259459459 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.259459459
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.409993973
Short name T434
Test name
Test status
Simulation time 51166789 ps
CPU time 1.16 seconds
Started May 18 04:03:07 PM PDT 24
Finished May 18 04:03:08 PM PDT 24
Peak memory 205604 kb
Host smart-03538c9c-e694-4219-b53c-0ac5b18a7770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409993973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.409993973
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4099629099
Short name T461
Test name
Test status
Simulation time 23911022 ps
CPU time 0.74 seconds
Started May 18 04:03:09 PM PDT 24
Finished May 18 04:03:11 PM PDT 24
Peak memory 205280 kb
Host smart-56d3406a-54dd-4aa0-89ef-eae582b81ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099629099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4099629099
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1730751408
Short name T512
Test name
Test status
Simulation time 438236298 ps
CPU time 10.9 seconds
Started May 18 04:03:08 PM PDT 24
Finished May 18 04:03:20 PM PDT 24
Peak memory 213948 kb
Host smart-9e6102ce-c13c-43e0-a194-13c34c5f634e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730751408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1730751408
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.836930238
Short name T542
Test name
Test status
Simulation time 220403400 ps
CPU time 1.66 seconds
Started May 18 04:03:08 PM PDT 24
Finished May 18 04:03:11 PM PDT 24
Peak memory 213848 kb
Host smart-c21abe9f-94e2-4199-bead-fc473abdb76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836930238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.836930238
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1885560646
Short name T139
Test name
Test status
Simulation time 468084719 ps
CPU time 9.05 seconds
Started May 18 04:03:06 PM PDT 24
Finished May 18 04:03:15 PM PDT 24
Peak memory 209192 kb
Host smart-156bd1dc-b311-4e0e-902e-fa93c1444bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885560646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1885560646
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3424103252
Short name T486
Test name
Test status
Simulation time 67900192 ps
CPU time 1.15 seconds
Started May 18 04:03:15 PM PDT 24
Finished May 18 04:03:17 PM PDT 24
Peak memory 205616 kb
Host smart-b070ecd2-89ed-4c12-a2d5-b4bf1ffd6000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424103252 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3424103252
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3109396542
Short name T132
Test name
Test status
Simulation time 33216822 ps
CPU time 0.69 seconds
Started May 18 04:03:07 PM PDT 24
Finished May 18 04:03:09 PM PDT 24
Peak memory 205272 kb
Host smart-235504a1-bd39-4285-8c5e-24bf23e0409b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109396542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3109396542
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2528569673
Short name T130
Test name
Test status
Simulation time 71411618 ps
CPU time 1.97 seconds
Started May 18 04:03:14 PM PDT 24
Finished May 18 04:03:17 PM PDT 24
Peak memory 205564 kb
Host smart-875249ba-e161-4993-80e8-be5230ac2bc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528569673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2528569673
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2751165253
Short name T116
Test name
Test status
Simulation time 2429721301 ps
CPU time 3.74 seconds
Started May 18 04:03:06 PM PDT 24
Finished May 18 04:03:11 PM PDT 24
Peak memory 214048 kb
Host smart-f3e72cfc-5e4d-4f3c-b9dd-47429cd1f9c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751165253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2751165253
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4177548886
Short name T517
Test name
Test status
Simulation time 826947746 ps
CPU time 9.07 seconds
Started May 18 04:03:11 PM PDT 24
Finished May 18 04:03:20 PM PDT 24
Peak memory 214020 kb
Host smart-39062ab0-231a-4220-9a58-fdcad760011f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177548886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4177548886
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1045211321
Short name T122
Test name
Test status
Simulation time 494022778 ps
CPU time 2.81 seconds
Started May 18 04:03:08 PM PDT 24
Finished May 18 04:03:11 PM PDT 24
Peak memory 213816 kb
Host smart-96f9214a-beac-4a58-9707-750161d71acc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045211321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1045211321
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1783368329
Short name T530
Test name
Test status
Simulation time 33499258 ps
CPU time 1.4 seconds
Started May 18 04:03:16 PM PDT 24
Finished May 18 04:03:19 PM PDT 24
Peak memory 213888 kb
Host smart-5533cb85-0ebf-4d62-aab1-f4807e56cf6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783368329 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1783368329
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3751214893
Short name T533
Test name
Test status
Simulation time 45095084 ps
CPU time 0.96 seconds
Started May 18 04:03:15 PM PDT 24
Finished May 18 04:03:17 PM PDT 24
Peak memory 205384 kb
Host smart-43d8cbcd-1423-4dc8-b2d1-5f65c9d6fb56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751214893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3751214893
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3669762443
Short name T435
Test name
Test status
Simulation time 73746526 ps
CPU time 0.73 seconds
Started May 18 04:03:16 PM PDT 24
Finished May 18 04:03:18 PM PDT 24
Peak memory 205180 kb
Host smart-2aad2b97-1bd9-4068-b394-78e896e835d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669762443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3669762443
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.86452515
Short name T446
Test name
Test status
Simulation time 60157320 ps
CPU time 2.08 seconds
Started May 18 04:03:16 PM PDT 24
Finished May 18 04:03:19 PM PDT 24
Peak memory 205552 kb
Host smart-475f972a-09ab-4b28-9a3e-faf587c1c399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86452515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sam
e_csr_outstanding.86452515
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3703566469
Short name T115
Test name
Test status
Simulation time 1588356397 ps
CPU time 2.9 seconds
Started May 18 04:03:14 PM PDT 24
Finished May 18 04:03:18 PM PDT 24
Peak memory 214104 kb
Host smart-945ccecd-6664-47ac-a6fb-b03d449f99a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703566469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3703566469
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1799103451
Short name T489
Test name
Test status
Simulation time 487797568 ps
CPU time 4.3 seconds
Started May 18 04:03:15 PM PDT 24
Finished May 18 04:03:21 PM PDT 24
Peak memory 216372 kb
Host smart-be027372-9b25-4d6d-8725-7a9a0f0446fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799103451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1799103451
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3546257779
Short name T495
Test name
Test status
Simulation time 64746822 ps
CPU time 1.4 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:32 PM PDT 24
Peak memory 213816 kb
Host smart-a09174f1-c3a9-4ff5-b050-e462bb0eafbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546257779 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3546257779
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1122080370
Short name T477
Test name
Test status
Simulation time 111568410 ps
CPU time 0.97 seconds
Started May 18 04:03:24 PM PDT 24
Finished May 18 04:03:26 PM PDT 24
Peak memory 205288 kb
Host smart-2088e534-2006-49eb-a0a5-08832062de9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122080370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1122080370
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.474547133
Short name T430
Test name
Test status
Simulation time 83230188 ps
CPU time 0.69 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:30 PM PDT 24
Peak memory 205252 kb
Host smart-4720242b-4577-4165-a9a4-44148e61365a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474547133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.474547133
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2443030783
Short name T454
Test name
Test status
Simulation time 3396309082 ps
CPU time 41.76 seconds
Started May 18 04:03:21 PM PDT 24
Finished May 18 04:04:03 PM PDT 24
Peak memory 230368 kb
Host smart-056e8d2d-54a4-43ff-ae59-732478b58cdc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443030783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2443030783
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.826595427
Short name T444
Test name
Test status
Simulation time 832973733 ps
CPU time 5.14 seconds
Started May 18 04:03:21 PM PDT 24
Finished May 18 04:03:27 PM PDT 24
Peak memory 213780 kb
Host smart-8886465e-5154-48b5-9a41-d0405f81c25b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826595427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.826595427
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2690770513
Short name T141
Test name
Test status
Simulation time 309473681 ps
CPU time 1.56 seconds
Started May 18 04:03:23 PM PDT 24
Finished May 18 04:03:25 PM PDT 24
Peak memory 213804 kb
Host smart-95ec9598-49eb-4c18-ac2c-aff17a5eb5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690770513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2690770513
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3892597433
Short name T170
Test name
Test status
Simulation time 26833940 ps
CPU time 1.54 seconds
Started May 18 04:03:28 PM PDT 24
Finished May 18 04:03:30 PM PDT 24
Peak memory 205616 kb
Host smart-84c18bed-da22-4db4-aba7-1c55213fd804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892597433 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3892597433
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2094744035
Short name T538
Test name
Test status
Simulation time 42604856 ps
CPU time 1.01 seconds
Started May 18 04:03:22 PM PDT 24
Finished May 18 04:03:23 PM PDT 24
Peak memory 205544 kb
Host smart-8fd26edc-28c9-42fd-ba20-0497c17775f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094744035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2094744035
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1396736644
Short name T508
Test name
Test status
Simulation time 9584334 ps
CPU time 0.81 seconds
Started May 18 04:03:24 PM PDT 24
Finished May 18 04:03:25 PM PDT 24
Peak memory 205364 kb
Host smart-bec73ebd-4fe2-4e53-ae0a-da4b4b8a67b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396736644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1396736644
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3802911525
Short name T156
Test name
Test status
Simulation time 464600320 ps
CPU time 4 seconds
Started May 18 04:03:24 PM PDT 24
Finished May 18 04:03:28 PM PDT 24
Peak memory 214024 kb
Host smart-f32ff2f1-0105-46b2-b7e5-a6853f49cec5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802911525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3802911525
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2175901245
Short name T485
Test name
Test status
Simulation time 408777907 ps
CPU time 11.39 seconds
Started May 18 04:03:22 PM PDT 24
Finished May 18 04:03:34 PM PDT 24
Peak memory 214016 kb
Host smart-3d130b07-69ab-47bb-980c-7138a6dcaa37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175901245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2175901245
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2885811306
Short name T473
Test name
Test status
Simulation time 204965561 ps
CPU time 2.67 seconds
Started May 18 04:03:28 PM PDT 24
Finished May 18 04:03:31 PM PDT 24
Peak memory 213884 kb
Host smart-372b4226-2b7a-4a94-b954-34824ce4aada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885811306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2885811306
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2997114728
Short name T516
Test name
Test status
Simulation time 84952889 ps
CPU time 1.31 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:31 PM PDT 24
Peak memory 213848 kb
Host smart-7c3cf375-933d-4497-a65d-3398f92e0823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997114728 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2997114728
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4124494561
Short name T128
Test name
Test status
Simulation time 93949769 ps
CPU time 1.09 seconds
Started May 18 04:03:28 PM PDT 24
Finished May 18 04:03:29 PM PDT 24
Peak memory 205480 kb
Host smart-7b3c6071-341a-4871-b47e-38dcc9aebb69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124494561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4124494561
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.8457968
Short name T423
Test name
Test status
Simulation time 42490675 ps
CPU time 0.86 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:31 PM PDT 24
Peak memory 205348 kb
Host smart-856e0ae4-5248-4488-a73f-f4ad9b5e98f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8457968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.8457968
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.353235843
Short name T541
Test name
Test status
Simulation time 89665057 ps
CPU time 3.65 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:35 PM PDT 24
Peak memory 205472 kb
Host smart-c6ec8a14-c7b4-4425-a75c-0521b500fa68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353235843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.353235843
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1633713891
Short name T492
Test name
Test status
Simulation time 1070017805 ps
CPU time 5.95 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:36 PM PDT 24
Peak memory 214040 kb
Host smart-b46b25c5-ee15-4e7d-8158-704aed80c7dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633713891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1633713891
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4062099417
Short name T503
Test name
Test status
Simulation time 395732555 ps
CPU time 5.03 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:35 PM PDT 24
Peak memory 213992 kb
Host smart-99715b06-b64a-4978-9fb0-bba1eee7b40e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062099417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4062099417
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.68127541
Short name T113
Test name
Test status
Simulation time 158081701 ps
CPU time 3.9 seconds
Started May 18 04:03:33 PM PDT 24
Finished May 18 04:03:38 PM PDT 24
Peak memory 216872 kb
Host smart-5b4d0e49-ff13-4bd5-8d80-af84aa0b0fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68127541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.68127541
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1307087703
Short name T168
Test name
Test status
Simulation time 464421414 ps
CPU time 1.37 seconds
Started May 18 04:03:35 PM PDT 24
Finished May 18 04:03:37 PM PDT 24
Peak memory 213412 kb
Host smart-97d5f33b-9055-47a1-bd99-eebee365030a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307087703 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1307087703
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.675890176
Short name T127
Test name
Test status
Simulation time 11281391 ps
CPU time 0.87 seconds
Started May 18 04:03:31 PM PDT 24
Finished May 18 04:03:33 PM PDT 24
Peak memory 205324 kb
Host smart-d0042063-fde4-47cc-bdf0-c6e80936ccd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675890176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.675890176
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.892875733
Short name T426
Test name
Test status
Simulation time 12863426 ps
CPU time 0.72 seconds
Started May 18 04:03:35 PM PDT 24
Finished May 18 04:03:37 PM PDT 24
Peak memory 204968 kb
Host smart-a6b16eef-8504-4831-b894-9e69a6930102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892875733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.892875733
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3904715393
Short name T488
Test name
Test status
Simulation time 41951973 ps
CPU time 1.36 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:33 PM PDT 24
Peak memory 205628 kb
Host smart-4028eb7f-92a8-47aa-aa64-31b9c4494024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904715393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3904715393
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4090727002
Short name T431
Test name
Test status
Simulation time 235455577 ps
CPU time 3.91 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:34 PM PDT 24
Peak memory 214028 kb
Host smart-7a80862d-1d98-455b-ae60-bab3ae2b805c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090727002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4090727002
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2421041111
Short name T528
Test name
Test status
Simulation time 105726810 ps
CPU time 4.72 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:35 PM PDT 24
Peak memory 220012 kb
Host smart-c0260b6f-696e-4d25-8ad4-748657b7c55e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421041111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2421041111
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2107722777
Short name T514
Test name
Test status
Simulation time 177868724 ps
CPU time 2.56 seconds
Started May 18 04:03:31 PM PDT 24
Finished May 18 04:03:34 PM PDT 24
Peak memory 214988 kb
Host smart-09a7cff0-e33c-46f2-bd1f-daef2c65c8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107722777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2107722777
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.736788620
Short name T374
Test name
Test status
Simulation time 147685202 ps
CPU time 3.73 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:35 PM PDT 24
Peak memory 208916 kb
Host smart-24e3a3bb-b40d-4c5a-b3cb-1d853cc12b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736788620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.736788620
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1883158795
Short name T475
Test name
Test status
Simulation time 19823911 ps
CPU time 1.48 seconds
Started May 18 04:03:48 PM PDT 24
Finished May 18 04:03:51 PM PDT 24
Peak memory 213780 kb
Host smart-024e3740-5e5a-4b81-ae28-be17c0498fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883158795 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1883158795
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1385324410
Short name T134
Test name
Test status
Simulation time 41844425 ps
CPU time 0.9 seconds
Started May 18 04:03:48 PM PDT 24
Finished May 18 04:03:51 PM PDT 24
Peak memory 205296 kb
Host smart-d2968ffe-a69f-4447-bb66-10eaf2573b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385324410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1385324410
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3368152822
Short name T494
Test name
Test status
Simulation time 28135444 ps
CPU time 0.82 seconds
Started May 18 04:03:39 PM PDT 24
Finished May 18 04:03:41 PM PDT 24
Peak memory 205336 kb
Host smart-ab3cb238-50cf-4b63-b8ec-43744fa57794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368152822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3368152822
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2447698826
Short name T169
Test name
Test status
Simulation time 224549007 ps
CPU time 2.57 seconds
Started May 18 04:03:29 PM PDT 24
Finished May 18 04:03:32 PM PDT 24
Peak memory 214012 kb
Host smart-1e79aa9b-8119-4bf4-8942-d874b10ff3d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447698826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2447698826
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.942336245
Short name T111
Test name
Test status
Simulation time 180233712 ps
CPU time 10.24 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:41 PM PDT 24
Peak memory 214020 kb
Host smart-0bb8a093-2bb7-4c40-b3b1-b5c5e5e53d1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942336245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.942336245
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.638536265
Short name T510
Test name
Test status
Simulation time 110220963 ps
CPU time 3.33 seconds
Started May 18 04:03:30 PM PDT 24
Finished May 18 04:03:34 PM PDT 24
Peak memory 213900 kb
Host smart-b22d00b7-f079-4d74-b6a2-cbd3c245927c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638536265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.638536265
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1881617059
Short name T126
Test name
Test status
Simulation time 2744064951 ps
CPU time 10.05 seconds
Started May 18 04:02:31 PM PDT 24
Finished May 18 04:02:41 PM PDT 24
Peak memory 205600 kb
Host smart-2179e02c-c2e3-4ee2-a106-239561010eb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881617059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
881617059
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3934695185
Short name T442
Test name
Test status
Simulation time 870468026 ps
CPU time 26.17 seconds
Started May 18 04:02:28 PM PDT 24
Finished May 18 04:02:55 PM PDT 24
Peak memory 205532 kb
Host smart-51e95983-b567-49b1-9c65-8c8e8e8c5b54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934695185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
934695185
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3426083848
Short name T167
Test name
Test status
Simulation time 129251775 ps
CPU time 1.53 seconds
Started May 18 04:02:28 PM PDT 24
Finished May 18 04:02:30 PM PDT 24
Peak memory 205548 kb
Host smart-9087ab30-8363-4315-908b-19bde50e83f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426083848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
426083848
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4199963919
Short name T491
Test name
Test status
Simulation time 20540302 ps
CPU time 1.28 seconds
Started May 18 04:02:33 PM PDT 24
Finished May 18 04:02:35 PM PDT 24
Peak memory 213668 kb
Host smart-9778c0de-706f-45c4-8263-1cf676d38928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199963919 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4199963919
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2836678188
Short name T499
Test name
Test status
Simulation time 15198845 ps
CPU time 1.01 seconds
Started May 18 04:02:27 PM PDT 24
Finished May 18 04:02:29 PM PDT 24
Peak memory 205576 kb
Host smart-c5a6b705-dbc6-4007-9d55-2f4241fc51a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836678188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2836678188
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3517154395
Short name T544
Test name
Test status
Simulation time 12362866 ps
CPU time 0.69 seconds
Started May 18 04:02:27 PM PDT 24
Finished May 18 04:02:28 PM PDT 24
Peak memory 205344 kb
Host smart-da38512a-2c41-4f5a-8118-4878ccd2d615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517154395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3517154395
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2793011134
Short name T465
Test name
Test status
Simulation time 49649040 ps
CPU time 2.34 seconds
Started May 18 04:02:33 PM PDT 24
Finished May 18 04:02:36 PM PDT 24
Peak memory 205532 kb
Host smart-ca9db488-786b-40e3-9ae0-1005493dff5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793011134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2793011134
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2338163854
Short name T155
Test name
Test status
Simulation time 152940345 ps
CPU time 4.94 seconds
Started May 18 04:02:21 PM PDT 24
Finished May 18 04:02:26 PM PDT 24
Peak memory 213968 kb
Host smart-38348f5f-26d1-4a44-b25e-06e5a0197271
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338163854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2338163854
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3464900416
Short name T506
Test name
Test status
Simulation time 629135932 ps
CPU time 8.43 seconds
Started May 18 04:02:20 PM PDT 24
Finished May 18 04:02:29 PM PDT 24
Peak memory 214028 kb
Host smart-e71ea3f8-64ca-4e01-a265-6db80c80d0de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464900416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3464900416
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2817966791
Short name T453
Test name
Test status
Simulation time 39919776 ps
CPU time 2.2 seconds
Started May 18 04:02:18 PM PDT 24
Finished May 18 04:02:21 PM PDT 24
Peak memory 216188 kb
Host smart-4d9b4dd2-c29e-4811-9b3e-7c8e9d9ed507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817966791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2817966791
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3898045969
Short name T507
Test name
Test status
Simulation time 17371028 ps
CPU time 0.74 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205316 kb
Host smart-4bc259e8-4699-42d3-9628-dbe918919e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898045969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3898045969
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.443969507
Short name T525
Test name
Test status
Simulation time 40880616 ps
CPU time 0.77 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205328 kb
Host smart-3c23ac0c-3ea7-4b40-8c6f-4503cd3a879b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443969507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.443969507
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4069739172
Short name T470
Test name
Test status
Simulation time 13991675 ps
CPU time 0.78 seconds
Started May 18 04:03:47 PM PDT 24
Finished May 18 04:03:49 PM PDT 24
Peak memory 205220 kb
Host smart-59eeb958-d6df-47a9-82c9-3f04e3fba7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069739172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4069739172
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2902913135
Short name T422
Test name
Test status
Simulation time 33310113 ps
CPU time 0.69 seconds
Started May 18 04:03:36 PM PDT 24
Finished May 18 04:03:38 PM PDT 24
Peak memory 205356 kb
Host smart-0dd70ba4-7976-4383-b359-2e3f83625c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902913135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2902913135
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3292895626
Short name T478
Test name
Test status
Simulation time 7825490 ps
CPU time 0.7 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205332 kb
Host smart-b5730804-8cfd-4332-b1d9-a507a265c4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292895626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3292895626
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1560643030
Short name T513
Test name
Test status
Simulation time 9963678 ps
CPU time 0.74 seconds
Started May 18 04:03:36 PM PDT 24
Finished May 18 04:03:38 PM PDT 24
Peak memory 205320 kb
Host smart-a721dbdf-4e66-4bc3-bfb1-d2c0e9f40d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560643030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1560643030
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2084008152
Short name T519
Test name
Test status
Simulation time 11695928 ps
CPU time 0.9 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 205256 kb
Host smart-68e12818-66c0-4dbd-9f78-94430f2c2019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084008152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2084008152
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3469624062
Short name T174
Test name
Test status
Simulation time 11999052 ps
CPU time 0.85 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205360 kb
Host smart-fda6eef7-2a9a-4edd-ad08-e820d6236f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469624062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3469624062
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1978026437
Short name T436
Test name
Test status
Simulation time 13303454 ps
CPU time 0.89 seconds
Started May 18 04:03:38 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 205484 kb
Host smart-d6c6b665-69ca-45a9-b814-299856d98438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978026437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1978026437
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3431863339
Short name T175
Test name
Test status
Simulation time 48082930 ps
CPU time 0.84 seconds
Started May 18 04:03:36 PM PDT 24
Finished May 18 04:03:37 PM PDT 24
Peak memory 205268 kb
Host smart-394161b9-9a7e-4440-993b-7d2ab91bba18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431863339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3431863339
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.597285346
Short name T480
Test name
Test status
Simulation time 128520443 ps
CPU time 9.18 seconds
Started May 18 04:02:41 PM PDT 24
Finished May 18 04:02:52 PM PDT 24
Peak memory 205584 kb
Host smart-cc762d20-d542-456a-a457-1a6279c3019c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597285346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.597285346
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1671675219
Short name T425
Test name
Test status
Simulation time 2980814696 ps
CPU time 14.78 seconds
Started May 18 04:02:44 PM PDT 24
Finished May 18 04:03:00 PM PDT 24
Peak memory 205612 kb
Host smart-07a48560-7cf2-4351-b169-e5752f4c495b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671675219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
671675219
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.764397286
Short name T433
Test name
Test status
Simulation time 257309818 ps
CPU time 0.94 seconds
Started May 18 04:02:34 PM PDT 24
Finished May 18 04:02:36 PM PDT 24
Peak memory 205400 kb
Host smart-c7215920-4db3-466b-862d-dc6e77be60bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764397286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.764397286
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2772061092
Short name T439
Test name
Test status
Simulation time 89162726 ps
CPU time 1.34 seconds
Started May 18 04:02:41 PM PDT 24
Finished May 18 04:02:43 PM PDT 24
Peak memory 213896 kb
Host smart-814af139-30d2-4260-b8d6-625a11a779f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772061092 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2772061092
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3624935662
Short name T532
Test name
Test status
Simulation time 19567050 ps
CPU time 1.3 seconds
Started May 18 04:02:32 PM PDT 24
Finished May 18 04:02:34 PM PDT 24
Peak memory 205636 kb
Host smart-c2239706-17ea-44b3-9973-edca589abfb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624935662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3624935662
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.261030449
Short name T462
Test name
Test status
Simulation time 71859794 ps
CPU time 0.87 seconds
Started May 18 04:02:33 PM PDT 24
Finished May 18 04:02:35 PM PDT 24
Peak memory 205348 kb
Host smart-10e05a5a-b35e-4a3b-8fb8-8635922d5243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261030449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.261030449
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.873416425
Short name T133
Test name
Test status
Simulation time 204942815 ps
CPU time 1.6 seconds
Started May 18 04:02:41 PM PDT 24
Finished May 18 04:02:44 PM PDT 24
Peak memory 205596 kb
Host smart-2b941c19-3da6-46c7-9688-c9fae067d792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873416425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.873416425
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4197470551
Short name T109
Test name
Test status
Simulation time 1623478803 ps
CPU time 15.6 seconds
Started May 18 04:02:34 PM PDT 24
Finished May 18 04:02:51 PM PDT 24
Peak memory 213908 kb
Host smart-8f7a2ecb-683c-47f7-b4d6-51bd558e03c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197470551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4197470551
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4291420432
Short name T460
Test name
Test status
Simulation time 634455248 ps
CPU time 9.96 seconds
Started May 18 04:02:32 PM PDT 24
Finished May 18 04:02:43 PM PDT 24
Peak memory 213920 kb
Host smart-568d9942-470e-4005-8a41-943d75259009
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291420432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4291420432
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3359985868
Short name T117
Test name
Test status
Simulation time 38853874 ps
CPU time 1.68 seconds
Started May 18 04:02:31 PM PDT 24
Finished May 18 04:02:33 PM PDT 24
Peak memory 213716 kb
Host smart-aa75a336-aee8-4fbe-a286-2392450c08fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359985868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3359985868
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.693243542
Short name T150
Test name
Test status
Simulation time 1813266403 ps
CPU time 16.23 seconds
Started May 18 04:02:32 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 209256 kb
Host smart-3fdba925-6d5b-4c22-b242-17634bd16a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693243542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
693243542
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2022138901
Short name T432
Test name
Test status
Simulation time 11943442 ps
CPU time 0.69 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205332 kb
Host smart-80dfc8ff-6e6f-40e0-b221-017dd9223f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022138901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2022138901
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.775273139
Short name T443
Test name
Test status
Simulation time 12039024 ps
CPU time 0.92 seconds
Started May 18 04:03:41 PM PDT 24
Finished May 18 04:03:43 PM PDT 24
Peak memory 205324 kb
Host smart-5064a4b8-d245-4eba-bdb2-42ae6a7c924e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775273139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.775273139
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1080980181
Short name T419
Test name
Test status
Simulation time 10161293 ps
CPU time 0.8 seconds
Started May 18 04:03:48 PM PDT 24
Finished May 18 04:03:49 PM PDT 24
Peak memory 205220 kb
Host smart-e0a65e84-b0c6-4787-b836-65578aee0f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080980181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1080980181
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3281214613
Short name T424
Test name
Test status
Simulation time 84027929 ps
CPU time 0.78 seconds
Started May 18 04:03:39 PM PDT 24
Finished May 18 04:03:42 PM PDT 24
Peak memory 205332 kb
Host smart-2e856ba2-4cf9-43e0-b2c4-1382650350a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281214613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3281214613
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3584098534
Short name T427
Test name
Test status
Simulation time 12316406 ps
CPU time 0.84 seconds
Started May 18 04:03:36 PM PDT 24
Finished May 18 04:03:39 PM PDT 24
Peak memory 205336 kb
Host smart-dbe3f7c9-b72c-4ff5-8ccf-91d269a7ecd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584098534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3584098534
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3404470132
Short name T438
Test name
Test status
Simulation time 65578841 ps
CPU time 0.81 seconds
Started May 18 04:03:39 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 205352 kb
Host smart-433b1f8b-9000-4b4f-80c7-6ed25c30fa85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404470132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3404470132
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1961477776
Short name T173
Test name
Test status
Simulation time 47021167 ps
CPU time 0.77 seconds
Started May 18 04:03:38 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 205336 kb
Host smart-98c7ed53-6c7b-4d1c-9e92-b978d321c605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961477776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1961477776
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4277953294
Short name T467
Test name
Test status
Simulation time 31410580 ps
CPU time 0.76 seconds
Started May 18 04:03:41 PM PDT 24
Finished May 18 04:03:43 PM PDT 24
Peak memory 205324 kb
Host smart-0952e292-5078-4445-a412-dce8a7075a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277953294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4277953294
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3223164788
Short name T535
Test name
Test status
Simulation time 34296833 ps
CPU time 0.84 seconds
Started May 18 04:03:35 PM PDT 24
Finished May 18 04:03:37 PM PDT 24
Peak memory 205292 kb
Host smart-90ae14f0-d250-45d5-8241-fab929101d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223164788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3223164788
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1809911207
Short name T129
Test name
Test status
Simulation time 35009343 ps
CPU time 0.83 seconds
Started May 18 04:03:49 PM PDT 24
Finished May 18 04:03:50 PM PDT 24
Peak memory 205216 kb
Host smart-e60fd3c3-4b62-465b-9552-7aa32dc70e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809911207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1809911207
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.74829999
Short name T464
Test name
Test status
Simulation time 408119708 ps
CPU time 7.64 seconds
Started May 18 04:02:49 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 205504 kb
Host smart-32a88bd5-2cf5-482d-bcb7-a7299e3a3b80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74829999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.74829999
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.188742817
Short name T140
Test name
Test status
Simulation time 21230947 ps
CPU time 1.16 seconds
Started May 18 04:02:40 PM PDT 24
Finished May 18 04:02:42 PM PDT 24
Peak memory 205556 kb
Host smart-9127fdde-231f-4650-be4e-77271c5e91fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188742817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.188742817
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2028409258
Short name T539
Test name
Test status
Simulation time 68599225 ps
CPU time 1.07 seconds
Started May 18 04:02:48 PM PDT 24
Finished May 18 04:02:50 PM PDT 24
Peak memory 205452 kb
Host smart-1a0fc129-c1be-4358-bc30-9640132caceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028409258 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2028409258
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2972442930
Short name T135
Test name
Test status
Simulation time 53719709 ps
CPU time 1.16 seconds
Started May 18 04:02:47 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 205560 kb
Host smart-9b42749f-30fb-4dce-8b25-361238e8ca0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972442930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2972442930
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2934850749
Short name T518
Test name
Test status
Simulation time 10497253 ps
CPU time 0.72 seconds
Started May 18 04:02:41 PM PDT 24
Finished May 18 04:02:43 PM PDT 24
Peak memory 205264 kb
Host smart-8561b3ce-0410-4570-88a5-b1b9bee3308e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934850749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2934850749
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2809674252
Short name T176
Test name
Test status
Simulation time 221784566 ps
CPU time 3.59 seconds
Started May 18 04:02:39 PM PDT 24
Finished May 18 04:02:43 PM PDT 24
Peak memory 214024 kb
Host smart-aa8ca5ee-6f1f-488f-a332-a1fc71aa867e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809674252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2809674252
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.638755836
Short name T451
Test name
Test status
Simulation time 792079380 ps
CPU time 5.98 seconds
Started May 18 04:02:41 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 214232 kb
Host smart-86c5a0e5-704e-4119-9a7c-636f8112d1b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638755836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.638755836
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1826591853
Short name T143
Test name
Test status
Simulation time 127325952 ps
CPU time 4.5 seconds
Started May 18 04:02:44 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 213724 kb
Host smart-89408e4f-d189-4b8b-9e1e-9ec2eafff223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826591853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1826591853
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.206780628
Short name T449
Test name
Test status
Simulation time 16327865 ps
CPU time 0.83 seconds
Started May 18 04:03:35 PM PDT 24
Finished May 18 04:03:37 PM PDT 24
Peak memory 205348 kb
Host smart-62b8ed06-8cd3-408d-bd42-062ea710a51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206780628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.206780628
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1108681387
Short name T534
Test name
Test status
Simulation time 41629579 ps
CPU time 0.72 seconds
Started May 18 04:03:48 PM PDT 24
Finished May 18 04:03:49 PM PDT 24
Peak memory 205144 kb
Host smart-e470db32-b696-4ebe-8ed8-19801c5d3521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108681387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1108681387
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.678463895
Short name T483
Test name
Test status
Simulation time 9074021 ps
CPU time 0.83 seconds
Started May 18 04:03:40 PM PDT 24
Finished May 18 04:03:43 PM PDT 24
Peak memory 205324 kb
Host smart-df47071a-748b-4ea9-9fd2-701511173d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678463895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.678463895
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.53728631
Short name T531
Test name
Test status
Simulation time 32945144 ps
CPU time 0.87 seconds
Started May 18 04:03:48 PM PDT 24
Finished May 18 04:03:50 PM PDT 24
Peak memory 205220 kb
Host smart-eca8fca5-7304-4f0a-9643-2ee103ba9fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53728631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.53728631
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4248310466
Short name T540
Test name
Test status
Simulation time 39689187 ps
CPU time 0.84 seconds
Started May 18 04:03:37 PM PDT 24
Finished May 18 04:03:40 PM PDT 24
Peak memory 205344 kb
Host smart-a7151736-e00e-4f28-b0ef-64e09b83e6b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248310466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4248310466
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1314287128
Short name T456
Test name
Test status
Simulation time 44279615 ps
CPU time 0.84 seconds
Started May 18 04:03:46 PM PDT 24
Finished May 18 04:03:47 PM PDT 24
Peak memory 205240 kb
Host smart-9bccc48f-5dec-4d5e-b2b8-c0d22d4f997d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314287128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1314287128
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3673371790
Short name T511
Test name
Test status
Simulation time 15465788 ps
CPU time 0.89 seconds
Started May 18 04:03:47 PM PDT 24
Finished May 18 04:03:48 PM PDT 24
Peak memory 205492 kb
Host smart-a80a9834-6960-43ad-afe0-044cc344289e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673371790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3673371790
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2860323715
Short name T459
Test name
Test status
Simulation time 11139908 ps
CPU time 0.8 seconds
Started May 18 04:03:45 PM PDT 24
Finished May 18 04:03:47 PM PDT 24
Peak memory 205340 kb
Host smart-9c955018-8348-4a9e-a61d-1da2c8cd2b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860323715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2860323715
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.527524611
Short name T481
Test name
Test status
Simulation time 47163749 ps
CPU time 0.74 seconds
Started May 18 04:03:41 PM PDT 24
Finished May 18 04:03:43 PM PDT 24
Peak memory 205332 kb
Host smart-298c706c-d0a5-4f34-95eb-81fdf445bdfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527524611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.527524611
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.6711328
Short name T501
Test name
Test status
Simulation time 7822420 ps
CPU time 0.71 seconds
Started May 18 04:03:43 PM PDT 24
Finished May 18 04:03:45 PM PDT 24
Peak memory 205220 kb
Host smart-ef74d249-2b4e-411d-b031-6377c52ccacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6711328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.6711328
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2086298126
Short name T120
Test name
Test status
Simulation time 26596241 ps
CPU time 1.53 seconds
Started May 18 04:02:47 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 213848 kb
Host smart-cd55a7cc-a714-48b9-96aa-c67cb22cd38e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086298126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2086298126
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2386528939
Short name T479
Test name
Test status
Simulation time 42724498 ps
CPU time 1.39 seconds
Started May 18 04:02:48 PM PDT 24
Finished May 18 04:02:50 PM PDT 24
Peak memory 205592 kb
Host smart-20bbbd92-8a83-42d8-8e05-c438081bda8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386528939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2386528939
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3841510665
Short name T529
Test name
Test status
Simulation time 10242135 ps
CPU time 0.91 seconds
Started May 18 04:02:47 PM PDT 24
Finished May 18 04:02:49 PM PDT 24
Peak memory 205320 kb
Host smart-0ff0ec25-78bd-456e-a88a-2bf5530d905b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841510665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3841510665
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.931792848
Short name T476
Test name
Test status
Simulation time 2497409620 ps
CPU time 7.2 seconds
Started May 18 04:02:47 PM PDT 24
Finished May 18 04:02:56 PM PDT 24
Peak memory 213796 kb
Host smart-e1dc3830-105a-4c92-bbc4-69e29be95f73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931792848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.931792848
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4069307959
Short name T151
Test name
Test status
Simulation time 227629762 ps
CPU time 3.59 seconds
Started May 18 04:02:48 PM PDT 24
Finished May 18 04:02:53 PM PDT 24
Peak memory 213704 kb
Host smart-8348b9b7-7b83-4f71-b3be-46ff5d9fd4af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069307959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4069307959
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3966198457
Short name T429
Test name
Test status
Simulation time 21376907 ps
CPU time 1.35 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 213820 kb
Host smart-de353cc3-bc16-4063-9019-6cf4320ac032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966198457 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3966198457
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1997539137
Short name T521
Test name
Test status
Simulation time 59008558 ps
CPU time 1.74 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 205452 kb
Host smart-9cb26561-ff88-4811-86ee-548e500cc8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997539137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1997539137
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1318882757
Short name T421
Test name
Test status
Simulation time 32016868 ps
CPU time 0.82 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:56 PM PDT 24
Peak memory 205548 kb
Host smart-44512ceb-2ca3-4f8f-a07e-1ee02891ee36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318882757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1318882757
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1014769717
Short name T437
Test name
Test status
Simulation time 348768049 ps
CPU time 2.55 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 205564 kb
Host smart-c312e06c-4eb8-43a7-905d-88ec48e2749d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014769717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1014769717
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2788892697
Short name T487
Test name
Test status
Simulation time 1349315902 ps
CPU time 24.37 seconds
Started May 18 04:02:51 PM PDT 24
Finished May 18 04:03:16 PM PDT 24
Peak memory 216044 kb
Host smart-40ac9014-c8f2-436b-86d6-6408dbc9b43f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788892697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2788892697
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3230870408
Short name T526
Test name
Test status
Simulation time 3160809003 ps
CPU time 7.38 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:03:02 PM PDT 24
Peak memory 214076 kb
Host smart-760a7ee8-6e05-4a25-bc33-420ba0d1b4f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230870408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3230870408
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1003010174
Short name T441
Test name
Test status
Simulation time 77766648 ps
CPU time 1.5 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 213884 kb
Host smart-7f6a702a-59a2-4778-9804-28038ec99ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003010174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1003010174
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.818286490
Short name T119
Test name
Test status
Simulation time 23554886 ps
CPU time 1.56 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 213872 kb
Host smart-f73a67e3-3679-4b58-8a5d-5ee3b1e2eb5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818286490 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.818286490
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1546309887
Short name T509
Test name
Test status
Simulation time 45997050 ps
CPU time 0.97 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:55 PM PDT 24
Peak memory 205364 kb
Host smart-f37d08a2-37fc-4b9f-b5de-b5592dd4697a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546309887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1546309887
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2531250518
Short name T463
Test name
Test status
Simulation time 16250467 ps
CPU time 0.72 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:56 PM PDT 24
Peak memory 205336 kb
Host smart-0f8262b5-a961-4d0a-8086-2abbf9145b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531250518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2531250518
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2245342749
Short name T455
Test name
Test status
Simulation time 249965720 ps
CPU time 2.78 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:58 PM PDT 24
Peak memory 214000 kb
Host smart-452608cc-ee00-4863-b91f-9f7fc9d0ee00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245342749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2245342749
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.986525373
Short name T484
Test name
Test status
Simulation time 62154521 ps
CPU time 2.57 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 216872 kb
Host smart-22284183-9add-40ce-86e2-c461ab99468d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986525373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.986525373
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4089449114
Short name T472
Test name
Test status
Simulation time 18221081 ps
CPU time 1.31 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:05 PM PDT 24
Peak memory 213756 kb
Host smart-ab3746ec-ef6e-4cc0-a650-2e83b7f5361b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089449114 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4089449114
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1404272782
Short name T496
Test name
Test status
Simulation time 17096890 ps
CPU time 1.25 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:02:55 PM PDT 24
Peak memory 205568 kb
Host smart-d50a9b09-70f8-402e-a645-8a18b18e3663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404272782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1404272782
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1257791525
Short name T458
Test name
Test status
Simulation time 18232142 ps
CPU time 0.71 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:56 PM PDT 24
Peak memory 205328 kb
Host smart-7ffbaeee-5b9f-4436-ba37-3c04fa7a0eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257791525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1257791525
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4114691776
Short name T457
Test name
Test status
Simulation time 152198434 ps
CPU time 1.95 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 205564 kb
Host smart-c8bdf572-e2a6-4d4c-9e46-a39d4d54f0d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114691776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4114691776
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1451743523
Short name T523
Test name
Test status
Simulation time 970933397 ps
CPU time 17.3 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:03:11 PM PDT 24
Peak memory 215248 kb
Host smart-736fc167-d998-4c32-81e0-cf9144f0a8b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451743523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1451743523
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2236897011
Short name T502
Test name
Test status
Simulation time 131113962 ps
CPU time 1.58 seconds
Started May 18 04:02:54 PM PDT 24
Finished May 18 04:02:57 PM PDT 24
Peak memory 213864 kb
Host smart-8c7e5ebd-1f2b-48ac-b151-c7284d93eee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236897011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2236897011
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1713401149
Short name T153
Test name
Test status
Simulation time 210410832 ps
CPU time 5.03 seconds
Started May 18 04:02:53 PM PDT 24
Finished May 18 04:03:00 PM PDT 24
Peak memory 209124 kb
Host smart-2e3beed1-21b0-4569-89b0-e6586ef46442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713401149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1713401149
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.255021679
Short name T448
Test name
Test status
Simulation time 64282387 ps
CPU time 1.18 seconds
Started May 18 04:03:00 PM PDT 24
Finished May 18 04:03:02 PM PDT 24
Peak memory 205540 kb
Host smart-583ce07d-0ea8-4a94-9960-cc94cc2533ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255021679 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.255021679
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1552198374
Short name T482
Test name
Test status
Simulation time 18454595 ps
CPU time 0.81 seconds
Started May 18 04:03:03 PM PDT 24
Finished May 18 04:03:04 PM PDT 24
Peak memory 205312 kb
Host smart-7f19fb94-652c-41ca-9a1c-d7f52c0083cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552198374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1552198374
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3926372110
Short name T466
Test name
Test status
Simulation time 21258706 ps
CPU time 1.72 seconds
Started May 18 04:03:00 PM PDT 24
Finished May 18 04:03:02 PM PDT 24
Peak memory 213804 kb
Host smart-4071619f-dbe0-4e7e-a364-4c86964e7026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926372110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3926372110
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4182357919
Short name T428
Test name
Test status
Simulation time 223707349 ps
CPU time 4.04 seconds
Started May 18 04:03:02 PM PDT 24
Finished May 18 04:03:07 PM PDT 24
Peak memory 222112 kb
Host smart-45937e4f-3547-4e5d-b99b-d51d8a8455e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182357919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4182357919
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3922876239
Short name T474
Test name
Test status
Simulation time 1153160499 ps
CPU time 4.46 seconds
Started May 18 04:03:02 PM PDT 24
Finished May 18 04:03:07 PM PDT 24
Peak memory 216140 kb
Host smart-470d036b-c0d3-42b8-bb49-7aa475293c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922876239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3922876239
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3141437836
Short name T574
Test name
Test status
Simulation time 19680701 ps
CPU time 0.98 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:52 PM PDT 24
Peak memory 205632 kb
Host smart-5c749f90-566e-4287-9047-a5e6cbc68b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141437836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3141437836
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3014878217
Short name T325
Test name
Test status
Simulation time 43312998 ps
CPU time 2.9 seconds
Started May 18 04:09:53 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 214020 kb
Host smart-2c971e45-80d4-46d1-8ce9-291175563163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014878217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3014878217
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3888672646
Short name T35
Test name
Test status
Simulation time 269832664 ps
CPU time 2.15 seconds
Started May 18 04:09:52 PM PDT 24
Finished May 18 04:09:56 PM PDT 24
Peak memory 208540 kb
Host smart-6b257f39-07ba-44cd-b59a-ba228de56616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888672646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3888672646
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3486141391
Short name T368
Test name
Test status
Simulation time 326378200 ps
CPU time 7.22 seconds
Started May 18 04:09:44 PM PDT 24
Finished May 18 04:09:52 PM PDT 24
Peak memory 214024 kb
Host smart-9e22b3a0-27b3-45ae-9ff4-1bb6a3f6e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486141391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3486141391
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1909795128
Short name T1050
Test name
Test status
Simulation time 118943141 ps
CPU time 4.99 seconds
Started May 18 04:09:51 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 214012 kb
Host smart-246e2a45-a32d-4e55-acb6-c957b99fd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909795128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1909795128
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.892944808
Short name T1040
Test name
Test status
Simulation time 336843203 ps
CPU time 4.21 seconds
Started May 18 04:09:45 PM PDT 24
Finished May 18 04:09:50 PM PDT 24
Peak memory 207184 kb
Host smart-f8400deb-fca9-47e7-a648-661f6dafddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892944808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.892944808
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2504684320
Short name T601
Test name
Test status
Simulation time 80571780 ps
CPU time 3.87 seconds
Started May 18 04:09:45 PM PDT 24
Finished May 18 04:09:50 PM PDT 24
Peak memory 209028 kb
Host smart-be0c16ef-3b2f-4f0b-9b45-d1625259f6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504684320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2504684320
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1608885553
Short name T297
Test name
Test status
Simulation time 23958933 ps
CPU time 1.91 seconds
Started May 18 04:09:43 PM PDT 24
Finished May 18 04:09:46 PM PDT 24
Peak memory 206568 kb
Host smart-713034d0-89ea-4662-b60d-2ea3f4f1c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608885553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1608885553
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1886167048
Short name T657
Test name
Test status
Simulation time 493885346 ps
CPU time 8.18 seconds
Started May 18 04:09:43 PM PDT 24
Finished May 18 04:09:52 PM PDT 24
Peak memory 207716 kb
Host smart-1b564223-3923-4df3-ab01-20f1b5b5fd03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886167048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1886167048
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2536698066
Short name T827
Test name
Test status
Simulation time 236234888 ps
CPU time 3.43 seconds
Started May 18 04:09:46 PM PDT 24
Finished May 18 04:09:51 PM PDT 24
Peak memory 208580 kb
Host smart-641202c5-dd74-43c4-b3b3-0bcdac796c3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536698066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2536698066
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1015667659
Short name T641
Test name
Test status
Simulation time 294088562 ps
CPU time 8.83 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:10:00 PM PDT 24
Peak memory 207780 kb
Host smart-311ceb4d-87c8-42cb-a266-b1a96e65fec9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015667659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1015667659
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1031523190
Short name T761
Test name
Test status
Simulation time 136329048 ps
CPU time 2.64 seconds
Started May 18 04:09:44 PM PDT 24
Finished May 18 04:09:48 PM PDT 24
Peak memory 218044 kb
Host smart-255c8118-5497-44c7-8dcc-37aa1a82818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031523190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1031523190
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1293418954
Short name T555
Test name
Test status
Simulation time 431113474 ps
CPU time 3.01 seconds
Started May 18 04:09:46 PM PDT 24
Finished May 18 04:09:49 PM PDT 24
Peak memory 206340 kb
Host smart-73652ea2-861c-4a58-a4ed-2e6bb23b2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293418954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1293418954
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.4174316979
Short name T962
Test name
Test status
Simulation time 1288251930 ps
CPU time 3.92 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:53 PM PDT 24
Peak memory 222276 kb
Host smart-c5634029-a33f-46a3-82bb-0c61a09a6a86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174316979 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.4174316979
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3501448318
Short name T681
Test name
Test status
Simulation time 400868858 ps
CPU time 9.62 seconds
Started May 18 04:09:46 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 207520 kb
Host smart-cd0f02ba-b8b8-4ebf-a6cb-70d01ed6516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501448318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3501448318
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1717982150
Short name T607
Test name
Test status
Simulation time 425399091 ps
CPU time 2.46 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:53 PM PDT 24
Peak memory 210020 kb
Host smart-0e4c0d7d-3cce-447f-87b4-5b7ed03dfeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717982150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1717982150
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1075424100
Short name T706
Test name
Test status
Simulation time 11428837 ps
CPU time 0.82 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:00 PM PDT 24
Peak memory 205540 kb
Host smart-c6e860f0-baf7-442c-993f-2fc0f729391b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075424100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1075424100
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2202427996
Short name T411
Test name
Test status
Simulation time 68632992 ps
CPU time 2.85 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:54 PM PDT 24
Peak memory 213960 kb
Host smart-3748b2a4-b28d-4d47-8c39-46f87fb977d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202427996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2202427996
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2775448766
Short name T720
Test name
Test status
Simulation time 633866260 ps
CPU time 2.46 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:54 PM PDT 24
Peak memory 208704 kb
Host smart-38e5848b-b23a-40b5-952c-3f1244a756b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775448766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2775448766
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2012817946
Short name T60
Test name
Test status
Simulation time 497516222 ps
CPU time 1.7 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:53 PM PDT 24
Peak memory 207348 kb
Host smart-eae7c639-e27e-4a0c-9432-df6166a8c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012817946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2012817946
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3587516877
Short name T63
Test name
Test status
Simulation time 1533853206 ps
CPU time 17.06 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:10:07 PM PDT 24
Peak memory 213972 kb
Host smart-02bd2be4-15a7-4155-b0d0-7310f29068f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587516877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3587516877
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.864865840
Short name T328
Test name
Test status
Simulation time 1969047282 ps
CPU time 5.57 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:55 PM PDT 24
Peak memory 211356 kb
Host smart-b83799f1-3c37-4384-8fd8-2705b53898bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864865840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.864865840
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3411016974
Short name T926
Test name
Test status
Simulation time 211309613 ps
CPU time 3.28 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:53 PM PDT 24
Peak memory 214628 kb
Host smart-26bce5fc-e250-40e1-89f6-5fca78357b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411016974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3411016974
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.177793363
Short name T842
Test name
Test status
Simulation time 3715922878 ps
CPU time 36.49 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:10:28 PM PDT 24
Peak memory 209276 kb
Host smart-35c3a300-807c-485f-ab1b-c98242077462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177793363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.177793363
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3109322149
Short name T13
Test name
Test status
Simulation time 2250041120 ps
CPU time 14.17 seconds
Started May 18 04:09:52 PM PDT 24
Finished May 18 04:10:08 PM PDT 24
Peak memory 236400 kb
Host smart-93c26456-5f43-4b8f-8589-d108917a7262
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109322149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3109322149
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3493744718
Short name T341
Test name
Test status
Simulation time 55151568 ps
CPU time 2.82 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:54 PM PDT 24
Peak memory 206524 kb
Host smart-e4c11457-76fd-4711-87d9-911570795fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493744718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3493744718
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4158123243
Short name T1038
Test name
Test status
Simulation time 114573962 ps
CPU time 3.03 seconds
Started May 18 04:09:52 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 206808 kb
Host smart-9b550c31-d77d-4fde-bab8-f172654234b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158123243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4158123243
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2752739254
Short name T899
Test name
Test status
Simulation time 221561510 ps
CPU time 7.04 seconds
Started May 18 04:09:51 PM PDT 24
Finished May 18 04:10:00 PM PDT 24
Peak memory 207872 kb
Host smart-e287a6dd-4fef-48cb-894b-2a245b235fe0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752739254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2752739254
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2590870747
Short name T648
Test name
Test status
Simulation time 756297008 ps
CPU time 6.41 seconds
Started May 18 04:09:52 PM PDT 24
Finished May 18 04:10:00 PM PDT 24
Peak memory 208496 kb
Host smart-175b2deb-5d74-421a-b70d-4d55fd265468
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590870747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2590870747
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1133207268
Short name T849
Test name
Test status
Simulation time 1046895386 ps
CPU time 3.49 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:55 PM PDT 24
Peak memory 215552 kb
Host smart-d55abc85-08b2-407c-8f0e-2ef87328c17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133207268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1133207268
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2125736393
Short name T693
Test name
Test status
Simulation time 888110160 ps
CPU time 6.17 seconds
Started May 18 04:09:49 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 207912 kb
Host smart-b21c00f4-1dd1-42c7-9f70-9ca5ab85a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125736393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2125736393
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2691074169
Short name T182
Test name
Test status
Simulation time 4909854465 ps
CPU time 28.05 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:10:19 PM PDT 24
Peak memory 214888 kb
Host smart-8792879e-f6da-4ddd-98ea-51274cfd98b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691074169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2691074169
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1535274493
Short name T225
Test name
Test status
Simulation time 210266807 ps
CPU time 5.81 seconds
Started May 18 04:09:50 PM PDT 24
Finished May 18 04:09:57 PM PDT 24
Peak memory 207420 kb
Host smart-4faef12a-6ffd-49fd-9f15-9af473ecb211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535274493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1535274493
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3438834062
Short name T397
Test name
Test status
Simulation time 47548989 ps
CPU time 3.59 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:38 PM PDT 24
Peak memory 213984 kb
Host smart-c88db29c-8a37-454a-b090-dcf0c136e4ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438834062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3438834062
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.945935626
Short name T848
Test name
Test status
Simulation time 54469350 ps
CPU time 2.58 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 209628 kb
Host smart-0ea5c3ec-2f4e-4d3a-861d-bd8f09c1f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945935626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.945935626
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2043316067
Short name T70
Test name
Test status
Simulation time 227129649 ps
CPU time 3.96 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:40 PM PDT 24
Peak memory 209924 kb
Host smart-39232f58-2ccc-41d1-9cc6-cb47f95731b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043316067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2043316067
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2926072160
Short name T88
Test name
Test status
Simulation time 68819163 ps
CPU time 3.37 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:40 PM PDT 24
Peak memory 218176 kb
Host smart-42182cc7-e05d-4410-8690-f96bd6c6a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926072160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2926072160
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.348800481
Short name T858
Test name
Test status
Simulation time 391329063 ps
CPU time 5.11 seconds
Started May 18 04:10:32 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 213900 kb
Host smart-cd25514f-0d3a-40b1-aaf5-a472359d3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348800481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.348800481
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2134448522
Short name T216
Test name
Test status
Simulation time 861225588 ps
CPU time 5.23 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 209028 kb
Host smart-c5c2cf6c-ccd2-4113-8b33-0beebf4fb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134448522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2134448522
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4255664668
Short name T1017
Test name
Test status
Simulation time 152699359 ps
CPU time 3.65 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 207252 kb
Host smart-87b294ba-7759-49da-a929-265643f2cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255664668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4255664668
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2323193668
Short name T741
Test name
Test status
Simulation time 824373172 ps
CPU time 2.84 seconds
Started May 18 04:10:37 PM PDT 24
Finished May 18 04:10:41 PM PDT 24
Peak memory 206460 kb
Host smart-8b352823-9578-46ec-bf8d-ad503dd4e554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323193668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2323193668
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1772508108
Short name T661
Test name
Test status
Simulation time 170556898 ps
CPU time 5.31 seconds
Started May 18 04:10:36 PM PDT 24
Finished May 18 04:10:43 PM PDT 24
Peak memory 206396 kb
Host smart-a4112320-e635-4df1-9a6f-2bde26fe1304
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772508108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1772508108
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1241344713
Short name T862
Test name
Test status
Simulation time 64421809 ps
CPU time 3.37 seconds
Started May 18 04:10:32 PM PDT 24
Finished May 18 04:10:37 PM PDT 24
Peak memory 208056 kb
Host smart-64756989-7e94-400d-b89a-eda16239f801
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241344713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1241344713
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3665034340
Short name T671
Test name
Test status
Simulation time 91493362 ps
CPU time 3.86 seconds
Started May 18 04:10:35 PM PDT 24
Finished May 18 04:10:41 PM PDT 24
Peak memory 206784 kb
Host smart-9f6d2711-c26d-49da-b909-05f6fa90a75d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665034340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3665034340
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3238820944
Short name T751
Test name
Test status
Simulation time 184870487 ps
CPU time 2.94 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:47 PM PDT 24
Peak memory 206972 kb
Host smart-e43833c2-6be8-4048-b595-682487abaff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238820944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3238820944
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1121838049
Short name T573
Test name
Test status
Simulation time 62174616 ps
CPU time 2.81 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 206352 kb
Host smart-c58bdab9-9346-4a68-84dd-55c6617bd003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121838049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1121838049
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3437144458
Short name T259
Test name
Test status
Simulation time 241630685 ps
CPU time 3.72 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:47 PM PDT 24
Peak memory 214996 kb
Host smart-487124e4-1709-4bc6-bcdb-050184edc323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437144458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3437144458
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.478909000
Short name T967
Test name
Test status
Simulation time 215867558 ps
CPU time 7.35 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:51 PM PDT 24
Peak memory 220624 kb
Host smart-3e1c92ed-42c6-4c69-ad56-8878c47def40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478909000 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.478909000
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.274832400
Short name T1033
Test name
Test status
Simulation time 415942657 ps
CPU time 4.94 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:41 PM PDT 24
Peak memory 209752 kb
Host smart-18d2f179-f85b-46c9-beb9-f1af28293afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274832400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.274832400
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1990648327
Short name T395
Test name
Test status
Simulation time 385452421 ps
CPU time 3.01 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 210164 kb
Host smart-ae1b33d5-e67d-4286-b104-45da683c425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990648327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1990648327
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.782410031
Short name T738
Test name
Test status
Simulation time 15687062 ps
CPU time 0.92 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:10:57 PM PDT 24
Peak memory 205748 kb
Host smart-42b61767-5a68-4e91-b7bf-864864972ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782410031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.782410031
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1420119857
Short name T687
Test name
Test status
Simulation time 184029363 ps
CPU time 3.72 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:47 PM PDT 24
Peak memory 218192 kb
Host smart-66fe0d11-9b12-4a7f-9d00-06eb05292323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420119857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1420119857
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.645028333
Short name T52
Test name
Test status
Simulation time 223827772 ps
CPU time 3.34 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 217860 kb
Host smart-cc3041ba-0141-47d0-8662-60c3326bf1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645028333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.645028333
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3313188076
Short name T603
Test name
Test status
Simulation time 3080339662 ps
CPU time 20.25 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:11:03 PM PDT 24
Peak memory 208996 kb
Host smart-068862df-2cdf-4bf6-8b8d-6cc07b4f2a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313188076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3313188076
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.139450798
Short name T810
Test name
Test status
Simulation time 591135659 ps
CPU time 4.76 seconds
Started May 18 04:10:43 PM PDT 24
Finished May 18 04:10:49 PM PDT 24
Peak memory 208540 kb
Host smart-fe6cb489-24f6-48c0-9677-ca2efc91cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139450798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.139450798
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.294409885
Short name T835
Test name
Test status
Simulation time 1107087738 ps
CPU time 9.05 seconds
Started May 18 04:10:39 PM PDT 24
Finished May 18 04:10:49 PM PDT 24
Peak memory 207856 kb
Host smart-d2fcaef0-d9fc-4274-b89d-a50d1d03f72d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294409885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.294409885
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1595889754
Short name T595
Test name
Test status
Simulation time 20911741 ps
CPU time 1.86 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 206440 kb
Host smart-3b548462-38b9-4bf5-b100-5d7903849cd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595889754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1595889754
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.497811252
Short name T777
Test name
Test status
Simulation time 58062105 ps
CPU time 3.08 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:10:47 PM PDT 24
Peak memory 208124 kb
Host smart-749d71bb-d5bc-48c3-a11d-3b0182a88802
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497811252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.497811252
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1271229347
Short name T582
Test name
Test status
Simulation time 81749767 ps
CPU time 3.65 seconds
Started May 18 04:10:39 PM PDT 24
Finished May 18 04:10:44 PM PDT 24
Peak memory 207088 kb
Host smart-24608389-1f55-4d7b-8b99-34a3b9d0fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271229347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1271229347
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1286165157
Short name T568
Test name
Test status
Simulation time 1473391452 ps
CPU time 22.21 seconds
Started May 18 04:10:42 PM PDT 24
Finished May 18 04:11:06 PM PDT 24
Peak memory 208364 kb
Host smart-d5cda935-0117-4096-973b-0843844a2f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286165157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1286165157
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3086230430
Short name T953
Test name
Test status
Simulation time 480797974 ps
CPU time 8.64 seconds
Started May 18 04:10:42 PM PDT 24
Finished May 18 04:10:53 PM PDT 24
Peak memory 219500 kb
Host smart-81fdfb2b-9902-4f25-8cb5-263a9fc9c194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086230430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3086230430
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1438960005
Short name T610
Test name
Test status
Simulation time 2541456700 ps
CPU time 82.22 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 208612 kb
Host smart-a9fb2899-b3fe-42d1-b05e-e0a1f0890940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438960005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1438960005
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3452646964
Short name T622
Test name
Test status
Simulation time 4513088882 ps
CPU time 32.87 seconds
Started May 18 04:10:41 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 210828 kb
Host smart-99f80933-6168-467f-9795-a38a09e59568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452646964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3452646964
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1386894332
Short name T624
Test name
Test status
Simulation time 41655869 ps
CPU time 0.89 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:10:57 PM PDT 24
Peak memory 205508 kb
Host smart-0431b425-3728-4daf-ab04-cfb9fac202d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386894332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1386894332
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.122315777
Short name T798
Test name
Test status
Simulation time 151825083 ps
CPU time 1.59 seconds
Started May 18 04:10:47 PM PDT 24
Finished May 18 04:10:50 PM PDT 24
Peak memory 207576 kb
Host smart-0c3fc980-a8d1-40cc-bf41-52a1b70faeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122315777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.122315777
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.166997275
Short name T960
Test name
Test status
Simulation time 63002362 ps
CPU time 2.52 seconds
Started May 18 04:10:46 PM PDT 24
Finished May 18 04:10:50 PM PDT 24
Peak memory 207688 kb
Host smart-def463e4-ba14-4ff6-8eaf-b0e2800bc69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166997275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.166997275
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1964575283
Short name T47
Test name
Test status
Simulation time 92941852 ps
CPU time 4.34 seconds
Started May 18 04:10:49 PM PDT 24
Finished May 18 04:10:54 PM PDT 24
Peak memory 219548 kb
Host smart-c53a6de1-605d-4735-974e-2e1a3cf73fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964575283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1964575283
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1177704284
Short name T763
Test name
Test status
Simulation time 9933352322 ps
CPU time 62.94 seconds
Started May 18 04:10:48 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 209212 kb
Host smart-a019a14e-6e9a-480c-b043-5023caa98f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177704284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1177704284
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.4287836958
Short name T961
Test name
Test status
Simulation time 24197835 ps
CPU time 1.82 seconds
Started May 18 04:10:46 PM PDT 24
Finished May 18 04:10:49 PM PDT 24
Peak memory 208336 kb
Host smart-47ed2b8c-675c-4b6a-9d97-3c5b03522b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287836958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.4287836958
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2994438103
Short name T909
Test name
Test status
Simulation time 164851892 ps
CPU time 2.44 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:10:59 PM PDT 24
Peak memory 207688 kb
Host smart-0cf07e30-e7cd-4076-b91c-56a020923138
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994438103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2994438103
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4175881616
Short name T925
Test name
Test status
Simulation time 35930540 ps
CPU time 2.45 seconds
Started May 18 04:10:47 PM PDT 24
Finished May 18 04:10:51 PM PDT 24
Peak memory 208096 kb
Host smart-9e3c7342-b8dc-4fcd-a92f-6c45da305439
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175881616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4175881616
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4230071939
Short name T891
Test name
Test status
Simulation time 469576076 ps
CPU time 3.63 seconds
Started May 18 04:10:45 PM PDT 24
Finished May 18 04:10:50 PM PDT 24
Peak memory 206528 kb
Host smart-a50cd2b4-0393-4933-ac1f-aa669c3216bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230071939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4230071939
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3640768678
Short name T625
Test name
Test status
Simulation time 727300126 ps
CPU time 15.67 seconds
Started May 18 04:10:47 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 209452 kb
Host smart-0d1a0c57-1f73-4a46-bec1-ce7b92b7ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640768678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3640768678
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.899461141
Short name T600
Test name
Test status
Simulation time 62280639 ps
CPU time 2.83 seconds
Started May 18 04:10:53 PM PDT 24
Finished May 18 04:10:58 PM PDT 24
Peak memory 208052 kb
Host smart-b67e07cc-6d63-47a8-bd0c-b320e54d462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899461141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.899461141
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1851920787
Short name T385
Test name
Test status
Simulation time 492061445 ps
CPU time 6.78 seconds
Started May 18 04:10:53 PM PDT 24
Finished May 18 04:11:02 PM PDT 24
Peak memory 221172 kb
Host smart-68112b01-f524-460f-9c8d-ffe28685a6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851920787 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1851920787
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.963355828
Short name T388
Test name
Test status
Simulation time 347040369 ps
CPU time 5.42 seconds
Started May 18 04:10:48 PM PDT 24
Finished May 18 04:10:54 PM PDT 24
Peak memory 214040 kb
Host smart-bee78813-7907-4440-9369-efc508007d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963355828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.963355828
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4111430910
Short name T940
Test name
Test status
Simulation time 86726950 ps
CPU time 1.52 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:10:57 PM PDT 24
Peak memory 209376 kb
Host smart-3594edbd-9df9-4c83-bab2-4faeb2087e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111430910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4111430910
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1137790455
Short name T753
Test name
Test status
Simulation time 147010213 ps
CPU time 0.76 seconds
Started May 18 04:10:57 PM PDT 24
Finished May 18 04:11:00 PM PDT 24
Peak memory 205576 kb
Host smart-89b19260-1b0f-40fb-b8a7-894ea2fe0368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137790455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1137790455
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2290456197
Short name T104
Test name
Test status
Simulation time 122177672 ps
CPU time 3.89 seconds
Started May 18 04:10:57 PM PDT 24
Finished May 18 04:11:03 PM PDT 24
Peak memory 222484 kb
Host smart-a1724816-9a8c-4393-9e85-96158d5f504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290456197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2290456197
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2529141685
Short name T64
Test name
Test status
Simulation time 31387629 ps
CPU time 1.95 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:10:59 PM PDT 24
Peak memory 207860 kb
Host smart-9a25d7b3-82c7-4635-8b43-aafd9f607a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529141685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2529141685
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1050224418
Short name T752
Test name
Test status
Simulation time 73549188 ps
CPU time 2.64 seconds
Started May 18 04:10:53 PM PDT 24
Finished May 18 04:10:56 PM PDT 24
Peak memory 219604 kb
Host smart-a95fc931-feaf-41a1-8516-ef9fa210c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050224418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1050224418
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1214905910
Short name T1024
Test name
Test status
Simulation time 763647784 ps
CPU time 7.27 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:05 PM PDT 24
Peak memory 222180 kb
Host smart-941740f5-2a04-43c2-a82d-653e13b9863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214905910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1214905910
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1523773553
Short name T218
Test name
Test status
Simulation time 1112896081 ps
CPU time 9 seconds
Started May 18 04:10:58 PM PDT 24
Finished May 18 04:11:08 PM PDT 24
Peak memory 222160 kb
Host smart-acd5496c-4ae1-4bd2-afe8-d9b0f6406817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523773553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1523773553
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3776405047
Short name T767
Test name
Test status
Simulation time 400735813 ps
CPU time 4.51 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:00 PM PDT 24
Peak memory 206620 kb
Host smart-48df6524-caae-423d-8fd3-18a32c28ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776405047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3776405047
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.688309142
Short name T270
Test name
Test status
Simulation time 167149771 ps
CPU time 5.29 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:03 PM PDT 24
Peak memory 208620 kb
Host smart-d617ffba-262c-427a-a15b-9bfdd9ffe19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688309142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.688309142
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1009381716
Short name T194
Test name
Test status
Simulation time 7110776640 ps
CPU time 49.44 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:45 PM PDT 24
Peak memory 208208 kb
Host smart-5946f7ad-c5ad-47d4-a63e-ac06a563e711
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009381716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1009381716
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2297679388
Short name T987
Test name
Test status
Simulation time 282766157 ps
CPU time 5.44 seconds
Started May 18 04:10:57 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 207648 kb
Host smart-bbe82b6a-a708-41ab-9773-e70be92688f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297679388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2297679388
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.78094193
Short name T708
Test name
Test status
Simulation time 118311039 ps
CPU time 3.93 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:01 PM PDT 24
Peak memory 206552 kb
Host smart-8be3b63e-4cc2-499e-b728-987da0a47f05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78094193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.78094193
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2332887654
Short name T771
Test name
Test status
Simulation time 248361759 ps
CPU time 3.83 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:02 PM PDT 24
Peak memory 217944 kb
Host smart-13bef5fd-4192-478e-b1d8-9948b91d1ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332887654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2332887654
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4158155769
Short name T561
Test name
Test status
Simulation time 20232663 ps
CPU time 1.68 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:10:59 PM PDT 24
Peak memory 206476 kb
Host smart-c2e5e640-c443-4afc-950a-5197294e5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158155769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4158155769
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.954508356
Short name T868
Test name
Test status
Simulation time 604300678 ps
CPU time 11.49 seconds
Started May 18 04:10:56 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 220476 kb
Host smart-92756b2d-4330-4073-bd29-8ff4a5e24b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954508356 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.954508356
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3205561935
Short name T223
Test name
Test status
Simulation time 293014794 ps
CPU time 3.99 seconds
Started May 18 04:10:56 PM PDT 24
Finished May 18 04:11:02 PM PDT 24
Peak memory 207220 kb
Host smart-553a4a38-5e21-4418-a673-33cc8afac84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205561935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3205561935
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4193739681
Short name T152
Test name
Test status
Simulation time 86944365 ps
CPU time 2.43 seconds
Started May 18 04:10:53 PM PDT 24
Finished May 18 04:10:56 PM PDT 24
Peak memory 209576 kb
Host smart-d3a0f68f-a72a-41c2-b256-456d82c5c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193739681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4193739681
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3066708865
Short name T606
Test name
Test status
Simulation time 17150580 ps
CPU time 0.76 seconds
Started May 18 04:11:04 PM PDT 24
Finished May 18 04:11:06 PM PDT 24
Peak memory 205592 kb
Host smart-743a6adc-5912-423f-836a-d59d8c5fbf25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066708865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3066708865
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2391342706
Short name T412
Test name
Test status
Simulation time 1808095298 ps
CPU time 87.02 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:12:23 PM PDT 24
Peak memory 222196 kb
Host smart-aacaa215-fd75-436f-8591-88c220f37454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391342706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2391342706
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1490340264
Short name T937
Test name
Test status
Simulation time 78742827 ps
CPU time 3.54 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:00 PM PDT 24
Peak memory 218156 kb
Host smart-fce9c04c-4839-4e21-9ef1-48f5620d0b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490340264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1490340264
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3184501643
Short name T83
Test name
Test status
Simulation time 468011901 ps
CPU time 15.42 seconds
Started May 18 04:11:06 PM PDT 24
Finished May 18 04:11:22 PM PDT 24
Peak memory 213944 kb
Host smart-1d031e72-76ae-4bb9-ace5-b1472c417044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184501643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3184501643
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3387878417
Short name T248
Test name
Test status
Simulation time 536943969 ps
CPU time 6.28 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 213900 kb
Host smart-84aa03d9-31ef-4c77-8d63-6082676369ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387878417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3387878417
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1688368886
Short name T851
Test name
Test status
Simulation time 193548095 ps
CPU time 4.67 seconds
Started May 18 04:10:56 PM PDT 24
Finished May 18 04:11:03 PM PDT 24
Peak memory 219828 kb
Host smart-a91ae3e1-5289-4773-923a-b07279e42405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688368886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1688368886
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4144282351
Short name T941
Test name
Test status
Simulation time 355951704 ps
CPU time 6.92 seconds
Started May 18 04:10:55 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 209816 kb
Host smart-062da428-b68d-4228-be63-5c6cc018a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144282351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4144282351
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2035755830
Short name T766
Test name
Test status
Simulation time 66380878 ps
CPU time 2.29 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:10:58 PM PDT 24
Peak memory 206424 kb
Host smart-eed0c9f4-0764-4ff7-aba7-7bcc24a48b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035755830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2035755830
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2605654073
Short name T928
Test name
Test status
Simulation time 4300546553 ps
CPU time 32.83 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 208356 kb
Host smart-c2338218-b917-4dad-b18b-fa02c4c9ddf1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605654073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2605654073
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.138532282
Short name T292
Test name
Test status
Simulation time 291880521 ps
CPU time 3.15 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:00 PM PDT 24
Peak memory 206612 kb
Host smart-7acf2a78-5ca7-4193-b1c8-4d3d3162a11a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138532282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.138532282
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1622985066
Short name T234
Test name
Test status
Simulation time 3600583830 ps
CPU time 22.41 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:20 PM PDT 24
Peak memory 208496 kb
Host smart-345311cc-958e-42d1-9953-722ac8329053
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622985066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1622985066
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.479615874
Short name T74
Test name
Test status
Simulation time 960988147 ps
CPU time 11.86 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 210108 kb
Host smart-0a1c6086-c34d-436c-9302-c7bbb9d84848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479615874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.479615874
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2065751285
Short name T666
Test name
Test status
Simulation time 906034063 ps
CPU time 5.7 seconds
Started May 18 04:10:54 PM PDT 24
Finished May 18 04:11:02 PM PDT 24
Peak memory 206352 kb
Host smart-c3a5c9ed-e390-4eaf-ab6c-7482a8577edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065751285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2065751285
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1895276246
Short name T172
Test name
Test status
Simulation time 22070147 ps
CPU time 0.84 seconds
Started May 18 04:11:07 PM PDT 24
Finished May 18 04:11:09 PM PDT 24
Peak memory 205524 kb
Host smart-f67016c4-31f1-464a-a91e-fa12a69ba3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895276246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1895276246
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.914874509
Short name T673
Test name
Test status
Simulation time 827928260 ps
CPU time 9.16 seconds
Started May 18 04:11:05 PM PDT 24
Finished May 18 04:11:15 PM PDT 24
Peak memory 222352 kb
Host smart-8dbeacb5-c284-4d95-ae47-6e83f3fa3710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914874509 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.914874509
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3892713412
Short name T326
Test name
Test status
Simulation time 523372352 ps
CPU time 5.3 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:09 PM PDT 24
Peak memory 207412 kb
Host smart-a757a187-484a-4a4a-95e9-dd0c1de57759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892713412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3892713412
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3516972827
Short name T959
Test name
Test status
Simulation time 1359600452 ps
CPU time 9.29 seconds
Started May 18 04:11:04 PM PDT 24
Finished May 18 04:11:15 PM PDT 24
Peak memory 210332 kb
Host smart-daeb5aa4-e9d3-4c4f-8f89-58fc55ebcdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516972827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3516972827
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.333461710
Short name T881
Test name
Test status
Simulation time 43598430 ps
CPU time 0.74 seconds
Started May 18 04:11:05 PM PDT 24
Finished May 18 04:11:07 PM PDT 24
Peak memory 205528 kb
Host smart-42c3e723-0777-4600-b4db-184ccd229339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333461710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.333461710
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4079468308
Short name T124
Test name
Test status
Simulation time 569344454 ps
CPU time 22.89 seconds
Started May 18 04:11:00 PM PDT 24
Finished May 18 04:11:24 PM PDT 24
Peak memory 214576 kb
Host smart-252854f1-ecdb-4970-9c1d-1971e9fd6955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079468308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4079468308
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2998486316
Short name T995
Test name
Test status
Simulation time 156683360 ps
CPU time 3.18 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:06 PM PDT 24
Peak memory 208128 kb
Host smart-41889942-de6a-4ca0-a4ff-f55f74e64483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998486316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2998486316
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1467104190
Short name T795
Test name
Test status
Simulation time 52187255 ps
CPU time 3.35 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:07 PM PDT 24
Peak memory 209992 kb
Host smart-1ed74655-300a-40d4-8848-1f2f1d906dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467104190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1467104190
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2333087936
Short name T1010
Test name
Test status
Simulation time 741118989 ps
CPU time 8.93 seconds
Started May 18 04:11:05 PM PDT 24
Finished May 18 04:11:15 PM PDT 24
Peak memory 219252 kb
Host smart-f38acb2a-1602-47ba-ab7f-c7dc7a372204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333087936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2333087936
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1193901709
Short name T733
Test name
Test status
Simulation time 104981108 ps
CPU time 5.14 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:08 PM PDT 24
Peak memory 220236 kb
Host smart-8835fa1c-1db6-473f-963d-cc612aaf292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193901709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1193901709
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1350374788
Short name T927
Test name
Test status
Simulation time 1261023716 ps
CPU time 9.75 seconds
Started May 18 04:11:06 PM PDT 24
Finished May 18 04:11:17 PM PDT 24
Peak memory 209964 kb
Host smart-20f237b6-61a7-4390-b45b-2cf3e9a4cc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350374788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1350374788
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.974027797
Short name T689
Test name
Test status
Simulation time 187814479 ps
CPU time 4.01 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:08 PM PDT 24
Peak memory 208068 kb
Host smart-42fc4634-6f8c-4cd8-8383-24fb52ee8641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974027797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.974027797
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3436895868
Short name T384
Test name
Test status
Simulation time 58115054 ps
CPU time 1.92 seconds
Started May 18 04:11:04 PM PDT 24
Finished May 18 04:11:07 PM PDT 24
Peak memory 206560 kb
Host smart-8d031a4a-99eb-4f4f-a761-609debd4cc28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436895868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3436895868
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.512845326
Short name T316
Test name
Test status
Simulation time 64787616 ps
CPU time 2.21 seconds
Started May 18 04:11:00 PM PDT 24
Finished May 18 04:11:03 PM PDT 24
Peak memory 208276 kb
Host smart-0e28c489-fda2-4f73-b8d5-5c6416638473
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512845326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.512845326
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.743080880
Short name T914
Test name
Test status
Simulation time 628511919 ps
CPU time 4.37 seconds
Started May 18 04:11:03 PM PDT 24
Finished May 18 04:11:09 PM PDT 24
Peak memory 206532 kb
Host smart-82499820-360b-4d33-bbdc-cdefa038a45e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743080880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.743080880
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.63910691
Short name T745
Test name
Test status
Simulation time 48374459 ps
CPU time 1.65 seconds
Started May 18 04:11:03 PM PDT 24
Finished May 18 04:11:06 PM PDT 24
Peak memory 207628 kb
Host smart-a0df3a52-07d8-4542-961b-28f5c7c3ccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63910691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.63910691
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1406242178
Short name T790
Test name
Test status
Simulation time 57645973 ps
CPU time 2.77 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:06 PM PDT 24
Peak memory 206408 kb
Host smart-2284e454-471d-4304-b1ed-e81f6a76ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406242178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1406242178
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1776258910
Short name T825
Test name
Test status
Simulation time 764160466 ps
CPU time 4.73 seconds
Started May 18 04:11:04 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 219024 kb
Host smart-094fcf48-941d-486e-b1ea-5a48c137a97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776258910 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1776258910
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2103957304
Short name T224
Test name
Test status
Simulation time 208924111 ps
CPU time 5.2 seconds
Started May 18 04:11:00 PM PDT 24
Finished May 18 04:11:07 PM PDT 24
Peak memory 219412 kb
Host smart-7bf3572a-add3-4b15-b177-563108e33d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103957304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2103957304
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2695547996
Short name T824
Test name
Test status
Simulation time 42000960 ps
CPU time 2.17 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 209636 kb
Host smart-f25303fd-f6c9-407c-b69b-cd87a09b6b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695547996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2695547996
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3601781842
Short name T589
Test name
Test status
Simulation time 13711097 ps
CPU time 0.94 seconds
Started May 18 04:11:07 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 205676 kb
Host smart-a788e8ba-7a3c-49c1-a7eb-954eb5d5bdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601781842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3601781842
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2644820330
Short name T219
Test name
Test status
Simulation time 856505443 ps
CPU time 12.5 seconds
Started May 18 04:11:11 PM PDT 24
Finished May 18 04:11:25 PM PDT 24
Peak memory 214328 kb
Host smart-9679a805-e511-45b8-af2e-53be98742e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644820330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2644820330
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.73706270
Short name T768
Test name
Test status
Simulation time 79047586 ps
CPU time 2.88 seconds
Started May 18 04:11:07 PM PDT 24
Finished May 18 04:11:12 PM PDT 24
Peak memory 209140 kb
Host smart-75ba3a4a-db87-4f8e-b1f1-2278d3665622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73706270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.73706270
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2309292570
Short name T252
Test name
Test status
Simulation time 62881768 ps
CPU time 2.29 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:13 PM PDT 24
Peak memory 209132 kb
Host smart-9bb34c95-c489-44fe-b53c-463748c79686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309292570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2309292570
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2679655862
Short name T765
Test name
Test status
Simulation time 238280099 ps
CPU time 7.11 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:19 PM PDT 24
Peak memory 214360 kb
Host smart-62360ae1-cad3-4359-9308-6e3b84dfc124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679655862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2679655862
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1060042849
Short name T1011
Test name
Test status
Simulation time 10474916145 ps
CPU time 96.04 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 219456 kb
Host smart-2bafba7d-f866-4cac-954a-91456d16a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060042849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1060042849
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3086302805
Short name T829
Test name
Test status
Simulation time 1405458169 ps
CPU time 11.01 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:13 PM PDT 24
Peak memory 207824 kb
Host smart-bd59fb47-96a1-4066-a48c-c26940664ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086302805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3086302805
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3470505438
Short name T1061
Test name
Test status
Simulation time 2205457153 ps
CPU time 7.06 seconds
Started May 18 04:11:04 PM PDT 24
Finished May 18 04:11:12 PM PDT 24
Peak memory 208204 kb
Host smart-fdfbbe34-db48-4129-850b-0dd9ec806923
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470505438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3470505438
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1161040047
Short name T188
Test name
Test status
Simulation time 155704666 ps
CPU time 2.01 seconds
Started May 18 04:11:01 PM PDT 24
Finished May 18 04:11:04 PM PDT 24
Peak memory 206600 kb
Host smart-82bec185-1ef9-45b4-9110-8557b1eca6ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161040047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1161040047
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3258065686
Short name T830
Test name
Test status
Simulation time 168387398 ps
CPU time 3.83 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:07 PM PDT 24
Peak memory 208628 kb
Host smart-53683660-9b49-4756-87d2-d7465c040343
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258065686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3258065686
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2282517874
Short name T1037
Test name
Test status
Simulation time 98952740 ps
CPU time 2.65 seconds
Started May 18 04:11:12 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 208872 kb
Host smart-e7fec4ae-8fc3-4025-b403-c82956ccf9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282517874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2282517874
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2585610287
Short name T788
Test name
Test status
Simulation time 838803006 ps
CPU time 22.28 seconds
Started May 18 04:11:02 PM PDT 24
Finished May 18 04:11:26 PM PDT 24
Peak memory 208156 kb
Host smart-16206b35-9700-4fb7-8a4a-12c6ad133bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585610287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2585610287
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1988251318
Short name T684
Test name
Test status
Simulation time 92568193 ps
CPU time 2.08 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:13 PM PDT 24
Peak memory 217492 kb
Host smart-04505b89-143a-4ff2-bd47-c8cf9e8a50af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988251318 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1988251318
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3768100735
Short name T685
Test name
Test status
Simulation time 199575951 ps
CPU time 4.88 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 209744 kb
Host smart-3a2302ad-96cd-4950-b841-4355f5a04f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768100735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3768100735
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3984218044
Short name T844
Test name
Test status
Simulation time 323547875 ps
CPU time 2.65 seconds
Started May 18 04:11:11 PM PDT 24
Finished May 18 04:11:15 PM PDT 24
Peak memory 210020 kb
Host smart-2b2e896c-5e88-430f-9601-9e3b72d91940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984218044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3984218044
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2201042927
Short name T965
Test name
Test status
Simulation time 16372578 ps
CPU time 0.76 seconds
Started May 18 04:11:16 PM PDT 24
Finished May 18 04:11:18 PM PDT 24
Peak memory 205548 kb
Host smart-94345fed-fee4-474c-8b62-6abe0616cb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201042927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2201042927
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1097153326
Short name T401
Test name
Test status
Simulation time 122147128 ps
CPU time 3.87 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 213956 kb
Host smart-d593fce2-ec37-47e2-acc2-4f4dc8a487ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097153326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1097153326
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3604558715
Short name T956
Test name
Test status
Simulation time 1190662002 ps
CPU time 21.13 seconds
Started May 18 04:11:11 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 213984 kb
Host smart-ce6204c8-d09d-457d-b92d-4a98d812b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604558715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3604558715
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1147225924
Short name T758
Test name
Test status
Simulation time 2794186133 ps
CPU time 13.35 seconds
Started May 18 04:11:10 PM PDT 24
Finished May 18 04:11:26 PM PDT 24
Peak memory 214020 kb
Host smart-ad9e5ece-ab9b-47df-9f45-38817574d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147225924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1147225924
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1401853152
Short name T855
Test name
Test status
Simulation time 84903703 ps
CPU time 4.04 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:13 PM PDT 24
Peak memory 219872 kb
Host smart-bbb84e53-6715-495a-8259-10421beead21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401853152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1401853152
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3771904265
Short name T345
Test name
Test status
Simulation time 127006262 ps
CPU time 3.37 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 208992 kb
Host smart-4a912eea-6c8e-4862-8864-705842923333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771904265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3771904265
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1921494474
Short name T287
Test name
Test status
Simulation time 728040730 ps
CPU time 5.45 seconds
Started May 18 04:11:07 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 208316 kb
Host smart-c1dcf964-48ea-4de6-9aae-d1a8f4fd7aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921494474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1921494474
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1673737032
Short name T635
Test name
Test status
Simulation time 83768289 ps
CPU time 3.72 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:14 PM PDT 24
Peak memory 208508 kb
Host smart-49ef7939-c718-4dcb-a455-a82a05f75915
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673737032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1673737032
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.752438065
Short name T569
Test name
Test status
Simulation time 749594112 ps
CPU time 5.97 seconds
Started May 18 04:11:12 PM PDT 24
Finished May 18 04:11:20 PM PDT 24
Peak memory 208344 kb
Host smart-00e1658f-e92c-430f-9573-ee51804630d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752438065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.752438065
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3576678172
Short name T1013
Test name
Test status
Simulation time 4598455583 ps
CPU time 43.14 seconds
Started May 18 04:11:10 PM PDT 24
Finished May 18 04:11:55 PM PDT 24
Peak memory 208308 kb
Host smart-76053736-56e9-4324-9606-2df1bb80a6e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576678172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3576678172
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3244361522
Short name T913
Test name
Test status
Simulation time 107241668 ps
CPU time 3.05 seconds
Started May 18 04:11:08 PM PDT 24
Finished May 18 04:11:13 PM PDT 24
Peak memory 217872 kb
Host smart-19b9bb84-227b-458a-bd5b-0a688510a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244361522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3244361522
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.206849830
Short name T1042
Test name
Test status
Simulation time 238131743 ps
CPU time 4.87 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 206300 kb
Host smart-4ffb0ca7-0ea1-4911-9b4a-871ba47f3f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206849830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.206849830
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.281611420
Short name T1049
Test name
Test status
Simulation time 2733136861 ps
CPU time 27.16 seconds
Started May 18 04:11:09 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 221276 kb
Host smart-da81344a-1428-4ed5-86de-40018f94bc41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281611420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.281611420
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.660735087
Short name T1032
Test name
Test status
Simulation time 111383125 ps
CPU time 3.25 seconds
Started May 18 04:11:11 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 210136 kb
Host smart-8e06957b-1b4a-491a-baf2-294f1d2d09a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660735087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.660735087
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4231982679
Short name T694
Test name
Test status
Simulation time 51291553 ps
CPU time 0.93 seconds
Started May 18 04:11:18 PM PDT 24
Finished May 18 04:11:21 PM PDT 24
Peak memory 205596 kb
Host smart-e9e64d0f-1be4-49e7-90c1-69117f802013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231982679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4231982679
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3636460294
Short name T10
Test name
Test status
Simulation time 3641692524 ps
CPU time 25.15 seconds
Started May 18 04:11:17 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 222160 kb
Host smart-8e89dad6-a99e-4fe9-bdc5-5c8ae666c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636460294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3636460294
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3273523284
Short name T654
Test name
Test status
Simulation time 462286613 ps
CPU time 4.56 seconds
Started May 18 04:11:15 PM PDT 24
Finished May 18 04:11:21 PM PDT 24
Peak memory 209344 kb
Host smart-c372c1f0-a532-4faa-a635-a617b311d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273523284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3273523284
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1275778267
Short name T760
Test name
Test status
Simulation time 394654779 ps
CPU time 4.77 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:11:27 PM PDT 24
Peak memory 214036 kb
Host smart-2cc0f5e5-dfc3-433b-855c-b70040554c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275778267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1275778267
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3253831357
Short name T915
Test name
Test status
Simulation time 367299216 ps
CPU time 3.64 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:11:26 PM PDT 24
Peak memory 215044 kb
Host smart-d53a14dc-a420-47fa-a92b-dae6b6fcf083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253831357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3253831357
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3731685622
Short name T237
Test name
Test status
Simulation time 6551779897 ps
CPU time 40.36 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:12:02 PM PDT 24
Peak memory 214064 kb
Host smart-1b599272-c4fa-4fc3-a5d6-d4f3484af013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731685622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3731685622
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2027404999
Short name T696
Test name
Test status
Simulation time 672836124 ps
CPU time 10.25 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 207452 kb
Host smart-90e42d09-271a-4d6a-a9aa-b3062e3ad2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027404999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2027404999
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1131393223
Short name T710
Test name
Test status
Simulation time 361115796 ps
CPU time 3.11 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 206796 kb
Host smart-31eae32a-3e71-49d4-96a3-3422dd0e7081
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131393223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1131393223
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3018143505
Short name T782
Test name
Test status
Simulation time 114923976 ps
CPU time 2.89 seconds
Started May 18 04:11:19 PM PDT 24
Finished May 18 04:11:24 PM PDT 24
Peak memory 208536 kb
Host smart-5aa5ec6b-7ef7-49a9-b382-a649d735fb06
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018143505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3018143505
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2777963789
Short name T642
Test name
Test status
Simulation time 70439207 ps
CPU time 2.58 seconds
Started May 18 04:11:16 PM PDT 24
Finished May 18 04:11:20 PM PDT 24
Peak memory 206520 kb
Host smart-29e30cf6-c922-49a8-8366-5f8827fe2de3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777963789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2777963789
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3841003418
Short name T974
Test name
Test status
Simulation time 61054490 ps
CPU time 3.23 seconds
Started May 18 04:11:16 PM PDT 24
Finished May 18 04:11:21 PM PDT 24
Peak memory 209880 kb
Host smart-6fca29f6-ad19-48a8-8064-a09257084357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841003418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3841003418
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2113496811
Short name T30
Test name
Test status
Simulation time 1062075599 ps
CPU time 16.3 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:11:38 PM PDT 24
Peak memory 208004 kb
Host smart-1886074a-43ee-440d-b086-722d179b2fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113496811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2113496811
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.811005460
Short name T322
Test name
Test status
Simulation time 1019883919 ps
CPU time 36.64 seconds
Started May 18 04:11:16 PM PDT 24
Finished May 18 04:11:54 PM PDT 24
Peak memory 216716 kb
Host smart-90c1c420-a69a-474e-a880-15b99dc77930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811005460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.811005460
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2717867608
Short name T878
Test name
Test status
Simulation time 231080073 ps
CPU time 3.02 seconds
Started May 18 04:11:18 PM PDT 24
Finished May 18 04:11:22 PM PDT 24
Peak memory 222472 kb
Host smart-bf170e4c-15ce-4a21-97e9-09616fc9e3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717867608 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2717867608
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3708528484
Short name T686
Test name
Test status
Simulation time 102860307 ps
CPU time 4.39 seconds
Started May 18 04:11:17 PM PDT 24
Finished May 18 04:11:23 PM PDT 24
Peak memory 213976 kb
Host smart-f116378c-c81e-4980-be30-551e3f3dd72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708528484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3708528484
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1059066686
Short name T702
Test name
Test status
Simulation time 397546785 ps
CPU time 5.18 seconds
Started May 18 04:11:21 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 210152 kb
Host smart-98a46ae9-cd29-4798-b382-3859238bd892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059066686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1059066686
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4170572574
Short name T581
Test name
Test status
Simulation time 39883502 ps
CPU time 0.75 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:30 PM PDT 24
Peak memory 205784 kb
Host smart-d2f5b275-ab67-4544-9ae7-d5f18d3d6107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170572574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4170572574
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.63308591
Short name T25
Test name
Test status
Simulation time 4686469628 ps
CPU time 43.23 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:12:14 PM PDT 24
Peak memory 214060 kb
Host smart-72147517-0c13-4392-9d0e-b7bbeab7e5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63308591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.63308591
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2616843081
Short name T367
Test name
Test status
Simulation time 53672166 ps
CPU time 1.87 seconds
Started May 18 04:11:18 PM PDT 24
Finished May 18 04:11:21 PM PDT 24
Peak memory 207476 kb
Host smart-68968510-8097-4c5a-9b0d-b616bd723bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616843081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2616843081
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3506301092
Short name T655
Test name
Test status
Simulation time 2847674261 ps
CPU time 72.88 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 214096 kb
Host smart-1766cb1c-dab0-4a0c-aaaa-5ad121e9596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506301092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3506301092
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1011932678
Short name T390
Test name
Test status
Simulation time 261606241 ps
CPU time 3.55 seconds
Started May 18 04:11:22 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 218772 kb
Host smart-cdb9f81a-9c60-4ca7-8441-6065a4956dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011932678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1011932678
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.903738987
Short name T807
Test name
Test status
Simulation time 169576628 ps
CPU time 3.99 seconds
Started May 18 04:11:17 PM PDT 24
Finished May 18 04:11:22 PM PDT 24
Peak memory 208784 kb
Host smart-ade36ecb-a856-4951-8652-5d3f4943681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903738987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.903738987
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.638658753
Short name T989
Test name
Test status
Simulation time 158502238 ps
CPU time 3.57 seconds
Started May 18 04:11:19 PM PDT 24
Finished May 18 04:11:25 PM PDT 24
Peak memory 208412 kb
Host smart-6453c4a4-4aca-44a0-acda-6c27d10d1f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638658753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.638658753
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2251930696
Short name T272
Test name
Test status
Simulation time 189249086 ps
CPU time 3.83 seconds
Started May 18 04:11:20 PM PDT 24
Finished May 18 04:11:26 PM PDT 24
Peak memory 208244 kb
Host smart-94434d42-702e-49ed-a79c-17cf0f126b84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251930696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2251930696
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1507317483
Short name T586
Test name
Test status
Simulation time 36622071 ps
CPU time 2.46 seconds
Started May 18 04:11:19 PM PDT 24
Finished May 18 04:11:24 PM PDT 24
Peak memory 207336 kb
Host smart-55599011-cbb0-43d4-b4c3-dbf6100ff166
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507317483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1507317483
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.572599698
Short name T644
Test name
Test status
Simulation time 208788892 ps
CPU time 5.91 seconds
Started May 18 04:11:15 PM PDT 24
Finished May 18 04:11:23 PM PDT 24
Peak memory 208192 kb
Host smart-e430770f-58c2-4d38-a986-c6f6b34a95d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572599698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.572599698
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2102510486
Short name T286
Test name
Test status
Simulation time 273497465 ps
CPU time 3.45 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 214032 kb
Host smart-a4a2ca17-a17c-49f0-ad7e-ffbee02afe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102510486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2102510486
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.119084538
Short name T380
Test name
Test status
Simulation time 3655778581 ps
CPU time 6.95 seconds
Started May 18 04:11:18 PM PDT 24
Finished May 18 04:11:27 PM PDT 24
Peak memory 206464 kb
Host smart-3ac53f74-090a-4184-b24e-e82bc23074b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119084538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.119084538
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2313551137
Short name T1008
Test name
Test status
Simulation time 27138778 ps
CPU time 2.06 seconds
Started May 18 04:11:22 PM PDT 24
Finished May 18 04:11:27 PM PDT 24
Peak memory 206972 kb
Host smart-6cad7308-e9fd-45d2-bdcb-2910ac0b5d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313551137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2313551137
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3185414983
Short name T614
Test name
Test status
Simulation time 300602126 ps
CPU time 12.42 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:42 PM PDT 24
Peak memory 220112 kb
Host smart-d95260e9-9921-4072-834e-97b8309b34f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185414983 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3185414983
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2733683852
Short name T275
Test name
Test status
Simulation time 180415843 ps
CPU time 5.15 seconds
Started May 18 04:11:22 PM PDT 24
Finished May 18 04:11:30 PM PDT 24
Peak memory 207784 kb
Host smart-0b386843-44dc-4e3d-b8c1-3e67385c7904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733683852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2733683852
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.173414665
Short name T709
Test name
Test status
Simulation time 1166883393 ps
CPU time 4.87 seconds
Started May 18 04:11:28 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 210300 kb
Host smart-77c35bac-a271-4d21-8a49-82e5411c0b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173414665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.173414665
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.451208191
Short name T730
Test name
Test status
Simulation time 13532212 ps
CPU time 0.78 seconds
Started May 18 04:10:06 PM PDT 24
Finished May 18 04:10:07 PM PDT 24
Peak memory 205448 kb
Host smart-6f1a4421-8b53-417e-87fc-52cff71aa9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451208191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.451208191
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3053391959
Short name T371
Test name
Test status
Simulation time 300793329 ps
CPU time 14.51 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:14 PM PDT 24
Peak memory 214624 kb
Host smart-e389a2e8-55d1-4e59-a608-3fc42410a48c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053391959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3053391959
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3382417293
Short name T809
Test name
Test status
Simulation time 209653162 ps
CPU time 4.22 seconds
Started May 18 04:10:01 PM PDT 24
Finished May 18 04:10:06 PM PDT 24
Peak memory 210144 kb
Host smart-2fb844b8-2c89-4298-a1f2-7eb878671b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382417293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3382417293
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.948553921
Short name T1019
Test name
Test status
Simulation time 257187227 ps
CPU time 3.97 seconds
Started May 18 04:09:59 PM PDT 24
Finished May 18 04:10:04 PM PDT 24
Peak memory 214068 kb
Host smart-31a29e91-0246-45a5-b8da-c891ab671f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948553921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.948553921
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4120199101
Short name T346
Test name
Test status
Simulation time 1862132795 ps
CPU time 12.5 seconds
Started May 18 04:10:00 PM PDT 24
Finished May 18 04:10:13 PM PDT 24
Peak memory 213948 kb
Host smart-cc1279a1-e197-476e-b530-2ec3f12b4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120199101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4120199101
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.681232361
Short name T857
Test name
Test status
Simulation time 111114344 ps
CPU time 2.25 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:01 PM PDT 24
Peak memory 207332 kb
Host smart-4bbdcc1f-3795-492d-bad9-edb5bf0b2cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681232361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.681232361
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.424193362
Short name T998
Test name
Test status
Simulation time 2512226308 ps
CPU time 54.16 seconds
Started May 18 04:09:59 PM PDT 24
Finished May 18 04:10:54 PM PDT 24
Peak memory 208520 kb
Host smart-2dd6dc35-e905-414e-b279-f95aee66da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424193362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.424193362
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2781406985
Short name T37
Test name
Test status
Simulation time 314424295 ps
CPU time 9.75 seconds
Started May 18 04:10:08 PM PDT 24
Finished May 18 04:10:19 PM PDT 24
Peak memory 237984 kb
Host smart-34a0c888-16d5-4036-873d-97da433392b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781406985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2781406985
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2901538054
Short name T1016
Test name
Test status
Simulation time 32276515 ps
CPU time 2.17 seconds
Started May 18 04:10:02 PM PDT 24
Finished May 18 04:10:05 PM PDT 24
Peak memory 206532 kb
Host smart-d255aea2-c00e-40b3-a287-cc10211a2045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901538054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2901538054
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3715927569
Short name T773
Test name
Test status
Simulation time 141292677 ps
CPU time 2.8 seconds
Started May 18 04:10:00 PM PDT 24
Finished May 18 04:10:04 PM PDT 24
Peak memory 208516 kb
Host smart-033ae808-e21a-4eb1-9911-d8f61fcdd395
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715927569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3715927569
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2598441266
Short name T781
Test name
Test status
Simulation time 615601885 ps
CPU time 5.83 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:04 PM PDT 24
Peak memory 207372 kb
Host smart-035a2d3f-456f-4097-8cc2-7c80b2df363f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598441266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2598441266
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.191693864
Short name T880
Test name
Test status
Simulation time 190676831 ps
CPU time 2.62 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:02 PM PDT 24
Peak memory 206612 kb
Host smart-38b83ed3-548d-457b-bc70-c1199a7bd998
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191693864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.191693864
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4020492720
Short name T1023
Test name
Test status
Simulation time 106303158 ps
CPU time 2.9 seconds
Started May 18 04:09:59 PM PDT 24
Finished May 18 04:10:03 PM PDT 24
Peak memory 217820 kb
Host smart-002ea221-3d76-42f6-810a-f5cbbb0b513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020492720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4020492720
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.525216950
Short name T723
Test name
Test status
Simulation time 293601097 ps
CPU time 3.04 seconds
Started May 18 04:09:57 PM PDT 24
Finished May 18 04:10:01 PM PDT 24
Peak memory 208164 kb
Host smart-f5d91c25-c485-4535-95ed-d11e051a163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525216950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.525216950
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1275083770
Short name T713
Test name
Test status
Simulation time 6523507071 ps
CPU time 52.22 seconds
Started May 18 04:10:01 PM PDT 24
Finished May 18 04:10:54 PM PDT 24
Peak memory 209388 kb
Host smart-8dea22de-d9f9-4072-b78e-18198dcc00df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275083770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1275083770
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1592817306
Short name T664
Test name
Test status
Simulation time 115258773 ps
CPU time 2.69 seconds
Started May 18 04:09:58 PM PDT 24
Finished May 18 04:10:02 PM PDT 24
Peak memory 209548 kb
Host smart-2f6987c8-ae39-4244-b8f8-545f5816b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592817306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1592817306
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.714089813
Short name T593
Test name
Test status
Simulation time 56241586 ps
CPU time 0.94 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:30 PM PDT 24
Peak memory 205692 kb
Host smart-8e4d3370-45c3-4858-b31e-b59e84b8acdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714089813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.714089813
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2323139714
Short name T242
Test name
Test status
Simulation time 50731051 ps
CPU time 3.21 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 215320 kb
Host smart-d5f972cb-8be7-4e63-8ba1-c499749d9294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323139714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2323139714
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3057588781
Short name T29
Test name
Test status
Simulation time 451542217 ps
CPU time 4.44 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 214400 kb
Host smart-22e00c79-5863-43ec-beb2-249c2c823de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057588781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3057588781
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4092849197
Short name T885
Test name
Test status
Simulation time 85480558 ps
CPU time 2.06 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 207244 kb
Host smart-4aa79bbe-6295-4f4e-bccc-65cec3fa3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092849197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4092849197
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4126329611
Short name T370
Test name
Test status
Simulation time 5345707745 ps
CPU time 42.02 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:12:11 PM PDT 24
Peak memory 222184 kb
Host smart-53102d87-e8cd-413b-a05c-0915428965b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126329611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4126329611
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.937106717
Short name T8
Test name
Test status
Simulation time 860539262 ps
CPU time 6.43 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 209440 kb
Host smart-812bffcb-22ae-42dd-b664-5a88a23c0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937106717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.937106717
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.138451578
Short name T1022
Test name
Test status
Simulation time 463742999 ps
CPU time 4 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 208544 kb
Host smart-b709ab91-c3c0-4cfa-a21e-ffd15c523296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138451578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.138451578
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3751439171
Short name T193
Test name
Test status
Simulation time 135285451 ps
CPU time 3.57 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 208076 kb
Host smart-d97f4439-525e-41b0-bcb3-6e74cccff193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751439171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3751439171
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4040165108
Short name T847
Test name
Test status
Simulation time 84993329 ps
CPU time 2.54 seconds
Started May 18 04:11:23 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 208196 kb
Host smart-c85bfa5d-e382-4238-bf8a-52fe25b836f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040165108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4040165108
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1134445705
Short name T727
Test name
Test status
Simulation time 75826654 ps
CPU time 2.51 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 206636 kb
Host smart-517f6e10-d31b-4631-9d9e-041f9444cdce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134445705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1134445705
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1773898195
Short name T611
Test name
Test status
Simulation time 227343276 ps
CPU time 2.82 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 206668 kb
Host smart-31e591af-90a2-4bab-a23b-db65555520f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773898195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1773898195
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.732617653
Short name T313
Test name
Test status
Simulation time 59899959 ps
CPU time 2.09 seconds
Started May 18 04:11:22 PM PDT 24
Finished May 18 04:11:27 PM PDT 24
Peak memory 207892 kb
Host smart-411bd857-0eaa-4e60-a0c0-7fc68f9556a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732617653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.732617653
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2891790067
Short name T545
Test name
Test status
Simulation time 475430122 ps
CPU time 2.42 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:31 PM PDT 24
Peak memory 206492 kb
Host smart-78e78e72-69dc-4f9c-9c75-73a46438a521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891790067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2891790067
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1393143172
Short name T649
Test name
Test status
Simulation time 316420175 ps
CPU time 6.25 seconds
Started May 18 04:11:23 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 222364 kb
Host smart-f6c81174-3284-4145-9e77-3dc615b31893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393143172 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1393143172
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4118286089
Short name T311
Test name
Test status
Simulation time 78278398 ps
CPU time 2.9 seconds
Started May 18 04:11:27 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 218060 kb
Host smart-71629e4d-06c4-457d-9c2f-f7dd705646e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118286089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4118286089
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1737091880
Short name T392
Test name
Test status
Simulation time 87637608 ps
CPU time 3.55 seconds
Started May 18 04:11:23 PM PDT 24
Finished May 18 04:11:30 PM PDT 24
Peak memory 209820 kb
Host smart-9ea5bae5-3cbc-4ff0-948c-1c5902eabd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737091880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1737091880
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2378849162
Short name T570
Test name
Test status
Simulation time 16015226 ps
CPU time 0.93 seconds
Started May 18 04:11:32 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 205784 kb
Host smart-cf75231f-9afc-4b8d-8466-f8b76469530a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378849162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2378849162
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3349589937
Short name T982
Test name
Test status
Simulation time 607456466 ps
CPU time 8.5 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 214880 kb
Host smart-bcb63364-62f8-46bf-bcce-54a85a6c586c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349589937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3349589937
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.288428223
Short name T840
Test name
Test status
Simulation time 195035779 ps
CPU time 4.16 seconds
Started May 18 04:11:29 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 209320 kb
Host smart-88bad0b9-b2ee-452b-8201-fae48d46eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288428223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.288428223
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1876229045
Short name T1004
Test name
Test status
Simulation time 265006475 ps
CPU time 7.92 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 208640 kb
Host smart-72299234-d4bb-4028-8792-fcb2f4bea710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876229045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1876229045
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3627438319
Short name T213
Test name
Test status
Simulation time 401674622 ps
CPU time 5.35 seconds
Started May 18 04:11:21 PM PDT 24
Finished May 18 04:11:29 PM PDT 24
Peak memory 213972 kb
Host smart-1adc872d-6d17-4349-b516-5aa3b0663315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627438319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3627438319
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1235272656
Short name T1051
Test name
Test status
Simulation time 371026661 ps
CPU time 7.31 seconds
Started May 18 04:11:25 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 209420 kb
Host smart-375f7d32-318f-4693-88f4-cb80292440ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235272656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1235272656
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3217201496
Short name T645
Test name
Test status
Simulation time 33997018 ps
CPU time 2.21 seconds
Started May 18 04:11:26 PM PDT 24
Finished May 18 04:11:33 PM PDT 24
Peak memory 206408 kb
Host smart-f9786778-b8f7-48aa-b334-e09f9ba2bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217201496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3217201496
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.758752307
Short name T873
Test name
Test status
Simulation time 136892579 ps
CPU time 5.19 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 208344 kb
Host smart-79e3a8c3-a777-42d8-bd85-6886a88d5022
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758752307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.758752307
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.575983666
Short name T834
Test name
Test status
Simulation time 247177404 ps
CPU time 3.65 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 206580 kb
Host smart-ad3725c4-88d0-4aa9-b8ac-e584c0543871
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575983666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.575983666
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1998130547
Short name T812
Test name
Test status
Simulation time 476913018 ps
CPU time 3.72 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:31 PM PDT 24
Peak memory 207036 kb
Host smart-90499a45-73b2-49fd-bc32-7de4b17b6628
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998130547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1998130547
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3178367589
Short name T101
Test name
Test status
Simulation time 41360666 ps
CPU time 2.63 seconds
Started May 18 04:11:33 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 209376 kb
Host smart-76a5ef18-fcbf-4159-ac7e-c34c60ea2202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178367589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3178367589
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1859336147
Short name T391
Test name
Test status
Simulation time 176022847 ps
CPU time 2.74 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:31 PM PDT 24
Peak memory 206364 kb
Host smart-5c892faa-7c99-4c79-81e9-c123be447a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859336147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1859336147
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1001097928
Short name T59
Test name
Test status
Simulation time 51374319 ps
CPU time 2.28 seconds
Started May 18 04:11:33 PM PDT 24
Finished May 18 04:11:38 PM PDT 24
Peak memory 209448 kb
Host smart-cbeec667-9e9d-4c0c-a6a9-84ec99e95b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001097928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1001097928
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3834095110
Short name T203
Test name
Test status
Simulation time 351715076 ps
CPU time 5.59 seconds
Started May 18 04:11:28 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 218580 kb
Host smart-44ecba5d-7758-4486-b9c7-e975e2cfb786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834095110 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3834095110
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2774809483
Short name T904
Test name
Test status
Simulation time 151830430 ps
CPU time 4.25 seconds
Started May 18 04:11:24 PM PDT 24
Finished May 18 04:11:32 PM PDT 24
Peak memory 208032 kb
Host smart-d17c814c-288e-4fe4-9170-ba4c8c16f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774809483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2774809483
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.340572698
Short name T892
Test name
Test status
Simulation time 191922242 ps
CPU time 5.17 seconds
Started May 18 04:11:31 PM PDT 24
Finished May 18 04:11:40 PM PDT 24
Peak memory 210676 kb
Host smart-3692813c-d24a-4755-94db-50ad8a60cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340572698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.340572698
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.22615122
Short name T731
Test name
Test status
Simulation time 20368101 ps
CPU time 0.87 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 205564 kb
Host smart-dca82f6c-dce3-4074-a5d2-f29f8e11dc35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.22615122
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3934867420
Short name T34
Test name
Test status
Simulation time 126647812 ps
CPU time 5.16 seconds
Started May 18 04:11:31 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 218316 kb
Host smart-88bbd086-d2a2-4954-a7f9-a6fa1a9efa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934867420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3934867420
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2040855898
Short name T690
Test name
Test status
Simulation time 100596010 ps
CPU time 2.73 seconds
Started May 18 04:11:30 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 208964 kb
Host smart-8a9e44cd-eea2-44ad-8b6d-2d8231c56262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040855898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2040855898
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.550789656
Short name T887
Test name
Test status
Simulation time 109232613 ps
CPU time 5.17 seconds
Started May 18 04:11:32 PM PDT 24
Finished May 18 04:11:40 PM PDT 24
Peak memory 213412 kb
Host smart-b97b0d39-41d2-4429-b5a3-7562d5258aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550789656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.550789656
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.843543018
Short name T976
Test name
Test status
Simulation time 105986867 ps
CPU time 5.45 seconds
Started May 18 04:11:33 PM PDT 24
Finished May 18 04:11:41 PM PDT 24
Peak memory 211016 kb
Host smart-ebc10b0e-e462-4e47-9405-aea6ad765ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843543018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.843543018
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2185698582
Short name T7
Test name
Test status
Simulation time 436433855 ps
CPU time 3.11 seconds
Started May 18 04:11:30 PM PDT 24
Finished May 18 04:11:36 PM PDT 24
Peak memory 207492 kb
Host smart-1f6e021e-a830-414e-82f1-1bf12173a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185698582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2185698582
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3291942833
Short name T320
Test name
Test status
Simulation time 147777369 ps
CPU time 5 seconds
Started May 18 04:11:31 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 209296 kb
Host smart-1583ae35-d312-4be7-a182-347a46324029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291942833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3291942833
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1269340061
Short name T296
Test name
Test status
Simulation time 1201419881 ps
CPU time 28.4 seconds
Started May 18 04:11:28 PM PDT 24
Finished May 18 04:12:00 PM PDT 24
Peak memory 207716 kb
Host smart-f5acff26-adbc-4d18-b8b2-3fab8588e9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269340061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1269340061
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.501536782
Short name T604
Test name
Test status
Simulation time 144069585 ps
CPU time 4.67 seconds
Started May 18 04:11:30 PM PDT 24
Finished May 18 04:11:38 PM PDT 24
Peak memory 208328 kb
Host smart-5fce40f0-3969-4a13-8f45-6b19a784477a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501536782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.501536782
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.603283947
Short name T197
Test name
Test status
Simulation time 112507756 ps
CPU time 1.97 seconds
Started May 18 04:11:32 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 208568 kb
Host smart-791435a9-faa1-4363-b84f-81432fcf21ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603283947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.603283947
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.226927328
Short name T323
Test name
Test status
Simulation time 322480112 ps
CPU time 3.91 seconds
Started May 18 04:11:32 PM PDT 24
Finished May 18 04:11:39 PM PDT 24
Peak memory 207800 kb
Host smart-a3ac3b19-ba96-42f2-a234-103ffccd8a27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226927328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.226927328
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1172988868
Short name T984
Test name
Test status
Simulation time 32578059 ps
CPU time 1.61 seconds
Started May 18 04:11:29 PM PDT 24
Finished May 18 04:11:34 PM PDT 24
Peak memory 207696 kb
Host smart-c667cff0-e278-480d-a940-f8399069da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172988868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1172988868
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.884187983
Short name T3
Test name
Test status
Simulation time 418697249 ps
CPU time 3.28 seconds
Started May 18 04:11:31 PM PDT 24
Finished May 18 04:11:37 PM PDT 24
Peak memory 208296 kb
Host smart-451fd965-9f20-4c03-bbc7-514e05006d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884187983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.884187983
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3864902862
Short name T235
Test name
Test status
Simulation time 690990051 ps
CPU time 26.15 seconds
Started May 18 04:11:30 PM PDT 24
Finished May 18 04:11:59 PM PDT 24
Peak memory 222128 kb
Host smart-eeb7bf6d-3e89-46b5-8d15-c986ad4c5efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864902862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3864902862
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2376984254
Short name T594
Test name
Test status
Simulation time 189474218 ps
CPU time 5.98 seconds
Started May 18 04:11:36 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 220060 kb
Host smart-e32f4a79-c5ba-4ef8-be83-b18b06853bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376984254 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2376984254
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1072980411
Short name T291
Test name
Test status
Simulation time 876887972 ps
CPU time 26.39 seconds
Started May 18 04:11:33 PM PDT 24
Finished May 18 04:12:02 PM PDT 24
Peak memory 208668 kb
Host smart-812f90af-7393-40c5-aa57-29c0d10097c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072980411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1072980411
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1272965157
Short name T789
Test name
Test status
Simulation time 328256896 ps
CPU time 5.78 seconds
Started May 18 04:11:32 PM PDT 24
Finished May 18 04:11:41 PM PDT 24
Peak memory 210104 kb
Host smart-d1c16b53-7536-44b7-8f60-ed36b8c55e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272965157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1272965157
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1289957854
Short name T650
Test name
Test status
Simulation time 43689687 ps
CPU time 0.83 seconds
Started May 18 04:11:36 PM PDT 24
Finished May 18 04:11:38 PM PDT 24
Peak memory 205536 kb
Host smart-cc861aef-3349-4c27-840a-63cc45d7d1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289957854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1289957854
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.878179490
Short name T416
Test name
Test status
Simulation time 51765160 ps
CPU time 3.48 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:48 PM PDT 24
Peak memory 214004 kb
Host smart-e41fcfed-56e0-451d-8309-e4972a62bf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878179490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.878179490
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3446001839
Short name T67
Test name
Test status
Simulation time 691213048 ps
CPU time 6.82 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:11:45 PM PDT 24
Peak memory 214036 kb
Host smart-815784ac-5b47-4471-8710-8a472ad03cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446001839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3446001839
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1729902152
Short name T96
Test name
Test status
Simulation time 622827411 ps
CPU time 4.9 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:49 PM PDT 24
Peak memory 218844 kb
Host smart-2b83261a-5f80-46b2-bcb4-e2b34e96cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729902152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1729902152
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.251473816
Short name T308
Test name
Test status
Simulation time 113253873 ps
CPU time 4.11 seconds
Started May 18 04:11:35 PM PDT 24
Finished May 18 04:11:41 PM PDT 24
Peak memory 210532 kb
Host smart-386fbf40-c5cf-4cf2-8fb4-40e10a7858db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251473816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.251473816
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.980382320
Short name T45
Test name
Test status
Simulation time 151360396 ps
CPU time 3.81 seconds
Started May 18 04:11:38 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 207644 kb
Host smart-0aa48bb6-7636-4a28-9a2f-fc34a3476fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980382320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.980382320
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.855649912
Short name T318
Test name
Test status
Simulation time 568197713 ps
CPU time 6.59 seconds
Started May 18 04:11:39 PM PDT 24
Finished May 18 04:11:47 PM PDT 24
Peak memory 207324 kb
Host smart-00a6cc36-796d-4d87-9540-94df32fe5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855649912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.855649912
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3165828930
Short name T347
Test name
Test status
Simulation time 114355769 ps
CPU time 2.56 seconds
Started May 18 04:11:36 PM PDT 24
Finished May 18 04:11:40 PM PDT 24
Peak memory 206400 kb
Host smart-e7525093-d2ee-46d4-8a5e-edf1dca15c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165828930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3165828930
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.252358638
Short name T832
Test name
Test status
Simulation time 114362143 ps
CPU time 2.83 seconds
Started May 18 04:11:39 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 208152 kb
Host smart-47a95bdc-77b4-4507-82e5-3de927d4826a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252358638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.252358638
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2747192794
Short name T376
Test name
Test status
Simulation time 4009525614 ps
CPU time 46.38 seconds
Started May 18 04:11:39 PM PDT 24
Finished May 18 04:12:27 PM PDT 24
Peak memory 207844 kb
Host smart-211e3e4d-6518-4b0c-88a8-4e5975e10d56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747192794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2747192794
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.311832333
Short name T933
Test name
Test status
Simulation time 467423371 ps
CPU time 3.68 seconds
Started May 18 04:11:39 PM PDT 24
Finished May 18 04:11:44 PM PDT 24
Peak memory 208236 kb
Host smart-d2210037-ce1b-41a6-84df-3245ab84f3ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311832333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.311832333
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3502627644
Short name T549
Test name
Test status
Simulation time 286618086 ps
CPU time 2.66 seconds
Started May 18 04:11:36 PM PDT 24
Finished May 18 04:11:40 PM PDT 24
Peak memory 208488 kb
Host smart-e2585385-0529-44f9-93a4-b65da61a2f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502627644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3502627644
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1668561367
Short name T1046
Test name
Test status
Simulation time 164314284 ps
CPU time 5.31 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:11:44 PM PDT 24
Peak memory 208136 kb
Host smart-3ce03715-3070-4f8a-8e71-53cee8410caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668561367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1668561367
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1647148689
Short name T204
Test name
Test status
Simulation time 272526074 ps
CPU time 11.08 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:11:49 PM PDT 24
Peak memory 222372 kb
Host smart-e195d73e-8661-4660-abce-d957350491ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647148689 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1647148689
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2115783296
Short name T981
Test name
Test status
Simulation time 66975934 ps
CPU time 2.48 seconds
Started May 18 04:11:42 PM PDT 24
Finished May 18 04:11:45 PM PDT 24
Peak memory 207704 kb
Host smart-c2693954-8e3e-47cf-86ff-5498d9412114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115783296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2115783296
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3616284852
Short name T108
Test name
Test status
Simulation time 97340579 ps
CPU time 2.25 seconds
Started May 18 04:11:38 PM PDT 24
Finished May 18 04:11:41 PM PDT 24
Peak memory 209528 kb
Host smart-c56ac149-e02f-4fe5-a63e-38157122cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616284852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3616284852
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3794427485
Short name T605
Test name
Test status
Simulation time 54047902 ps
CPU time 0.79 seconds
Started May 18 04:11:55 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 205528 kb
Host smart-27517a13-5d5b-4ccb-a7f7-a10bb103e122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794427485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3794427485
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.456127987
Short name T265
Test name
Test status
Simulation time 321840635 ps
CPU time 6.24 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:55 PM PDT 24
Peak memory 215072 kb
Host smart-1e37e70f-b083-4a6a-9063-58c5d0fbae8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456127987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.456127987
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3678868821
Short name T305
Test name
Test status
Simulation time 284366229 ps
CPU time 8.58 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 218112 kb
Host smart-d2bdbc0b-e9f9-47a7-a374-8663649641f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678868821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3678868821
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3023338120
Short name T251
Test name
Test status
Simulation time 810156929 ps
CPU time 6.44 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 213948 kb
Host smart-c4d53d34-575e-4e4c-85f7-23457be03963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023338120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3023338120
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1959526429
Short name T331
Test name
Test status
Simulation time 40832987 ps
CPU time 3.13 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:00 PM PDT 24
Peak memory 209240 kb
Host smart-6b908793-4a5a-46dd-8b83-3cc9e91dba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959526429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1959526429
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.551601887
Short name T672
Test name
Test status
Simulation time 317709150 ps
CPU time 2.92 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 214064 kb
Host smart-95836ceb-42da-4acf-a6cd-20253df97922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551601887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.551601887
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1761602663
Short name T333
Test name
Test status
Simulation time 2786791735 ps
CPU time 18.94 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 214112 kb
Host smart-ca814902-1140-4544-a7c5-051ee2af7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761602663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1761602663
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.778148960
Short name T222
Test name
Test status
Simulation time 147860543 ps
CPU time 2.48 seconds
Started May 18 04:11:38 PM PDT 24
Finished May 18 04:11:42 PM PDT 24
Peak memory 206564 kb
Host smart-5221a450-54d2-40ca-89b9-e72139aeba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778148960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.778148960
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.744427703
Short name T875
Test name
Test status
Simulation time 1458816970 ps
CPU time 35.86 seconds
Started May 18 04:11:37 PM PDT 24
Finished May 18 04:12:14 PM PDT 24
Peak memory 208188 kb
Host smart-50d5e370-2393-44b8-a340-97d168c9c84e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744427703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.744427703
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.392289808
Short name T579
Test name
Test status
Simulation time 1624835353 ps
CPU time 39.92 seconds
Started May 18 04:11:38 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 207764 kb
Host smart-2dd8fc33-8807-40fc-830d-7d5b79253b76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392289808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.392289808
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.870240565
Short name T553
Test name
Test status
Simulation time 126023160 ps
CPU time 4.88 seconds
Started May 18 04:11:41 PM PDT 24
Finished May 18 04:11:47 PM PDT 24
Peak memory 208268 kb
Host smart-7e5ec62b-36db-4285-833f-1d587bc051d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870240565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.870240565
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2260690267
Short name T1003
Test name
Test status
Simulation time 279251639 ps
CPU time 2.46 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 208452 kb
Host smart-a357f784-122b-4d58-aeca-6e6780cb08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260690267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2260690267
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3720313514
Short name T1053
Test name
Test status
Simulation time 63743148 ps
CPU time 2.98 seconds
Started May 18 04:11:39 PM PDT 24
Finished May 18 04:11:43 PM PDT 24
Peak memory 208252 kb
Host smart-2f124596-751d-408e-b38c-7bf6b5184e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720313514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3720313514
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1604681405
Short name T105
Test name
Test status
Simulation time 414534365 ps
CPU time 19.64 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:12:09 PM PDT 24
Peak memory 215032 kb
Host smart-dfef72a2-d78f-4cb8-afdd-3d018bcf6367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604681405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1604681405
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3425252838
Short name T695
Test name
Test status
Simulation time 173315148 ps
CPU time 4.81 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 219736 kb
Host smart-ed225d02-cc66-46d4-a038-58cd902107cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425252838 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3425252838
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.851899076
Short name T919
Test name
Test status
Simulation time 201640855 ps
CPU time 4.8 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 207332 kb
Host smart-a5d24c52-a0f8-4c8c-8be7-57ac28ca8ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851899076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.851899076
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.302188270
Short name T48
Test name
Test status
Simulation time 71085906 ps
CPU time 2.16 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:11:49 PM PDT 24
Peak memory 209744 kb
Host smart-e7a1eeaa-a60f-417c-8609-7485ce9535da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302188270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.302188270
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.174941079
Short name T939
Test name
Test status
Simulation time 14441305 ps
CPU time 0.75 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:46 PM PDT 24
Peak memory 205544 kb
Host smart-2be7e58c-0198-402c-b4b3-80d203bd96b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174941079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.174941079
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2715977087
Short name T405
Test name
Test status
Simulation time 301068991 ps
CPU time 8.65 seconds
Started May 18 04:11:56 PM PDT 24
Finished May 18 04:12:06 PM PDT 24
Peak memory 214928 kb
Host smart-ed542fec-6dfa-46ab-b081-b1cfb7150aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715977087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2715977087
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3851913061
Short name T243
Test name
Test status
Simulation time 28088946 ps
CPU time 1.82 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:47 PM PDT 24
Peak memory 207012 kb
Host smart-ac1f0199-ba09-42d8-af50-6ed6cfd8c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851913061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3851913061
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.196304661
Short name T837
Test name
Test status
Simulation time 892287037 ps
CPU time 3.64 seconds
Started May 18 04:11:48 PM PDT 24
Finished May 18 04:11:53 PM PDT 24
Peak memory 214180 kb
Host smart-4af450fd-77d9-4c66-86b7-f534778414eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196304661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.196304661
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1042280467
Short name T229
Test name
Test status
Simulation time 57749348 ps
CPU time 3.2 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 222148 kb
Host smart-61cc5221-930e-46dd-b2f9-8ecadf9d007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042280467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1042280467
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.2777490872
Short name T189
Test name
Test status
Simulation time 75595015 ps
CPU time 3.78 seconds
Started May 18 04:11:48 PM PDT 24
Finished May 18 04:11:54 PM PDT 24
Peak memory 206984 kb
Host smart-106fe1c1-a1fd-4231-972e-e33eb1909234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777490872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2777490872
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4071177318
Short name T578
Test name
Test status
Simulation time 217031548 ps
CPU time 3.82 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:53 PM PDT 24
Peak memory 206496 kb
Host smart-869bc66d-105a-48b8-87b2-114122c987ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071177318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4071177318
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.434182595
Short name T896
Test name
Test status
Simulation time 498460600 ps
CPU time 3 seconds
Started May 18 04:11:48 PM PDT 24
Finished May 18 04:11:53 PM PDT 24
Peak memory 206420 kb
Host smart-106e3444-2eaf-4fca-a8ce-5b4b0919f63c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434182595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.434182595
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.44621364
Short name T551
Test name
Test status
Simulation time 233446078 ps
CPU time 3.24 seconds
Started May 18 04:11:46 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 208180 kb
Host smart-188b5d74-3c1a-4975-861a-6b95e49de94a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44621364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.44621364
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3251176223
Short name T772
Test name
Test status
Simulation time 189387817 ps
CPU time 2.8 seconds
Started May 18 04:11:48 PM PDT 24
Finished May 18 04:11:53 PM PDT 24
Peak memory 207856 kb
Host smart-feb42ad7-c286-4d26-a33c-16243c7e504b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251176223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3251176223
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2051188406
Short name T1001
Test name
Test status
Simulation time 22018361 ps
CPU time 1.66 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:48 PM PDT 24
Peak memory 207036 kb
Host smart-92f9ddec-00aa-4f42-b339-8bad87314370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051188406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2051188406
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2871967182
Short name T563
Test name
Test status
Simulation time 79147280 ps
CPU time 2.71 seconds
Started May 18 04:11:48 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 206372 kb
Host smart-8743beff-348a-4f86-aa76-e0df3cfa635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871967182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2871967182
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2413420954
Short name T716
Test name
Test status
Simulation time 1816794008 ps
CPU time 29.16 seconds
Started May 18 04:11:42 PM PDT 24
Finished May 18 04:12:12 PM PDT 24
Peak memory 214764 kb
Host smart-931ebe91-fb00-443e-a938-59559d684f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413420954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2413420954
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1525201642
Short name T580
Test name
Test status
Simulation time 147322608 ps
CPU time 3.62 seconds
Started May 18 04:11:46 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 218348 kb
Host smart-8b3da6af-36cf-42c5-a6c7-732d2ea5e769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525201642 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1525201642
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2534670223
Short name T863
Test name
Test status
Simulation time 1323065471 ps
CPU time 30.81 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:12:25 PM PDT 24
Peak memory 213996 kb
Host smart-67d1d8ac-e7cd-4788-8a07-146ba45ed770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534670223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2534670223
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3874049419
Short name T36
Test name
Test status
Simulation time 129978490 ps
CPU time 2.62 seconds
Started May 18 04:11:43 PM PDT 24
Finished May 18 04:11:46 PM PDT 24
Peak memory 209752 kb
Host smart-c16e7cfa-482f-4cf3-8aa0-61ea284939f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874049419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3874049419
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2575143656
Short name T936
Test name
Test status
Simulation time 187631344 ps
CPU time 0.97 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 205772 kb
Host smart-ab8c0271-1a52-42e8-bbc3-7e3a10ece58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575143656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2575143656
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3439859730
Short name T261
Test name
Test status
Simulation time 40314073 ps
CPU time 2.79 seconds
Started May 18 04:11:47 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 214344 kb
Host smart-ea264d7f-5800-4eb3-8100-3aed0a035dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439859730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3439859730
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.146324550
Short name T71
Test name
Test status
Simulation time 80512254 ps
CPU time 3.28 seconds
Started May 18 04:11:46 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 213960 kb
Host smart-d1a4e385-256a-4063-b6f9-215efdf68884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146324550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.146324550
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3980758846
Short name T787
Test name
Test status
Simulation time 2831837264 ps
CPU time 26.59 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 214040 kb
Host smart-157e12a5-3e67-4df6-a1b7-7d77c78312d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980758846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3980758846
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1854006523
Short name T246
Test name
Test status
Simulation time 60856144 ps
CPU time 3.51 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 211220 kb
Host smart-5aef61d5-0559-45ba-9d13-f092e419f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854006523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1854006523
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3789936869
Short name T854
Test name
Test status
Simulation time 59723033 ps
CPU time 3.66 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 210116 kb
Host smart-02cc15c1-007b-4e9e-bf85-ee08d53040b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789936869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3789936869
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2745716785
Short name T757
Test name
Test status
Simulation time 399907758 ps
CPU time 7.45 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:11:54 PM PDT 24
Peak memory 214000 kb
Host smart-f078f9ef-51d7-4222-b63f-fbd35ec3b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745716785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2745716785
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3290748826
Short name T1043
Test name
Test status
Simulation time 3949073438 ps
CPU time 16.97 seconds
Started May 18 04:11:45 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 208436 kb
Host smart-4956ad40-92aa-4693-9bd5-61ffa71805f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290748826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3290748826
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2219191573
Short name T636
Test name
Test status
Simulation time 26106598 ps
CPU time 2.16 seconds
Started May 18 04:11:46 PM PDT 24
Finished May 18 04:11:51 PM PDT 24
Peak memory 208328 kb
Host smart-ca298f72-0f88-4fba-96c7-ffa265d8ad67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219191573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2219191573
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.159527651
Short name T675
Test name
Test status
Simulation time 1030219346 ps
CPU time 13.09 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 207552 kb
Host smart-050518fa-4913-415a-8e21-02154bd232eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159527651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.159527651
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2288255596
Short name T294
Test name
Test status
Simulation time 239708336 ps
CPU time 6.43 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:52 PM PDT 24
Peak memory 207616 kb
Host smart-6dbbcecc-f774-482b-a3d2-18b13f423eb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288255596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2288255596
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1076375208
Short name T986
Test name
Test status
Simulation time 5117128141 ps
CPU time 13.95 seconds
Started May 18 04:11:56 PM PDT 24
Finished May 18 04:12:12 PM PDT 24
Peak memory 214072 kb
Host smart-0a56e34c-5895-4c8c-9ad3-8fafc39f0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076375208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1076375208
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.673779314
Short name T377
Test name
Test status
Simulation time 808836170 ps
CPU time 3.38 seconds
Started May 18 04:11:44 PM PDT 24
Finished May 18 04:11:48 PM PDT 24
Peak memory 208248 kb
Host smart-b5d23886-3a52-4a33-93a7-80b67a4ffd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673779314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.673779314
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1657334490
Short name T957
Test name
Test status
Simulation time 1067864981 ps
CPU time 16.55 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:13 PM PDT 24
Peak memory 222352 kb
Host smart-f63623b9-3fbd-41de-be1f-b5d0652d2850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657334490 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1657334490
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3978899049
Short name T634
Test name
Test status
Simulation time 195771207 ps
CPU time 4.76 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:12:00 PM PDT 24
Peak memory 210192 kb
Host smart-fac724f6-e2fe-46c6-8224-7ef4d1a70ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978899049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3978899049
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3543397358
Short name T670
Test name
Test status
Simulation time 133891612 ps
CPU time 3.15 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:59 PM PDT 24
Peak memory 210644 kb
Host smart-7652b3cf-f778-4b81-bd81-946b293fd7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543397358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3543397358
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.4172467625
Short name T800
Test name
Test status
Simulation time 57008704 ps
CPU time 0.79 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:11:53 PM PDT 24
Peak memory 205548 kb
Host smart-d94e0460-d843-439e-ab35-342a32c53fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172467625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.4172467625
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1899143293
Short name T1035
Test name
Test status
Simulation time 78230615 ps
CPU time 2.34 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 214480 kb
Host smart-202b0e59-365d-4fbd-b24b-001750a0fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899143293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1899143293
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2994663044
Short name T734
Test name
Test status
Simulation time 85964683 ps
CPU time 3.56 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:11:55 PM PDT 24
Peak memory 208632 kb
Host smart-59d770aa-c618-4f78-9b9b-86e1dff6d4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994663044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2994663044
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3595439417
Short name T929
Test name
Test status
Simulation time 75546161 ps
CPU time 3.38 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:59 PM PDT 24
Peak memory 209192 kb
Host smart-3f307b13-0d02-42f6-b0f0-aea370305e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595439417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3595439417
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2248384892
Short name T185
Test name
Test status
Simulation time 203571434 ps
CPU time 3.87 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 222128 kb
Host smart-59cd1a5a-4244-4f9c-83ba-5dfdab7cd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248384892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2248384892
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.590844949
Short name T50
Test name
Test status
Simulation time 138504541 ps
CPU time 2.6 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 218368 kb
Host smart-3b032e1e-a23f-447f-8c2d-72b4ad24bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590844949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.590844949
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.545397325
Short name T233
Test name
Test status
Simulation time 276928640 ps
CPU time 7.81 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 209020 kb
Host smart-bfdb5a95-3e4b-42fb-b98a-3601f7f56a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545397325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.545397325
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2934721930
Short name T76
Test name
Test status
Simulation time 989638308 ps
CPU time 6.34 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 207804 kb
Host smart-d991f409-dd3f-428d-a691-115967a6e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934721930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2934721930
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1575099190
Short name T567
Test name
Test status
Simulation time 567820161 ps
CPU time 9.4 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 207644 kb
Host smart-38ce18c7-33a4-435a-9ce0-ae2e2e879ea2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575099190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1575099190
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3287546337
Short name T930
Test name
Test status
Simulation time 80396069 ps
CPU time 2.43 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 206588 kb
Host smart-06336781-a551-4fed-8f39-1f588f2c266b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287546337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3287546337
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1848128553
Short name T1000
Test name
Test status
Simulation time 318894321 ps
CPU time 3.76 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:12:00 PM PDT 24
Peak memory 208684 kb
Host smart-4cd6d60a-25db-40bb-be8f-3483a10f5ea4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848128553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1848128553
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.439083139
Short name T991
Test name
Test status
Simulation time 601792924 ps
CPU time 4.84 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 209320 kb
Host smart-187563c6-6a58-4334-a5a9-1c515eb59458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439083139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.439083139
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.494687946
Short name T1055
Test name
Test status
Simulation time 144411830 ps
CPU time 2.56 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 208104 kb
Host smart-791ac904-5b46-43ae-b337-709c7860f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494687946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.494687946
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1695482707
Short name T334
Test name
Test status
Simulation time 520428542 ps
CPU time 9.62 seconds
Started May 18 04:11:50 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 220472 kb
Host smart-43e0451b-a042-44a7-92db-eaf5297160ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695482707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1695482707
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2923210145
Short name T931
Test name
Test status
Simulation time 239663929 ps
CPU time 3.99 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 218136 kb
Host smart-6fde17fd-8525-4785-87bd-69d3676c4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923210145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2923210145
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1122585913
Short name T49
Test name
Test status
Simulation time 51546651 ps
CPU time 2.42 seconds
Started May 18 04:11:53 PM PDT 24
Finished May 18 04:11:58 PM PDT 24
Peak memory 209912 kb
Host smart-5380f30f-7063-4d6f-852d-994199e00c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122585913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1122585913
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3324210485
Short name T871
Test name
Test status
Simulation time 14490728 ps
CPU time 0.96 seconds
Started May 18 04:12:00 PM PDT 24
Finished May 18 04:12:02 PM PDT 24
Peak memory 205772 kb
Host smart-53fa8bef-32b7-4711-afe6-bad7ec0a9da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324210485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3324210485
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1653846489
Short name T27
Test name
Test status
Simulation time 961327908 ps
CPU time 10.93 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 214372 kb
Host smart-90214356-954c-43ba-a983-8739f6c95f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653846489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1653846489
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.687862974
Short name T54
Test name
Test status
Simulation time 354556541 ps
CPU time 3.84 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 219432 kb
Host smart-8af998b1-e605-482b-8c2b-e73a55f3a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687862974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.687862974
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.549441221
Short name T845
Test name
Test status
Simulation time 4718794285 ps
CPU time 47.04 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 214000 kb
Host smart-1a2975b4-5016-41c5-96ec-5d59e74da6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549441221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.549441221
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.761055826
Short name T307
Test name
Test status
Simulation time 294166813 ps
CPU time 5.31 seconds
Started May 18 04:12:00 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 222104 kb
Host smart-17d73621-ee0f-4f0e-a4fe-3f7a396acbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761055826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.761055826
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1322569992
Short name T759
Test name
Test status
Simulation time 93050674 ps
CPU time 4.74 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:05 PM PDT 24
Peak memory 209912 kb
Host smart-78a7d9d6-259a-4706-941f-ead430c3a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322569992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1322569992
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1730471595
Short name T722
Test name
Test status
Simulation time 153889744 ps
CPU time 5.04 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:05 PM PDT 24
Peak memory 207036 kb
Host smart-10aa36a6-6dc3-44f7-8852-e16a399cf385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730471595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1730471595
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3158435893
Short name T332
Test name
Test status
Simulation time 380623260 ps
CPU time 8.66 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 208464 kb
Host smart-2a9dd282-c694-44d2-8c68-5480ac061e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158435893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3158435893
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3000907507
Short name T705
Test name
Test status
Simulation time 699435808 ps
CPU time 5.34 seconds
Started May 18 04:11:52 PM PDT 24
Finished May 18 04:12:01 PM PDT 24
Peak memory 207692 kb
Host smart-fa058686-b6e7-4463-a222-57e965086cab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000907507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3000907507
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2194982919
Short name T349
Test name
Test status
Simulation time 119706610 ps
CPU time 3.96 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:05 PM PDT 24
Peak memory 208388 kb
Host smart-bf18fa94-b15b-460c-9d85-8f036fa8ba01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194982919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2194982919
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3488767668
Short name T743
Test name
Test status
Simulation time 525737304 ps
CPU time 6.2 seconds
Started May 18 04:12:02 PM PDT 24
Finished May 18 04:12:09 PM PDT 24
Peak memory 217992 kb
Host smart-7f2321d2-c8e9-43f4-9d4f-2d134a648299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488767668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3488767668
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3353359016
Short name T906
Test name
Test status
Simulation time 38697248 ps
CPU time 2.24 seconds
Started May 18 04:11:51 PM PDT 24
Finished May 18 04:11:57 PM PDT 24
Peak memory 206536 kb
Host smart-7058d749-92eb-4c54-98d3-beabd295105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353359016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3353359016
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.943566876
Short name T860
Test name
Test status
Simulation time 59784227 ps
CPU time 3.74 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 207680 kb
Host smart-477bdae6-653f-4202-a3a8-d92b7f16ca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943566876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.943566876
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2925990849
Short name T147
Test name
Test status
Simulation time 131097226 ps
CPU time 1.8 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:01 PM PDT 24
Peak memory 209628 kb
Host smart-3aa3b876-844c-418b-b5f5-bf55cf481bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925990849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2925990849
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.892324846
Short name T652
Test name
Test status
Simulation time 7683440 ps
CPU time 0.73 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:08 PM PDT 24
Peak memory 205580 kb
Host smart-ac3fa86c-b34a-497a-ad62-76b56e8f9422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892324846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.892324846
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1317197573
Short name T413
Test name
Test status
Simulation time 80691219 ps
CPU time 2.72 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 214668 kb
Host smart-ce6cf04d-4038-44e4-801d-23ff8f2bb6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317197573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1317197573
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3276112563
Short name T978
Test name
Test status
Simulation time 617831109 ps
CPU time 2.31 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 222592 kb
Host smart-ff9a165e-cf44-4ce3-9a53-104dbe284860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276112563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3276112563
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3659429100
Short name T1012
Test name
Test status
Simulation time 43426831 ps
CPU time 2.95 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 214016 kb
Host smart-d5004728-00e7-4edd-b019-0b454b094ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659429100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3659429100
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2295240265
Short name T599
Test name
Test status
Simulation time 1567884012 ps
CPU time 4.87 seconds
Started May 18 04:12:00 PM PDT 24
Finished May 18 04:12:06 PM PDT 24
Peak memory 207840 kb
Host smart-c433ab75-e0aa-438f-87ac-d59e61ffafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295240265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2295240265
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2715631748
Short name T103
Test name
Test status
Simulation time 63814123 ps
CPU time 4.19 seconds
Started May 18 04:12:01 PM PDT 24
Finished May 18 04:12:06 PM PDT 24
Peak memory 222100 kb
Host smart-1815ec47-eb1a-4b38-989c-afb604109dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715631748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2715631748
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2588098113
Short name T241
Test name
Test status
Simulation time 58389255 ps
CPU time 3.53 seconds
Started May 18 04:12:03 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 207568 kb
Host smart-f5fede92-b9fc-4c79-bce0-025f4e046d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588098113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2588098113
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3324751569
Short name T903
Test name
Test status
Simulation time 225870737 ps
CPU time 4.98 seconds
Started May 18 04:12:02 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 206376 kb
Host smart-bcec750c-8307-4257-8cd8-2c2e6b8f82dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324751569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3324751569
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.641970559
Short name T668
Test name
Test status
Simulation time 137683942 ps
CPU time 2.64 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:02 PM PDT 24
Peak memory 208244 kb
Host smart-36c8ca68-ff20-4f3c-866e-49dd3e9e6f7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641970559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.641970559
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3296975081
Short name T302
Test name
Test status
Simulation time 64892901 ps
CPU time 3.4 seconds
Started May 18 04:12:03 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 207196 kb
Host smart-5aea5e1b-3781-4ca4-9f96-db487aff3017
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296975081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3296975081
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1615418679
Short name T805
Test name
Test status
Simulation time 173323890 ps
CPU time 3.41 seconds
Started May 18 04:11:58 PM PDT 24
Finished May 18 04:12:03 PM PDT 24
Peak memory 206600 kb
Host smart-e5138211-49ab-45c9-a2bf-7b83cdcf14b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615418679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1615418679
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1877709649
Short name T977
Test name
Test status
Simulation time 922822293 ps
CPU time 5.19 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:12 PM PDT 24
Peak memory 220228 kb
Host smart-c8e761f7-8954-4589-8506-4aeb23305054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877709649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1877709649
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3055023922
Short name T808
Test name
Test status
Simulation time 71213962 ps
CPU time 3.37 seconds
Started May 18 04:12:00 PM PDT 24
Finished May 18 04:12:04 PM PDT 24
Peak memory 206736 kb
Host smart-f160b67a-17ab-4786-a3eb-ead8700eef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055023922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3055023922
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3330617089
Short name T833
Test name
Test status
Simulation time 816984028 ps
CPU time 27.43 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 215336 kb
Host smart-53f0c074-090a-4338-b4fa-5be7d55a71c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330617089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3330617089
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3168092105
Short name T206
Test name
Test status
Simulation time 85562866 ps
CPU time 6.46 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:14 PM PDT 24
Peak memory 219492 kb
Host smart-406fadc0-fed9-44a9-a1b4-20afe9e3b1d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168092105 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3168092105
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4224476046
Short name T121
Test name
Test status
Simulation time 97691177 ps
CPU time 4.98 seconds
Started May 18 04:11:59 PM PDT 24
Finished May 18 04:12:05 PM PDT 24
Peak memory 209132 kb
Host smart-234ffcad-247e-4135-bed1-6882a61b5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224476046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4224476046
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3138205836
Short name T393
Test name
Test status
Simulation time 110469789 ps
CPU time 1.78 seconds
Started May 18 04:12:07 PM PDT 24
Finished May 18 04:12:09 PM PDT 24
Peak memory 209808 kb
Host smart-1c108240-cda8-4c17-be11-89d6433b2c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138205836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3138205836
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1255506781
Short name T1021
Test name
Test status
Simulation time 17149161 ps
CPU time 0.8 seconds
Started May 18 04:10:07 PM PDT 24
Finished May 18 04:10:09 PM PDT 24
Peak memory 205496 kb
Host smart-540e27ff-6311-4f86-ab87-a51ead6e9164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255506781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1255506781
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4187107272
Short name T406
Test name
Test status
Simulation time 1158595169 ps
CPU time 63.6 seconds
Started May 18 04:10:06 PM PDT 24
Finished May 18 04:11:10 PM PDT 24
Peak memory 215136 kb
Host smart-070ad0db-cd30-45e1-8cb9-ee1c6cc88f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187107272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4187107272
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2032044212
Short name T321
Test name
Test status
Simulation time 229773214 ps
CPU time 3.13 seconds
Started May 18 04:10:07 PM PDT 24
Finished May 18 04:10:10 PM PDT 24
Peak memory 207240 kb
Host smart-414f1988-c2ba-4bda-89d4-0e881a2398d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032044212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2032044212
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3382945201
Short name T353
Test name
Test status
Simulation time 5148432693 ps
CPU time 93.78 seconds
Started May 18 04:10:10 PM PDT 24
Finished May 18 04:11:45 PM PDT 24
Peak memory 223956 kb
Host smart-27d40c44-1cdf-4f52-a8cd-0ec02f52cacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382945201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3382945201
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.47259784
Short name T846
Test name
Test status
Simulation time 115827586 ps
CPU time 4.67 seconds
Started May 18 04:10:04 PM PDT 24
Finished May 18 04:10:10 PM PDT 24
Peak memory 214064 kb
Host smart-38f0ba25-32bf-4fac-b7fa-ca65abccba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47259784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.47259784
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2903018828
Short name T900
Test name
Test status
Simulation time 1373120349 ps
CPU time 15.5 seconds
Started May 18 04:10:08 PM PDT 24
Finished May 18 04:10:24 PM PDT 24
Peak memory 218092 kb
Host smart-2a2dad10-f07f-4971-972a-5de881fbdeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903018828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2903018828
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3464192437
Short name T14
Test name
Test status
Simulation time 39202397122 ps
CPU time 371.01 seconds
Started May 18 04:10:08 PM PDT 24
Finished May 18 04:16:20 PM PDT 24
Peak memory 308404 kb
Host smart-50b1b3e4-a75c-417d-8112-5d63972ebfb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464192437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3464192437
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3918235667
Short name T378
Test name
Test status
Simulation time 685021881 ps
CPU time 11.84 seconds
Started May 18 04:10:05 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 207980 kb
Host smart-2354cd8a-92cb-4a9c-af32-116af0f484b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918235667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3918235667
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4145883820
Short name T640
Test name
Test status
Simulation time 927397830 ps
CPU time 6.42 seconds
Started May 18 04:10:04 PM PDT 24
Finished May 18 04:10:10 PM PDT 24
Peak memory 206456 kb
Host smart-c07c1a30-5d0d-4889-8602-9bdb08542228
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145883820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4145883820
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1607266616
Short name T556
Test name
Test status
Simulation time 30900183 ps
CPU time 2.04 seconds
Started May 18 04:10:05 PM PDT 24
Finished May 18 04:10:08 PM PDT 24
Peak memory 208152 kb
Host smart-47e07697-467b-469f-8521-c38e547ada11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607266616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1607266616
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4019268472
Short name T792
Test name
Test status
Simulation time 122518752 ps
CPU time 2.5 seconds
Started May 18 04:10:10 PM PDT 24
Finished May 18 04:10:13 PM PDT 24
Peak memory 206896 kb
Host smart-90a41789-881c-45f2-915d-fe9d8234dd15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019268472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4019268472
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2626217292
Short name T1015
Test name
Test status
Simulation time 98253302 ps
CPU time 2.96 seconds
Started May 18 04:10:05 PM PDT 24
Finished May 18 04:10:09 PM PDT 24
Peak memory 206896 kb
Host smart-e227b243-9e96-485b-95fe-3f5d00791d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626217292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2626217292
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2007849519
Short name T1
Test name
Test status
Simulation time 1032425078 ps
CPU time 10.11 seconds
Started May 18 04:10:06 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 208000 kb
Host smart-0000c84a-4255-483d-bccc-c753cfe19da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007849519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2007849519
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.194893095
Short name T409
Test name
Test status
Simulation time 103393042 ps
CPU time 4.92 seconds
Started May 18 04:10:09 PM PDT 24
Finished May 18 04:10:15 PM PDT 24
Peak memory 220980 kb
Host smart-5d203798-c654-4b31-88eb-f8d199182040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194893095 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.194893095
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.311349374
Short name T762
Test name
Test status
Simulation time 59822128 ps
CPU time 3.17 seconds
Started May 18 04:10:04 PM PDT 24
Finished May 18 04:10:08 PM PDT 24
Peak memory 207392 kb
Host smart-e78ffffa-3877-49c6-8ff4-d5bd446d23e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311349374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.311349374
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3983353065
Short name T146
Test name
Test status
Simulation time 1111793953 ps
CPU time 22.49 seconds
Started May 18 04:10:05 PM PDT 24
Finished May 18 04:10:28 PM PDT 24
Peak memory 210596 kb
Host smart-774ed5bb-0b34-48c7-adb0-0fcc4ec285c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983353065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3983353065
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2699874510
Short name T971
Test name
Test status
Simulation time 57749598 ps
CPU time 0.82 seconds
Started May 18 04:12:12 PM PDT 24
Finished May 18 04:12:14 PM PDT 24
Peak memory 205592 kb
Host smart-3031e9ec-f071-4751-84fd-103777b78ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699874510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2699874510
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1665907457
Short name T660
Test name
Test status
Simulation time 156753196 ps
CPU time 4.59 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:11 PM PDT 24
Peak memory 207732 kb
Host smart-fd0554cb-45b7-4f83-b939-9147ab98862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665907457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1665907457
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3346796525
Short name T609
Test name
Test status
Simulation time 1908234910 ps
CPU time 4.97 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 217752 kb
Host smart-29353351-a857-498a-83b7-940509471f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346796525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3346796525
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.930822855
Short name T355
Test name
Test status
Simulation time 524325132 ps
CPU time 9.32 seconds
Started May 18 04:12:11 PM PDT 24
Finished May 18 04:12:21 PM PDT 24
Peak memory 214048 kb
Host smart-b9add1f0-01f9-40e3-9449-fdebaa1a5043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930822855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.930822855
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1672730698
Short name T245
Test name
Test status
Simulation time 391947623 ps
CPU time 5.37 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:11 PM PDT 24
Peak memory 213920 kb
Host smart-d01706ab-67ce-493e-a98d-b64676d0f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672730698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1672730698
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3091134184
Short name T208
Test name
Test status
Simulation time 442234472 ps
CPU time 6.41 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:13 PM PDT 24
Peak memory 214000 kb
Host smart-e5328699-a555-42a4-b934-95dd1d5b9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091134184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3091134184
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.169866140
Short name T749
Test name
Test status
Simulation time 1675993031 ps
CPU time 5.64 seconds
Started May 18 04:12:05 PM PDT 24
Finished May 18 04:12:12 PM PDT 24
Peak memory 206912 kb
Host smart-e5af8247-f098-4ff2-892b-72454024d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169866140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.169866140
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.179266970
Short name T195
Test name
Test status
Simulation time 395009807 ps
CPU time 9.77 seconds
Started May 18 04:12:11 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 207428 kb
Host smart-5ae771f8-53fd-45ef-8d30-ac05460d22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179266970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.179266970
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3782283768
Short name T418
Test name
Test status
Simulation time 60792224 ps
CPU time 3.13 seconds
Started May 18 04:12:07 PM PDT 24
Finished May 18 04:12:11 PM PDT 24
Peak memory 206468 kb
Host smart-f2ffc183-734d-4e2b-9bc0-3350d6787347
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782283768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3782283768
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3743390292
Short name T983
Test name
Test status
Simulation time 2201629008 ps
CPU time 15.4 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:21 PM PDT 24
Peak memory 207840 kb
Host smart-dc8fc606-73f7-4948-8727-cb816dd72285
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743390292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3743390292
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1035343719
Short name T746
Test name
Test status
Simulation time 40711002 ps
CPU time 1.93 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 206920 kb
Host smart-d17d4bb6-b826-4689-aa5b-56186f194af2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035343719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1035343719
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3593670196
Short name T359
Test name
Test status
Simulation time 140220114 ps
CPU time 2.51 seconds
Started May 18 04:12:06 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 217912 kb
Host smart-f8aa63f4-415d-445d-9ece-9979e3b64b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593670196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3593670196
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1012915168
Short name T859
Test name
Test status
Simulation time 837860052 ps
CPU time 15.65 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:21 PM PDT 24
Peak memory 208304 kb
Host smart-7c98d3e6-83fa-4821-a7db-d086d89d523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012915168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1012915168
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2211843581
Short name T877
Test name
Test status
Simulation time 69200456 ps
CPU time 4.5 seconds
Started May 18 04:12:11 PM PDT 24
Finished May 18 04:12:16 PM PDT 24
Peak memory 218348 kb
Host smart-0b42b7db-55ec-4259-954b-2dc5bf2391a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211843581 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2211843581
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4026623177
Short name T327
Test name
Test status
Simulation time 1622723092 ps
CPU time 10.84 seconds
Started May 18 04:12:10 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 218344 kb
Host smart-8e83e40d-b487-4c1e-9ce8-d8d52010b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026623177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4026623177
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2391716978
Short name T1014
Test name
Test status
Simulation time 360346853 ps
CPU time 3.59 seconds
Started May 18 04:12:10 PM PDT 24
Finished May 18 04:12:15 PM PDT 24
Peak memory 209536 kb
Host smart-afda1189-4178-4b68-aa37-065e29f18c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391716978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2391716978
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1479026092
Short name T94
Test name
Test status
Simulation time 47399112 ps
CPU time 0.91 seconds
Started May 18 04:12:16 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 205784 kb
Host smart-2bcb53b2-a118-48f2-8631-3afc3d90fbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479026092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1479026092
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.977458290
Short name T407
Test name
Test status
Simulation time 284260118 ps
CPU time 14.6 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:30 PM PDT 24
Peak memory 214056 kb
Host smart-6a7a69ca-cba9-4a34-a78f-270216b210ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977458290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.977458290
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.31433830
Short name T994
Test name
Test status
Simulation time 178419721 ps
CPU time 3.37 seconds
Started May 18 04:12:19 PM PDT 24
Finished May 18 04:12:24 PM PDT 24
Peak memory 208480 kb
Host smart-33d0fe1a-cf07-4ada-9788-5e905115c67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31433830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.31433830
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3023835441
Short name T338
Test name
Test status
Simulation time 66915177 ps
CPU time 3.15 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 207576 kb
Host smart-69fc4e96-ed54-478f-91ae-8d7df0f86333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023835441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3023835441
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2317139080
Short name T91
Test name
Test status
Simulation time 855834989 ps
CPU time 26.59 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:12:44 PM PDT 24
Peak memory 214044 kb
Host smart-630abec2-77c1-4479-a448-8686b02fb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317139080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2317139080
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2718210288
Short name T955
Test name
Test status
Simulation time 685072273 ps
CPU time 3.36 seconds
Started May 18 04:12:16 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 219996 kb
Host smart-6ecc3cda-35a6-465b-b83a-a7735abb03bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718210288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2718210288
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1135686665
Short name T192
Test name
Test status
Simulation time 666540664 ps
CPU time 15.84 seconds
Started May 18 04:12:13 PM PDT 24
Finished May 18 04:12:30 PM PDT 24
Peak memory 218092 kb
Host smart-fbfa0f21-ca47-43f2-aab2-6cc359ac9fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135686665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1135686665
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3371747262
Short name T924
Test name
Test status
Simulation time 72432632 ps
CPU time 4 seconds
Started May 18 04:12:05 PM PDT 24
Finished May 18 04:12:10 PM PDT 24
Peak memory 208008 kb
Host smart-8458beca-2438-4deb-a672-fb9b5e9069af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371747262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3371747262
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2280670269
Short name T597
Test name
Test status
Simulation time 21658298 ps
CPU time 1.8 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:07 PM PDT 24
Peak memory 206440 kb
Host smart-57b6a4c9-aee9-4ce7-a712-b1379a9b88cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280670269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2280670269
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1412986236
Short name T348
Test name
Test status
Simulation time 62250215 ps
CPU time 2.31 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:21 PM PDT 24
Peak memory 206596 kb
Host smart-a4860ff2-d8a6-4c71-81cf-0cc343d55a9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412986236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1412986236
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3466923655
Short name T801
Test name
Test status
Simulation time 72267651 ps
CPU time 3.25 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 208260 kb
Host smart-6e1fbc40-7554-4bf4-888f-40af23c62c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466923655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3466923655
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.587736858
Short name T816
Test name
Test status
Simulation time 141246271 ps
CPU time 3.78 seconds
Started May 18 04:12:04 PM PDT 24
Finished May 18 04:12:09 PM PDT 24
Peak memory 206324 kb
Host smart-e9b2fefb-36d2-4121-8f19-540008614116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587736858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.587736858
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2049171840
Short name T260
Test name
Test status
Simulation time 880182357 ps
CPU time 33.03 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 222136 kb
Host smart-1f9e0e9b-e535-4d92-9616-0238cd1ada83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049171840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2049171840
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3598686350
Short name T1036
Test name
Test status
Simulation time 411476897 ps
CPU time 7.56 seconds
Started May 18 04:12:15 PM PDT 24
Finished May 18 04:12:24 PM PDT 24
Peak memory 219760 kb
Host smart-969883c0-1a5e-4add-82bc-d25013b08f29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598686350 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3598686350
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3863894885
Short name T227
Test name
Test status
Simulation time 364818282 ps
CPU time 4.56 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:24 PM PDT 24
Peak memory 208848 kb
Host smart-550cae8f-2357-48b3-b65b-55232bb10a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863894885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3863894885
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2640062918
Short name T669
Test name
Test status
Simulation time 104712753 ps
CPU time 2.99 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 209468 kb
Host smart-1e6cfee3-0571-473d-8f7c-2c31b2aac221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640062918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2640062918
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4070055395
Short name T879
Test name
Test status
Simulation time 23776824 ps
CPU time 0.91 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 205604 kb
Host smart-c573ea52-846e-4d12-b54c-8c74d9e55323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070055395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4070055395
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1042680154
Short name T262
Test name
Test status
Simulation time 81291080 ps
CPU time 4.24 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 214184 kb
Host smart-42fa472d-9db4-44ee-b4fa-f459b9b58c5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042680154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1042680154
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3924855255
Short name T813
Test name
Test status
Simulation time 326261354 ps
CPU time 2.67 seconds
Started May 18 04:12:19 PM PDT 24
Finished May 18 04:12:23 PM PDT 24
Peak memory 222520 kb
Host smart-28abc319-6ed4-4c4e-9031-ccad2e8c34c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924855255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3924855255
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2320317191
Short name T659
Test name
Test status
Simulation time 209076071 ps
CPU time 3.18 seconds
Started May 18 04:12:16 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 219324 kb
Host smart-9f58c30f-df38-4171-9cd6-40b45ec15bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320317191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2320317191
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3135396020
Short name T230
Test name
Test status
Simulation time 331485335 ps
CPU time 2.36 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 209124 kb
Host smart-3ce5e937-7510-4919-887f-143d37e9c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135396020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3135396020
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2655905275
Short name T200
Test name
Test status
Simulation time 249766651 ps
CPU time 2.99 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:18 PM PDT 24
Peak memory 215016 kb
Host smart-3fbffb5d-6b6e-4df7-b640-4f8bc3e386cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655905275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2655905275
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1425714236
Short name T269
Test name
Test status
Simulation time 2481564512 ps
CPU time 13.22 seconds
Started May 18 04:12:19 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 208496 kb
Host smart-cb629be8-0ad0-46be-98a3-4e326d769e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425714236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1425714236
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3779919554
Short name T870
Test name
Test status
Simulation time 58680328 ps
CPU time 2.9 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:12:21 PM PDT 24
Peak memory 206472 kb
Host smart-22df0af6-0836-4a0b-a299-a1640d942af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779919554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3779919554
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3880437386
Short name T282
Test name
Test status
Simulation time 121370249 ps
CPU time 3.42 seconds
Started May 18 04:12:16 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 208580 kb
Host smart-28a82c6b-1638-470d-bbd3-a69ffa830ea8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880437386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3880437386
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.20951552
Short name T1058
Test name
Test status
Simulation time 342654191 ps
CPU time 3.47 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 206580 kb
Host smart-3485074e-edf0-48ef-8b30-91be08560235
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.20951552
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2618139144
Short name T191
Test name
Test status
Simulation time 133201523 ps
CPU time 4.88 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:12:23 PM PDT 24
Peak memory 206672 kb
Host smart-c5ffa718-b60c-430b-b98a-e08e97fffe5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618139144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2618139144
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1016377863
Short name T238
Test name
Test status
Simulation time 2277020840 ps
CPU time 13.25 seconds
Started May 18 04:12:12 PM PDT 24
Finished May 18 04:12:27 PM PDT 24
Peak memory 209896 kb
Host smart-e8c552c4-b5a1-47af-a9ae-f72ea018da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016377863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1016377863
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2614103661
Short name T883
Test name
Test status
Simulation time 272610895 ps
CPU time 2.95 seconds
Started May 18 04:12:15 PM PDT 24
Finished May 18 04:12:19 PM PDT 24
Peak memory 207496 kb
Host smart-35bb61bd-f5df-4acb-86ec-15e200a5200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614103661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2614103661
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3939968995
Short name T637
Test name
Test status
Simulation time 236022314 ps
CPU time 7.3 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 222360 kb
Host smart-e0550b3a-8686-40b5-b48a-2cb9ef242da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939968995 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3939968995
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3874094756
Short name T336
Test name
Test status
Simulation time 124733139 ps
CPU time 4.37 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 207008 kb
Host smart-8d82bf97-84a8-4ef6-b4a5-4ab078c02f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874094756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3874094756
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3673734559
Short name T678
Test name
Test status
Simulation time 140510521 ps
CPU time 0.76 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 205576 kb
Host smart-50bb0be8-cf0a-44fc-935d-de9725122076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673734559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3673734559
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.87760737
Short name T979
Test name
Test status
Simulation time 242617268 ps
CPU time 2.96 seconds
Started May 18 04:12:21 PM PDT 24
Finished May 18 04:12:25 PM PDT 24
Peak memory 209532 kb
Host smart-5ed95417-6a9b-46e3-9000-f4457b553559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87760737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.87760737
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1265321204
Short name T663
Test name
Test status
Simulation time 4561061923 ps
CPU time 26.51 seconds
Started May 18 04:12:20 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 208508 kb
Host smart-7336757c-604f-45bd-8077-f220469ce41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265321204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1265321204
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2336773607
Short name T954
Test name
Test status
Simulation time 107983741 ps
CPU time 3.81 seconds
Started May 18 04:12:30 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 208784 kb
Host smart-38e83afb-ec5d-45d2-a72f-e7cc0f75fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336773607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2336773607
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2259198086
Short name T988
Test name
Test status
Simulation time 110317736 ps
CPU time 2.45 seconds
Started May 18 04:12:23 PM PDT 24
Finished May 18 04:12:27 PM PDT 24
Peak memory 210568 kb
Host smart-82f0383b-21d6-4bbf-8708-5b8ba38d19f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259198086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2259198086
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3223545417
Short name T57
Test name
Test status
Simulation time 44713530 ps
CPU time 2.91 seconds
Started May 18 04:12:20 PM PDT 24
Finished May 18 04:12:23 PM PDT 24
Peak memory 209260 kb
Host smart-ff0d8538-5eb7-4e0b-9b59-19493cbdded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223545417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3223545417
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2919567234
Short name T728
Test name
Test status
Simulation time 212072101 ps
CPU time 3.73 seconds
Started May 18 04:12:15 PM PDT 24
Finished May 18 04:12:19 PM PDT 24
Peak memory 207912 kb
Host smart-30606d21-40e1-4c69-8b2a-3a89b4833057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919567234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2919567234
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.299368514
Short name T638
Test name
Test status
Simulation time 83046178 ps
CPU time 3.77 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 208056 kb
Host smart-1026ea8b-388f-48f6-aed1-a5cefa5d5f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299368514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.299368514
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4212956529
Short name T608
Test name
Test status
Simulation time 1458521124 ps
CPU time 44.95 seconds
Started May 18 04:12:17 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 208648 kb
Host smart-5d2ae78f-a729-49dc-a67b-58d7ab759100
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212956529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4212956529
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1088432453
Short name T78
Test name
Test status
Simulation time 235154283 ps
CPU time 3.05 seconds
Started May 18 04:12:18 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 206724 kb
Host smart-0c735e19-b44f-4e42-8f51-c524dea4d9c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088432453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1088432453
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1830199122
Short name T612
Test name
Test status
Simulation time 79461930 ps
CPU time 2.4 seconds
Started May 18 04:12:19 PM PDT 24
Finished May 18 04:12:22 PM PDT 24
Peak memory 206700 kb
Host smart-a886ac6b-87b2-44dd-8c0b-f9d486d76c53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830199122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1830199122
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2981377970
Short name T80
Test name
Test status
Simulation time 146958198 ps
CPU time 2.64 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 218012 kb
Host smart-1c976bf3-45f2-4828-afa6-9a19f0176387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981377970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2981377970
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2985136982
Short name T769
Test name
Test status
Simulation time 215069984 ps
CPU time 4.37 seconds
Started May 18 04:12:14 PM PDT 24
Finished May 18 04:12:20 PM PDT 24
Peak memory 206512 kb
Host smart-2c80082b-c13c-4d0c-bea8-11e7339df665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985136982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2985136982
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1570091887
Short name T901
Test name
Test status
Simulation time 127825655 ps
CPU time 2.91 seconds
Started May 18 04:12:20 PM PDT 24
Finished May 18 04:12:24 PM PDT 24
Peak memory 222364 kb
Host smart-30c64384-dc13-4b02-a6b8-17ca07b4bef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570091887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1570091887
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4173994145
Short name T737
Test name
Test status
Simulation time 450125202 ps
CPU time 4.52 seconds
Started May 18 04:12:26 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 214128 kb
Host smart-e0b5de5b-e884-4965-a8e2-95323c167747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173994145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4173994145
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.858217719
Short name T715
Test name
Test status
Simulation time 81802747 ps
CPU time 2.35 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 209376 kb
Host smart-cdf8c24b-7135-4544-bcd0-fae1205f04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858217719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.858217719
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1880788141
Short name T639
Test name
Test status
Simulation time 42875384 ps
CPU time 0.97 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 205592 kb
Host smart-79b96273-29b4-4868-8122-1c8fadc72bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880788141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1880788141
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1705051878
Short name T1006
Test name
Test status
Simulation time 130533502 ps
CPU time 3.03 seconds
Started May 18 04:12:26 PM PDT 24
Finished May 18 04:12:30 PM PDT 24
Peak memory 214352 kb
Host smart-91fd86b6-9815-400c-95bc-6438f8072e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705051878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1705051878
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1717471559
Short name T630
Test name
Test status
Simulation time 52576466 ps
CPU time 2.34 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 214016 kb
Host smart-824110d7-2e39-471c-b990-bb2c0829209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717471559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1717471559
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.517025004
Short name T16
Test name
Test status
Simulation time 132101107 ps
CPU time 5.45 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:36 PM PDT 24
Peak memory 214028 kb
Host smart-33e2b6c6-8e2c-49b5-9c39-82e0bb50a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517025004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.517025004
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2992439598
Short name T214
Test name
Test status
Simulation time 74569202 ps
CPU time 3.48 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:34 PM PDT 24
Peak memory 209096 kb
Host smart-c6a3e660-51a9-4cdc-9f89-16ee6b38bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992439598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2992439598
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3519624334
Short name T596
Test name
Test status
Simulation time 76521937 ps
CPU time 3.42 seconds
Started May 18 04:12:26 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 207508 kb
Host smart-ea80f43e-9bc9-4a5a-bea1-2033be36ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519624334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3519624334
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3236781364
Short name T779
Test name
Test status
Simulation time 634212498 ps
CPU time 15.69 seconds
Started May 18 04:12:26 PM PDT 24
Finished May 18 04:12:43 PM PDT 24
Peak memory 207796 kb
Host smart-a4e82c52-c979-48e8-aad4-fd0d805fd9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236781364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3236781364
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1234201529
Short name T797
Test name
Test status
Simulation time 50325781 ps
CPU time 2.87 seconds
Started May 18 04:12:22 PM PDT 24
Finished May 18 04:12:26 PM PDT 24
Peak memory 206620 kb
Host smart-d6427d4e-4cad-4671-9be0-501c2c1d9f23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234201529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1234201529
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1832231331
Short name T804
Test name
Test status
Simulation time 1248566783 ps
CPU time 8.64 seconds
Started May 18 04:12:24 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 208384 kb
Host smart-96fbfee7-276b-4a20-830c-8bd989d7db21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832231331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1832231331
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3140927320
Short name T943
Test name
Test status
Simulation time 2197305841 ps
CPU time 19.3 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 207920 kb
Host smart-eb422bae-37df-4aba-abcf-181f99fc929a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140927320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3140927320
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.610467496
Short name T682
Test name
Test status
Simulation time 202292504 ps
CPU time 3.37 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 207616 kb
Host smart-17dc5df2-292f-4175-b90f-9e44a8deb567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610467496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.610467496
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.697371435
Short name T946
Test name
Test status
Simulation time 187822166 ps
CPU time 3.97 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 207484 kb
Host smart-82e6088b-f4c1-4927-b86f-71e3b2b294f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697371435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.697371435
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2743195477
Short name T73
Test name
Test status
Simulation time 1477115814 ps
CPU time 12.22 seconds
Started May 18 04:12:22 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 215332 kb
Host smart-f6e68a5d-de14-4668-a7b2-c71fba50804c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743195477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2743195477
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3131727062
Short name T852
Test name
Test status
Simulation time 138879785 ps
CPU time 8.65 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 222356 kb
Host smart-3d1c3dce-5221-4d0e-a7d2-0014a088ac4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131727062 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3131727062
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2801350114
Short name T714
Test name
Test status
Simulation time 596903179 ps
CPU time 6.15 seconds
Started May 18 04:12:23 PM PDT 24
Finished May 18 04:12:30 PM PDT 24
Peak memory 207804 kb
Host smart-f47cbf31-66ea-4f5a-8e2a-07a378aa05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801350114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2801350114
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4240592994
Short name T144
Test name
Test status
Simulation time 70310451 ps
CPU time 1.9 seconds
Started May 18 04:12:30 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 210084 kb
Host smart-c8a44df4-5ae1-445c-ae90-49dd0180efb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240592994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4240592994
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1788757583
Short name T557
Test name
Test status
Simulation time 24886326 ps
CPU time 0.88 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:36 PM PDT 24
Peak memory 205576 kb
Host smart-93e274fe-5049-46e9-a0b6-b2fb0a0eaee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788757583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1788757583
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3779063859
Short name T399
Test name
Test status
Simulation time 525049595 ps
CPU time 4.69 seconds
Started May 18 04:12:23 PM PDT 24
Finished May 18 04:12:29 PM PDT 24
Peak memory 215264 kb
Host smart-492bb849-4db4-41c8-b881-f45ffadd3392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779063859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3779063859
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.77078874
Short name T20
Test name
Test status
Simulation time 91698957 ps
CPU time 2.42 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:34 PM PDT 24
Peak memory 222504 kb
Host smart-142a9e50-7a2a-4038-a207-39209763b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77078874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.77078874
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.543973975
Short name T293
Test name
Test status
Simulation time 384337282 ps
CPU time 2.92 seconds
Started May 18 04:12:27 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 218072 kb
Host smart-6913cda2-bfbc-48de-a3b1-d4eaedbc92a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543973975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.543973975
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1649501751
Short name T822
Test name
Test status
Simulation time 205039559 ps
CPU time 2.72 seconds
Started May 18 04:12:23 PM PDT 24
Finished May 18 04:12:27 PM PDT 24
Peak memory 214096 kb
Host smart-289eb258-be0c-42cd-a60f-5b75ba422038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649501751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1649501751
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2973240026
Short name T44
Test name
Test status
Simulation time 76746579 ps
CPU time 2.15 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 213952 kb
Host smart-676d3860-c3b0-461d-bb56-cc6f57ae647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973240026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2973240026
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1451434281
Short name T712
Test name
Test status
Simulation time 105931934 ps
CPU time 4.32 seconds
Started May 18 04:12:32 PM PDT 24
Finished May 18 04:12:38 PM PDT 24
Peak memory 209880 kb
Host smart-a40ecd96-433a-409d-82ff-a746510d9d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451434281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1451434281
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.102965467
Short name T923
Test name
Test status
Simulation time 691138056 ps
CPU time 9.65 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 208332 kb
Host smart-f8e9631d-6321-4418-909b-e590d142b745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102965467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.102965467
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3891544492
Short name T1031
Test name
Test status
Simulation time 92691953 ps
CPU time 4.01 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 208496 kb
Host smart-8182b489-fe1f-4a89-86a7-974ed2f0f9bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891544492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3891544492
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.742539462
Short name T350
Test name
Test status
Simulation time 78756797 ps
CPU time 2.38 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 206552 kb
Host smart-bf102e51-03d1-4ed8-8400-0e31639c58f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742539462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.742539462
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1059467598
Short name T707
Test name
Test status
Simulation time 298830113 ps
CPU time 8.11 seconds
Started May 18 04:12:22 PM PDT 24
Finished May 18 04:12:31 PM PDT 24
Peak memory 208524 kb
Host smart-20c29596-a64d-4992-953e-4f14dc04330c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059467598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1059467598
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4092989435
Short name T289
Test name
Test status
Simulation time 131629802 ps
CPU time 2.14 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:40 PM PDT 24
Peak memory 209452 kb
Host smart-a0de320a-7ad8-4557-9ad2-3466196c6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092989435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4092989435
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1185782733
Short name T389
Test name
Test status
Simulation time 1575603777 ps
CPU time 29.27 seconds
Started May 18 04:12:26 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 207828 kb
Host smart-936f1ca4-d3f6-4e95-8878-574899e2c3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185782733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1185782733
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2882692873
Short name T198
Test name
Test status
Simulation time 522258593 ps
CPU time 7.73 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:43 PM PDT 24
Peak memory 222328 kb
Host smart-e4015091-b980-49eb-a700-df0b70845886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882692873 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2882692873
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2944433776
Short name T785
Test name
Test status
Simulation time 415134696 ps
CPU time 7.98 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:37 PM PDT 24
Peak memory 209776 kb
Host smart-6030fddc-9045-44f1-8c83-13853ddbe82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944433776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2944433776
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3156508691
Short name T841
Test name
Test status
Simulation time 318721234 ps
CPU time 5.48 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 210592 kb
Host smart-964a6e63-1d10-4510-be00-29882294d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156508691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3156508691
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.510700349
Short name T703
Test name
Test status
Simulation time 154698737 ps
CPU time 0.8 seconds
Started May 18 04:12:31 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 205608 kb
Host smart-620d01c6-cf72-4d3b-9fec-b6f74bb3a1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510700349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.510700349
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1220013459
Short name T999
Test name
Test status
Simulation time 306475634 ps
CPU time 3.18 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:44 PM PDT 24
Peak memory 218676 kb
Host smart-db1cca68-321a-418a-9066-c5b3daa3a287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220013459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1220013459
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2499562827
Short name T66
Test name
Test status
Simulation time 1396972291 ps
CPU time 14.75 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:50 PM PDT 24
Peak memory 207980 kb
Host smart-dff5aa2d-3fc2-4cb5-853c-177b660839a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499562827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2499562827
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4240083790
Short name T697
Test name
Test status
Simulation time 412699360 ps
CPU time 3.59 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 218132 kb
Host smart-80518a51-835a-4c9e-98d5-d1565480c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240083790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4240083790
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.177540424
Short name T181
Test name
Test status
Simulation time 165704041 ps
CPU time 3.27 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 210148 kb
Host smart-92770b86-a4b7-4de2-a590-4c90da944cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177540424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.177540424
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2938465738
Short name T627
Test name
Test status
Simulation time 111614915 ps
CPU time 3.47 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:38 PM PDT 24
Peak memory 207864 kb
Host smart-42a4447c-ce87-4e13-a34b-5cd5952167cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938465738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2938465738
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2354518393
Short name T820
Test name
Test status
Simulation time 119320052 ps
CPU time 5.18 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:45 PM PDT 24
Peak memory 207024 kb
Host smart-b47bf9ff-4b48-4a86-8b71-44f4a4ac87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354518393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2354518393
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3479999014
Short name T667
Test name
Test status
Simulation time 209384547 ps
CPU time 2.96 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 208048 kb
Host smart-2631ef86-6a28-4aeb-951f-aa468035935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479999014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3479999014
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3274103901
Short name T592
Test name
Test status
Simulation time 37975000 ps
CPU time 2.6 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 208492 kb
Host smart-517012ca-3eae-4c50-9038-78a9bbf6cba9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274103901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3274103901
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1494810617
Short name T780
Test name
Test status
Simulation time 218020853 ps
CPU time 5.87 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 208028 kb
Host smart-9e616a7f-0755-45f9-b841-da9ac095d160
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494810617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1494810617
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4257056413
Short name T839
Test name
Test status
Simulation time 63797842 ps
CPU time 3.27 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 206588 kb
Host smart-bcb65ce5-029a-496c-8d42-f2d818f27b61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257056413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4257056413
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2428671387
Short name T1045
Test name
Test status
Simulation time 47256410 ps
CPU time 2.35 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 207592 kb
Host smart-887f2333-67af-4422-b340-0c7d6dba7818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428671387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2428671387
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3578757821
Short name T554
Test name
Test status
Simulation time 41339380 ps
CPU time 2.19 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:33 PM PDT 24
Peak memory 207776 kb
Host smart-79c80865-5c64-4f06-a44f-a9bcfd5f4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578757821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3578757821
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.537002916
Short name T550
Test name
Test status
Simulation time 76440369 ps
CPU time 3.03 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 222360 kb
Host smart-4f6af010-9847-4120-9e1d-703f0fa04f24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537002916 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.537002916
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4269081151
Short name T633
Test name
Test status
Simulation time 54835638 ps
CPU time 3.35 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 207776 kb
Host smart-8658bee9-fb08-40e3-a28e-18640009e71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269081151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4269081151
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3157348710
Short name T373
Test name
Test status
Simulation time 352334047 ps
CPU time 2.67 seconds
Started May 18 04:12:28 PM PDT 24
Finished May 18 04:12:32 PM PDT 24
Peak memory 209720 kb
Host smart-8fd242c8-f396-4923-9c81-2f156f93cc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157348710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3157348710
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3525443085
Short name T571
Test name
Test status
Simulation time 59809386 ps
CPU time 0.98 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:12:44 PM PDT 24
Peak memory 205744 kb
Host smart-377a612b-a9d1-4bde-b738-4a78bdf8a354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525443085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3525443085
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2903749655
Short name T632
Test name
Test status
Simulation time 44998091 ps
CPU time 2.26 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:40 PM PDT 24
Peak memory 209268 kb
Host smart-912f3507-4bbf-4316-9ec4-43206d149010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903749655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2903749655
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1744420325
Short name T239
Test name
Test status
Simulation time 174352974 ps
CPU time 2.16 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:43 PM PDT 24
Peak memory 214056 kb
Host smart-b83092db-b0d3-464f-ab54-4ef4f60a6966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744420325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1744420325
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.517618358
Short name T621
Test name
Test status
Simulation time 181215414 ps
CPU time 4.32 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:44 PM PDT 24
Peak memory 214076 kb
Host smart-a7f64f97-705e-4554-b22a-f6e1ff4f34e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517618358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.517618358
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1872123476
Short name T100
Test name
Test status
Simulation time 979703665 ps
CPU time 7.39 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:48 PM PDT 24
Peak memory 213988 kb
Host smart-f6659f55-945a-4cb3-85bb-624473181f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872123476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1872123476
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2953478967
Short name T46
Test name
Test status
Simulation time 98579530 ps
CPU time 3.67 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 219932 kb
Host smart-39cd2a98-6597-4643-a7e1-f6fb6b296df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953478967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2953478967
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2136622440
Short name T856
Test name
Test status
Simulation time 520533468 ps
CPU time 7.62 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:48 PM PDT 24
Peak memory 209432 kb
Host smart-60f4fd4c-dc61-47fa-ac26-1078b961be0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136622440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2136622440
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3864343279
Short name T662
Test name
Test status
Simulation time 51285061 ps
CPU time 2.8 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 206420 kb
Host smart-a61a5750-ccdf-4558-bc90-2aeb41f3b85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864343279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3864343279
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2885697932
Short name T1047
Test name
Test status
Simulation time 528876493 ps
CPU time 5.84 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 208232 kb
Host smart-35426a09-e74e-46e8-804a-72979a2b10b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885697932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2885697932
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3976554577
Short name T747
Test name
Test status
Simulation time 726652121 ps
CPU time 5.47 seconds
Started May 18 04:12:33 PM PDT 24
Finished May 18 04:12:40 PM PDT 24
Peak memory 208428 kb
Host smart-8a82f188-5873-4c65-8fac-e79cc756b7a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976554577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3976554577
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1099270139
Short name T190
Test name
Test status
Simulation time 297498646 ps
CPU time 7.81 seconds
Started May 18 04:12:29 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 208420 kb
Host smart-a825c4ba-2fd6-44c3-b8f4-36e7d00d2dff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099270139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1099270139
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.420641853
Short name T676
Test name
Test status
Simulation time 9568044618 ps
CPU time 23.11 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:13:02 PM PDT 24
Peak memory 208972 kb
Host smart-553fd295-b71b-4f8c-85cc-33fc2670b501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420641853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.420641853
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2421965362
Short name T417
Test name
Test status
Simulation time 125471384 ps
CPU time 2.93 seconds
Started May 18 04:12:30 PM PDT 24
Finished May 18 04:12:35 PM PDT 24
Peak memory 208284 kb
Host smart-d9f55e46-93b1-4270-bded-1ed005fe8395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421965362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2421965362
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2510151233
Short name T811
Test name
Test status
Simulation time 870235478 ps
CPU time 21.33 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 214016 kb
Host smart-a1068946-b108-4aee-b7be-e474c55416e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510151233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2510151233
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3851879678
Short name T916
Test name
Test status
Simulation time 117504262 ps
CPU time 2.47 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 206748 kb
Host smart-41e95534-cf87-4ea2-8a23-7ae7df4b3159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851879678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3851879678
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.453050223
Short name T1002
Test name
Test status
Simulation time 50001755 ps
CPU time 2.1 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:40 PM PDT 24
Peak memory 209656 kb
Host smart-e1a91f92-cd9f-483c-b683-d9b8297e397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453050223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.453050223
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3967299656
Short name T628
Test name
Test status
Simulation time 13621581 ps
CPU time 0.91 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 205656 kb
Host smart-3b1cd1b1-2633-49bb-b7b7-1026a9cce699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967299656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3967299656
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.821939573
Short name T756
Test name
Test status
Simulation time 321823496 ps
CPU time 4.69 seconds
Started May 18 04:12:39 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 216332 kb
Host smart-bbf2d48d-f6a8-43c9-8f03-ca02e50160b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821939573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.821939573
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.734669216
Short name T315
Test name
Test status
Simulation time 43864800 ps
CPU time 2.94 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 214000 kb
Host smart-402e79d1-ae46-4c39-a485-3a9626136c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734669216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.734669216
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1514567031
Short name T285
Test name
Test status
Simulation time 118570243 ps
CPU time 4.77 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 219784 kb
Host smart-1eff76ed-1799-410b-95ea-0822b8cf2d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514567031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1514567031
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1846258347
Short name T993
Test name
Test status
Simulation time 681184749 ps
CPU time 6.3 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 222120 kb
Host smart-c6734067-a790-4a14-9972-6d32d43d8a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846258347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1846258347
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.724401439
Short name T806
Test name
Test status
Simulation time 149797237 ps
CPU time 2.85 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 214024 kb
Host smart-931b55e5-f605-4191-ac1f-f0870b6cac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724401439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.724401439
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3491744801
Short name T935
Test name
Test status
Simulation time 2876202712 ps
CPU time 24.45 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:13:02 PM PDT 24
Peak memory 214128 kb
Host smart-b2be768c-0c77-4464-8fbe-5dead587f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491744801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3491744801
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1769615978
Short name T1018
Test name
Test status
Simulation time 64846706 ps
CPU time 3.2 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:41 PM PDT 24
Peak memory 206584 kb
Host smart-69795f17-d024-42c2-8664-da1b3f6c483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769615978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1769615978
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1659133354
Short name T344
Test name
Test status
Simulation time 35059666 ps
CPU time 2.23 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:42 PM PDT 24
Peak memory 206492 kb
Host smart-b94ff71f-c8c3-483c-b402-12509d0a2eee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659133354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1659133354
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.872914788
Short name T591
Test name
Test status
Simulation time 54162898 ps
CPU time 3.04 seconds
Started May 18 04:12:38 PM PDT 24
Finished May 18 04:12:44 PM PDT 24
Peak memory 206316 kb
Host smart-0fa986e9-43ee-43ae-aadc-cab13c71ffd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872914788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.872914788
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4122773724
Short name T304
Test name
Test status
Simulation time 254062366 ps
CPU time 7.31 seconds
Started May 18 04:12:36 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 207504 kb
Host smart-09eaacab-bc9b-45e2-ba51-b992c1dd405b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122773724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4122773724
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2109278744
Short name T732
Test name
Test status
Simulation time 83362153 ps
CPU time 4.19 seconds
Started May 18 04:12:39 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 209932 kb
Host smart-7ad9bc9e-9516-4c54-b3f1-da14964855d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109278744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2109278744
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3941267693
Short name T1044
Test name
Test status
Simulation time 68481849 ps
CPU time 2.56 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:43 PM PDT 24
Peak memory 206960 kb
Host smart-6b4bb78b-bb8f-4c9a-90e8-428402d9d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941267693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3941267693
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3141354345
Short name T254
Test name
Test status
Simulation time 495493214 ps
CPU time 16.62 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:54 PM PDT 24
Peak memory 218672 kb
Host smart-f1921aff-befc-4659-a3ca-ea6d70f4f86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141354345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3141354345
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3707697387
Short name T895
Test name
Test status
Simulation time 210880336 ps
CPU time 6.37 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 222296 kb
Host smart-6a4a4270-f73c-4981-8053-56cbf821f4ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707697387 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3707697387
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2072473349
Short name T564
Test name
Test status
Simulation time 108145199 ps
CPU time 1.58 seconds
Started May 18 04:12:35 PM PDT 24
Finished May 18 04:12:39 PM PDT 24
Peak memory 209704 kb
Host smart-fd6d4051-546f-47c4-b120-790711cdb364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072473349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2072473349
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.588928238
Short name T93
Test name
Test status
Simulation time 45955071 ps
CPU time 0.75 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 205596 kb
Host smart-4079f347-d76d-4f9b-83b8-a94f89581da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588928238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.588928238
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.817278610
Short name T410
Test name
Test status
Simulation time 1224171762 ps
CPU time 64.22 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:13:49 PM PDT 24
Peak memory 214068 kb
Host smart-b1bd54e7-6206-4f01-930e-795eec99d2bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817278610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.817278610
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1966970222
Short name T24
Test name
Test status
Simulation time 135576054 ps
CPU time 2.63 seconds
Started May 18 04:12:42 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 207980 kb
Host smart-26f3b592-5b16-4179-8ef9-3af97bd55b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966970222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1966970222
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2657734065
Short name T408
Test name
Test status
Simulation time 2687734298 ps
CPU time 25.22 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:13:09 PM PDT 24
Peak memory 208964 kb
Host smart-cbe797d1-fbae-4539-a821-86dfee1d9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657734065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2657734065
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.202894326
Short name T87
Test name
Test status
Simulation time 154752318 ps
CPU time 3.63 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 214016 kb
Host smart-a77aa200-e238-45af-9557-871691975965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202894326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.202894326
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.124253667
Short name T354
Test name
Test status
Simulation time 145300229 ps
CPU time 6.59 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 213968 kb
Host smart-fc86bf9a-d90e-4708-a2d0-d235c6bc48c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124253667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.124253667
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4030022934
Short name T729
Test name
Test status
Simulation time 180752061 ps
CPU time 4.23 seconds
Started May 18 04:12:47 PM PDT 24
Finished May 18 04:12:54 PM PDT 24
Peak memory 208288 kb
Host smart-3466c48f-cb52-442d-85fe-4b3ba4ae1a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030022934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4030022934
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2015641595
Short name T319
Test name
Test status
Simulation time 1965796207 ps
CPU time 47.31 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:13:35 PM PDT 24
Peak memory 218500 kb
Host smart-95907598-392d-4101-bc27-0a10760761dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015641595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2015641595
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1177674564
Short name T700
Test name
Test status
Simulation time 2330732418 ps
CPU time 41.81 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:13:30 PM PDT 24
Peak memory 208696 kb
Host smart-b60d22c6-afea-49b0-9584-f375886576eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177674564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1177674564
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1136688821
Short name T699
Test name
Test status
Simulation time 112160725 ps
CPU time 2.97 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 208312 kb
Host smart-51e8070e-3f48-40b9-8470-adec40016c9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136688821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1136688821
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.550150398
Short name T784
Test name
Test status
Simulation time 697002918 ps
CPU time 6.41 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:54 PM PDT 24
Peak memory 207472 kb
Host smart-ca0ebf02-a4ca-4d5f-98de-a2c72b8a31bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550150398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.550150398
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.928583788
Short name T382
Test name
Test status
Simulation time 10617488511 ps
CPU time 63.35 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:13:51 PM PDT 24
Peak memory 207944 kb
Host smart-bac4acbd-cbe3-431b-aab2-d96b975637ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928583788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.928583788
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2192141200
Short name T692
Test name
Test status
Simulation time 215700669 ps
CPU time 5.51 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:12:54 PM PDT 24
Peak memory 209636 kb
Host smart-f3c785e9-bfa9-4f95-9932-da2dbff92f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192141200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2192141200
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1995857099
Short name T615
Test name
Test status
Simulation time 208507517 ps
CPU time 2.68 seconds
Started May 18 04:12:37 PM PDT 24
Finished May 18 04:12:43 PM PDT 24
Peak memory 208240 kb
Host smart-b9b1ccac-369e-442d-a0d6-22fb3f7a0f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995857099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1995857099
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3429990080
Short name T990
Test name
Test status
Simulation time 176674277 ps
CPU time 7.85 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 219412 kb
Host smart-ff10125f-1c98-4b5a-ae44-0bd2a37ddc0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429990080 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3429990080
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1842094372
Short name T271
Test name
Test status
Simulation time 446136428 ps
CPU time 5.06 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 208784 kb
Host smart-ba219025-45c0-4d7f-b93c-0ca4a98b6c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842094372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1842094372
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2552949055
Short name T735
Test name
Test status
Simulation time 18489062 ps
CPU time 0.75 seconds
Started May 18 04:10:16 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 205600 kb
Host smart-4475d188-459f-4dec-a7e6-c4670bc97bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552949055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2552949055
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1195237727
Short name T400
Test name
Test status
Simulation time 42419790 ps
CPU time 3.14 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 214024 kb
Host smart-18d5090d-d4a6-4576-a63c-0ddc0b8dafbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195237727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1195237727
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1335632791
Short name T1057
Test name
Test status
Simulation time 1114132309 ps
CPU time 7.18 seconds
Started May 18 04:10:16 PM PDT 24
Finished May 18 04:10:24 PM PDT 24
Peak memory 214308 kb
Host smart-1fc194b6-641b-4fde-8556-4fac52511f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335632791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1335632791
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2359023951
Short name T351
Test name
Test status
Simulation time 244307005 ps
CPU time 5.12 seconds
Started May 18 04:10:12 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 209008 kb
Host smart-77e5842d-faef-4666-b293-a342c4f05126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359023951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2359023951
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3187970536
Short name T917
Test name
Test status
Simulation time 856822175 ps
CPU time 9.02 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:23 PM PDT 24
Peak memory 210896 kb
Host smart-81e5e60b-d406-49a9-96a7-c550785e0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187970536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3187970536
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1365675229
Short name T898
Test name
Test status
Simulation time 472962879 ps
CPU time 3.97 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:20 PM PDT 24
Peak memory 219896 kb
Host smart-fdfc6eed-f097-400e-9cf7-7073025a5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365675229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1365675229
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1417711136
Short name T921
Test name
Test status
Simulation time 603443055 ps
CPU time 5.58 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:29 PM PDT 24
Peak memory 214016 kb
Host smart-a0b2f071-69ff-46a1-a7a6-d06249d84961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417711136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1417711136
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1299350484
Short name T97
Test name
Test status
Simulation time 2056663054 ps
CPU time 38.95 seconds
Started May 18 04:10:14 PM PDT 24
Finished May 18 04:10:54 PM PDT 24
Peak memory 235516 kb
Host smart-d789b738-8c05-4c1a-a902-aaf6ddd5d064
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299350484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1299350484
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3505058573
Short name T4
Test name
Test status
Simulation time 495670345 ps
CPU time 4.05 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 208084 kb
Host smart-2d71b4de-a983-4cd0-b57b-b193a8c24ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505058573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3505058573
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2908557646
Short name T276
Test name
Test status
Simulation time 80900944 ps
CPU time 1.92 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:22 PM PDT 24
Peak memory 207140 kb
Host smart-0c5ff837-767e-48ee-b207-f2de28509ee6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908557646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2908557646
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2365995229
Short name T945
Test name
Test status
Simulation time 65604023 ps
CPU time 2.91 seconds
Started May 18 04:10:14 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 206652 kb
Host smart-5888273e-c623-47c3-b175-e6f0151120c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365995229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2365995229
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.537288346
Short name T992
Test name
Test status
Simulation time 104001787 ps
CPU time 2.71 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 206476 kb
Host smart-e7e2ec4b-33b5-4ac8-9dcf-d36ead6ac089
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537288346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.537288346
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1183182485
Short name T838
Test name
Test status
Simulation time 157026751 ps
CPU time 3.9 seconds
Started May 18 04:10:14 PM PDT 24
Finished May 18 04:10:19 PM PDT 24
Peak memory 215860 kb
Host smart-c2e992e4-f755-4c57-b50a-1edd18a02204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183182485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1183182485
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.978509736
Short name T565
Test name
Test status
Simulation time 84572907 ps
CPU time 3.34 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 208196 kb
Host smart-49ccf5d8-5400-4784-97e2-156294e15c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978509736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.978509736
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1685682
Short name T618
Test name
Test status
Simulation time 1037483036 ps
CPU time 6.5 seconds
Started May 18 04:10:17 PM PDT 24
Finished May 18 04:10:24 PM PDT 24
Peak memory 222280 kb
Host smart-7ac0a24c-5cd7-469a-aa24-adb60e4df061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685682 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1685682
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.821108681
Short name T793
Test name
Test status
Simulation time 1771732444 ps
CPU time 24.33 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:38 PM PDT 24
Peak memory 214028 kb
Host smart-f84d95e4-2367-4a80-99e8-be5ecb448da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821108681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.821108681
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1917356156
Short name T783
Test name
Test status
Simulation time 53301476 ps
CPU time 1.32 seconds
Started May 18 04:10:12 PM PDT 24
Finished May 18 04:10:14 PM PDT 24
Peak memory 208392 kb
Host smart-f1223ba8-4a4f-43eb-9aac-39198a99c86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917356156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1917356156
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.727051136
Short name T629
Test name
Test status
Simulation time 8005745 ps
CPU time 0.73 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 205548 kb
Host smart-1ab4ec6a-4c92-4dfa-b5e6-8df07f15dc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727051136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.727051136
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3361203479
Short name T42
Test name
Test status
Simulation time 141193869 ps
CPU time 3.3 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:12:50 PM PDT 24
Peak memory 209724 kb
Host smart-c25d20b2-4372-44bf-989a-c3fa51bc737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361203479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3361203479
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.20796878
Short name T283
Test name
Test status
Simulation time 323857244 ps
CPU time 3.59 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 214196 kb
Host smart-59f52f19-13bd-44bb-a5e7-781aae9dc885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20796878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.20796878
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3659678909
Short name T99
Test name
Test status
Simulation time 415475925 ps
CPU time 4.86 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:12:50 PM PDT 24
Peak memory 213912 kb
Host smart-b7012446-bd3c-48a5-b8c2-d31d3a22d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659678909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3659678909
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3787063120
Short name T910
Test name
Test status
Simulation time 158501272 ps
CPU time 7.43 seconds
Started May 18 04:12:42 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 218604 kb
Host smart-9169eda3-3d6a-4d94-ac2d-c2f994662b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787063120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3787063120
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.975073824
Short name T299
Test name
Test status
Simulation time 7770616170 ps
CPU time 39.37 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:13:23 PM PDT 24
Peak memory 209320 kb
Host smart-7b390440-80b3-4814-a33b-c268680d4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975073824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.975073824
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2761814216
Short name T339
Test name
Test status
Simulation time 381000525 ps
CPU time 4.47 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 207980 kb
Host smart-0ff60875-c360-401d-a373-43adcf49a9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761814216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2761814216
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2405473130
Short name T383
Test name
Test status
Simulation time 886732390 ps
CPU time 26.7 seconds
Started May 18 04:12:47 PM PDT 24
Finished May 18 04:13:16 PM PDT 24
Peak memory 207596 kb
Host smart-e4be6095-c662-46bb-82be-da4f6c1d3921
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405473130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2405473130
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2409592452
Short name T865
Test name
Test status
Simulation time 164362285 ps
CPU time 4.26 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 208584 kb
Host smart-b851b234-42d9-4488-b83f-e43e2f07d3c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409592452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2409592452
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.777803247
Short name T584
Test name
Test status
Simulation time 145028594 ps
CPU time 2.52 seconds
Started May 18 04:12:41 PM PDT 24
Finished May 18 04:12:46 PM PDT 24
Peak memory 207212 kb
Host smart-b0be5a4f-443e-4249-8f40-859684210d08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777803247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.777803247
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.473736120
Short name T295
Test name
Test status
Simulation time 751006401 ps
CPU time 2.61 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:12:49 PM PDT 24
Peak memory 217596 kb
Host smart-02944861-a1c4-4f57-bbd2-af54bd2be180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473736120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.473736120
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2272681617
Short name T725
Test name
Test status
Simulation time 39004807 ps
CPU time 2.06 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:12:47 PM PDT 24
Peak memory 206428 kb
Host smart-4e71ca8b-d3cd-4783-a2e6-f8eb045b56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272681617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2272681617
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3953261137
Short name T310
Test name
Test status
Simulation time 23072900433 ps
CPU time 126.48 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:14:52 PM PDT 24
Peak memory 216384 kb
Host smart-1dc6e679-15eb-4ad1-b2b2-10299fb56c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953261137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3953261137
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1239438634
Short name T818
Test name
Test status
Simulation time 378452218 ps
CPU time 9.44 seconds
Started May 18 04:12:42 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 207984 kb
Host smart-32d44401-c8f1-48fa-80cf-2dc3ab729250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239438634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1239438634
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2931589864
Short name T1054
Test name
Test status
Simulation time 57559316 ps
CPU time 2.7 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 209616 kb
Host smart-74172d9c-c950-4ae7-83b6-bbc7db8ed68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931589864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2931589864
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2612921338
Short name T794
Test name
Test status
Simulation time 46737023 ps
CPU time 0.88 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 205576 kb
Host smart-6136022f-ec5a-46a2-a9be-54f5a61876c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612921338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2612921338
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2775170830
Short name T21
Test name
Test status
Simulation time 40677355 ps
CPU time 2.64 seconds
Started May 18 04:12:50 PM PDT 24
Finished May 18 04:12:55 PM PDT 24
Peak memory 214348 kb
Host smart-edae36b3-1ff6-40f0-8074-dc45c9e5045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775170830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2775170830
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.238915922
Short name T626
Test name
Test status
Simulation time 125699836 ps
CPU time 2.61 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 207116 kb
Host smart-847a72c7-1607-4a10-bdb0-9ab1836afea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238915922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.238915922
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.434647983
Short name T23
Test name
Test status
Simulation time 279178974 ps
CPU time 6.51 seconds
Started May 18 04:12:51 PM PDT 24
Finished May 18 04:13:00 PM PDT 24
Peak memory 222184 kb
Host smart-1ab9b914-bf27-4c11-9a83-f6863c07429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434647983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.434647983
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.833515658
Short name T179
Test name
Test status
Simulation time 333622774 ps
CPU time 6.14 seconds
Started May 18 04:12:48 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 214004 kb
Host smart-5a5c17bd-e45a-4ad8-954d-c3802621357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833515658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.833515658
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.290992731
Short name T980
Test name
Test status
Simulation time 43051273 ps
CPU time 2.21 seconds
Started May 18 04:12:48 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 218740 kb
Host smart-81683907-2757-45b0-b1b1-482367a929bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290992731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.290992731
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3331879360
Short name T819
Test name
Test status
Simulation time 286586483 ps
CPU time 3.91 seconds
Started May 18 04:12:47 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 206812 kb
Host smart-3aae9290-3f87-4218-8ed1-4c7ce3d01835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331879360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3331879360
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3052456895
Short name T1034
Test name
Test status
Simulation time 1129559988 ps
CPU time 31.13 seconds
Started May 18 04:12:45 PM PDT 24
Finished May 18 04:13:18 PM PDT 24
Peak memory 207752 kb
Host smart-898cd561-be6b-4220-939d-a93995635828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052456895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3052456895
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.326647670
Short name T861
Test name
Test status
Simulation time 1133380487 ps
CPU time 8.44 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:12:55 PM PDT 24
Peak memory 208308 kb
Host smart-f4921fad-3edc-443d-978c-cbc032e40daf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326647670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.326647670
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3839962479
Short name T588
Test name
Test status
Simulation time 3755906061 ps
CPU time 53.8 seconds
Started May 18 04:12:44 PM PDT 24
Finished May 18 04:13:40 PM PDT 24
Peak memory 208144 kb
Host smart-72464583-3e23-4715-9d62-effb90adfdb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839962479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3839962479
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1528414824
Short name T598
Test name
Test status
Simulation time 161400903 ps
CPU time 5.72 seconds
Started May 18 04:12:43 PM PDT 24
Finished May 18 04:12:51 PM PDT 24
Peak memory 208556 kb
Host smart-0d3684af-3069-4130-8322-a443c6c1a933
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528414824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1528414824
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.296863056
Short name T826
Test name
Test status
Simulation time 336979140 ps
CPU time 3.61 seconds
Started May 18 04:12:51 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 209364 kb
Host smart-20a8386c-7dd1-4e90-8663-ae33693a3a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296863056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.296863056
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2887474722
Short name T619
Test name
Test status
Simulation time 2108466038 ps
CPU time 7.28 seconds
Started May 18 04:12:46 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 208372 kb
Host smart-635fe08a-c8a2-4809-bf58-9208f49e6db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887474722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2887474722
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1879606177
Short name T205
Test name
Test status
Simulation time 76775308 ps
CPU time 5.88 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:57 PM PDT 24
Peak memory 219504 kb
Host smart-13a5a1d4-f17c-411b-bad5-244e9ecc40c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879606177 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1879606177
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4231357885
Short name T724
Test name
Test status
Simulation time 103385325 ps
CPU time 4.85 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 217916 kb
Host smart-7b455739-383d-4881-8aa1-f780b525ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231357885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4231357885
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3080225187
Short name T755
Test name
Test status
Simulation time 67002484 ps
CPU time 3.34 seconds
Started May 18 04:12:53 PM PDT 24
Finished May 18 04:12:57 PM PDT 24
Peak memory 209892 kb
Host smart-2318f9c4-5346-4c66-a3f7-6576410fce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080225187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3080225187
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3392310512
Short name T562
Test name
Test status
Simulation time 47423104 ps
CPU time 0.77 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:13:00 PM PDT 24
Peak memory 205504 kb
Host smart-bdb57323-b218-4f7b-8c9e-a65209ed021b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392310512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3392310512
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2031590759
Short name T253
Test name
Test status
Simulation time 53870775 ps
CPU time 3.75 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:55 PM PDT 24
Peak memory 214632 kb
Host smart-2efd4762-37a5-47a6-b43f-b4c784ece579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031590759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2031590759
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3697445565
Short name T778
Test name
Test status
Simulation time 1375864807 ps
CPU time 12.73 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 208516 kb
Host smart-55787d90-c112-4e6e-912b-f7c7d28f6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697445565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3697445565
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4157134309
Short name T231
Test name
Test status
Simulation time 384406954 ps
CPU time 6.08 seconds
Started May 18 04:12:51 PM PDT 24
Finished May 18 04:12:59 PM PDT 24
Peak memory 219032 kb
Host smart-d4b0b381-79b8-4e70-9ce1-06ac21b38944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157134309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4157134309
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.587468567
Short name T942
Test name
Test status
Simulation time 132872751 ps
CPU time 4.47 seconds
Started May 18 04:12:54 PM PDT 24
Finished May 18 04:12:59 PM PDT 24
Peak memory 213968 kb
Host smart-fa7aad92-0835-4f07-9d43-00939c396acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587468567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.587468567
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2444556005
Short name T631
Test name
Test status
Simulation time 90433895 ps
CPU time 4.22 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 219376 kb
Host smart-3315396d-4eef-4306-9f6e-da711215f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444556005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2444556005
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2600694723
Short name T616
Test name
Test status
Simulation time 93790914 ps
CPU time 4.62 seconds
Started May 18 04:12:51 PM PDT 24
Finished May 18 04:12:57 PM PDT 24
Peak memory 208796 kb
Host smart-4b5933d1-10eb-4d68-be6c-5bd5a367f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600694723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2600694723
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1163403658
Short name T386
Test name
Test status
Simulation time 97459562 ps
CPU time 3.58 seconds
Started May 18 04:12:48 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 208532 kb
Host smart-36686ddc-57db-4b69-94f3-b72746773bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163403658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1163403658
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.561718220
Short name T643
Test name
Test status
Simulation time 81864513 ps
CPU time 3.6 seconds
Started May 18 04:12:50 PM PDT 24
Finished May 18 04:12:55 PM PDT 24
Peak memory 208084 kb
Host smart-357ea4b4-0ce4-4795-9a01-e6a65335d26b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561718220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.561718220
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1880902846
Short name T647
Test name
Test status
Simulation time 62761705 ps
CPU time 3.18 seconds
Started May 18 04:12:50 PM PDT 24
Finished May 18 04:12:55 PM PDT 24
Peak memory 208160 kb
Host smart-c3ae6a5d-9799-4dc8-a58e-4270f40cb14f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880902846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1880902846
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4236719793
Short name T1028
Test name
Test status
Simulation time 34488429 ps
CPU time 2.5 seconds
Started May 18 04:12:47 PM PDT 24
Finished May 18 04:12:52 PM PDT 24
Peak memory 208660 kb
Host smart-e436f2b4-3b43-482a-8364-f34d67b11205
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236719793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4236719793
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4041326834
Short name T912
Test name
Test status
Simulation time 264957336 ps
CPU time 4.05 seconds
Started May 18 04:12:50 PM PDT 24
Finished May 18 04:12:56 PM PDT 24
Peak memory 215704 kb
Host smart-f4bd5a50-5077-4e28-9ba6-2f9dbcb7add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041326834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4041326834
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1506844413
Short name T566
Test name
Test status
Simulation time 55807144 ps
CPU time 2.61 seconds
Started May 18 04:12:48 PM PDT 24
Finished May 18 04:12:53 PM PDT 24
Peak memory 206672 kb
Host smart-5226d99b-01b8-4754-b892-e527c548699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506844413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1506844413
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.162940736
Short name T273
Test name
Test status
Simulation time 28566343439 ps
CPU time 317.19 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:18:16 PM PDT 24
Peak memory 217036 kb
Host smart-e98894cb-c02d-471f-9170-9157f0a49aee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162940736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.162940736
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3438120116
Short name T1062
Test name
Test status
Simulation time 120406119 ps
CPU time 7.89 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:09 PM PDT 24
Peak memory 223476 kb
Host smart-5eb25ce9-1c3a-4589-bd49-3e51c9fffb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438120116 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3438120116
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.617813194
Short name T184
Test name
Test status
Simulation time 188367791 ps
CPU time 7.18 seconds
Started May 18 04:12:49 PM PDT 24
Finished May 18 04:12:58 PM PDT 24
Peak memory 209552 kb
Host smart-04a31a87-8111-46b2-9c34-45e728510242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617813194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.617813194
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4114530948
Short name T677
Test name
Test status
Simulation time 57759487 ps
CPU time 2.55 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 209732 kb
Host smart-849ceca8-0ad8-4eaf-90e5-918d28891ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114530948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4114530948
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.68454735
Short name T1026
Test name
Test status
Simulation time 78206085 ps
CPU time 0.85 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:12:59 PM PDT 24
Peak memory 205592 kb
Host smart-edc01da4-3e46-4e3a-bd10-a64b89c04225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68454735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.68454735
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3157243002
Short name T278
Test name
Test status
Simulation time 953150560 ps
CPU time 6.61 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 215260 kb
Host smart-6e3d2147-da93-40ec-80dc-626384479dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157243002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3157243002
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1496473263
Short name T11
Test name
Test status
Simulation time 114960700 ps
CPU time 4.35 seconds
Started May 18 04:13:00 PM PDT 24
Finished May 18 04:13:06 PM PDT 24
Peak memory 222492 kb
Host smart-b9122c2f-8d67-4050-b7c9-f3191a57b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496473263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1496473263
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.429135217
Short name T58
Test name
Test status
Simulation time 266210432 ps
CPU time 2.49 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:00 PM PDT 24
Peak memory 207324 kb
Host smart-2d486e10-d41a-416e-a51c-d63a95847366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429135217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.429135217
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2032151707
Short name T89
Test name
Test status
Simulation time 82281048 ps
CPU time 3.81 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:05 PM PDT 24
Peak memory 218888 kb
Host smart-0f56cbb1-43dd-467f-a5f9-573057dbb2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032151707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2032151707
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3200626837
Short name T352
Test name
Test status
Simulation time 225214516 ps
CPU time 5.57 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:13:05 PM PDT 24
Peak memory 211148 kb
Host smart-e5232170-f719-41b5-a605-7e914db83f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200626837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3200626837
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1822476641
Short name T850
Test name
Test status
Simulation time 80587310 ps
CPU time 1.75 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:00 PM PDT 24
Peak memory 214040 kb
Host smart-ead08331-4418-4ce7-8346-fed68f4ce78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822476641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1822476641
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.136457934
Short name T1041
Test name
Test status
Simulation time 166777895 ps
CPU time 5.31 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 214020 kb
Host smart-6c982ae3-08ed-4427-a87c-879dc77b3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136457934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.136457934
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.368613781
Short name T274
Test name
Test status
Simulation time 26580218 ps
CPU time 2.18 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:00 PM PDT 24
Peak memory 208060 kb
Host smart-fce31dca-86e8-4023-879e-3357c3c80cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368613781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.368613781
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1822653937
Short name T750
Test name
Test status
Simulation time 103648552 ps
CPU time 4.59 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:02 PM PDT 24
Peak memory 208472 kb
Host smart-51c8dd41-95a7-4a74-b3ac-53fa506d7210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822653937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1822653937
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1742206695
Short name T613
Test name
Test status
Simulation time 237599697 ps
CPU time 2.92 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 206412 kb
Host smart-72c17187-978a-4e11-85c6-371d779421af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742206695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1742206695
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2010755383
Short name T905
Test name
Test status
Simulation time 776145646 ps
CPU time 8.81 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 206640 kb
Host smart-4465b03b-2939-4279-bd2c-5bba8e9b64d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010755383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2010755383
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.913399966
Short name T236
Test name
Test status
Simulation time 105784966 ps
CPU time 2.86 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 208344 kb
Host smart-0ccbdd6e-d801-469c-aea7-17e87b5c7659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913399966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.913399966
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3561489223
Short name T623
Test name
Test status
Simulation time 536325914 ps
CPU time 2.84 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 208064 kb
Host smart-dca2de89-4fc6-4a4b-8f53-f75fb3201c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561489223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3561489223
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3629890617
Short name T72
Test name
Test status
Simulation time 1044614398 ps
CPU time 26.18 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:27 PM PDT 24
Peak memory 216680 kb
Host smart-d1fc5095-6348-4d6f-99cc-2e35e4b54a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629890617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3629890617
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3526717211
Short name T964
Test name
Test status
Simulation time 616066446 ps
CPU time 10.08 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:10 PM PDT 24
Peak memory 222460 kb
Host smart-5a4cc937-7d56-427f-bfe7-ae380847fb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526717211 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3526717211
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4249334484
Short name T1060
Test name
Test status
Simulation time 184037411 ps
CPU time 4.78 seconds
Started May 18 04:13:04 PM PDT 24
Finished May 18 04:13:10 PM PDT 24
Peak memory 208652 kb
Host smart-f8efb875-b689-42cb-9acb-1a64e59a63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249334484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4249334484
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2998091624
Short name T33
Test name
Test status
Simulation time 123980439 ps
CPU time 3.21 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 209596 kb
Host smart-08b6746a-0093-46b4-93c6-bb5b2a7b66c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998091624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2998091624
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.325122300
Short name T867
Test name
Test status
Simulation time 13859348 ps
CPU time 0.73 seconds
Started May 18 04:13:04 PM PDT 24
Finished May 18 04:13:06 PM PDT 24
Peak memory 205556 kb
Host smart-0a1be75e-750a-45e4-92e5-1854311ff309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325122300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.325122300
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.286987971
Short name T301
Test name
Test status
Simulation time 478385260 ps
CPU time 2.68 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 214044 kb
Host smart-2fbd7003-bb5d-4623-98b4-9f3dd1e08e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286987971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.286987971
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2376849875
Short name T775
Test name
Test status
Simulation time 169132796 ps
CPU time 2.4 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 221024 kb
Host smart-aaeb4a7a-78cf-4d49-a647-e22571ba19b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376849875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2376849875
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3144522164
Short name T1027
Test name
Test status
Simulation time 465728996 ps
CPU time 8.26 seconds
Started May 18 04:12:57 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 207480 kb
Host smart-16a14f83-18d9-4da9-99cd-e01e8929537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144522164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3144522164
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3218229072
Short name T869
Test name
Test status
Simulation time 618438595 ps
CPU time 6.22 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 213936 kb
Host smart-550f4d3b-24bc-43c6-813e-15cd7e7c42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218229072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3218229072
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.426035730
Short name T56
Test name
Test status
Simulation time 126678767 ps
CPU time 3.62 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:02 PM PDT 24
Peak memory 209180 kb
Host smart-17e8e60d-c712-497b-afd1-2e35b1659af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426035730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.426035730
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1510463929
Short name T726
Test name
Test status
Simulation time 239568885 ps
CPU time 4.06 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 218112 kb
Host smart-fba7b156-0af4-46be-bc82-d6e2a6cc8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510463929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1510463929
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3546522496
Short name T98
Test name
Test status
Simulation time 266647996 ps
CPU time 7.08 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 207516 kb
Host smart-e3a738fb-2ef4-411d-8330-cef807201c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546522496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3546522496
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1909312906
Short name T680
Test name
Test status
Simulation time 110170137 ps
CPU time 3.37 seconds
Started May 18 04:12:56 PM PDT 24
Finished May 18 04:13:01 PM PDT 24
Peak memory 208268 kb
Host smart-162074c4-b8f6-491b-870a-0515198b97e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909312906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1909312906
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3627165651
Short name T379
Test name
Test status
Simulation time 418191223 ps
CPU time 5.09 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 208560 kb
Host smart-02825616-2eac-433b-a93e-85932eb44663
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627165651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3627165651
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4016696727
Short name T552
Test name
Test status
Simulation time 907258618 ps
CPU time 30.31 seconds
Started May 18 04:13:00 PM PDT 24
Finished May 18 04:13:32 PM PDT 24
Peak memory 208348 kb
Host smart-ed890205-e98b-4242-b888-6fa69d16e86d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016696727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4016696727
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4091571780
Short name T740
Test name
Test status
Simulation time 1541402859 ps
CPU time 14.4 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:14 PM PDT 24
Peak memory 209376 kb
Host smart-17767994-cee2-4e23-833e-0924dc844a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091571780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4091571780
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1903611751
Short name T656
Test name
Test status
Simulation time 33090524 ps
CPU time 2.27 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 206460 kb
Host smart-2c4d7876-ef57-4d71-8382-cc00e087e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903611751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1903611751
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1767233243
Short name T337
Test name
Test status
Simulation time 649169015 ps
CPU time 10.57 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 215104 kb
Host smart-8a6b6c41-543d-46f9-bf1e-1d05c2634caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767233243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1767233243
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1531018472
Short name T658
Test name
Test status
Simulation time 153000544 ps
CPU time 2.78 seconds
Started May 18 04:12:59 PM PDT 24
Finished May 18 04:13:04 PM PDT 24
Peak memory 208772 kb
Host smart-56d77520-4e32-4503-a073-8b0ab29a49e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531018472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1531018472
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.18363273
Short name T394
Test name
Test status
Simulation time 90189934 ps
CPU time 2.28 seconds
Started May 18 04:12:58 PM PDT 24
Finished May 18 04:13:03 PM PDT 24
Peak memory 210260 kb
Host smart-2159a0dd-5162-4a45-9ff7-e81847decb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18363273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.18363273
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2362944717
Short name T583
Test name
Test status
Simulation time 61090122 ps
CPU time 0.75 seconds
Started May 18 04:13:07 PM PDT 24
Finished May 18 04:13:09 PM PDT 24
Peak memory 205524 kb
Host smart-4e7978fc-4555-40fb-a9eb-59a46d8b3339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362944717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2362944717
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.724194657
Short name T575
Test name
Test status
Simulation time 525869165 ps
CPU time 12.01 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:29 PM PDT 24
Peak memory 218000 kb
Host smart-11630401-0ce1-42da-9ba2-c2ef182e8bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724194657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.724194657
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3884892658
Short name T920
Test name
Test status
Simulation time 421573489 ps
CPU time 4.58 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 218924 kb
Host smart-42e0adfa-2d10-4595-980c-5bf1dfd7bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884892658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3884892658
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3361233275
Short name T874
Test name
Test status
Simulation time 72728977 ps
CPU time 4.81 seconds
Started May 18 04:13:03 PM PDT 24
Finished May 18 04:13:08 PM PDT 24
Peak memory 213956 kb
Host smart-6464bddc-3da7-4a78-b4a7-4489638e9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361233275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3361233275
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.32816691
Short name T548
Test name
Test status
Simulation time 193909209 ps
CPU time 4.32 seconds
Started May 18 04:13:04 PM PDT 24
Finished May 18 04:13:10 PM PDT 24
Peak memory 208556 kb
Host smart-8c82c70e-b472-4d8b-801a-001a310af9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32816691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.32816691
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.997858480
Short name T1030
Test name
Test status
Simulation time 288878585 ps
CPU time 4.11 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 207164 kb
Host smart-baad81fd-a8f9-4323-bdba-c34a6cb1ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997858480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.997858480
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2190183741
Short name T263
Test name
Test status
Simulation time 256637577 ps
CPU time 2.58 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:13 PM PDT 24
Peak memory 206576 kb
Host smart-a8cd0500-072d-489f-87d4-d0639cc81b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190183741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2190183741
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4008766641
Short name T966
Test name
Test status
Simulation time 359120403 ps
CPU time 6.92 seconds
Started May 18 04:13:04 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 206976 kb
Host smart-83ecedab-4758-4a8f-8adc-86252d754e91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008766641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4008766641
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.456739174
Short name T889
Test name
Test status
Simulation time 369710613 ps
CPU time 7.2 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:25 PM PDT 24
Peak memory 208048 kb
Host smart-db2cd9d6-c9e3-4789-87d0-53d5a608316d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456739174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.456739174
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2163200100
Short name T718
Test name
Test status
Simulation time 3043314425 ps
CPU time 36.84 seconds
Started May 18 04:13:03 PM PDT 24
Finished May 18 04:13:41 PM PDT 24
Peak memory 208212 kb
Host smart-c2c3c448-683a-4a16-a773-8e3d2dd30b57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163200100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2163200100
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2822590491
Short name T688
Test name
Test status
Simulation time 118630964 ps
CPU time 4.16 seconds
Started May 18 04:13:07 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 209924 kb
Host smart-9bcab805-63bb-41fd-a708-acd8c2615fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822590491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2822590491
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3246094619
Short name T876
Test name
Test status
Simulation time 159242914 ps
CPU time 2.5 seconds
Started May 18 04:13:06 PM PDT 24
Finished May 18 04:13:10 PM PDT 24
Peak memory 205844 kb
Host smart-c17ae713-754c-4001-98b9-d444b93af433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246094619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3246094619
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2292246664
Short name T701
Test name
Test status
Simulation time 745108848 ps
CPU time 9.85 seconds
Started May 18 04:13:02 PM PDT 24
Finished May 18 04:13:12 PM PDT 24
Peak memory 218096 kb
Host smart-94ac7d7f-40ba-45d9-a73d-3a887526caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292246664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2292246664
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2007968569
Short name T572
Test name
Test status
Simulation time 34266659 ps
CPU time 1.96 seconds
Started May 18 04:13:06 PM PDT 24
Finished May 18 04:13:09 PM PDT 24
Peak memory 209580 kb
Host smart-7dbbec54-5e51-4306-9775-1122dc14937e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007968569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2007968569
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3444101562
Short name T558
Test name
Test status
Simulation time 126933987 ps
CPU time 1.05 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:15 PM PDT 24
Peak memory 205752 kb
Host smart-8a743e7b-e3cb-4dd6-a569-064de7232dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444101562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3444101562
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2291924852
Short name T398
Test name
Test status
Simulation time 1588116613 ps
CPU time 13.61 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 214052 kb
Host smart-ecea7f75-073f-4582-a492-131d6f9013e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291924852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2291924852
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.607889626
Short name T68
Test name
Test status
Simulation time 1050941547 ps
CPU time 20.97 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:38 PM PDT 24
Peak memory 214108 kb
Host smart-ef764790-b087-4fcd-b665-f97c30d8b74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607889626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.607889626
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.424536241
Short name T799
Test name
Test status
Simulation time 514252350 ps
CPU time 7.3 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:19 PM PDT 24
Peak memory 219420 kb
Host smart-14b5381c-ba6d-467e-8118-997d67987c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424536241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.424536241
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3077683698
Short name T864
Test name
Test status
Simulation time 373448392 ps
CPU time 5.09 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:18 PM PDT 24
Peak memory 209764 kb
Host smart-c5942aa6-9162-48a2-b0ec-db46cc9ac06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077683698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3077683698
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2100238626
Short name T739
Test name
Test status
Simulation time 52518783 ps
CPU time 2.53 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:17 PM PDT 24
Peak memory 214040 kb
Host smart-c2a1fc3f-43a0-4c91-8864-febab36bfafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100238626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2100238626
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4070958004
Short name T577
Test name
Test status
Simulation time 488049747 ps
CPU time 5.1 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:17 PM PDT 24
Peak memory 209644 kb
Host smart-218bdbff-14ee-4b44-8a52-4c832a2a09eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070958004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4070958004
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4179382274
Short name T952
Test name
Test status
Simulation time 242299052 ps
CPU time 5.74 seconds
Started May 18 04:13:07 PM PDT 24
Finished May 18 04:13:13 PM PDT 24
Peak memory 207456 kb
Host smart-a3361b25-68d8-4ba2-89e4-e42a078d02bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179382274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4179382274
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1272022969
Short name T866
Test name
Test status
Simulation time 161839054 ps
CPU time 2.43 seconds
Started May 18 04:13:03 PM PDT 24
Finished May 18 04:13:07 PM PDT 24
Peak memory 206692 kb
Host smart-83236c7f-a02b-4101-b7f0-840becf84695
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272022969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1272022969
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2690117272
Short name T908
Test name
Test status
Simulation time 183709714 ps
CPU time 2.85 seconds
Started May 18 04:13:04 PM PDT 24
Finished May 18 04:13:08 PM PDT 24
Peak memory 206808 kb
Host smart-edaaeefa-5e93-44c7-bf96-1711cbd77feb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690117272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2690117272
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2961702981
Short name T823
Test name
Test status
Simulation time 222717797 ps
CPU time 6.19 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:23 PM PDT 24
Peak memory 206568 kb
Host smart-8228da92-0944-47bc-977e-87b2d43a2b98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961702981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2961702981
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1255476859
Short name T817
Test name
Test status
Simulation time 52874387 ps
CPU time 2.2 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:20 PM PDT 24
Peak memory 209476 kb
Host smart-507d3d86-85f7-4f39-ab3d-5a3634e2217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255476859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1255476859
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3547791835
Short name T1009
Test name
Test status
Simulation time 449789199 ps
CPU time 5.11 seconds
Started May 18 04:13:05 PM PDT 24
Finished May 18 04:13:11 PM PDT 24
Peak memory 206560 kb
Host smart-c2da0e07-32ec-4c16-8b14-dce8c96d48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547791835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3547791835
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.892826439
Short name T106
Test name
Test status
Simulation time 70421512 ps
CPU time 6.01 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:19 PM PDT 24
Peak memory 222280 kb
Host smart-137b2765-fae4-4ee1-873f-fd07a76a5883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892826439 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.892826439
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3990880544
Short name T888
Test name
Test status
Simulation time 808137692 ps
CPU time 20.64 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:34 PM PDT 24
Peak memory 209508 kb
Host smart-976c51e0-3e3f-4f20-81c4-774b6015fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990880544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3990880544
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3112558880
Short name T51
Test name
Test status
Simulation time 93974145 ps
CPU time 1.9 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:16 PM PDT 24
Peak memory 210000 kb
Host smart-45a06be5-f0af-41c6-8968-d7239987f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112558880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3112558880
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2709761539
Short name T764
Test name
Test status
Simulation time 36492323 ps
CPU time 0.8 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:15 PM PDT 24
Peak memory 205604 kb
Host smart-fdc4e063-72bf-461e-8c67-3c0d516cf3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709761539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2709761539
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.855816856
Short name T220
Test name
Test status
Simulation time 981077870 ps
CPU time 51.11 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:14:06 PM PDT 24
Peak memory 214044 kb
Host smart-ef8cf396-28b0-4703-8363-5c993597337a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855816856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.855816856
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1690092925
Short name T65
Test name
Test status
Simulation time 181853838 ps
CPU time 3.9 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:18 PM PDT 24
Peak memory 218332 kb
Host smart-b7bac6f2-55ce-4643-ad21-6d995c291a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690092925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1690092925
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.129471024
Short name T944
Test name
Test status
Simulation time 147420218 ps
CPU time 1.58 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:16 PM PDT 24
Peak memory 206620 kb
Host smart-eda76dc6-b106-4715-a186-e44bb78c0161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129471024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.129471024
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1338855135
Short name T387
Test name
Test status
Simulation time 229261523 ps
CPU time 6.75 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:21 PM PDT 24
Peak memory 209304 kb
Host smart-db28c6e7-491a-4f9c-a01a-04c3e98bad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338855135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1338855135
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1684417671
Short name T776
Test name
Test status
Simulation time 195558808 ps
CPU time 2.86 seconds
Started May 18 04:13:12 PM PDT 24
Finished May 18 04:13:17 PM PDT 24
Peak memory 206512 kb
Host smart-c4b06726-7ae4-4b39-a105-1ccab61488af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684417671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1684417671
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3558438992
Short name T717
Test name
Test status
Simulation time 38039159 ps
CPU time 2.58 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:20 PM PDT 24
Peak memory 208272 kb
Host smart-a062e99b-b87f-4d16-ae46-eda135c4b6a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558438992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3558438992
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2912632255
Short name T748
Test name
Test status
Simulation time 63225882 ps
CPU time 3.4 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:16 PM PDT 24
Peak memory 208204 kb
Host smart-79e9c4e0-cb67-4010-afe2-28fc4da3efad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912632255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2912632255
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1232220728
Short name T1005
Test name
Test status
Simulation time 53759719 ps
CPU time 2.71 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:14 PM PDT 24
Peak memory 206620 kb
Host smart-9d39d48b-4019-4624-8ae4-ffa701dfc0da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232220728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1232220728
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3377772542
Short name T736
Test name
Test status
Simulation time 2117762060 ps
CPU time 23.69 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:34 PM PDT 24
Peak memory 210148 kb
Host smart-3c26fab7-04b9-4a62-9d51-9130c7974131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377772542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3377772542
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.118887913
Short name T911
Test name
Test status
Simulation time 336594125 ps
CPU time 4.64 seconds
Started May 18 04:13:13 PM PDT 24
Finished May 18 04:13:19 PM PDT 24
Peak memory 207924 kb
Host smart-580727dd-9d7a-458e-b7e0-d50e210da851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118887913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.118887913
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1943648519
Short name T698
Test name
Test status
Simulation time 2069015192 ps
CPU time 9.12 seconds
Started May 18 04:13:10 PM PDT 24
Finished May 18 04:13:20 PM PDT 24
Peak memory 208508 kb
Host smart-7cd34b30-7538-4972-bd7d-ecf0d6eea814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943648519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1943648519
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3917858539
Short name T281
Test name
Test status
Simulation time 230423477 ps
CPU time 12.59 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:31 PM PDT 24
Peak memory 222424 kb
Host smart-a21d2051-86d9-4cae-8f6a-c475df3aa1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917858539 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3917858539
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1206685772
Short name T665
Test name
Test status
Simulation time 845222961 ps
CPU time 5.54 seconds
Started May 18 04:13:11 PM PDT 24
Finished May 18 04:13:18 PM PDT 24
Peak memory 207540 kb
Host smart-347dce34-a2b0-4403-87f3-de6632f83019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206685772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1206685772
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.4276060525
Short name T620
Test name
Test status
Simulation time 594838468 ps
CPU time 11.7 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:30 PM PDT 24
Peak memory 210672 kb
Host smart-457fae94-f6ca-419a-b944-7e4cf4728767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276060525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.4276060525
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3522349360
Short name T546
Test name
Test status
Simulation time 10769838 ps
CPU time 0.85 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:23 PM PDT 24
Peak memory 205592 kb
Host smart-61c55bc9-645f-4074-8315-00582010fca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522349360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3522349360
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.594296725
Short name T396
Test name
Test status
Simulation time 463333776 ps
CPU time 6.21 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 214692 kb
Host smart-205b48ee-44a2-4998-8433-6f43a1777a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594296725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.594296725
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1384615368
Short name T288
Test name
Test status
Simulation time 148295204 ps
CPU time 6.3 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 210188 kb
Host smart-e3f10751-25ab-45c3-89d6-2110795e0a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384615368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1384615368
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.266038957
Short name T821
Test name
Test status
Simulation time 394474595 ps
CPU time 8.49 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 217872 kb
Host smart-8dc7efca-0009-426e-849e-0eabaa62a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266038957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.266038957
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1343019848
Short name T357
Test name
Test status
Simulation time 3052726558 ps
CPU time 8.9 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 214096 kb
Host smart-9af02fb7-37c6-4b98-b467-826ae4695948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343019848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1343019848
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2930625803
Short name T329
Test name
Test status
Simulation time 199959005 ps
CPU time 2.86 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 209380 kb
Host smart-b7b9236a-6a6e-4472-81c8-060ac12b8a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930625803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2930625803
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2923720746
Short name T674
Test name
Test status
Simulation time 653224073 ps
CPU time 7.98 seconds
Started May 18 04:13:20 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 209420 kb
Host smart-bb99ba41-ca37-4531-aaf6-bdb62519207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923720746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2923720746
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3278151797
Short name T719
Test name
Test status
Simulation time 342157933 ps
CPU time 7.31 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:26 PM PDT 24
Peak memory 208676 kb
Host smart-84dbcb02-b29b-42be-8e85-c689f7fd72a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278151797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3278151797
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3419351312
Short name T1025
Test name
Test status
Simulation time 107619552 ps
CPU time 2.72 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 208304 kb
Host smart-36a18655-6863-4ba8-a009-d3568659f48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419351312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3419351312
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2839843491
Short name T950
Test name
Test status
Simulation time 45304857 ps
CPU time 2.52 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:25 PM PDT 24
Peak memory 206580 kb
Host smart-5c8047ca-2858-46ea-ae4c-61b385ebef23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839843491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2839843491
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1282550531
Short name T742
Test name
Test status
Simulation time 1726207106 ps
CPU time 39.29 seconds
Started May 18 04:13:17 PM PDT 24
Finished May 18 04:13:57 PM PDT 24
Peak memory 208240 kb
Host smart-11e3af24-3935-4eae-b5b6-8b1ef50f21de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282550531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1282550531
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3440517928
Short name T335
Test name
Test status
Simulation time 106324091 ps
CPU time 4.26 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:24 PM PDT 24
Peak memory 208300 kb
Host smart-b170ed89-251b-4f46-8508-8bc091bfde85
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440517928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3440517928
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1033795994
Short name T653
Test name
Test status
Simulation time 90885680 ps
CPU time 2.07 seconds
Started May 18 04:13:20 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 215568 kb
Host smart-30b825f7-06cf-41f2-b919-383cff13cad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033795994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1033795994
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1800387254
Short name T886
Test name
Test status
Simulation time 802785473 ps
CPU time 3.81 seconds
Started May 18 04:13:14 PM PDT 24
Finished May 18 04:13:19 PM PDT 24
Peak memory 208300 kb
Host smart-a123c868-ac3d-46f6-b03d-e0eb1390640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800387254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1800387254
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2229907022
Short name T1059
Test name
Test status
Simulation time 292937924 ps
CPU time 8.46 seconds
Started May 18 04:13:25 PM PDT 24
Finished May 18 04:13:34 PM PDT 24
Peak memory 207688 kb
Host smart-b2444845-8a42-4043-87b7-9682260a9324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229907022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2229907022
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4215350324
Short name T602
Test name
Test status
Simulation time 37877699 ps
CPU time 2 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:24 PM PDT 24
Peak memory 209668 kb
Host smart-af2d0b9e-4e27-4d93-b9c4-31526f8bbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215350324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4215350324
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.358722291
Short name T81
Test name
Test status
Simulation time 13324745 ps
CPU time 0.92 seconds
Started May 18 04:13:22 PM PDT 24
Finished May 18 04:13:24 PM PDT 24
Peak memory 205528 kb
Host smart-7f04f77e-17d2-4195-9336-5e03f2fb759a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358722291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.358722291
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2207624361
Short name T791
Test name
Test status
Simulation time 56918819 ps
CPU time 2.14 seconds
Started May 18 04:13:18 PM PDT 24
Finished May 18 04:13:22 PM PDT 24
Peak memory 207932 kb
Host smart-f656987f-75cf-4bdc-842a-b1c4c5308920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207624361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2207624361
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2777227868
Short name T590
Test name
Test status
Simulation time 310447646 ps
CPU time 9.79 seconds
Started May 18 04:13:31 PM PDT 24
Finished May 18 04:13:41 PM PDT 24
Peak memory 208968 kb
Host smart-20598979-dd12-46f7-a4be-978d86219e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777227868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2777227868
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3198854597
Short name T330
Test name
Test status
Simulation time 426650941 ps
CPU time 12.28 seconds
Started May 18 04:13:17 PM PDT 24
Finished May 18 04:13:31 PM PDT 24
Peak memory 222112 kb
Host smart-91134f78-d104-4839-a791-0b5edd958c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198854597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3198854597
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.149447193
Short name T303
Test name
Test status
Simulation time 252641837 ps
CPU time 7.99 seconds
Started May 18 04:13:16 PM PDT 24
Finished May 18 04:13:26 PM PDT 24
Peak memory 217920 kb
Host smart-0544ae19-c043-454e-aa3e-324444f67348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149447193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.149447193
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.818683478
Short name T770
Test name
Test status
Simulation time 124753336 ps
CPU time 3 seconds
Started May 18 04:13:24 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 206520 kb
Host smart-e0aef599-420c-4ea3-843b-d51e4ffe64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818683478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.818683478
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3894721642
Short name T975
Test name
Test status
Simulation time 204124735 ps
CPU time 2.82 seconds
Started May 18 04:13:26 PM PDT 24
Finished May 18 04:13:30 PM PDT 24
Peak memory 206572 kb
Host smart-a3d41658-b154-49cb-873c-f38961d55c5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894721642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3894721642
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3194617496
Short name T651
Test name
Test status
Simulation time 2043808674 ps
CPU time 6.85 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:29 PM PDT 24
Peak memory 208052 kb
Host smart-ba466273-b85d-4853-8a3b-31ec3ad2e1cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194617496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3194617496
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3986575344
Short name T831
Test name
Test status
Simulation time 43722010 ps
CPU time 2.4 seconds
Started May 18 04:13:22 PM PDT 24
Finished May 18 04:13:25 PM PDT 24
Peak memory 206832 kb
Host smart-246bcb72-a3f0-48d4-89de-a445dff7d3fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986575344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3986575344
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3534892387
Short name T691
Test name
Test status
Simulation time 345950047 ps
CPU time 4.97 seconds
Started May 18 04:13:19 PM PDT 24
Finished May 18 04:13:25 PM PDT 24
Peak memory 214036 kb
Host smart-445aca96-357b-4ba4-b1b7-b963ac6beeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534892387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3534892387
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3767415377
Short name T938
Test name
Test status
Simulation time 196577261 ps
CPU time 2.22 seconds
Started May 18 04:13:17 PM PDT 24
Finished May 18 04:13:21 PM PDT 24
Peak memory 206520 kb
Host smart-257e4202-4d35-4f45-8634-22263699196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767415377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3767415377
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3773252160
Short name T951
Test name
Test status
Simulation time 2691404992 ps
CPU time 19.31 seconds
Started May 18 04:13:17 PM PDT 24
Finished May 18 04:13:38 PM PDT 24
Peak memory 216528 kb
Host smart-c25cd38a-8f38-46fe-acf7-6586a89ca078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773252160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3773252160
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1410491594
Short name T948
Test name
Test status
Simulation time 169846319 ps
CPU time 5.55 seconds
Started May 18 04:13:21 PM PDT 24
Finished May 18 04:13:28 PM PDT 24
Peak memory 207056 kb
Host smart-7bfa7751-8d6c-46f4-aa74-047e96197ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410491594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1410491594
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3204275475
Short name T53
Test name
Test status
Simulation time 73766999 ps
CPU time 2.63 seconds
Started May 18 04:13:20 PM PDT 24
Finished May 18 04:13:23 PM PDT 24
Peak memory 210280 kb
Host smart-b1722e9e-528d-4f5b-bdeb-9ace7bd41102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204275475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3204275475
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2542093583
Short name T721
Test name
Test status
Simulation time 47861599 ps
CPU time 0.85 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:25 PM PDT 24
Peak memory 205492 kb
Host smart-44c6a074-f9c3-4f9e-a08a-40254b336468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542093583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2542093583
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3351923622
Short name T1020
Test name
Test status
Simulation time 27162293 ps
CPU time 1.56 seconds
Started May 18 04:10:16 PM PDT 24
Finished May 18 04:10:19 PM PDT 24
Peak memory 208384 kb
Host smart-f4821f1c-0ff1-452b-9a62-35dd081fd0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351923622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3351923622
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2843321572
Short name T872
Test name
Test status
Simulation time 10062197477 ps
CPU time 30.51 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 214080 kb
Host smart-786572f0-fcad-45cf-b307-1ff476ab9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843321572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2843321572
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4082457234
Short name T250
Test name
Test status
Simulation time 123169655 ps
CPU time 4.06 seconds
Started May 18 04:10:11 PM PDT 24
Finished May 18 04:10:15 PM PDT 24
Peak memory 214008 kb
Host smart-f6bce1f0-5de2-45ff-8ea0-8530d085f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082457234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4082457234
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3571560278
Short name T828
Test name
Test status
Simulation time 410174230 ps
CPU time 4.17 seconds
Started May 18 04:10:17 PM PDT 24
Finished May 18 04:10:23 PM PDT 24
Peak memory 207984 kb
Host smart-b98aa20f-19fb-4966-9823-a3f63d881ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571560278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3571560278
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2725415622
Short name T365
Test name
Test status
Simulation time 210455335 ps
CPU time 4.97 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:21 PM PDT 24
Peak memory 208612 kb
Host smart-fe7880e9-f1f2-408b-b3af-f5ac739a7998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725415622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2725415622
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1351846428
Short name T802
Test name
Test status
Simulation time 16833371241 ps
CPU time 57.05 seconds
Started May 18 04:10:12 PM PDT 24
Finished May 18 04:11:09 PM PDT 24
Peak memory 208372 kb
Host smart-f74c08e0-f692-4874-b9d1-d7b5d45420a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351846428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1351846428
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.426529248
Short name T786
Test name
Test status
Simulation time 789584408 ps
CPU time 7.39 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:21 PM PDT 24
Peak memory 207588 kb
Host smart-8c37d8d3-9d27-4730-bc92-4fe958947013
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426529248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.426529248
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.890283013
Short name T587
Test name
Test status
Simulation time 210148692 ps
CPU time 3.26 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:17 PM PDT 24
Peak memory 206508 kb
Host smart-2d326f0f-67b3-4fa6-bffb-ae4da30d44cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890283013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.890283013
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.110874129
Short name T968
Test name
Test status
Simulation time 65217783 ps
CPU time 3.25 seconds
Started May 18 04:10:14 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 208636 kb
Host smart-235c5c98-508a-410a-a286-56b491e42eba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110874129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.110874129
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3373457653
Short name T361
Test name
Test status
Simulation time 1562055049 ps
CPU time 29.28 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:45 PM PDT 24
Peak memory 208548 kb
Host smart-08eda81d-2c20-4fd7-8851-2efdab20ee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373457653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3373457653
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3043697544
Short name T177
Test name
Test status
Simulation time 116307100 ps
CPU time 2.24 seconds
Started May 18 04:10:15 PM PDT 24
Finished May 18 04:10:18 PM PDT 24
Peak memory 206524 kb
Host smart-686dc521-abe8-4931-8b06-e0a6505474bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043697544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3043697544
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2588335573
Short name T884
Test name
Test status
Simulation time 375190686 ps
CPU time 10.49 seconds
Started May 18 04:10:13 PM PDT 24
Finished May 18 04:10:24 PM PDT 24
Peak memory 219848 kb
Host smart-afea34af-3e98-47d0-8ac0-6be6b1d5f210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588335573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2588335573
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4165981370
Short name T1056
Test name
Test status
Simulation time 1162659497 ps
CPU time 11.4 seconds
Started May 18 04:10:14 PM PDT 24
Finished May 18 04:10:27 PM PDT 24
Peak memory 222012 kb
Host smart-2de78f11-5ba3-4d89-b6c4-e0f863fad68d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165981370 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4165981370
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.64861093
Short name T996
Test name
Test status
Simulation time 688970139 ps
CPU time 18.09 seconds
Started May 18 04:10:17 PM PDT 24
Finished May 18 04:10:35 PM PDT 24
Peak memory 214048 kb
Host smart-1b9412cc-019b-4ea8-b7c9-e1262e5d2ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64861093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.64861093
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2136072664
Short name T102
Test name
Test status
Simulation time 44664712 ps
CPU time 0.87 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:21 PM PDT 24
Peak memory 205480 kb
Host smart-e00a1a6d-b553-4460-93be-c1478658487d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136072664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2136072664
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2605896062
Short name T362
Test name
Test status
Simulation time 64575319 ps
CPU time 3.02 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:23 PM PDT 24
Peak memory 214052 kb
Host smart-3da3f638-00a2-45ad-8580-379095c04f6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605896062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2605896062
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2528480658
Short name T17
Test name
Test status
Simulation time 100813040 ps
CPU time 2.33 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:22 PM PDT 24
Peak memory 222528 kb
Host smart-5f9964f9-0b3b-463a-8814-d16406e5e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528480658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2528480658
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1983876462
Short name T62
Test name
Test status
Simulation time 91274340 ps
CPU time 1.92 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:26 PM PDT 24
Peak memory 206820 kb
Host smart-4b4f9d7d-d519-4d4f-991a-538400e6f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983876462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1983876462
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1965099492
Short name T947
Test name
Test status
Simulation time 542208230 ps
CPU time 14.32 seconds
Started May 18 04:10:21 PM PDT 24
Finished May 18 04:10:36 PM PDT 24
Peak memory 214244 kb
Host smart-4dbe23b7-7c8f-4b89-b332-4f4d5bad9697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965099492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1965099492
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3182905376
Short name T958
Test name
Test status
Simulation time 385249368 ps
CPU time 4.75 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:28 PM PDT 24
Peak memory 217436 kb
Host smart-3e43f95b-4b15-4f15-b729-3aa2744243a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182905376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3182905376
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.345364086
Short name T560
Test name
Test status
Simulation time 11914380596 ps
CPU time 64.95 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:11:28 PM PDT 24
Peak memory 208108 kb
Host smart-536acf70-9f9d-4a93-8a01-02283d07a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345364086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.345364086
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2396049669
Short name T228
Test name
Test status
Simulation time 96624621 ps
CPU time 2.81 seconds
Started May 18 04:10:23 PM PDT 24
Finished May 18 04:10:27 PM PDT 24
Peak memory 206544 kb
Host smart-590b7f40-d2b5-4571-9b3c-60537e3234bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396049669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2396049669
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2340242952
Short name T679
Test name
Test status
Simulation time 346755574 ps
CPU time 8.1 seconds
Started May 18 04:10:21 PM PDT 24
Finished May 18 04:10:31 PM PDT 24
Peak memory 207456 kb
Host smart-7118ecf2-3131-4285-9e8f-5c13c8136c0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340242952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2340242952
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2354150056
Short name T1039
Test name
Test status
Simulation time 42038006 ps
CPU time 2.33 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:23 PM PDT 24
Peak memory 206600 kb
Host smart-d9b83fb8-75a8-4a95-b780-e0c9294406ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354150056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2354150056
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.902600526
Short name T617
Test name
Test status
Simulation time 146468829 ps
CPU time 5.01 seconds
Started May 18 04:10:20 PM PDT 24
Finished May 18 04:10:25 PM PDT 24
Peak memory 207748 kb
Host smart-4acbfccf-fe9f-4d0a-a6cc-d18f3a0e1314
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902600526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.902600526
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1016005711
Short name T972
Test name
Test status
Simulation time 42330206 ps
CPU time 2.1 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:25 PM PDT 24
Peak memory 217896 kb
Host smart-059e917a-cb4a-497f-a07d-3fb31dfd213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016005711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1016005711
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1309066586
Short name T754
Test name
Test status
Simulation time 1044178423 ps
CPU time 5.13 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:25 PM PDT 24
Peak memory 208140 kb
Host smart-8981a27c-22bd-409c-8b55-2f03c8e2b843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309066586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1309066586
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3941387334
Short name T836
Test name
Test status
Simulation time 385082775 ps
CPU time 14.63 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:38 PM PDT 24
Peak memory 222304 kb
Host smart-47019f07-bb60-4ee3-92a7-f06c2562ecd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941387334 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3941387334
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1818836961
Short name T907
Test name
Test status
Simulation time 537130323 ps
CPU time 5.39 seconds
Started May 18 04:10:21 PM PDT 24
Finished May 18 04:10:27 PM PDT 24
Peak memory 213924 kb
Host smart-61d4693d-a946-405b-b10c-e6d261dbe241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818836961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1818836961
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1606062272
Short name T893
Test name
Test status
Simulation time 2566588053 ps
CPU time 4.92 seconds
Started May 18 04:10:21 PM PDT 24
Finished May 18 04:10:28 PM PDT 24
Peak memory 210512 kb
Host smart-9f9f1d31-4e6b-4af3-bbeb-36217b737f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606062272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1606062272
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.371638191
Short name T918
Test name
Test status
Simulation time 70900630 ps
CPU time 0.82 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:36 PM PDT 24
Peak memory 205488 kb
Host smart-05e24789-3150-4af2-8cec-c5a8d76e6e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371638191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.371638191
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4100889608
Short name T268
Test name
Test status
Simulation time 209494494 ps
CPU time 9.7 seconds
Started May 18 04:10:28 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 215004 kb
Host smart-f7267912-6a1a-415a-9f3c-4f5e723fd8a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100889608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4100889608
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.404179103
Short name T843
Test name
Test status
Simulation time 104405796 ps
CPU time 3.87 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 217508 kb
Host smart-f8191af1-29e0-4684-923d-f24bc25a3ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404179103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.404179103
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.562676191
Short name T547
Test name
Test status
Simulation time 40372843 ps
CPU time 1.82 seconds
Started May 18 04:10:25 PM PDT 24
Finished May 18 04:10:29 PM PDT 24
Peak memory 206384 kb
Host smart-e496a001-d952-471f-8f4a-89ac4c1e6bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562676191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.562676191
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.208493454
Short name T372
Test name
Test status
Simulation time 265751995 ps
CPU time 3.89 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 208628 kb
Host smart-8a162c0a-1416-4654-940d-1e2404c25830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208493454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.208493454
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3834431402
Short name T890
Test name
Test status
Simulation time 522274948 ps
CPU time 4.51 seconds
Started May 18 04:10:38 PM PDT 24
Finished May 18 04:10:44 PM PDT 24
Peak memory 219744 kb
Host smart-005712ee-f9cb-42a5-b59b-945f43094557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834431402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3834431402
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1806253563
Short name T922
Test name
Test status
Simulation time 178322685 ps
CPU time 4.52 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 217924 kb
Host smart-2990cecc-6da0-43c2-994f-07941971f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806253563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1806253563
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1654597485
Short name T366
Test name
Test status
Simulation time 926003423 ps
CPU time 6.29 seconds
Started May 18 04:10:19 PM PDT 24
Finished May 18 04:10:26 PM PDT 24
Peak memory 206432 kb
Host smart-892e8a6e-9434-4bd7-8523-a151f3a3e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654597485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1654597485
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2591313773
Short name T585
Test name
Test status
Simulation time 2668877623 ps
CPU time 6.76 seconds
Started May 18 04:10:23 PM PDT 24
Finished May 18 04:10:31 PM PDT 24
Peak memory 208224 kb
Host smart-43b8a9f0-4dc5-42c6-9ebe-378c6949b551
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591313773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2591313773
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1139361725
Short name T375
Test name
Test status
Simulation time 285889600 ps
CPU time 3.69 seconds
Started May 18 04:10:23 PM PDT 24
Finished May 18 04:10:28 PM PDT 24
Peak memory 207984 kb
Host smart-14bba1d6-e90b-437d-997b-7c7878c9d441
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139361725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1139361725
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.869361018
Short name T997
Test name
Test status
Simulation time 540990992 ps
CPU time 3.13 seconds
Started May 18 04:10:20 PM PDT 24
Finished May 18 04:10:24 PM PDT 24
Peak memory 206600 kb
Host smart-82bcdcea-06a9-4e7d-a263-4af06709eee5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869361018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.869361018
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4214276613
Short name T232
Test name
Test status
Simulation time 405714484 ps
CPU time 4.54 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 214092 kb
Host smart-30ac9c93-669a-4d57-ba04-30fefb087149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214276613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4214276613
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1790670577
Short name T744
Test name
Test status
Simulation time 2610952237 ps
CPU time 24.15 seconds
Started May 18 04:10:22 PM PDT 24
Finished May 18 04:10:48 PM PDT 24
Peak memory 208896 kb
Host smart-2c5aca4d-7909-4bc5-8f80-0a43e1a9bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790670577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1790670577
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.433289781
Short name T969
Test name
Test status
Simulation time 149558646 ps
CPU time 6.96 seconds
Started May 18 04:10:38 PM PDT 24
Finished May 18 04:10:46 PM PDT 24
Peak memory 219416 kb
Host smart-4efb4c9e-256b-471f-aa65-cf33354d24cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433289781 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.433289781
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1439842906
Short name T1052
Test name
Test status
Simulation time 154087149 ps
CPU time 4.64 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 207328 kb
Host smart-9786725c-e7e3-40a8-9575-1e6c082ea731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439842906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1439842906
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1101220527
Short name T576
Test name
Test status
Simulation time 57035256 ps
CPU time 2.57 seconds
Started May 18 04:10:25 PM PDT 24
Finished May 18 04:10:30 PM PDT 24
Peak memory 209852 kb
Host smart-1dc9367e-87dd-4453-9806-bf8c1e8006af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101220527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1101220527
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1683048440
Short name T803
Test name
Test status
Simulation time 12789550 ps
CPU time 0.89 seconds
Started May 18 04:10:40 PM PDT 24
Finished May 18 04:10:42 PM PDT 24
Peak memory 205708 kb
Host smart-b27b7fc6-bba5-40ef-a2a8-b046700b2527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683048440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1683048440
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.680260391
Short name T257
Test name
Test status
Simulation time 59100702 ps
CPU time 4.18 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 215240 kb
Host smart-7c429ec9-2604-45d1-82b1-ec4d8d8782c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680260391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.680260391
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.17769714
Short name T902
Test name
Test status
Simulation time 91423923 ps
CPU time 3.04 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 221500 kb
Host smart-50fb6f97-8b80-4756-9ef4-fa246edab79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17769714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.17769714
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2684934357
Short name T312
Test name
Test status
Simulation time 118560582 ps
CPU time 1.89 seconds
Started May 18 04:10:39 PM PDT 24
Finished May 18 04:10:42 PM PDT 24
Peak memory 209940 kb
Host smart-309c5552-0ca7-4888-8d69-7e5e481b2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684934357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2684934357
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1975883775
Short name T1029
Test name
Test status
Simulation time 2263487183 ps
CPU time 5.78 seconds
Started May 18 04:10:28 PM PDT 24
Finished May 18 04:10:35 PM PDT 24
Peak memory 208308 kb
Host smart-e2cdc3a6-ac11-41ff-8e13-ee4ff80be247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975883775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1975883775
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2276622809
Short name T95
Test name
Test status
Simulation time 316651939 ps
CPU time 9.06 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:43 PM PDT 24
Peak memory 222048 kb
Host smart-471d2509-1d21-4f69-b583-cd6e8223e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276622809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2276622809
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1084745509
Short name T853
Test name
Test status
Simulation time 222166798 ps
CPU time 3.3 seconds
Started May 18 04:10:30 PM PDT 24
Finished May 18 04:10:34 PM PDT 24
Peak memory 207480 kb
Host smart-a2f5ad48-b733-4d43-8729-93b6d24f9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084745509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1084745509
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3927272373
Short name T226
Test name
Test status
Simulation time 140978412 ps
CPU time 4.3 seconds
Started May 18 04:10:25 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 217880 kb
Host smart-9ef8fc8a-9ebb-461e-a4f5-7134e963f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927272373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3927272373
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2102532578
Short name T815
Test name
Test status
Simulation time 85790059 ps
CPU time 1.93 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:29 PM PDT 24
Peak memory 206560 kb
Host smart-1d20c174-7768-4f5d-8b8b-e385b5127046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102532578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2102532578
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3312005386
Short name T774
Test name
Test status
Simulation time 1540770839 ps
CPU time 4.72 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 208168 kb
Host smart-cc7a1be0-1527-4572-ad6d-f99f256d6d70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312005386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3312005386
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.184163255
Short name T196
Test name
Test status
Simulation time 35179948 ps
CPU time 2.31 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:30 PM PDT 24
Peak memory 206960 kb
Host smart-e436f5d5-4912-4548-a8de-0b8037f4f0c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184163255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.184163255
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1141099075
Short name T814
Test name
Test status
Simulation time 267770420 ps
CPU time 3.45 seconds
Started May 18 04:10:39 PM PDT 24
Finished May 18 04:10:44 PM PDT 24
Peak memory 208676 kb
Host smart-a69164a4-0518-4e40-ace3-80be8bc12c17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141099075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1141099075
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1940301154
Short name T186
Test name
Test status
Simulation time 56776278 ps
CPU time 2.67 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:10:31 PM PDT 24
Peak memory 208272 kb
Host smart-19e02c13-0377-4878-a6cf-4895ee7fe382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940301154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1940301154
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3067495839
Short name T646
Test name
Test status
Simulation time 83029276 ps
CPU time 2.43 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:38 PM PDT 24
Peak memory 206464 kb
Host smart-446c3515-710d-41a3-8d37-5694c908cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067495839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3067495839
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1564806268
Short name T358
Test name
Test status
Simulation time 4552436575 ps
CPU time 48.77 seconds
Started May 18 04:10:26 PM PDT 24
Finished May 18 04:11:16 PM PDT 24
Peak memory 216040 kb
Host smart-55139487-0508-4b2e-92de-cdc532fdc837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564806268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1564806268
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2387221305
Short name T402
Test name
Test status
Simulation time 700020735 ps
CPU time 4.21 seconds
Started May 18 04:10:27 PM PDT 24
Finished May 18 04:10:32 PM PDT 24
Peak memory 222344 kb
Host smart-b099f17a-2c82-4971-b1e3-17bca8eed882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387221305 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2387221305
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.281644489
Short name T963
Test name
Test status
Simulation time 258154627 ps
CPU time 6.28 seconds
Started May 18 04:10:25 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 208360 kb
Host smart-a67af7a2-175d-45b5-bafe-ae5d4aa9b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281644489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.281644489
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1025268881
Short name T932
Test name
Test status
Simulation time 63966814 ps
CPU time 2.55 seconds
Started May 18 04:10:25 PM PDT 24
Finished May 18 04:10:30 PM PDT 24
Peak memory 209844 kb
Host smart-66bf7d5f-b06f-4d60-aca5-bd85521332cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025268881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1025268881
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.931696176
Short name T894
Test name
Test status
Simulation time 126240547 ps
CPU time 0.84 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:37 PM PDT 24
Peak memory 205468 kb
Host smart-232c2a60-71f3-420f-8532-dee8a4cd2c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931696176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.931696176
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4164016502
Short name T343
Test name
Test status
Simulation time 40160236 ps
CPU time 2.96 seconds
Started May 18 04:10:36 PM PDT 24
Finished May 18 04:10:40 PM PDT 24
Peak memory 215488 kb
Host smart-d6e68d1e-e6f3-4e1e-9698-67d11cc175bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164016502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4164016502
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2439520667
Short name T970
Test name
Test status
Simulation time 1053153123 ps
CPU time 7.27 seconds
Started May 18 04:10:35 PM PDT 24
Finished May 18 04:10:44 PM PDT 24
Peak memory 217884 kb
Host smart-ef9b0f58-3971-4e9f-87b9-6ecfeb8ee311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439520667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2439520667
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2413500714
Short name T279
Test name
Test status
Simulation time 29914237 ps
CPU time 1.62 seconds
Started May 18 04:10:31 PM PDT 24
Finished May 18 04:10:33 PM PDT 24
Peak memory 207288 kb
Host smart-18880c95-34f2-42db-964f-f4457c310bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413500714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2413500714
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3086134662
Short name T5
Test name
Test status
Simulation time 6270328359 ps
CPU time 20.72 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:57 PM PDT 24
Peak memory 208992 kb
Host smart-bb9b9009-c0eb-4063-8715-725def58c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086134662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3086134662
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1045830279
Short name T369
Test name
Test status
Simulation time 568761041 ps
CPU time 21.23 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:58 PM PDT 24
Peak memory 222160 kb
Host smart-e8ef1329-a153-493c-a97f-0c886adbd171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045830279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1045830279
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3054688509
Short name T683
Test name
Test status
Simulation time 495799457 ps
CPU time 3.81 seconds
Started May 18 04:10:32 PM PDT 24
Finished May 18 04:10:37 PM PDT 24
Peak memory 208908 kb
Host smart-0ad39322-1a50-4372-8975-e7d93e7b1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054688509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3054688509
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3130641903
Short name T704
Test name
Test status
Simulation time 114128550 ps
CPU time 5.02 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:42 PM PDT 24
Peak memory 207436 kb
Host smart-15781a9c-7cea-48cc-8c5e-a3eca2694617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130641903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3130641903
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1361124154
Short name T934
Test name
Test status
Simulation time 61169042 ps
CPU time 3.28 seconds
Started May 18 04:10:35 PM PDT 24
Finished May 18 04:10:40 PM PDT 24
Peak memory 208212 kb
Host smart-01918315-a839-4f3f-9b1c-bf77cc7a3463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361124154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1361124154
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2519886675
Short name T559
Test name
Test status
Simulation time 36133435 ps
CPU time 2.36 seconds
Started May 18 04:10:36 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 206576 kb
Host smart-975919b9-a981-427d-a6e9-761391ce8ddc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519886675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2519886675
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.494707064
Short name T381
Test name
Test status
Simulation time 174825654 ps
CPU time 5.16 seconds
Started May 18 04:10:32 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 208288 kb
Host smart-265f738e-dda7-48e3-9e35-74a6e870726d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494707064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.494707064
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3945238867
Short name T985
Test name
Test status
Simulation time 80073899 ps
CPU time 3.07 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:39 PM PDT 24
Peak memory 206572 kb
Host smart-49e020b7-1a2e-41ff-8c5f-66dc78170567
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945238867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3945238867
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.372991377
Short name T711
Test name
Test status
Simulation time 272595485 ps
CPU time 3.8 seconds
Started May 18 04:10:36 PM PDT 24
Finished May 18 04:10:41 PM PDT 24
Peak memory 209424 kb
Host smart-64c9b2d1-48d3-4516-ba79-e278ca119128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372991377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.372991377
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2004184132
Short name T1048
Test name
Test status
Simulation time 760101070 ps
CPU time 20.08 seconds
Started May 18 04:10:34 PM PDT 24
Finished May 18 04:10:56 PM PDT 24
Peak memory 208332 kb
Host smart-322b229c-bf25-4212-a1d6-514fdceb9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004184132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2004184132
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.381423417
Short name T290
Test name
Test status
Simulation time 210700319 ps
CPU time 9.69 seconds
Started May 18 04:10:32 PM PDT 24
Finished May 18 04:10:43 PM PDT 24
Peak memory 221212 kb
Host smart-a177a401-83fb-4648-969a-1b04a889a354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381423417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.381423417
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1409892555
Short name T796
Test name
Test status
Simulation time 7969113642 ps
CPU time 19.82 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:55 PM PDT 24
Peak memory 208332 kb
Host smart-5583be47-c83f-4a65-b007-757ddd6c0c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409892555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1409892555
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.499980442
Short name T882
Test name
Test status
Simulation time 48017173 ps
CPU time 2.14 seconds
Started May 18 04:10:33 PM PDT 24
Finished May 18 04:10:38 PM PDT 24
Peak memory 209324 kb
Host smart-ba4f04cc-d0c7-4226-b974-88e41c9e3b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499980442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.499980442
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%