Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
79.37 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 0 14 100.00
Crosses 49 13 36 73.47


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 0 5 100.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 12 23 65.71 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 81 1 T40 1 T41 1 T42 1
auto[OpGenId] 19 1 T41 1 T118 2 T62 1
auto[OpGenSwOut] 30 1 T7 1 T53 1 T221 2
auto[OpGenHwOut] 31 1 T7 1 T8 1 T221 1
auto[OpDisable] 1 1 T221 1 - - - -


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1596 1 T25 3 T59 2 T7 2
auto[StInit] 174 1 T1 1 T40 1 T49 1
auto[StCreatorRootKey] 60 1 T16 1 T7 1 T53 1
auto[StOwnerIntKey] 27 1 T17 1 T55 1 T54 1
auto[StOwnerKey] 35 1 T2 1 T41 1 T118 1
auto[StDisabled] 379 1 T25 7 T34 1 T59 11
auto[StInvalid] 39 1 T35 1 T50 1 T24 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3213 1 T1 2 T2 2 T3 1
auto[1] 162 1 T40 1 T7 2 T41 2


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1583 1 T25 3 T59 2 T7 2
auto[StReset] auto[1] 13 1 T222 2 T223 1 T46 1
auto[StInit] auto[0] 85 1 T1 1 T49 1 T224 1
auto[StInit] auto[1] 89 1 T40 1 T7 1 T53 1
auto[StCreatorRootKey] auto[0] 36 1 T16 1 T53 1 T52 1
auto[StCreatorRootKey] auto[1] 24 1 T7 1 T42 1 T8 1
auto[StOwnerIntKey] auto[0] 18 1 T17 1 T55 1 T54 1
auto[StOwnerIntKey] auto[1] 9 1 T225 1 T226 1 T12 1
auto[StOwnerKey] auto[0] 25 1 T2 1 T36 1 T61 1
auto[StOwnerKey] auto[1] 10 1 T41 1 T118 1 T62 1
auto[StDisabled] auto[0] 362 1 T25 7 T34 1 T59 11
auto[StDisabled] auto[1] 17 1 T41 1 T64 1 T37 1
auto[StInvalid] auto[0] 39 1 T35 1 T50 1 T24 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 12 23 65.71 12


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId] , auto[OpGenSwOut]] -- -- 2
[auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]] [auto[OpDisable]] -- -- 4


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 12 1 T222 2 T223 1 T46 1
auto[StReset] auto[OpGenHwOut] 1 1 T163 1 - - - -
auto[StInit] auto[OpAdvance] 41 1 T40 1 T221 2 T72 1
auto[StInit] auto[OpGenId] 11 1 T118 1 T227 1 T228 2
auto[StInit] auto[OpGenSwOut] 18 1 T53 1 T221 2 T73 1
auto[StInit] auto[OpGenHwOut] 18 1 T7 1 T221 1 T229 1
auto[StInit] auto[OpDisable] 1 1 T221 1 - - - -
auto[StCreatorRootKey] auto[OpAdvance] 12 1 T42 1 T227 1 T223 1
auto[StCreatorRootKey] auto[OpGenId] 2 1 T230 1 T231 1 - -
auto[StCreatorRootKey] auto[OpGenSwOut] 4 1 T7 1 T227 1 T232 1
auto[StCreatorRootKey] auto[OpGenHwOut] 6 1 T8 1 T31 1 T233 1
auto[StOwnerIntKey] auto[OpAdvance] 2 1 T225 1 T12 1 - -
auto[StOwnerIntKey] auto[OpGenId] 1 1 T234 1 - - - -
auto[StOwnerIntKey] auto[OpGenSwOut] 3 1 T57 1 T162 1 T235 1
auto[StOwnerIntKey] auto[OpGenHwOut] 3 1 T226 1 T161 1 T236 1
auto[StOwnerKey] auto[OpAdvance] 4 1 T237 1 T63 1 T238 1
auto[StOwnerKey] auto[OpGenId] 4 1 T41 1 T118 1 T62 1
auto[StOwnerKey] auto[OpGenSwOut] 1 1 T239 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T240 1 - - - -
auto[StDisabled] auto[OpAdvance] 10 1 T41 1 T64 1 T37 1
auto[StDisabled] auto[OpGenId] 1 1 T46 1 - - - -
auto[StDisabled] auto[OpGenSwOut] 4 1 T241 1 T242 1 T243 1
auto[StDisabled] auto[OpGenHwOut] 2 1 T244 1 T245 1 - -