Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11325

1

T1

1

T2

14

T4

5

auto[Attestation]

7884

1

T2

5

T4

3

T5

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2822	1			T2	3		T4	1		T6	2
auto[Aes]	3472	1			T2	1		T4	1		T5	3
auto[Kmac]	3387	1			T4	1		T5	2		T6	5
auto[Otbn]	3495	1			T2	2		T4	1		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7512	1			T1	1		T2	4		T4	8
auto[OpGenId]	6033	1			T1	1		T2	13		T4	4
auto[OpGenSwOut]	5913	1			T2	4		T4	4		T5	4
auto[OpGenHwOut]	7263	1			T2	2		T5	3		T6	12
auto[OpDisable]	137	1			T25	1		T44	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9924

1

T1

1

T2

12

T4

8

auto[OpDoneFail]

16934

1

T1

1

T2

11

T4

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6482	1			T1	1		T2	10		T4	1
auto[StInit]	4346	1			T1	1		T2	3		T4	2
auto[StCreatorRootKey]	3003	1			T2	4		T4	2		T5	2
auto[StOwnerIntKey]	2587	1			T2	5		T4	2		T5	2
auto[StOwnerKey]	2222	1			T2	1		T4	2		T5	2
auto[StDisabled]	7365	1			T4	7		T5	7		T6	17
auto[StInvalid]	853	1			T35	14		T50	30		T24	21

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	329	1			T16	3		T18	3		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	121	1			T15	1		T25	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	68	1			T59	1		T52	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	80	1			T2	1		T88	1		T150	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T25	1		T59	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T4	1		T25	2		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	23	1			T50	1		T24	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	317	1			T18	1		T40	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T197	1		T59	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T17	1		T198	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	57	1			T17	1		T200	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T198	1		T124	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	183	1			T6	1		T197	1		T59	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T35	1		T50	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	325	1			T16	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	104	1			T6	1		T16	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T59	1		T200	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T25	1		T198	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T34	1		T59	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	181	1			T6	2		T18	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	23	1			T202	1		T203	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	358	1			T15	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T25	1		T205	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T44	1		T125	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	59	1			T2	1		T25	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	37	1			T25	1		T7	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	208	1			T4	1		T198	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T50	1		T207	1		T203	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	81	1			T25	1		T59	2		T68	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	114	1			T2	1		T15	3		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T197	1		T199	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T34	1		T124	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T18	1		T25	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	205	1			T18	1		T25	2		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	22	1			T50	1		T24	1		T103	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T68	1		T72	1		T73	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	131	1			T15	3		T25	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T18	1		T25	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	61	1			T2	1		T6	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	52	1			T25	1		T7	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	208	1			T4	1		T5	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	22	1			T24	1		T203	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	70	1			T25	2		T59	2		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	128	1			T35	1		T59	2		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T4	1		T59	2		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	56	1			T5	1		T41	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T25	1		T124	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	198	1			T25	2		T59	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T35	1		T50	1		T24	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T25	4		T59	2		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T15	1		T25	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T59	1		T208	1		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T17	1		T18	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	51	1			T198	1		T59	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	195	1			T5	1		T25	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	24	1			T203	1		T204	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	284	1			T2	1		T15	1		T88	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T6	1		T16	1		T22	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T34	1		T198	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	55	1			T25	1		T44	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	41	1			T210	1		T85	1		T8	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T6	1		T25	2		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T50	1		T24	2		T202	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T16	1		T17	1		T40	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T15	1		T211	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	122	1			T6	1		T25	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T211	1		T212	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T6	1		T214	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	288	1			T25	1		T88	1		T150	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	20	1			T207	2		T103	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	449	1			T25	2		T39	4		T148	16
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	141	1			T15	1		T25	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	116	1			T39	1		T148	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T25	2		T148	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	76	1			T5	1		T149	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	251	1			T6	1		T25	2		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T24	1		T215	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	506	1			T2	1		T15	4		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	134	1			T15	2		T17	2		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T25	1		T35	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	104	1			T6	1		T17	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T218	1		T198	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	269	1			T5	1		T6	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T35	2		T50	2		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T25	2		T59	1		T68	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T15	1		T25	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T17	1		T45	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T53	1		T213	1		T219	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T34	1		T7	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	172	1			T25	3		T88	1		T198	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T50	1		T24	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T25	2		T68	3		T103	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	133	1			T15	2		T16	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T5	1		T88	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	94	1			T25	2		T34	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	90	1			T6	1		T34	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	270	1			T6	2		T25	2		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T24	1		T203	1		T215	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	56	1			T25	5		T59	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T15	1		T17	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T16	1		T34	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T6	1		T25	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T25	1		T39	1		T148	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	267	1			T39	1		T148	1		T149	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T35	1		T50	4		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T25	1		T68	2		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	140	1			T218	1		T217	1		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T218	1		T35	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T218	1		T124	1		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	73	1			T25	1		T41	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	294	1			T6	1		T25	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T35	1		T50	1		T24	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T2	1		T25	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	674	1			T4	1		T15	1		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T17	2		T198	2		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	661	1			T6	1		T18	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T25	1		T34	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	642	1			T6	3		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	164	1			T2	1		T25	2		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	729	1			T4	1		T15	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	175	1			T18	1		T25	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	448	1			T2	1		T15	3		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	189	1			T2	1		T6	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	438	1			T4	1		T5	2		T15	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	183	1			T4	1		T5	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	434	1			T25	4		T35	2		T59	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	180	1			T17	1		T18	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	417	1			T5	1		T15	1		T25	6
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	151	1			T25	1		T34	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	628	1			T2	1		T6	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	278	1			T6	1		T25	1		T211	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	922	1			T6	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T5	1		T25	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	892	1			T6	1		T15	1		T25	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T17	1		T25	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	955	1			T2	1		T5	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	166	1			T17	1		T34	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	393	1			T15	1		T25	6		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	281	1			T5	1		T6	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	520	1			T6	2		T15	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T6	1		T16	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	497	1			T15	1		T17	1		T25	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T25	1		T218	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	527	1			T6	1		T25	2		T218	3