Unified Coverage Report :: Group Instance : attest_sw_binding

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	30865	1		T1	3	T2	25	T4	21
auto[134217728:268435455]	8	1		T126	1	T292	1	T258	2
auto[268435456:402653183]	4	1		T125	1	T117	1	T366	1
auto[402653184:536870911]	5	1		T126	1	T258	1	T407	1
auto[536870912:671088639]	12	1		T124	1	T125	1	T292	1
auto[671088640:805306367]	8	1		T125	1	T269	1	T258	1
auto[805306368:939524095]	9	1		T254	1	T408	2	T407	2
auto[939524096:1073741823]	19	1		T125	1	T126	1	T258	1
auto[1073741824:1207959551]	5	1		T258	1	T302	1	T409	1
auto[1207959552:1342177279]	9	1		T126	1	T371	1	T117	1
auto[1342177280:1476395007]	11	1		T125	1	T254	1	T410	1
auto[1476395008:1610612735]	7	1		T408	1	T358	1	T411	1
auto[1610612736:1744830463]	10	1		T124	1	T258	1	T370	2
auto[1744830464:1879048191]	7	1		T124	1	T126	2	T258	1
auto[1879048192:2013265919]	8	1		T125	1	T254	1	T302	1
auto[2013265920:2147483647]	10	1		T124	1	T272	1	T254	1
auto[2147483648:2281701375]	6	1		T125	1	T302	1	T370	1
auto[2281701376:2415919103]	6	1		T126	1	T254	1	T409	1
auto[2415919104:2550136831]	11	1		T126	1	T254	1	T302	2
auto[2550136832:2684354559]	11	1		T126	2	T254	1	T302	1
auto[2684354560:2818572287]	11	1		T126	1	T333	1	T371	2
auto[2818572288:2952790015]	9	1		T126	1	T302	1	T412	2
auto[2952790016:3087007743]	9	1		T125	1	T126	1	T292	1
auto[3087007744:3221225471]	5	1		T254	1	T333	1	T370	1
auto[3221225472:3355443199]	8	1		T258	1	T117	1	T408	1
auto[3355443200:3489660927]	9	1		T124	1	T117	1	T409	1
auto[3489660928:3623878655]	3	1		T117	1	T381	1	T413	1
auto[3623878656:3758096383]	3	1		T411	1	T414	1	T415	1
auto[3758096384:3892314111]	5	1		T258	1	T412	1	T416	1
auto[3892314112:4026531839]	2	1		T353	1	T380	1	-	-
auto[4026531840:4160749567]	5	1		T333	1	T370	2	T408	1
auto[4160749568:4294967295]	3	1		T126	1	T340	2	-	-

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	30	34	53.12	30

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[2952790016:3087007743]]	[auto[0]]	--	--	22
[auto[3221225472:3355443199] - auto[4160749568:4294967295]]	[auto[0]]	--	--	8

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	30858	1		T1	3	T2	25	T4	21
auto[0:134217727]	auto[1]	7	1		T370	1	T371	1	T409	2
auto[134217728:268435455]	auto[1]	8	1		T126	1	T292	1	T258	2
auto[268435456:402653183]	auto[1]	4	1		T125	1	T117	1	T366	1
auto[402653184:536870911]	auto[1]	5	1		T126	1	T258	1	T407	1
auto[536870912:671088639]	auto[1]	12	1		T124	1	T125	1	T292	1
auto[671088640:805306367]	auto[1]	8	1		T125	1	T269	1	T258	1
auto[805306368:939524095]	auto[1]	9	1		T254	1	T408	2	T407	2
auto[939524096:1073741823]	auto[1]	19	1		T125	1	T126	1	T258	1
auto[1073741824:1207959551]	auto[1]	5	1		T258	1	T302	1	T409	1
auto[1207959552:1342177279]	auto[1]	9	1		T126	1	T371	1	T117	1
auto[1342177280:1476395007]	auto[1]	11	1		T125	1	T254	1	T410	1
auto[1476395008:1610612735]	auto[1]	7	1		T408	1	T358	1	T411	1
auto[1610612736:1744830463]	auto[1]	10	1		T124	1	T258	1	T370	2
auto[1744830464:1879048191]	auto[1]	7	1		T124	1	T126	2	T258	1
auto[1879048192:2013265919]	auto[1]	8	1		T125	1	T254	1	T302	1
auto[2013265920:2147483647]	auto[1]	10	1		T124	1	T272	1	T254	1
auto[2147483648:2281701375]	auto[1]	6	1		T125	1	T302	1	T370	1
auto[2281701376:2415919103]	auto[1]	6	1		T126	1	T254	1	T409	1
auto[2415919104:2550136831]	auto[1]	11	1		T126	1	T254	1	T302	2
auto[2550136832:2684354559]	auto[1]	11	1		T126	2	T254	1	T302	1
auto[2684354560:2818572287]	auto[1]	11	1		T126	1	T333	1	T371	2
auto[2818572288:2952790015]	auto[1]	9	1		T126	1	T302	1	T412	2
auto[2952790016:3087007743]	auto[1]	9	1		T125	1	T126	1	T292	1
auto[3087007744:3221225471]	auto[0]	1	1		T333	1	-	-	-	-
auto[3087007744:3221225471]	auto[1]	4	1		T254	1	T370	1	T358	1
auto[3221225472:3355443199]	auto[1]	8	1		T258	1	T117	1	T408	1
auto[3355443200:3489660927]	auto[1]	9	1		T124	1	T117	1	T409	1
auto[3489660928:3623878655]	auto[1]	3	1		T117	1	T381	1	T413	1
auto[3623878656:3758096383]	auto[1]	3	1		T411	1	T414	1	T415	1
auto[3758096384:3892314111]	auto[1]	5	1		T258	1	T412	1	T416	1
auto[3892314112:4026531839]	auto[1]	2	1		T353	1	T380	1	-	-
auto[4026531840:4160749567]	auto[1]	5	1		T333	1	T370	2	T408	1
auto[4160749568:4294967295]	auto[1]	3	1		T126	1	T340	2	-	-

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1619

T15

T25

auto[1]

1708

T25

T34

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	125	1		T25	2	T49	1	T35	3
auto[134217728:268435455]	107	1		T25	2	T49	1	T45	1
auto[268435456:402653183]	113	1		T34	1	T40	1	T49	1
auto[402653184:536870911]	96	1		T150	1	T35	2	T7	1
auto[536870912:671088639]	105	1		T25	1	T40	1	T150	1
auto[671088640:805306367]	105	1		T6	1	T59	1	T7	1
auto[805306368:939524095]	94	1		T40	2	T35	1	T197	1
auto[939524096:1073741823]	107	1		T25	2	T197	1	T124	1
auto[1073741824:1207959551]	122	1		T6	1	T40	1	T199	1
auto[1207959552:1342177279]	100	1		T15	1	T45	1	T59	3
auto[1342177280:1476395007]	113	1		T198	1	T7	2	T53	2
auto[1476395008:1610612735]	113	1		T25	1	T35	1	T59	1
auto[1610612736:1744830463]	110	1		T6	1	T25	1	T40	1
auto[1744830464:1879048191]	99	1		T6	1	T34	1	T150	1
auto[1879048192:2013265919]	99	1		T34	1	T59	1	T7	2
auto[2013265920:2147483647]	94	1		T150	1	T49	1	T59	1
auto[2147483648:2281701375]	107	1		T6	1	T49	1	T198	1
auto[2281701376:2415919103]	103	1		T224	1	T68	2	T60	1
auto[2415919104:2550136831]	91	1		T25	2	T150	1	T49	2
auto[2550136832:2684354559]	120	1		T35	1	T197	1	T59	1
auto[2684354560:2818572287]	93	1		T25	2	T199	1	T124	1
auto[2818572288:2952790015]	96	1		T150	1	T35	1	T7	3
auto[2952790016:3087007743]	87	1		T25	2	T198	1	T124	1
auto[3087007744:3221225471]	95	1		T49	1	T199	3	T59	1
auto[3221225472:3355443199]	105	1		T124	1	T59	2	T7	2
auto[3355443200:3489660927]	107	1		T44	1	T150	1	T35	1
auto[3489660928:3623878655]	97	1		T15	1	T25	2	T22	1
auto[3623878656:3758096383]	118	1		T40	1	T59	2	T7	1
auto[3758096384:3892314111]	105	1		T15	1	T25	1	T198	1
auto[3892314112:4026531839]	99	1		T25	1	T197	1	T59	1
auto[4026531840:4160749567]	109	1		T35	1	T59	3	T224	1
auto[4160749568:4294967295]	93	1		T40	1	T35	1	T59	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	67	1		T25	1	T49	1	T35	1
auto[0:134217727]	auto[1]	58	1		T25	1	T35	2	T247	1
auto[134217728:268435455]	auto[0]	59	1		T49	1	T45	1	T200	1
auto[134217728:268435455]	auto[1]	48	1		T25	2	T200	1	T92	1
auto[268435456:402653183]	auto[0]	52	1		T40	1	T35	1	T59	1
auto[268435456:402653183]	auto[1]	61	1		T34	1	T49	1	T7	1
auto[402653184:536870911]	auto[0]	41	1		T35	1	T7	1	T41	1
auto[402653184:536870911]	auto[1]	55	1		T150	1	T35	1	T53	1
auto[536870912:671088639]	auto[0]	59	1		T25	1	T40	1	T198	1
auto[536870912:671088639]	auto[1]	46	1		T150	1	T290	1	T68	1
auto[671088640:805306367]	auto[0]	48	1		T6	1	T8	1	T72	1
auto[671088640:805306367]	auto[1]	57	1		T59	1	T7	1	T53	1
auto[805306368:939524095]	auto[0]	51	1		T40	2	T35	1	T59	1
auto[805306368:939524095]	auto[1]	43	1		T197	1	T124	1	T125	1
auto[939524096:1073741823]	auto[0]	45	1		T25	1	T125	1	T60	1
auto[939524096:1073741823]	auto[1]	62	1		T25	1	T197	1	T124	1
auto[1073741824:1207959551]	auto[0]	47	1		T40	1	T199	1	T224	1
auto[1073741824:1207959551]	auto[1]	75	1		T6	1	T59	1	T41	2
auto[1207959552:1342177279]	auto[0]	55	1		T15	1	T45	1	T59	2
auto[1207959552:1342177279]	auto[1]	45	1		T59	1	T7	1	T417	1
auto[1342177280:1476395007]	auto[0]	57	1		T7	1	T53	1	T68	2
auto[1342177280:1476395007]	auto[1]	56	1		T198	1	T7	1	T53	1
auto[1476395008:1610612735]	auto[0]	56	1		T35	1	T59	1	T22	1
auto[1476395008:1610612735]	auto[1]	57	1		T25	1	T41	1	T86	1
auto[1610612736:1744830463]	auto[0]	41	1		T224	1	T118	1	T251	1
auto[1610612736:1744830463]	auto[1]	69	1		T6	1	T25	1	T40	1
auto[1744830464:1879048191]	auto[0]	49	1		T150	1	T59	1	T41	1
auto[1744830464:1879048191]	auto[1]	50	1		T6	1	T34	1	T59	1
auto[1879048192:2013265919]	auto[0]	44	1		T34	1	T291	1	T247	1
auto[1879048192:2013265919]	auto[1]	55	1		T59	1	T7	2	T41	1
auto[2013265920:2147483647]	auto[0]	40	1		T150	1	T200	1	T22	1
auto[2013265920:2147483647]	auto[1]	54	1		T49	1	T59	1	T213	1
auto[2147483648:2281701375]	auto[0]	58	1		T6	1	T49	1	T59	1
auto[2147483648:2281701375]	auto[1]	49	1		T198	1	T59	1	T70	1
auto[2281701376:2415919103]	auto[0]	55	1		T68	1	T60	1	T42	2
auto[2281701376:2415919103]	auto[1]	48	1		T224	1	T68	1	T8	1
auto[2415919104:2550136831]	auto[0]	41	1		T49	2	T41	2	T8	1
auto[2415919104:2550136831]	auto[1]	50	1		T25	2	T150	1	T45	1
auto[2550136832:2684354559]	auto[0]	62	1		T35	1	T417	1	T60	1
auto[2550136832:2684354559]	auto[1]	58	1		T197	1	T59	1	T200	1
auto[2684354560:2818572287]	auto[0]	38	1		T25	2	T199	1	T124	1
auto[2684354560:2818572287]	auto[1]	55	1		T59	1	T201	1	T210	1
auto[2818572288:2952790015]	auto[0]	49	1		T35	1	T7	1	T417	1
auto[2818572288:2952790015]	auto[1]	47	1		T150	1	T7	2	T205	1
auto[2952790016:3087007743]	auto[0]	40	1		T25	2	T198	1	T52	1
auto[2952790016:3087007743]	auto[1]	47	1		T124	1	T53	2	T23	1
auto[3087007744:3221225471]	auto[0]	46	1		T49	1	T68	1	T60	1
auto[3087007744:3221225471]	auto[1]	49	1		T199	3	T59	1	T68	1
auto[3221225472:3355443199]	auto[0]	59	1		T124	1	T7	1	T224	1
auto[3221225472:3355443199]	auto[1]	46	1		T59	2	T7	1	T125	1
auto[3355443200:3489660927]	auto[0]	57	1		T150	1	T35	1	T22	1
auto[3355443200:3489660927]	auto[1]	50	1		T44	1	T59	2	T205	1
auto[3489660928:3623878655]	auto[0]	48	1		T15	1	T25	1	T22	1
auto[3489660928:3623878655]	auto[1]	49	1		T25	1	T41	3	T206	1
auto[3623878656:3758096383]	auto[0]	65	1		T59	1	T205	1	T201	1
auto[3623878656:3758096383]	auto[1]	53	1		T40	1	T59	1	T7	1
auto[3758096384:3892314111]	auto[0]	51	1		T15	1	T198	1	T41	1
auto[3758096384:3892314111]	auto[1]	54	1		T25	1	T8	1	T26	1
auto[3892314112:4026531839]	auto[0]	42	1		T25	1	T417	1	T290	1
auto[3892314112:4026531839]	auto[1]	57	1		T197	1	T59	1	T200	1
auto[4026531840:4160749567]	auto[0]	59	1		T35	1	T59	2	T224	1
auto[4026531840:4160749567]	auto[1]	50	1		T59	1	T53	1	T417	1
auto[4160749568:4294967295]	auto[0]	38	1		T35	1	T53	2	T86	1
auto[4160749568:4294967295]	auto[1]	55	1		T40	1	T59	1	T53	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1628

T15

T25

auto[1]

1702

T15

T25

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	98	1		T59	1	T125	1	T53	2
auto[134217728:268435455]	95	1		T150	1	T59	1	T41	1
auto[268435456:402653183]	110	1		T25	1	T40	1	T150	1
auto[402653184:536870911]	118	1		T15	1	T197	1	T59	2
auto[536870912:671088639]	108	1		T150	1	T35	1	T124	1
auto[671088640:805306367]	121	1		T15	1	T59	2	T7	1
auto[805306368:939524095]	105	1		T49	1	T35	1	T198	1
auto[939524096:1073741823]	106	1		T199	1	T200	2	T201	1
auto[1073741824:1207959551]	97	1		T45	2	T199	1	T59	1
auto[1207959552:1342177279]	93	1		T197	1	T59	1	T7	1
auto[1342177280:1476395007]	110	1		T34	1	T40	1	T49	1
auto[1476395008:1610612735]	113	1		T25	1	T7	1	T41	1
auto[1610612736:1744830463]	98	1		T198	1	T7	1	T22	1
auto[1744830464:1879048191]	89	1		T25	1	T59	1	T7	1
auto[1879048192:2013265919]	123	1		T15	1	T25	1	T35	1
auto[2013265920:2147483647]	101	1		T6	1	T35	1	T124	1
auto[2147483648:2281701375]	92	1		T40	1	T49	1	T124	1
auto[2281701376:2415919103]	107	1		T25	1	T35	1	T59	2
auto[2415919104:2550136831]	98	1		T6	1	T25	1	T124	1
auto[2550136832:2684354559]	85	1		T25	1	T40	1	T35	1
auto[2684354560:2818572287]	103	1		T25	1	T35	1	T53	1
auto[2818572288:2952790015]	94	1		T6	1	T40	1	T59	1
auto[2952790016:3087007743]	95	1		T34	1	T49	2	T59	1
auto[3087007744:3221225471]	127	1		T25	4	T49	1	T35	1
auto[3221225472:3355443199]	95	1		T59	1	T7	1	T201	1
auto[3355443200:3489660927]	111	1		T25	1	T40	1	T35	1
auto[3489660928:3623878655]	111	1		T25	1	T44	1	T150	3
auto[3623878656:3758096383]	112	1		T40	1	T150	1	T35	1
auto[3758096384:3892314111]	94	1		T34	1	T49	1	T35	3
auto[3892314112:4026531839]	114	1		T6	2	T25	2	T49	1
auto[4026531840:4160749567]	108	1		T25	2	T59	1	T7	1
auto[4160749568:4294967295]	99	1		T25	1	T40	1	T197	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	46	1		T125	1	T53	1	T8	1
auto[0:134217727]	auto[1]	52	1		T59	1	T53	1	T288	1
auto[134217728:268435455]	auto[0]	50	1		T150	1	T41	1	T53	1
auto[134217728:268435455]	auto[1]	45	1		T59	1	T290	1	T42	1
auto[268435456:402653183]	auto[0]	55	1		T41	1	T53	1	T417	1
auto[268435456:402653183]	auto[1]	55	1		T25	1	T40	1	T150	1
auto[402653184:536870911]	auto[0]	49	1		T15	1	T59	1	T22	1
auto[402653184:536870911]	auto[1]	69	1		T197	1	T59	1	T7	1
auto[536870912:671088639]	auto[0]	55	1		T124	1	T126	1	T213	1
auto[536870912:671088639]	auto[1]	53	1		T150	1	T35	1	T417	1
auto[671088640:805306367]	auto[0]	61	1		T59	1	T7	1	T200	1
auto[671088640:805306367]	auto[1]	60	1		T15	1	T59	1	T125	1
auto[805306368:939524095]	auto[0]	55	1		T35	1	T59	3	T7	2
auto[805306368:939524095]	auto[1]	50	1		T49	1	T198	1	T59	1
auto[939524096:1073741823]	auto[0]	48	1		T200	1	T125	1	T41	1
auto[939524096:1073741823]	auto[1]	58	1		T199	1	T200	1	T201	1
auto[1073741824:1207959551]	auto[0]	51	1		T45	2	T199	1	T7	1
auto[1073741824:1207959551]	auto[1]	46	1		T59	1	T41	1	T81	1
auto[1207959552:1342177279]	auto[0]	39	1		T59	1	T417	1	T68	1
auto[1207959552:1342177279]	auto[1]	54	1		T197	1	T7	1	T205	1
auto[1342177280:1476395007]	auto[0]	49	1		T40	1	T199	1	T7	1
auto[1342177280:1476395007]	auto[1]	61	1		T34	1	T49	1	T199	1
auto[1476395008:1610612735]	auto[0]	50	1		T25	1	T41	1	T86	2
auto[1476395008:1610612735]	auto[1]	63	1		T7	1	T69	1	T210	1
auto[1610612736:1744830463]	auto[0]	46	1		T7	1	T22	1	T60	1
auto[1610612736:1744830463]	auto[1]	52	1		T198	1	T290	1	T219	1
auto[1744830464:1879048191]	auto[0]	46	1		T7	1	T60	1	T54	1
auto[1744830464:1879048191]	auto[1]	43	1		T25	1	T59	1	T126	1
auto[1879048192:2013265919]	auto[0]	57	1		T15	1	T25	1	T35	1
auto[1879048192:2013265919]	auto[1]	66	1		T59	1	T68	1	T85	1
auto[2013265920:2147483647]	auto[0]	58	1		T35	1	T205	1	T53	1
auto[2013265920:2147483647]	auto[1]	43	1		T6	1	T124	1	T41	1
auto[2147483648:2281701375]	auto[0]	40	1		T40	1	T49	1	T68	4
auto[2147483648:2281701375]	auto[1]	52	1		T124	1	T59	1	T201	1
auto[2281701376:2415919103]	auto[0]	52	1		T25	1	T35	1	T201	1
auto[2281701376:2415919103]	auto[1]	55	1		T59	2	T53	1	T68	1
auto[2415919104:2550136831]	auto[0]	48	1		T25	1	T59	1	T7	1
auto[2415919104:2550136831]	auto[1]	50	1		T6	1	T124	1	T417	1
auto[2550136832:2684354559]	auto[0]	50	1		T25	1	T35	1	T59	1
auto[2550136832:2684354559]	auto[1]	35	1		T40	1	T45	1	T199	1
auto[2684354560:2818572287]	auto[0]	53	1		T35	1	T53	1	T81	1
auto[2684354560:2818572287]	auto[1]	50	1		T25	1	T247	1	T418	1
auto[2818572288:2952790015]	auto[0]	43	1		T40	1	T53	1	T206	1
auto[2818572288:2952790015]	auto[1]	51	1		T6	1	T59	1	T210	1
auto[2952790016:3087007743]	auto[0]	50	1		T49	2	T224	1	T53	1
auto[2952790016:3087007743]	auto[1]	45	1		T34	1	T59	1	T41	1
auto[3087007744:3221225471]	auto[0]	67	1		T25	2	T49	1	T35	1
auto[3087007744:3221225471]	auto[1]	60	1		T25	2	T59	1	T53	1
auto[3221225472:3355443199]	auto[0]	48	1		T7	1	T417	1	T290	1
auto[3221225472:3355443199]	auto[1]	47	1		T59	1	T201	1	T41	1
auto[3355443200:3489660927]	auto[0]	47	1		T40	1	T35	1	T124	1
auto[3355443200:3489660927]	auto[1]	64	1		T25	1	T198	1	T7	1
auto[3489660928:3623878655]	auto[0]	52	1		T25	1	T150	2	T126	1
auto[3489660928:3623878655]	auto[1]	59	1		T44	1	T150	1	T205	1
auto[3623878656:3758096383]	auto[0]	57	1		T40	1	T41	1	T53	1
auto[3623878656:3758096383]	auto[1]	55	1		T150	1	T35	1	T59	1
auto[3758096384:3892314111]	auto[0]	44	1		T49	1	T35	3	T198	1
auto[3758096384:3892314111]	auto[1]	50	1		T34	1	T197	1	T59	1
auto[3892314112:4026531839]	auto[0]	58	1		T6	1	T25	1	T49	1
auto[3892314112:4026531839]	auto[1]	56	1		T6	1	T25	1	T59	1
auto[4026531840:4160749567]	auto[0]	60	1		T25	1	T200	1	T201	1
auto[4026531840:4160749567]	auto[1]	48	1		T25	1	T59	1	T7	1
auto[4160749568:4294967295]	auto[0]	44	1		T40	1	T291	1	T210	1
auto[4160749568:4294967295]	auto[1]	55	1		T25	1	T197	1	T68	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1621

T15

T25

auto[1]

1707

T25

T34

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	106	1		T6	1	T25	1	T40	1
auto[134217728:268435455]	112	1		T205	1	T201	1	T41	1
auto[268435456:402653183]	111	1		T198	1	T59	1	T7	1
auto[402653184:536870911]	101	1		T34	1	T44	1	T35	1
auto[536870912:671088639]	113	1		T25	3	T40	1	T199	1
auto[671088640:805306367]	108	1		T25	1	T59	2	T200	1
auto[805306368:939524095]	100	1		T6	1	T150	1	T49	1
auto[939524096:1073741823]	99	1		T6	1	T35	1	T197	1
auto[1073741824:1207959551]	102	1		T34	1	T35	2	T118	1
auto[1207959552:1342177279]	102	1		T15	1	T40	1	T198	1
auto[1342177280:1476395007]	110	1		T25	1	T34	1	T150	1
auto[1476395008:1610612735]	89	1		T25	1	T7	2	T201	1
auto[1610612736:1744830463]	105	1		T150	1	T197	1	T59	1
auto[1744830464:1879048191]	132	1		T40	1	T150	1	T49	1
auto[1879048192:2013265919]	104	1		T199	1	T59	1	T7	1
auto[2013265920:2147483647]	112	1		T25	1	T40	1	T150	2
auto[2147483648:2281701375]	91	1		T41	2	T118	1	T417	1
auto[2281701376:2415919103]	115	1		T25	2	T59	3	T7	1
auto[2415919104:2550136831]	101	1		T25	2	T35	1	T59	1
auto[2550136832:2684354559]	97	1		T6	1	T45	1	T7	1
auto[2684354560:2818572287]	98	1		T15	1	T49	1	T197	1
auto[2818572288:2952790015]	115	1		T25	1	T40	2	T49	2
auto[2952790016:3087007743]	91	1		T25	1	T59	1	T53	1
auto[3087007744:3221225471]	89	1		T25	1	T40	1	T35	1
auto[3221225472:3355443199]	98	1		T25	1	T49	1	T200	2
auto[3355443200:3489660927]	107	1		T41	1	T53	1	T290	1
auto[3489660928:3623878655]	105	1		T49	1	T197	1	T199	1
auto[3623878656:3758096383]	109	1		T25	1	T59	1	T7	1
auto[3758096384:3892314111]	98	1		T35	2	T198	1	T59	1
auto[3892314112:4026531839]	103	1		T25	1	T59	1	T7	1
auto[4026531840:4160749567]	108	1		T6	1	T25	1	T35	1
auto[4160749568:4294967295]	97	1		T15	1	T150	1	T49	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	53	1		T6	1	T25	1	T40	1
auto[0:134217727]	auto[1]	53	1		T59	1	T41	1	T60	1
auto[134217728:268435455]	auto[0]	47	1		T205	1	T213	1	T207	1
auto[134217728:268435455]	auto[1]	65	1		T201	1	T41	1	T210	1
auto[268435456:402653183]	auto[0]	61	1		T198	1	T59	1	T7	1
auto[268435456:402653183]	auto[1]	50	1		T41	1	T69	1	T213	1
auto[402653184:536870911]	auto[0]	45	1		T34	1	T59	1	T68	1
auto[402653184:536870911]	auto[1]	56	1		T44	1	T35	1	T199	1
auto[536870912:671088639]	auto[0]	55	1		T25	1	T40	1	T22	1
auto[536870912:671088639]	auto[1]	58	1		T25	2	T199	1	T288	1
auto[671088640:805306367]	auto[0]	56	1		T25	1	T59	2	T81	1
auto[671088640:805306367]	auto[1]	52	1		T200	1	T85	1	T8	2
auto[805306368:939524095]	auto[0]	49	1		T49	1	T35	1	T205	1
auto[805306368:939524095]	auto[1]	51	1		T6	1	T150	1	T35	1
auto[939524096:1073741823]	auto[0]	48	1		T7	2	T41	1	T290	1
auto[939524096:1073741823]	auto[1]	51	1		T6	1	T35	1	T197	1
auto[1073741824:1207959551]	auto[0]	52	1		T35	2	T291	1	T68	2
auto[1073741824:1207959551]	auto[1]	50	1		T34	1	T118	1	T219	1
auto[1207959552:1342177279]	auto[0]	57	1		T15	1	T198	1	T201	1
auto[1207959552:1342177279]	auto[1]	45	1		T40	1	T59	1	T7	1
auto[1342177280:1476395007]	auto[0]	55	1		T150	1	T124	1	T50	2
auto[1342177280:1476395007]	auto[1]	55	1		T25	1	T34	1	T68	1
auto[1476395008:1610612735]	auto[0]	48	1		T25	1	T7	1	T201	1
auto[1476395008:1610612735]	auto[1]	41	1		T7	1	T8	1	T54	1
auto[1610612736:1744830463]	auto[0]	53	1		T150	1	T59	1	T50	1
auto[1610612736:1744830463]	auto[1]	52	1		T197	1	T417	1	T68	1
auto[1744830464:1879048191]	auto[0]	64	1		T40	1	T59	1	T7	2
auto[1744830464:1879048191]	auto[1]	68	1		T150	1	T49	1	T59	2
auto[1879048192:2013265919]	auto[0]	49	1		T199	1	T7	1	T200	1
auto[1879048192:2013265919]	auto[1]	55	1		T59	1	T53	1	T23	1
auto[2013265920:2147483647]	auto[0]	52	1		T25	1	T40	1	T150	1
auto[2013265920:2147483647]	auto[1]	60	1		T150	1	T59	4	T201	1
auto[2147483648:2281701375]	auto[0]	43	1		T41	1	T118	1	T417	1
auto[2147483648:2281701375]	auto[1]	48	1		T41	1	T23	1	T42	1
auto[2281701376:2415919103]	auto[0]	64	1		T59	1	T41	2	T210	1
auto[2281701376:2415919103]	auto[1]	51	1		T25	2	T59	2	T7	1
auto[2415919104:2550136831]	auto[0]	46	1		T35	1	T224	1	T417	1
auto[2415919104:2550136831]	auto[1]	55	1		T25	2	T59	1	T70	1
auto[2550136832:2684354559]	auto[0]	44	1		T45	1	T68	2	T60	1
auto[2550136832:2684354559]	auto[1]	53	1		T6	1	T7	1	T126	1
auto[2684354560:2818572287]	auto[0]	55	1		T15	1	T49	1	T45	2
auto[2684354560:2818572287]	auto[1]	43	1		T197	1	T198	1	T290	1
auto[2818572288:2952790015]	auto[0]	58	1		T25	1	T40	1	T49	1
auto[2818572288:2952790015]	auto[1]	57	1		T40	1	T49	1	T59	1
auto[2952790016:3087007743]	auto[0]	37	1		T53	1	T68	1	T11	1
auto[2952790016:3087007743]	auto[1]	54	1		T25	1	T59	1	T68	1
auto[3087007744:3221225471]	auto[0]	44	1		T199	1	T68	1	T24	1
auto[3087007744:3221225471]	auto[1]	45	1		T25	1	T40	1	T35	1
auto[3221225472:3355443199]	auto[0]	39	1		T49	1	T41	1	T24	1
auto[3221225472:3355443199]	auto[1]	59	1		T25	1	T200	2	T41	2
auto[3355443200:3489660927]	auto[0]	42	1		T41	1	T53	1	T290	1
auto[3355443200:3489660927]	auto[1]	65	1		T85	1	T247	1	T219	1
auto[3489660928:3623878655]	auto[0]	58	1		T49	1	T199	1	T59	1
auto[3489660928:3623878655]	auto[1]	47	1		T197	1	T124	1	T59	1
auto[3623878656:3758096383]	auto[0]	53	1		T7	1	T53	2	T255	1
auto[3623878656:3758096383]	auto[1]	56	1		T25	1	T59	1	T291	1
auto[3758096384:3892314111]	auto[0]	49	1		T35	2	T59	1	T7	1
auto[3758096384:3892314111]	auto[1]	49	1		T198	1	T53	1	T68	1
auto[3892314112:4026531839]	auto[0]	51	1		T25	1	T200	1	T68	1
auto[3892314112:4026531839]	auto[1]	52	1		T59	1	T7	1	T41	1
auto[4026531840:4160749567]	auto[0]	53	1		T35	1	T198	1	T59	1
auto[4026531840:4160749567]	auto[1]	55	1		T6	1	T25	1	T124	1
auto[4160749568:4294967295]	auto[0]	41	1		T15	1	T49	1	T118	1
auto[4160749568:4294967295]	auto[1]	56	1		T150	1	T7	1	T205	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1600

T15

T25

auto[1]

1729

T25

T34

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	101	1		T150	1	T49	1	T197	1
auto[134217728:268435455]	107	1		T197	1	T201	1	T53	1
auto[268435456:402653183]	106	1		T25	2	T40	1	T199	1
auto[402653184:536870911]	102	1		T6	1	T34	1	T150	1
auto[536870912:671088639]	104	1		T6	1	T25	1	T150	1
auto[671088640:805306367]	108	1		T15	1	T25	1	T34	1
auto[805306368:939524095]	113	1		T25	2	T150	1	T49	1
auto[939524096:1073741823]	106	1		T25	1	T59	1	T224	1
auto[1073741824:1207959551]	94	1		T35	1	T198	1	T59	1
auto[1207959552:1342177279]	117	1		T44	1	T198	1	T124	2
auto[1342177280:1476395007]	96	1		T40	1	T35	1	T59	1
auto[1476395008:1610612735]	98	1		T205	1	T41	2	T68	1
auto[1610612736:1744830463]	101	1		T25	2	T150	1	T35	1
auto[1744830464:1879048191]	104	1		T197	1	T198	1	T59	1
auto[1879048192:2013265919]	88	1		T7	2	T125	1	T53	1
auto[2013265920:2147483647]	93	1		T15	1	T25	1	T34	1
auto[2147483648:2281701375]	112	1		T6	1	T40	1	T150	1
auto[2281701376:2415919103]	127	1		T25	1	T59	1	T200	1
auto[2415919104:2550136831]	97	1		T40	1	T199	1	T59	3
auto[2550136832:2684354559]	111	1		T59	1	T224	1	T41	1
auto[2684354560:2818572287]	103	1		T35	2	T45	1	T199	1
auto[2818572288:2952790015]	97	1		T49	1	T35	1	T201	1
auto[2952790016:3087007743]	110	1		T35	1	T59	1	T7	1
auto[3087007744:3221225471]	110	1		T6	1	T45	1	T224	1
auto[3221225472:3355443199]	105	1		T40	2	T199	1	T7	1
auto[3355443200:3489660927]	97	1		T150	1	T35	1	T200	1
auto[3489660928:3623878655]	91	1		T15	1	T49	1	T59	3
auto[3623878656:3758096383]	86	1		T40	1	T35	1	T205	1
auto[3758096384:3892314111]	111	1		T25	3	T45	1	T59	1
auto[3892314112:4026531839]	110	1		T6	1	T25	1	T35	1
auto[4026531840:4160749567]	110	1		T25	1	T35	2	T197	1
auto[4160749568:4294967295]	114	1		T25	3	T49	1	T59	1