Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2903

1

T6

5

T15

3

T25

19

auto[1]

289

1

T124

6

T125

6

T126

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T35	1		T59	2		T126	1
auto[134217728:268435455]	101	1			T197	1		T199	1		T124	1
auto[268435456:402653183]	89	1			T6	1		T25	1		T35	1
auto[402653184:536870911]	114	1			T40	1		T49	1		T59	1
auto[536870912:671088639]	94	1			T25	1		T198	1		T124	1
auto[671088640:805306367]	104	1			T25	3		T197	1		T45	1
auto[805306368:939524095]	108	1			T25	1		T150	1		T35	1
auto[939524096:1073741823]	92	1			T25	1		T35	1		T59	2
auto[1073741824:1207959551]	115	1			T25	1		T124	1		T59	2
auto[1207959552:1342177279]	93	1			T15	1		T49	1		T59	1
auto[1342177280:1476395007]	66	1			T40	1		T197	1		T205	1
auto[1476395008:1610612735]	89	1			T25	2		T34	1		T205	1
auto[1610612736:1744830463]	107	1			T25	1		T44	1		T198	1
auto[1744830464:1879048191]	117	1			T35	1		T41	2		T70	1
auto[1879048192:2013265919]	95	1			T15	1		T199	1		T59	1
auto[2013265920:2147483647]	105	1			T40	1		T35	1		T45	1
auto[2147483648:2281701375]	107	1			T25	1		T35	1		T198	1
auto[2281701376:2415919103]	107	1			T150	2		T126	1		T69	1
auto[2415919104:2550136831]	94	1			T25	1		T150	1		T199	1
auto[2550136832:2684354559]	95	1			T34	1		T59	2		T22	1
auto[2684354560:2818572287]	100	1			T6	1		T15	1		T198	1
auto[2818572288:2952790015]	99	1			T25	1		T35	1		T199	1
auto[2952790016:3087007743]	103	1			T25	1		T150	1		T59	1
auto[3087007744:3221225471]	89	1			T59	1		T224	1		T41	1
auto[3221225472:3355443199]	122	1			T25	1		T124	2		T59	4
auto[3355443200:3489660927]	107	1			T25	1		T35	1		T124	1
auto[3489660928:3623878655]	101	1			T6	1		T150	1		T35	2
auto[3623878656:3758096383]	108	1			T6	1		T59	1		T125	1
auto[3758096384:3892314111]	78	1			T25	1		T198	1		T205	1
auto[3892314112:4026531839]	93	1			T6	1		T197	1		T41	1
auto[4026531840:4160749567]	95	1			T25	1		T45	1		T124	1
auto[4160749568:4294967295]	102	1			T150	1		T35	2		T125	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	92	1			T35	1		T59	2		T53	2
auto[0:134217727]	auto[1]	11	1			T126	1		T258	2		T408	1
auto[134217728:268435455]	auto[0]	95	1			T197	1		T199	1		T124	1
auto[134217728:268435455]	auto[1]	6	1			T126	1		T407	1		T421	2
auto[268435456:402653183]	auto[0]	84	1			T6	1		T25	1		T35	1
auto[268435456:402653183]	auto[1]	5	1			T254	1		T258	1		T409	1
auto[402653184:536870911]	auto[0]	103	1			T40	1		T49	1		T59	1
auto[402653184:536870911]	auto[1]	11	1			T409	1		T346	1		T353	1
auto[536870912:671088639]	auto[0]	82	1			T25	1		T198	1		T200	1
auto[536870912:671088639]	auto[1]	12	1			T124	1		T258	2		T370	1
auto[671088640:805306367]	auto[0]	95	1			T25	3		T197	1		T45	1
auto[671088640:805306367]	auto[1]	9	1			T124	1		T408	1		T409	2
auto[805306368:939524095]	auto[0]	102	1			T25	1		T150	1		T35	1
auto[805306368:939524095]	auto[1]	6	1			T408	1		T346	1		T412	1
auto[939524096:1073741823]	auto[0]	80	1			T25	1		T35	1		T59	2
auto[939524096:1073741823]	auto[1]	12	1			T85	1		T272	1		T302	1
auto[1073741824:1207959551]	auto[0]	109	1			T25	1		T124	1		T59	2
auto[1073741824:1207959551]	auto[1]	6	1			T302	1		T416	1		T348	1
auto[1207959552:1342177279]	auto[0]	85	1			T15	1		T49	1		T59	1
auto[1207959552:1342177279]	auto[1]	8	1			T125	1		T410	2		T407	1
auto[1342177280:1476395007]	auto[0]	59	1			T40	1		T197	1		T205	1
auto[1342177280:1476395007]	auto[1]	7	1			T117	1		T348	2		T411	1
auto[1476395008:1610612735]	auto[0]	81	1			T25	2		T34	1		T205	1
auto[1476395008:1610612735]	auto[1]	8	1			T126	2		T85	1		T353	2
auto[1610612736:1744830463]	auto[0]	103	1			T25	1		T44	1		T198	1
auto[1610612736:1744830463]	auto[1]	4	1			T409	1		T422	1		T366	1
auto[1744830464:1879048191]	auto[0]	109	1			T35	1		T41	2		T70	1
auto[1744830464:1879048191]	auto[1]	8	1			T272	1		T258	1		T420	1
auto[1879048192:2013265919]	auto[0]	86	1			T15	1		T199	1		T59	1
auto[1879048192:2013265919]	auto[1]	9	1			T126	1		T258	1		T370	1
auto[2013265920:2147483647]	auto[0]	92	1			T40	1		T35	1		T45	1
auto[2013265920:2147483647]	auto[1]	13	1			T126	1		T85	1		T254	1
auto[2147483648:2281701375]	auto[0]	95	1			T25	1		T35	1		T198	1
auto[2147483648:2281701375]	auto[1]	12	1			T124	1		T302	1		T370	1
auto[2281701376:2415919103]	auto[0]	94	1			T150	2		T69	1		T53	2
auto[2281701376:2415919103]	auto[1]	13	1			T126	1		T292	1		T254	1
auto[2415919104:2550136831]	auto[0]	88	1			T25	1		T150	1		T199	1
auto[2415919104:2550136831]	auto[1]	6	1			T126	1		T272	1		T302	1
auto[2550136832:2684354559]	auto[0]	85	1			T34	1		T59	2		T22	1
auto[2550136832:2684354559]	auto[1]	10	1			T254	1		T258	1		T371	1
auto[2684354560:2818572287]	auto[0]	90	1			T6	1		T15	1		T198	1
auto[2684354560:2818572287]	auto[1]	10	1			T126	2		T258	1		T408	1
auto[2818572288:2952790015]	auto[0]	93	1			T25	1		T35	1		T199	1
auto[2818572288:2952790015]	auto[1]	6	1			T126	2		T409	1		T422	1
auto[2952790016:3087007743]	auto[0]	91	1			T25	1		T150	1		T59	1
auto[2952790016:3087007743]	auto[1]	12	1			T409	1		T346	1		T428	1
auto[3087007744:3221225471]	auto[0]	81	1			T59	1		T224	1		T41	1
auto[3087007744:3221225471]	auto[1]	8	1			T292	1		T376	1		T407	1
auto[3221225472:3355443199]	auto[0]	104	1			T25	1		T59	4		T7	1
auto[3221225472:3355443199]	auto[1]	18	1			T124	2		T269	1		T292	1
auto[3355443200:3489660927]	auto[0]	97	1			T25	1		T35	1		T124	1
auto[3355443200:3489660927]	auto[1]	10	1			T125	1		T269	1		T408	1
auto[3489660928:3623878655]	auto[0]	91	1			T6	1		T150	1		T35	2
auto[3489660928:3623878655]	auto[1]	10	1			T124	1		T254	2		T408	1
auto[3623878656:3758096383]	auto[0]	100	1			T6	1		T59	1		T290	1
auto[3623878656:3758096383]	auto[1]	8	1			T125	1		T370	1		T421	1
auto[3758096384:3892314111]	auto[0]	72	1			T25	1		T198	1		T205	1
auto[3758096384:3892314111]	auto[1]	6	1			T125	1		T126	1		T376	1
auto[3892314112:4026531839]	auto[0]	86	1			T6	1		T197	1		T41	1
auto[3892314112:4026531839]	auto[1]	7	1			T408	1		T409	1		T407	1
auto[4026531840:4160749567]	auto[0]	86	1			T25	1		T45	1		T124	1
auto[4026531840:4160749567]	auto[1]	9	1			T258	1		T407	1		T346	1
auto[4160749568:4294967295]	auto[0]	93	1			T150	1		T35	2		T41	1
auto[4160749568:4294967295]	auto[1]	9	1			T125	2		T85	1		T371	1