Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.88	99.10	97.99	98.76	100.00	99.12	98.41	91.81

Total test records in report: 1065

T355	/workspace/coverage/default/13.keymgr_random.785641967	May 25 02:14:28 PM PDT 24	May 25 02:14:32 PM PDT 24	56946612 ps
T1015	/workspace/coverage/default/29.keymgr_sync_async_fault_cross.3712665623	May 25 02:15:26 PM PDT 24	May 25 02:15:29 PM PDT 24	487241679 ps
T1016	/workspace/coverage/default/29.keymgr_alert_test.1369929521	May 25 02:15:24 PM PDT 24	May 25 02:15:25 PM PDT 24	48805065 ps
T1017	/workspace/coverage/default/20.keymgr_alert_test.3614649530	May 25 02:15:00 PM PDT 24	May 25 02:15:01 PM PDT 24	40913381 ps
T314	/workspace/coverage/default/37.keymgr_stress_all.2425161172	May 25 02:15:51 PM PDT 24	May 25 02:16:34 PM PDT 24	1104985134 ps
T1018	/workspace/coverage/default/28.keymgr_sideload_protect.1619311538	May 25 02:15:21 PM PDT 24	May 25 02:15:24 PM PDT 24	27376833 ps
T1019	/workspace/coverage/default/42.keymgr_sideload_aes.3600842985	May 25 02:16:06 PM PDT 24	May 25 02:16:10 PM PDT 24	37297195 ps
T296	/workspace/coverage/default/32.keymgr_kmac_rsp_err.3794082039	May 25 02:15:36 PM PDT 24	May 25 02:15:43 PM PDT 24	84243241 ps
T169	/workspace/coverage/default/16.keymgr_custom_cm.4139179822	May 25 02:14:50 PM PDT 24	May 25 02:14:56 PM PDT 24	116206724 ps
T1020	/workspace/coverage/default/23.keymgr_sideload.12037600	May 25 02:15:05 PM PDT 24	May 25 02:15:09 PM PDT 24	83417608 ps
T1021	/workspace/coverage/default/38.keymgr_random.1067926774	May 25 02:15:52 PM PDT 24	May 25 02:15:59 PM PDT 24	1511184933 ps
T347	/workspace/coverage/default/28.keymgr_cfg_regwen.2872772482	May 25 02:15:19 PM PDT 24	May 25 02:15:25 PM PDT 24	229552585 ps
T1022	/workspace/coverage/default/5.keymgr_stress_all.91533388	May 25 02:13:57 PM PDT 24	May 25 02:17:35 PM PDT 24	8875668149 ps
T1023	/workspace/coverage/default/34.keymgr_hwsw_invalid_input.840231603	May 25 02:15:38 PM PDT 24	May 25 02:15:53 PM PDT 24	644186028 ps
T1024	/workspace/coverage/default/30.keymgr_sideload_kmac.2343595211	May 25 02:15:32 PM PDT 24	May 25 02:15:39 PM PDT 24	358674655 ps
T1025	/workspace/coverage/default/44.keymgr_alert_test.1522744854	May 25 02:16:11 PM PDT 24	May 25 02:16:13 PM PDT 24	50755188 ps
T359	/workspace/coverage/default/2.keymgr_sw_invalid_input.4076444156	May 25 02:13:54 PM PDT 24	May 25 02:14:01 PM PDT 24	497763454 ps
T1026	/workspace/coverage/default/22.keymgr_sideload.2329333577	May 25 02:15:02 PM PDT 24	May 25 02:15:08 PM PDT 24	109080473 ps
T1027	/workspace/coverage/default/27.keymgr_smoke.1688479971	May 25 02:15:19 PM PDT 24	May 25 02:15:23 PM PDT 24	380408454 ps
T1028	/workspace/coverage/default/19.keymgr_smoke.2264885106	May 25 02:14:51 PM PDT 24	May 25 02:14:58 PM PDT 24	1011498178 ps
T1029	/workspace/coverage/default/9.keymgr_direct_to_disabled.4013955794	May 25 02:14:22 PM PDT 24	May 25 02:14:25 PM PDT 24	397757326 ps
T1030	/workspace/coverage/default/41.keymgr_stress_all.3159235433	May 25 02:16:03 PM PDT 24	May 25 02:16:12 PM PDT 24	1891066763 ps
T392	/workspace/coverage/default/29.keymgr_kmac_rsp_err.3772745526	May 25 02:15:18 PM PDT 24	May 25 02:15:28 PM PDT 24	347913703 ps
T1031	/workspace/coverage/default/26.keymgr_alert_test.3367249394	May 25 02:15:14 PM PDT 24	May 25 02:15:15 PM PDT 24	154909743 ps
T1032	/workspace/coverage/default/4.keymgr_sideload_kmac.3795791652	May 25 02:13:59 PM PDT 24	May 25 02:14:05 PM PDT 24	453101498 ps
T1033	/workspace/coverage/default/48.keymgr_sideload_kmac.1388027441	May 25 02:16:28 PM PDT 24	May 25 02:16:35 PM PDT 24	486709149 ps
T1034	/workspace/coverage/default/16.keymgr_sideload_aes.3546507103	May 25 02:14:46 PM PDT 24	May 25 02:14:51 PM PDT 24	133657933 ps
T1035	/workspace/coverage/default/32.keymgr_random.394070734	May 25 02:15:29 PM PDT 24	May 25 02:15:38 PM PDT 24	1698692964 ps
T48	/workspace/coverage/default/12.keymgr_stress_all.2911698848	May 25 02:14:35 PM PDT 24	May 25 02:14:52 PM PDT 24	577268313 ps
T1036	/workspace/coverage/default/15.keymgr_hwsw_invalid_input.2429852261	May 25 02:14:29 PM PDT 24	May 25 02:14:32 PM PDT 24	188309612 ps
T1037	/workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.458729110	May 25 02:14:16 PM PDT 24	May 25 02:14:24 PM PDT 24	374671639 ps
T1038	/workspace/coverage/default/3.keymgr_sideload_otbn.3093902540	May 25 02:14:01 PM PDT 24	May 25 02:14:05 PM PDT 24	105963488 ps
T1039	/workspace/coverage/default/18.keymgr_alert_test.1666628734	May 25 02:14:51 PM PDT 24	May 25 02:14:53 PM PDT 24	26587797 ps
T180	/workspace/coverage/default/5.keymgr_sync_async_fault_cross.2665207304	May 25 02:13:54 PM PDT 24	May 25 02:13:57 PM PDT 24	74057249 ps
T1040	/workspace/coverage/default/44.keymgr_sideload_kmac.3278246338	May 25 02:16:09 PM PDT 24	May 25 02:16:57 PM PDT 24	5424212917 ps
T1041	/workspace/coverage/default/23.keymgr_smoke.938454938	May 25 02:15:04 PM PDT 24	May 25 02:15:26 PM PDT 24	1349152662 ps
T415	/workspace/coverage/default/22.keymgr_cfg_regwen.3873957373	May 25 02:15:02 PM PDT 24	May 25 02:15:07 PM PDT 24	60442452 ps
T1042	/workspace/coverage/default/7.keymgr_lc_disable.2508983143	May 25 02:14:07 PM PDT 24	May 25 02:14:13 PM PDT 24	71210301 ps
T338	/workspace/coverage/default/14.keymgr_kmac_rsp_err.4054090762	May 25 02:14:30 PM PDT 24	May 25 02:14:45 PM PDT 24	1242018645 ps
T1043	/workspace/coverage/default/9.keymgr_custom_cm.3004055502	May 25 02:14:22 PM PDT 24	May 25 02:14:25 PM PDT 24	335792788 ps
T1044	/workspace/coverage/default/9.keymgr_sideload_protect.3416092523	May 25 02:14:15 PM PDT 24	May 25 02:14:18 PM PDT 24	251311056 ps
T1045	/workspace/coverage/default/25.keymgr_stress_all.2305385707	May 25 02:15:13 PM PDT 24	May 25 02:15:30 PM PDT 24	776922092 ps
T413	/workspace/coverage/default/33.keymgr_cfg_regwen.2307055976	May 25 02:15:37 PM PDT 24	May 25 02:15:44 PM PDT 24	74204675 ps
T432	/workspace/coverage/default/5.keymgr_cfg_regwen.585723044	May 25 02:13:53 PM PDT 24	May 25 02:13:58 PM PDT 24	80101308 ps
T1046	/workspace/coverage/default/12.keymgr_direct_to_disabled.3764138837	May 25 02:14:18 PM PDT 24	May 25 02:15:02 PM PDT 24	10959292377 ps
T1047	/workspace/coverage/default/24.keymgr_sideload_otbn.1811550148	May 25 02:15:07 PM PDT 24	May 25 02:15:11 PM PDT 24	185477626 ps
T305	/workspace/coverage/default/30.keymgr_cfg_regwen.2059848039	May 25 02:15:27 PM PDT 24	May 25 02:15:40 PM PDT 24	238485678 ps
T1048	/workspace/coverage/default/23.keymgr_sideload_kmac.3811981281	May 25 02:15:04 PM PDT 24	May 25 02:15:13 PM PDT 24	877380073 ps
T1049	/workspace/coverage/default/48.keymgr_sideload_protect.1243090048	May 25 02:16:25 PM PDT 24	May 25 02:16:29 PM PDT 24	175682238 ps
T1050	/workspace/coverage/default/19.keymgr_lc_disable.574339819	May 25 02:14:54 PM PDT 24	May 25 02:14:58 PM PDT 24	159447317 ps
T1051	/workspace/coverage/default/8.keymgr_sideload_aes.1149312326	May 25 02:14:06 PM PDT 24	May 25 02:14:09 PM PDT 24	50590319 ps
T1052	/workspace/coverage/default/4.keymgr_sideload_aes.3130126193	May 25 02:13:59 PM PDT 24	May 25 02:14:03 PM PDT 24	54625522 ps
T1053	/workspace/coverage/default/16.keymgr_sync_async_fault_cross.4152106306	May 25 02:14:47 PM PDT 24	May 25 02:14:52 PM PDT 24	228136005 ps
T1054	/workspace/coverage/default/39.keymgr_sw_invalid_input.807948502	May 25 02:15:59 PM PDT 24	May 25 02:16:03 PM PDT 24	39320469 ps
T1055	/workspace/coverage/default/12.keymgr_sideload_aes.3458371697	May 25 02:14:18 PM PDT 24	May 25 02:14:22 PM PDT 24	122477208 ps
T1056	/workspace/coverage/default/28.keymgr_sync_async_fault_cross.1473696422	May 25 02:15:23 PM PDT 24	May 25 02:15:33 PM PDT 24	1038624053 ps
T1057	/workspace/coverage/default/31.keymgr_smoke.1615758221	May 25 02:15:35 PM PDT 24	May 25 02:15:37 PM PDT 24	21463807 ps
T1058	/workspace/coverage/default/26.keymgr_cfg_regwen.2749045960	May 25 02:15:10 PM PDT 24	May 25 02:15:14 PM PDT 24	47392245 ps
T1059	/workspace/coverage/default/13.keymgr_hwsw_invalid_input.3237294873	May 25 02:14:38 PM PDT 24	May 25 02:14:44 PM PDT 24	211522192 ps
T1060	/workspace/coverage/default/43.keymgr_sideload_kmac.4062214869	May 25 02:16:08 PM PDT 24	May 25 02:16:11 PM PDT 24	100207483 ps
T1061	/workspace/coverage/default/47.keymgr_sideload_aes.799715265	May 25 02:16:23 PM PDT 24	May 25 02:16:31 PM PDT 24	275462576 ps
T1062	/workspace/coverage/default/15.keymgr_sw_invalid_input.1696854013	May 25 02:14:31 PM PDT 24	May 25 02:14:34 PM PDT 24	64443634 ps
T1063	/workspace/coverage/default/31.keymgr_sideload_aes.3629067457	May 25 02:15:30 PM PDT 24	May 25 02:15:33 PM PDT 24	500478166 ps
T1064	/workspace/coverage/default/35.keymgr_sideload_protect.2140200477	May 25 02:15:49 PM PDT 24	May 25 02:15:52 PM PDT 24	57048299 ps
T1065	/workspace/coverage/default/10.keymgr_sideload_kmac.1482941190	May 25 02:14:20 PM PDT 24	May 25 02:14:24 PM PDT 24	461233877 ps

Test location	/workspace/coverage/default/15.keymgr_custom_cm.1207822599
Short name	T1
Test name
Test status
Simulation time	193536066 ps
CPU time	4.63 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:42 PM PDT 24
Peak memory	221308 kb
Host	smart-936aee87-fa15-467a-95d2-05df212a26ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207822599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1207822599
Directory	/workspace/15.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all.4283805600
Short name	T68
Test name
Test status
Simulation time	954004710 ps
CPU time	32.33 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	220344 kb
Host	smart-375271e3-1bdf-42ed-854c-69261d763b9c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283805600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4283805600
Directory	/workspace/15.keymgr_stress_all/latest

Test location	/workspace/coverage/default/36.keymgr_stress_all.3105317464
Short name	T25
Test name
Test status
Simulation time	748220617 ps
CPU time	26.59 seconds
Started	May 25 02:15:54 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	214804 kb
Host	smart-ecfa8f97-f50a-4207-9057-219e240f37b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105317464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3105317464
Directory	/workspace/36.keymgr_stress_all/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all.3492311257
Short name	T8
Test name
Test status
Simulation time	488286052 ps
CPU time	23.08 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:50 PM PDT 24
Peak memory	222196 kb
Host	smart-23701e13-a105-4476-b3e1-41402a445835
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492311257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3492311257
Directory	/workspace/48.keymgr_stress_all/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.22945851
Short name	T81
Test name
Test status
Simulation time	527533804 ps
CPU time	11.69 seconds
Started	May 25 02:16:04 PM PDT 24
Finished	May 25 02:16:16 PM PDT 24
Peak memory	222348 kb
Host	smart-5930a6f9-2c59-44f0-8fbd-0ae5f4bc5bb0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22945851 -assert nopostp roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.22945851
Directory	/workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.keymgr_sec_cm.3652339888
Short name	T9
Test name
Test status
Simulation time	714182926 ps
CPU time	12.56 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	231412 kb
Host	smart-11fb258d-25ea-48fa-8c94-9cb2a1237838
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652339888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3652339888
Directory	/workspace/1.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all.2251434458
Short name	T41
Test name
Test status
Simulation time	789748054 ps
CPU time	20.77 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	222104 kb
Host	smart-ee026efa-32a9-483c-b9c2-343c6e57f688
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251434458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2251434458
Directory	/workspace/17.keymgr_stress_all/latest

Test location	/workspace/coverage/default/18.keymgr_custom_cm.2385308408
Short name	T12
Test name
Test status
Simulation time	103730777 ps
CPU time	3.66 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	214316 kb
Host	smart-cb40eb12-7685-4268-85fd-f096d38e4a38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385308408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2385308408
Directory	/workspace/18.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/34.keymgr_cfg_regwen.2930450909
Short name	T126
Test name
Test status
Simulation time	7912749855 ps
CPU time	108.06 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:17:27 PM PDT 24
Peak memory	215976 kb
Host	smart-254cb01f-9640-4e1a-9040-2719878d5a8a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2930450909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2930450909
Directory	/workspace/34.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2452319142
Short name	T121
Test name
Test status
Simulation time	201290446 ps
CPU time	4.32 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:20 PM PDT 24
Peak memory	214008 kb
Host	smart-2da2995d-36e4-46ee-a08b-d92b3e839f89
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452319142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. keymgr_shadow_reg_errors_with_csr_rw.2452319142
Directory	/workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all.1462109478
Short name	T59
Test name
Test status
Simulation time	1060476744 ps
CPU time	38.1 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	222100 kb
Host	smart-9f4530b6-44c4-4b7d-bfd7-5234fc939e2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462109478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1462109478
Directory	/workspace/21.keymgr_stress_all/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all.2019863558
Short name	T46
Test name
Test status
Simulation time	6842686848 ps
CPU time	119.69 seconds
Started	May 25 02:15:34 PM PDT 24
Finished	May 25 02:17:35 PM PDT 24
Peak memory	222300 kb
Host	smart-4f5f6092-3846-4187-891e-e074d9ebbd2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019863558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2019863558
Directory	/workspace/31.keymgr_stress_all/latest

Test location	/workspace/coverage/default/45.keymgr_kmac_rsp_err.626832222
Short name	T202
Test name
Test status
Simulation time	527213952 ps
CPU time	5.58 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	222172 kb
Host	smart-cc1e7792-4216-4b57-b06e-2402b6b41a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626832222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.626832222
Directory	/workspace/45.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/18.keymgr_cfg_regwen.524352704
Short name	T124
Test name
Test status
Simulation time	1249726489 ps
CPU time	10.75 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:15:01 PM PDT 24
Peak memory	213968 kb
Host	smart-05ff4f76-7446-4e1c-8d92-2792fc6c975a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=524352704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.524352704
Directory	/workspace/18.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/16.keymgr_cfg_regwen.3264600365
Short name	T412
Test name
Test status
Simulation time	234233309 ps
CPU time	11.81 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:15:02 PM PDT 24
Peak memory	214852 kb
Host	smart-14f8dc39-2788-4e44-9921-50c13372980f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3264600365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3264600365
Directory	/workspace/16.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all.580448002
Short name	T75
Test name
Test status
Simulation time	2987650968 ps
CPU time	67.68 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:17:25 PM PDT 24
Peak memory	222224 kb
Host	smart-392cd7e2-5fea-4bc1-b057-4db742cb88f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580448002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.580448002
Directory	/workspace/45.keymgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1756298387
Short name	T123
Test name
Test status
Simulation time	2689902229 ps
CPU time	69.44 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:07:20 PM PDT 24
Peak memory	211540 kb
Host	smart-7b587261-606c-418f-9b35-64613683af6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756298387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err .1756298387
Directory	/workspace/3.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/36.keymgr_hwsw_invalid_input.2233983080
Short name	T92
Test name
Test status
Simulation time	321493600 ps
CPU time	3.59 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	219948 kb
Host	smart-f1093c4c-a8f1-4133-b130-717dd6cec456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233983080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2233983080
Directory	/workspace/36.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_cfg_regwen.2872220882
Short name	T380
Test name
Test status
Simulation time	1563389044 ps
CPU time	85.19 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:17:02 PM PDT 24
Peak memory	217792 kb
Host	smart-1cc6f36c-2bef-49b7-a75f-61e79fe675a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2872220882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2872220882
Directory	/workspace/31.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/0.keymgr_stress_all.3785882552
Short name	T53
Test name
Test status
Simulation time	32172814281 ps
CPU time	135.19 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	218192 kb
Host	smart-ff9a047c-3e56-462f-8c0a-22e515838c7e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785882552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3785882552
Directory	/workspace/0.keymgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.114667013
Short name	T128
Test name
Test status
Simulation time	468014375 ps
CPU time	4.58 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:28 PM PDT 24
Peak memory	214032 kb
Host	smart-1fca8326-7ed5-4c62-8426-c5d6b29d6254
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114667013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado w_reg_errors.114667013
Directory	/workspace/10.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/49.keymgr_cfg_regwen.356447970
Short name	T254
Test name
Test status
Simulation time	7588096877 ps
CPU time	51.28 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:17:16 PM PDT 24
Peak memory	215564 kb
Host	smart-8b7f4d7a-0cd9-4894-b1b6-9eed99eab683
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=356447970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.356447970
Directory	/workspace/49.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/4.keymgr_hwsw_invalid_input.3236641876
Short name	T21
Test name
Test status
Simulation time	75143729 ps
CPU time	2.87 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	208336 kb
Host	smart-cc2b43f7-7f01-4494-8d15-7c4f98d77b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236641876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3236641876
Directory	/workspace/4.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.580697891
Short name	T118
Test name
Test status
Simulation time	96143992 ps
CPU time	7.12 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	222372 kb
Host	smart-20497398-7413-4efa-9534-5e4d4ef47ec5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580697891 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.580697891
Directory	/workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.keymgr_cfg_regwen.413411301
Short name	T407
Test name
Test status
Simulation time	744898374 ps
CPU time	18.17 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:35 PM PDT 24
Peak memory	214008 kb
Host	smart-c3c77c1d-68f0-45e8-9c82-e06832595ff1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=413411301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.413411301
Directory	/workspace/10.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/22.keymgr_custom_cm.393353571
Short name	T614
Test name
Test status
Simulation time	129512756 ps
CPU time	3.53 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	207720 kb
Host	smart-5cea8f92-e50e-4294-9db4-f4e6d09ddefa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=393353571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.393353571
Directory	/workspace/22.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/8.keymgr_stress_all.1457974191
Short name	T54
Test name
Test status
Simulation time	1270361547 ps
CPU time	13 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:30 PM PDT 24
Peak memory	222128 kb
Host	smart-ed418276-75dd-402f-93cd-18b0dbafbb7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457974191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1457974191
Directory	/workspace/8.keymgr_stress_all/latest

Test location	/workspace/coverage/default/40.keymgr_kmac_rsp_err.1222941256
Short name	T203
Test name
Test status
Simulation time	124782105 ps
CPU time	4.67 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	213884 kb
Host	smart-040afd0b-5824-447c-a87d-9546672a64df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222941256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1222941256
Directory	/workspace/40.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/49.keymgr_custom_cm.3625456189
Short name	T31
Test name
Test status
Simulation time	155667613 ps
CPU time	2.88 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	217352 kb
Host	smart-13f72e42-f6e7-447d-94e4-6ab900a03ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625456189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3625456189
Directory	/workspace/49.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/27.keymgr_cfg_regwen.184224359
Short name	T371
Test name
Test status
Simulation time	315732663 ps
CPU time	4.99 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	214044 kb
Host	smart-498eef9b-1442-496f-84f1-6507bce39780
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=184224359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.184224359
Directory	/workspace/27.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/47.keymgr_custom_cm.3192094321
Short name	T162
Test name
Test status
Simulation time	441951539 ps
CPU time	4.64 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:32 PM PDT 24
Peak memory	222352 kb
Host	smart-4769da18-2948-4121-ad1a-f67e8dc0370b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192094321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3192094321
Directory	/workspace/47.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/30.keymgr_cfg_regwen.2059848039
Short name	T305
Test name
Test status
Simulation time	238485678 ps
CPU time	12.88 seconds
Started	May 25 02:15:27 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	214048 kb
Host	smart-0eac636a-54d4-44d5-8653-bcec6f94a68a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2059848039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2059848039
Directory	/workspace/30.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all.2675340768
Short name	T242
Test name
Test status
Simulation time	7556520294 ps
CPU time	52.44 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:58 PM PDT 24
Peak memory	222272 kb
Host	smart-de25757e-310f-4510-96d8-905b9b66a4f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675340768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2675340768
Directory	/workspace/39.keymgr_stress_all/latest

Test location	/workspace/coverage/default/44.keymgr_kmac_rsp_err.3335049949
Short name	T103
Test name
Test status
Simulation time	117962287 ps
CPU time	5.76 seconds
Started	May 25 02:16:14 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	222152 kb
Host	smart-d5420f91-37b8-40b0-8e0e-a76c5b696846
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335049949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3335049949
Directory	/workspace/44.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/32.keymgr_custom_cm.76080482
Short name	T27
Test name
Test status
Simulation time	326526007 ps
CPU time	5.1 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:45 PM PDT 24
Peak memory	209528 kb
Host	smart-e823e1b4-0611-41eb-a868-9013750636bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76080482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.76080482
Directory	/workspace/32.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/10.keymgr_stress_all.1113153359
Short name	T77
Test name
Test status
Simulation time	1758439481 ps
CPU time	33.37 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:50 PM PDT 24
Peak memory	215500 kb
Host	smart-7b3d21fe-e741-4bd2-9ba1-c831a444243f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113153359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1113153359
Directory	/workspace/10.keymgr_stress_all/latest

Test location	/workspace/coverage/default/14.keymgr_stress_all.1583950713
Short name	T7
Test name
Test status
Simulation time	2979855615 ps
CPU time	38.04 seconds
Started	May 25 02:14:27 PM PDT 24
Finished	May 25 02:15:05 PM PDT 24
Peak memory	216596 kb
Host	smart-8298ecbd-c50c-4b44-a1ad-68d755dac55c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583950713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1583950713
Directory	/workspace/14.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_kmac_rsp_err.679037336
Short name	T204
Test name
Test status
Simulation time	193257629 ps
CPU time	6.15 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	222164 kb
Host	smart-4a656ce4-a230-494f-a5b3-5f2b4e3df1d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679037336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.679037336
Directory	/workspace/35.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/8.keymgr_cfg_regwen.4209862591
Short name	T269
Test name
Test status
Simulation time	1058722865 ps
CPU time	14.66 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:35 PM PDT 24
Peak memory	215280 kb
Host	smart-8454415c-e42d-420a-8b25-c611e486c4d1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4209862591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4209862591
Directory	/workspace/8.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/1.keymgr_alert_test.4158558782
Short name	T582
Test name
Test status
Simulation time	44458448 ps
CPU time	0.8 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	205472 kb
Host	smart-d6d3324c-365c-4382-8b71-2515d0b4ff1a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158558782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4158558782
Directory	/workspace/1.keymgr_alert_test/latest

Test location	/workspace/coverage/default/38.keymgr_cfg_regwen.889940623
Short name	T117
Test name
Test status
Simulation time	267210895 ps
CPU time	15.92 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	222040 kb
Host	smart-5bca2d23-fe81-436a-b5af-6f357b3ecd68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=889940623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.889940623
Directory	/workspace/38.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/49.keymgr_hwsw_invalid_input.3893086714
Short name	T15
Test name
Test status
Simulation time	3495755650 ps
CPU time	41.5 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:17:11 PM PDT 24
Peak memory	214068 kb
Host	smart-beb8898b-c53c-4679-b40d-35fffc781d62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893086714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3893086714
Directory	/workspace/49.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2011990506
Short name	T177
Test name
Test status
Simulation time	224232177 ps
CPU time	6.08 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	213748 kb
Host	smart-bd449891-9b4f-480b-b3a9-c62d028570fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011990506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err .2011990506
Directory	/workspace/9.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_aes.4137616696
Short name	T303
Test name
Test status
Simulation time	31356189 ps
CPU time	2.34 seconds
Started	May 25 02:14:35 PM PDT 24
Finished	May 25 02:14:38 PM PDT 24
Peak memory	208376 kb
Host	smart-7c43be10-678e-47f8-a22c-55955ab82650
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137616696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4137616696
Directory	/workspace/14.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/16.keymgr_stress_all.3374775738
Short name	T382
Test name
Test status
Simulation time	2477031278 ps
CPU time	47.12 seconds
Started	May 25 02:14:46 PM PDT 24
Finished	May 25 02:15:33 PM PDT 24
Peak memory	216656 kb
Host	smart-5cf4da23-f8c6-44c2-8be7-1285d9d90c6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374775738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3374775738
Directory	/workspace/16.keymgr_stress_all/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all.2425161172
Short name	T314
Test name
Test status
Simulation time	1104985134 ps
CPU time	41.6 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:16:34 PM PDT 24
Peak memory	216368 kb
Host	smart-43c87c83-a1f9-462f-a133-f778d671656b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425161172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2425161172
Directory	/workspace/37.keymgr_stress_all/latest

Test location	/workspace/coverage/default/46.keymgr_cfg_regwen.1592071733
Short name	T333
Test name
Test status
Simulation time	168300749 ps
CPU time	2.72 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	214044 kb
Host	smart-d4673ce2-1e82-493f-91e1-ccd08fe1bd97
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1592071733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1592071733
Directory	/workspace/46.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/47.keymgr_kmac_rsp_err.3880055880
Short name	T215
Test name
Test status
Simulation time	530838283 ps
CPU time	2.82 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	214032 kb
Host	smart-d34f80d7-8567-4f3b-a302-6a07a46bd3cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880055880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3880055880
Directory	/workspace/47.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1119254521
Short name	T174
Test name
Test status
Simulation time	285082204 ps
CPU time	6.42 seconds
Started	May 25 02:06:28 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	208980 kb
Host	smart-d909d51f-967d-4855-a6af-970d30fee1cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119254521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er r.1119254521
Directory	/workspace/11.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1743685553
Short name	T170
Test name
Test status
Simulation time	799107824 ps
CPU time	14.01 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:38 PM PDT 24
Peak memory	213756 kb
Host	smart-226c2fde-f453-47bb-8a8e-7411e094deac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743685553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er r.1743685553
Directory	/workspace/10.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/26.keymgr_custom_cm.1070523286
Short name	T66
Test name
Test status
Simulation time	438239307 ps
CPU time	6.59 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:21 PM PDT 24
Peak memory	214444 kb
Host	smart-76109102-ba07-4843-aaeb-bb48ebb2ae5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070523286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1070523286
Directory	/workspace/26.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/31.keymgr_custom_cm.3270070929
Short name	T71
Test name
Test status
Simulation time	204551245 ps
CPU time	2.31 seconds
Started	May 25 02:15:32 PM PDT 24
Finished	May 25 02:15:35 PM PDT 24
Peak memory	215232 kb
Host	smart-31d27e6a-097c-425c-b44c-6b3c53b9712d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270070929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3270070929
Directory	/workspace/31.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/8.keymgr_custom_cm.2586182262
Short name	T160
Test name
Test status
Simulation time	277337602 ps
CPU time	3.25 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:21 PM PDT 24
Peak memory	217088 kb
Host	smart-f3eee0b8-3c33-40ba-b683-367910bc5a4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586182262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2586182262
Directory	/workspace/8.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/41.keymgr_custom_cm.491612693
Short name	T163
Test name
Test status
Simulation time	422026962 ps
CPU time	12.36 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	217364 kb
Host	smart-ca0857e5-4fd6-468c-b38a-f7aebd4d6c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491612693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.491612693
Directory	/workspace/41.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/47.keymgr_cfg_regwen.1891190351
Short name	T125
Test name
Test status
Simulation time	70434579 ps
CPU time	4.29 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	213904 kb
Host	smart-1ec9cfc1-90f2-4586-accb-500e30396b43
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1891190351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1891190351
Directory	/workspace/47.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/37.keymgr_hwsw_invalid_input.3707656055
Short name	T90
Test name
Test status
Simulation time	1721225803 ps
CPU time	17.44 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	214108 kb
Host	smart-3f91d216-297a-47cc-ab1c-909f9de1dafe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707656055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3707656055
Directory	/workspace/37.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3823081090
Short name	T173
Test name
Test status
Simulation time	455489688 ps
CPU time	5.25 seconds
Started	May 25 02:06:31 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	213752 kb
Host	smart-fb86afab-bf55-48fa-be1a-13f904f7bad8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823081090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er r.3823081090
Directory	/workspace/14.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2252193747
Short name	T138
Test name
Test status
Simulation time	13275512841 ps
CPU time	84.61 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:07:49 PM PDT 24
Peak memory	232012 kb
Host	smart-7fde0c6c-42e0-48f1-9637-1c8243c52d35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252193747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err .2252193747
Directory	/workspace/8.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.keymgr_custom_cm.3915013167
Short name	T167
Test name
Test status
Simulation time	56135720 ps
CPU time	3.06 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	222328 kb
Host	smart-2c2a5f6e-9347-4482-8dac-7191b2b20ec8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915013167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3915013167
Directory	/workspace/0.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/46.keymgr_custom_cm.1819557896
Short name	T159
Test name
Test status
Simulation time	664598271 ps
CPU time	4.66 seconds
Started	May 25 02:16:20 PM PDT 24
Finished	May 25 02:16:25 PM PDT 24
Peak memory	216984 kb
Host	smart-2bdf2ebc-10e3-45e7-b067-dd595f516c94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819557896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1819557896
Directory	/workspace/46.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/24.keymgr_custom_cm.3568288031
Short name	T161
Test name
Test status
Simulation time	187089854 ps
CPU time	3.66 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	222248 kb
Host	smart-a76dad5d-1197-477c-9558-ad8c301c0e74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568288031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3568288031
Directory	/workspace/24.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/12.keymgr_cfg_regwen.776524247
Short name	T85
Test name
Test status
Simulation time	84780781 ps
CPU time	3.13 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:21 PM PDT 24
Peak memory	214892 kb
Host	smart-a8dabb30-46f3-4434-a305-5e3d4b8d5b01
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=776524247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.776524247
Directory	/workspace/12.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all.921341122
Short name	T73
Test name
Test status
Simulation time	7153876661 ps
CPU time	65.77 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	222316 kb
Host	smart-2f02684b-3810-4998-a12e-34dbe1e662e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921341122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.921341122
Directory	/workspace/13.keymgr_stress_all/latest

Test location	/workspace/coverage/default/22.keymgr_cfg_regwen.3873957373
Short name	T415
Test name
Test status
Simulation time	60442452 ps
CPU time	3.79 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	214940 kb
Host	smart-22d172f9-a9aa-423f-8520-de4223358be8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3873957373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3873957373
Directory	/workspace/22.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_kmac.886521059
Short name	T400
Test name
Test status
Simulation time	251128263 ps
CPU time	9.39 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	207996 kb
Host	smart-6614c2f8-bf8f-461f-b3de-fa32bbe9f948
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886521059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.886521059
Directory	/workspace/25.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/32.keymgr_kmac_rsp_err.3794082039
Short name	T296
Test name
Test status
Simulation time	84243241 ps
CPU time	5.34 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	222136 kb
Host	smart-b8d49896-0fda-4b87-acc7-9f346f951e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794082039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3794082039
Directory	/workspace/32.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/42.keymgr_hwsw_invalid_input.3984710172
Short name	T286
Test name
Test status
Simulation time	31100672 ps
CPU time	2.31 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	208664 kb
Host	smart-6eb218e6-a555-497b-9cdf-3661bc9a52ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984710172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3984710172
Directory	/workspace/42.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_kmac_rsp_err.3260671216
Short name	T50
Test name
Test status
Simulation time	38775594 ps
CPU time	2.9 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	209228 kb
Host	smart-4bbdd8de-1926-4989-ae1a-c63fd46352e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260671216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3260671216
Directory	/workspace/42.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/11.keymgr_custom_cm.1779364277
Short name	T165
Test name
Test status
Simulation time	171879380 ps
CPU time	5.11 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	217140 kb
Host	smart-9a01522a-c17c-4c99-833d-e1a9774f5185
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779364277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1779364277
Directory	/workspace/11.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_sw_invalid_input.4075025140
Short name	T300
Test name
Test status
Simulation time	710073782 ps
CPU time	22.67 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:17 PM PDT 24
Peak memory	217924 kb
Host	smart-da26cad4-3a60-4d45-ab05-8a1663d0a276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075025140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4075025140
Directory	/workspace/1.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_kmac_rsp_err.911436178
Short name	T273
Test name
Test status
Simulation time	342570049 ps
CPU time	5.89 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	213824 kb
Host	smart-1d64b4d6-558d-47f1-afe2-09104e4f7015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=911436178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.911436178
Directory	/workspace/11.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_aes.1579512898
Short name	T260
Test name
Test status
Simulation time	369509660 ps
CPU time	3.54 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	208344 kb
Host	smart-7f7f5592-3eb4-4688-8d5b-0634ae8f8383
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579512898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1579512898
Directory	/workspace/17.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/22.keymgr_kmac_rsp_err.908633378
Short name	T297
Test name
Test status
Simulation time	5844290887 ps
CPU time	112.49 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:17:01 PM PDT 24
Peak memory	232864 kb
Host	smart-ec569c4d-6d3e-45e3-918e-541a05e03326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908633378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.908633378
Directory	/workspace/22.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all.2652697491
Short name	T232
Test name
Test status
Simulation time	8341461376 ps
CPU time	57.11 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:16:15 PM PDT 24
Peak memory	222352 kb
Host	smart-467b5955-a89c-4400-920f-a3887cd530d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652697491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2652697491
Directory	/workspace/27.keymgr_stress_all/latest

Test location	/workspace/coverage/default/29.keymgr_stress_all.3473498074
Short name	T917
Test name
Test status
Simulation time	4320171060 ps
CPU time	28.35 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:51 PM PDT 24
Peak memory	215024 kb
Host	smart-09e1b450-1fc3-49ee-b070-a97fbaba029c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473498074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3473498074
Directory	/workspace/29.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_cfg_regwen.1927221725
Short name	T358
Test name
Test status
Simulation time	313332222 ps
CPU time	3.73 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	213992 kb
Host	smart-887debd3-53ff-424c-8018-728e7bad14ea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1927221725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1927221725
Directory	/workspace/32.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/33.keymgr_kmac_rsp_err.748136694
Short name	T377
Test name
Test status
Simulation time	126581231 ps
CPU time	4.59 seconds
Started	May 25 02:15:39 PM PDT 24
Finished	May 25 02:15:45 PM PDT 24
Peak memory	210508 kb
Host	smart-4d98584d-5006-4cc2-b354-8f68230e29b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748136694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.748136694
Directory	/workspace/33.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3916938255
Short name	T221
Test name
Test status
Simulation time	714896815 ps
CPU time	15.13 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	222432 kb
Host	smart-10aa73ff-bdea-4c89-8022-05ba970e0c3b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916938255 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3916938255
Directory	/workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.keymgr_kmac_rsp_err.2898840452
Short name	T337
Test name
Test status
Simulation time	2195209045 ps
CPU time	14.39 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:17 PM PDT 24
Peak memory	211664 kb
Host	smart-14b593b8-c8d7-43ee-9382-8fdb02271fec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898840452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2898840452
Directory	/workspace/39.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/40.keymgr_cfg_regwen.330199766
Short name	T340
Test name
Test status
Simulation time	271517119 ps
CPU time	5.36 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	214012 kb
Host	smart-f920b658-3c72-4af8-aca3-365388a82280
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=330199766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.330199766
Directory	/workspace/40.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/48.keymgr_cfg_regwen.8968221
Short name	T353
Test name
Test status
Simulation time	6249598578 ps
CPU time	86.36 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:17:55 PM PDT 24
Peak memory	214792 kb
Host	smart-bb3d3811-c7a2-4695-9435-2ee9d9777059
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=8968221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.8968221
Directory	/workspace/48.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_kmac.1206008663
Short name	T311
Test name
Test status
Simulation time	60068543 ps
CPU time	2.94 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:32 PM PDT 24
Peak memory	206724 kb
Host	smart-4c01b0fc-58ce-445f-a071-f2d4a827316c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206008663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1206008663
Directory	/workspace/49.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2614878410
Short name	T467
Test name
Test status
Simulation time	534733381 ps
CPU time	3.79 seconds
Started	May 25 02:06:27 PM PDT 24
Finished	May 25 02:06:32 PM PDT 24
Peak memory	213792 kb
Host	smart-279e7df4-e449-4183-86ad-14b6a1137f9f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614878410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2614878410
Directory	/workspace/11.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1224546987
Short name	T172
Test name
Test status
Simulation time	493278699 ps
CPU time	7.97 seconds
Started	May 25 02:06:17 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	209088 kb
Host	smart-5bcc83e9-11e1-49be-a665-e2b64063570d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224546987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err .1224546987
Directory	/workspace/7.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/default/13.keymgr_custom_cm.665631281
Short name	T978
Test name
Test status
Simulation time	58822792 ps
CPU time	3.45 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:33 PM PDT 24
Peak memory	209020 kb
Host	smart-6d2a54b2-8622-4b9b-ba07-ac7ee8156136
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665631281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.665631281
Directory	/workspace/13.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/45.keymgr_sync_async_fault_cross.3973908821
Short name	T171
Test name
Test status
Simulation time	112554116 ps
CPU time	1.83 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	209728 kb
Host	smart-bbee296d-a6ec-460a-8ec0-28e4aee232a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973908821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3973908821
Directory	/workspace/45.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/12.keymgr_custom_cm.264439332
Short name	T168
Test name
Test status
Simulation time	73955792 ps
CPU time	3.8 seconds
Started	May 25 02:14:28 PM PDT 24
Finished	May 25 02:14:33 PM PDT 24
Peak memory	218236 kb
Host	smart-5bdadfab-4436-43b6-841a-00b568a9ae83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264439332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.264439332
Directory	/workspace/12.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_sec_cm.1148162211
Short name	T13
Test name
Test status
Simulation time	817329114 ps
CPU time	7.51 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:02 PM PDT 24
Peak memory	233520 kb
Host	smart-8a54c9e5-e408-429b-b35b-e136afeeee2a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148162211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1148162211
Directory	/workspace/0.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/16.keymgr_custom_cm.4139179822
Short name	T169
Test name
Test status
Simulation time	116206724 ps
CPU time	5.15 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	217588 kb
Host	smart-826e099e-a457-4762-a28f-91e4cc9ad73f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139179822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4139179822
Directory	/workspace/16.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/2.keymgr_custom_cm.1657439794
Short name	T158
Test name
Test status
Simulation time	41706627 ps
CPU time	3.17 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:56 PM PDT 24
Peak memory	222316 kb
Host	smart-fb155d5a-ba95-44ba-9cfa-00ac5d0056aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657439794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1657439794
Directory	/workspace/2.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/27.keymgr_custom_cm.3615410332
Short name	T164
Test name
Test status
Simulation time	290348708 ps
CPU time	9.37 seconds
Started	May 25 02:15:16 PM PDT 24
Finished	May 25 02:15:26 PM PDT 24
Peak memory	217808 kb
Host	smart-1f62442d-cb79-4e4c-b1e5-95816867b06b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615410332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3615410332
Directory	/workspace/27.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/0.keymgr_lc_disable.2174081401
Short name	T265
Test name
Test status
Simulation time	184797101 ps
CPU time	3.58 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	208616 kb
Host	smart-09b1e57d-e536-4a30-bd36-899cc8cee04a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174081401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2174081401
Directory	/workspace/0.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/0.keymgr_sync_async_fault_cross.855726733
Short name	T929
Test name
Test status
Simulation time	312632775 ps
CPU time	4.1 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	210476 kb
Host	smart-47172498-73ae-4e0c-b85c-db81ef65c1ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855726733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.855726733
Directory	/workspace/0.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/10.keymgr_lc_disable.74217301
Short name	T234
Test name
Test status
Simulation time	66591136 ps
CPU time	3.77 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	209348 kb
Host	smart-0c46f6c8-2247-4b88-b3f0-c3151d49fd9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74217301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.74217301
Directory	/workspace/10.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_aes.2043778873
Short name	T566
Test name
Test status
Simulation time	294159907 ps
CPU time	2.67 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	206468 kb
Host	smart-ec3d9688-de06-46da-8fb9-b5a994698594
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043778873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2043778873
Directory	/workspace/10.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/11.keymgr_cfg_regwen.2870866135
Short name	T430
Test name
Test status
Simulation time	2686222335 ps
CPU time	10.11 seconds
Started	May 25 02:14:20 PM PDT 24
Finished	May 25 02:14:31 PM PDT 24
Peak memory	222160 kb
Host	smart-d396b5a1-adad-4e1b-bb4a-ccfc498d7c58
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2870866135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2870866135
Directory	/workspace/11.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/11.keymgr_direct_to_disabled.4126382187
Short name	T364
Test name
Test status
Simulation time	195201169 ps
CPU time	6.99 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	217992 kb
Host	smart-32ec7253-eb31-4f6a-868c-fd427331a4ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126382187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4126382187
Directory	/workspace/11.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/11.keymgr_sideload.3018490428
Short name	T981
Test name
Test status
Simulation time	74702921 ps
CPU time	3.23 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	206484 kb
Host	smart-0fe166e9-b4d5-4187-bb8b-725a9ebaafd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018490428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3018490428
Directory	/workspace/11.keymgr_sideload/latest

Test location	/workspace/coverage/default/11.keymgr_sync_async_fault_cross.2339665367
Short name	T577
Test name
Test status
Simulation time	121772034 ps
CPU time	3.18 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	209944 kb
Host	smart-a0572072-7b62-41e7-b746-ef36f7e6116a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339665367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2339665367
Directory	/workspace/11.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/12.keymgr_kmac_rsp_err.4272509149
Short name	T391
Test name
Test status
Simulation time	56617169 ps
CPU time	3.27 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:35 PM PDT 24
Peak memory	210760 kb
Host	smart-c8b3fb98-dfb5-44e3-9eea-9bfde3ce83fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272509149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4272509149
Directory	/workspace/12.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/12.keymgr_lc_disable.1031921343
Short name	T240
Test name
Test status
Simulation time	458080611 ps
CPU time	5.45 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	214012 kb
Host	smart-cfac9a81-09f3-4674-9c94-6d17cec45c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031921343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1031921343
Directory	/workspace/12.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/13.keymgr_sw_invalid_input.1647505394
Short name	T326
Test name
Test status
Simulation time	1006574540 ps
CPU time	8.08 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:39 PM PDT 24
Peak memory	207820 kb
Host	smart-340e5288-807d-47c7-a465-e35ee7482a03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647505394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1647505394
Directory	/workspace/13.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_kmac_rsp_err.1310631801
Short name	T317
Test name
Test status
Simulation time	1268130964 ps
CPU time	4.57 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	222096 kb
Host	smart-dd7580d0-1a70-42e1-a7dc-3d60148fa4d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310631801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1310631801
Directory	/workspace/16.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/17.keymgr_hwsw_invalid_input.2012408578
Short name	T281
Test name
Test status
Simulation time	207496909 ps
CPU time	5.7 seconds
Started	May 25 02:14:47 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	207564 kb
Host	smart-13d55543-8658-44a8-9c12-a74e10ff487f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012408578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2012408578
Directory	/workspace/17.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_lc_disable.2739234772
Short name	T385
Test name
Test status
Simulation time	227138160 ps
CPU time	10.75 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:06 PM PDT 24
Peak memory	219904 kb
Host	smart-05394745-b6a7-4093-9105-88c8befa01e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739234772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2739234772
Directory	/workspace/2.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/21.keymgr_sw_invalid_input.3466401877
Short name	T321
Test name
Test status
Simulation time	52556671 ps
CPU time	3.77 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	214004 kb
Host	smart-b4c6b5cb-4c8d-41a2-ae9a-d9f91c519cac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466401877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3466401877
Directory	/workspace/21.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all.2626561973
Short name	T230
Test name
Test status
Simulation time	1508901118 ps
CPU time	47.2 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	219364 kb
Host	smart-3ca16b10-dc89-4536-a2aa-4960b3312402
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626561973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2626561973
Directory	/workspace/22.keymgr_stress_all/latest

Test location	/workspace/coverage/default/24.keymgr_kmac_rsp_err.1079316403
Short name	T256
Test name
Test status
Simulation time	187194300 ps
CPU time	5.81 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	209692 kb
Host	smart-70c37dab-3df1-4ba3-8ff2-fe28277215d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1079316403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1079316403
Directory	/workspace/24.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.685877849
Short name	T237
Test name
Test status
Simulation time	693484930 ps
CPU time	10.01 seconds
Started	May 25 02:15:15 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	222312 kb
Host	smart-b5ebb8da-8131-4d2a-9062-551dbc3a3166
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685877849 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.685877849
Directory	/workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.keymgr_cfg_regwen.2872772482
Short name	T347
Test name
Test status
Simulation time	229552585 ps
CPU time	4.34 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	215336 kb
Host	smart-e5ba6b94-c695-4c0f-9892-c1638f1712cc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2872772482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2872772482
Directory	/workspace/28.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/28.keymgr_hwsw_invalid_input.3217101062
Short name	T93
Test name
Test status
Simulation time	396235823 ps
CPU time	4.68 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:15:28 PM PDT 24
Peak memory	219336 kb
Host	smart-47787e56-54be-45c8-8bfd-b7bc62c19bf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217101062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3217101062
Directory	/workspace/28.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_lc_disable.130972636
Short name	T239
Test name
Test status
Simulation time	51001327 ps
CPU time	2.63 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	209864 kb
Host	smart-8edb6695-4847-4ac1-b33b-6c3049a9c497
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130972636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.130972636
Directory	/workspace/30.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/44.keymgr_stress_all.2219707946
Short name	T244
Test name
Test status
Simulation time	350282802 ps
CPU time	4.79 seconds
Started	May 25 02:16:15 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	220188 kb
Host	smart-6471e8a0-7e70-4bb7-b505-6cc8e1f71948
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219707946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2219707946
Directory	/workspace/44.keymgr_stress_all/latest

Test location	/workspace/coverage/default/3.keymgr_custom_cm.1270336453
Short name	T157
Test name
Test status
Simulation time	201395784 ps
CPU time	6.24 seconds
Started	May 25 02:14:03 PM PDT 24
Finished	May 25 02:14:10 PM PDT 24
Peak memory	222188 kb
Host	smart-99a23dd2-e5aa-4559-98f5-104ebb18dcd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270336453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1270336453
Directory	/workspace/3.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/4.keymgr_custom_cm.1793162895
Short name	T52
Test name
Test status
Simulation time	175134218 ps
CPU time	4.05 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:07 PM PDT 24
Peak memory	217964 kb
Host	smart-b4f93d59-09ad-4c40-8c4c-5bc82dbd483b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793162895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1793162895
Directory	/workspace/4.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/7.keymgr_custom_cm.320082005
Short name	T166
Test name
Test status
Simulation time	253300818 ps
CPU time	2.94 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:14:11 PM PDT 24
Peak memory	222364 kb
Host	smart-9d173be3-95b9-4fc0-a8c7-4f561103d175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320082005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.320082005
Directory	/workspace/7.keymgr_custom_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.811103444
Short name	T442
Test name
Test status
Simulation time	1432707236 ps
CPU time	9.13 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:21 PM PDT 24
Peak memory	205712 kb
Host	smart-7188a4dd-b61a-404a-a75a-feba70318a62
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811103444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.811103444
Directory	/workspace/0.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.145184189
Short name	T529
Test name
Test status
Simulation time	1798403312 ps
CPU time	11.84 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:22 PM PDT 24
Peak memory	205484 kb
Host	smart-1f0a9f55-762e-4bda-8d84-78d91f920015
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145184189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.145184189
Directory	/workspace/0.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2905093332
Short name	T555
Test name
Test status
Simulation time	24707632 ps
CPU time	0.96 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	205352 kb
Host	smart-4fe09494-ce75-4a12-b074-8fbc022ceba8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905093332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2 905093332
Directory	/workspace/0.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1410522412
Short name	T506
Test name
Test status
Simulation time	97681846 ps
CPU time	1.49 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	221584 kb
Host	smart-4003cf28-ae6a-4b48-b5f5-4232b25c6350
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410522412 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1410522412
Directory	/workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1998983998
Short name	T462
Test name
Test status
Simulation time	20048834 ps
CPU time	1 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	205360 kb
Host	smart-29e84b69-2372-4554-89d8-e4587db6092f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998983998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1998983998
Directory	/workspace/0.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_intr_test.411217175
Short name	T514
Test name
Test status
Simulation time	93608980 ps
CPU time	0.87 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:11 PM PDT 24
Peak memory	205360 kb
Host	smart-37ea5b20-3df6-4c69-b219-4a3837e2c610
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411217175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.411217175
Directory	/workspace/0.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2840790567
Short name	T133
Test name
Test status
Simulation time	140760448 ps
CPU time	3.89 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:17 PM PDT 24
Peak memory	218692 kb
Host	smart-71108b0a-bd35-4a6c-9071-0cd342b5742c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840790567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado w_reg_errors.2840790567
Directory	/workspace/0.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3209278236
Short name	T545
Test name
Test status
Simulation time	647165780 ps
CPU time	16.58 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:27 PM PDT 24
Peak memory	221540 kb
Host	smart-5b1176e4-87bc-4dd1-a070-b6e53cb88df8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209278236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. keymgr_shadow_reg_errors_with_csr_rw.3209278236
Directory	/workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1947600201
Short name	T145
Test name
Test status
Simulation time	221078547 ps
CPU time	2.62 seconds
Started	May 25 02:06:10 PM PDT 24
Finished	May 25 02:06:14 PM PDT 24
Peak memory	213856 kb
Host	smart-12bd0202-34a4-4e66-b062-fe866df758a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947600201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1947600201
Directory	/workspace/0.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.181510824
Short name	T134
Test name
Test status
Simulation time	3471910767 ps
CPU time	55.66 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:07:06 PM PDT 24
Peak memory	214768 kb
Host	smart-6b9090ea-e334-41ad-a6b8-3840f3dc3787
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181510824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err. 181510824
Directory	/workspace/0.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3048033965
Short name	T515
Test name
Test status
Simulation time	375971865 ps
CPU time	10.32 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205664 kb
Host	smart-54e86dc4-8f2b-48fe-be61-4379ef89d214
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048033965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3 048033965
Directory	/workspace/1.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1238190593
Short name	T544
Test name
Test status
Simulation time	1089459664 ps
CPU time	14.36 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	205656 kb
Host	smart-be6066f9-5013-4745-8457-6d43bac4489e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238190593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1 238190593
Directory	/workspace/1.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.976186736
Short name	T185
Test name
Test status
Simulation time	33003974 ps
CPU time	1.43 seconds
Started	May 25 02:06:10 PM PDT 24
Finished	May 25 02:06:12 PM PDT 24
Peak memory	205500 kb
Host	smart-26142530-a206-4395-8c94-44f6f8827260
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976186736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.976186736
Directory	/workspace/1.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4072320463
Short name	T439
Test name
Test status
Simulation time	19915622 ps
CPU time	0.97 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	205472 kb
Host	smart-30568c21-a942-4673-a3c6-5e1c56987be8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072320463 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.4072320463
Directory	/workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_intr_test.1544059190
Short name	T510
Test name
Test status
Simulation time	11747164 ps
CPU time	0.89 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205372 kb
Host	smart-1feeae72-7d8b-426a-8b6f-a1a0ee71069a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544059190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1544059190
Directory	/workspace/1.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1053356556
Short name	T190
Test name
Test status
Simulation time	62011220 ps
CPU time	1.69 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205568 kb
Host	smart-9125a9bd-f257-4830-9aa3-3b3f708da391
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053356556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa me_csr_outstanding.1053356556
Directory	/workspace/1.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3024536359
Short name	T517
Test name
Test status
Simulation time	832888599 ps
CPU time	6.93 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:20 PM PDT 24
Peak memory	214052 kb
Host	smart-6f9f2d0c-81b7-4ecb-928b-c42aa45765a4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024536359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado w_reg_errors.3024536359
Directory	/workspace/1.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3709991728
Short name	T484
Test name
Test status
Simulation time	984175210 ps
CPU time	4.07 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	214124 kb
Host	smart-225b00ac-df9e-42e4-abca-7d1785fdfebb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709991728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. keymgr_shadow_reg_errors_with_csr_rw.3709991728
Directory	/workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1255103525
Short name	T466
Test name
Test status
Simulation time	32260618 ps
CPU time	2.24 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:19 PM PDT 24
Peak memory	213776 kb
Host	smart-31e2f475-57c4-4b76-a303-32ee4291540c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255103525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1255103525
Directory	/workspace/1.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1545078765
Short name	T447
Test name
Test status
Simulation time	145902339 ps
CPU time	0.94 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205496 kb
Host	smart-ffb3a1a3-918c-4fc6-b622-fdff549a5fb0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545078765 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1545078765
Directory	/workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_intr_test.2475525566
Short name	T485
Test name
Test status
Simulation time	13988827 ps
CPU time	0.75 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:24 PM PDT 24
Peak memory	205332 kb
Host	smart-7614af66-d223-4119-88de-c047c3edf192
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475525566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2475525566
Directory	/workspace/10.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.284545997
Short name	T452
Test name
Test status
Simulation time	143046475 ps
CPU time	2.35 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	205660 kb
Host	smart-926d28e3-cc74-459e-ae09-5ba77c91e1e4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284545997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa me_csr_outstanding.284545997
Directory	/workspace/10.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3746419279
Short name	T556
Test name
Test status
Simulation time	291441625 ps
CPU time	6.11 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	214008 kb
Host	smart-4de5deeb-90c8-424e-9b38-6e7567b8e18c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746419279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .keymgr_shadow_reg_errors_with_csr_rw.3746419279
Directory	/workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3786648958
Short name	T495
Test name
Test status
Simulation time	687442211 ps
CPU time	5.51 seconds
Started	May 25 02:06:24 PM PDT 24
Finished	May 25 02:06:30 PM PDT 24
Peak memory	217096 kb
Host	smart-949049a4-092d-42c8-a11c-de33e03acfa5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786648958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3786648958
Directory	/workspace/10.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2807774194
Short name	T135
Test name
Test status
Simulation time	27707093 ps
CPU time	1.75 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	213816 kb
Host	smart-3fa3de7d-53da-4e71-beaf-9ab97c7d5cb5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807774194 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2807774194
Directory	/workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1205819315
Short name	T131
Test name
Test status
Simulation time	50063178 ps
CPU time	0.86 seconds
Started	May 25 02:06:24 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205412 kb
Host	smart-f2721f4f-aa5a-4f34-a3ae-57a7cbe3d50f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205819315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1205819315
Directory	/workspace/11.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_intr_test.1127399844
Short name	T196
Test name
Test status
Simulation time	259397518 ps
CPU time	0.79 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:24 PM PDT 24
Peak memory	205368 kb
Host	smart-8307c445-ae50-4cc8-b42b-73af0cd9342f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127399844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1127399844
Directory	/workspace/11.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.822183548
Short name	T187
Test name
Test status
Simulation time	886149841 ps
CPU time	4.68 seconds
Started	May 25 02:06:24 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	213940 kb
Host	smart-113e0717-dcab-4b1b-b90d-1a474b78806d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822183548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado w_reg_errors.822183548
Directory	/workspace/11.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1720014985
Short name	T560
Test name
Test status
Simulation time	694411894 ps
CPU time	7.66 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	214032 kb
Host	smart-e6e118c8-8e02-4213-90f7-6baeb98b1862
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720014985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .keymgr_shadow_reg_errors_with_csr_rw.1720014985
Directory	/workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2346516775
Short name	T547
Test name
Test status
Simulation time	50238274 ps
CPU time	1.07 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205608 kb
Host	smart-34916f46-3ba2-4e27-b65c-1276db315c46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346516775 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2346516775
Directory	/workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1051562212
Short name	T539
Test name
Test status
Simulation time	19528638 ps
CPU time	1 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205396 kb
Host	smart-b502bf95-e864-4181-ab01-fdf05fa3d79a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051562212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1051562212
Directory	/workspace/12.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_intr_test.2401733636
Short name	T548
Test name
Test status
Simulation time	11070055 ps
CPU time	0.75 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:23 PM PDT 24
Peak memory	205324 kb
Host	smart-d427615a-94e8-4000-88ae-bd67a96f1085
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401733636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2401733636
Directory	/workspace/12.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2980517702
Short name	T481
Test name
Test status
Simulation time	219750228 ps
CPU time	2.63 seconds
Started	May 25 02:06:28 PM PDT 24
Finished	May 25 02:06:32 PM PDT 24
Peak memory	218552 kb
Host	smart-a39fb589-2b50-428a-899e-e6d4532ddd56
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980517702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad ow_reg_errors.2980517702
Directory	/workspace/12.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4099484633
Short name	T454
Test name
Test status
Simulation time	826351769 ps
CPU time	4.17 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:27 PM PDT 24
Peak memory	213908 kb
Host	smart-f704bc62-2a76-4066-9bff-dda7db28ba58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099484633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4099484633
Directory	/workspace/12.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1166627331
Short name	T178
Test name
Test status
Simulation time	59648323 ps
CPU time	3.33 seconds
Started	May 25 02:06:19 PM PDT 24
Finished	May 25 02:06:23 PM PDT 24
Peak memory	209276 kb
Host	smart-e57f91b8-f5f3-474a-905c-faa663fdd34b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166627331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er r.1166627331
Directory	/workspace/12.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.860748385
Short name	T450
Test name
Test status
Simulation time	20268296 ps
CPU time	0.99 seconds
Started	May 25 02:06:19 PM PDT 24
Finished	May 25 02:06:20 PM PDT 24
Peak memory	205460 kb
Host	smart-68fd642c-532c-4465-9709-862a1f0f7c26
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860748385 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.860748385
Directory	/workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1515878249
Short name	T540
Test name
Test status
Simulation time	32415366 ps
CPU time	0.9 seconds
Started	May 25 02:06:34 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	205200 kb
Host	smart-40589295-5da0-4c0e-9256-fbc7f74cee3f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515878249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1515878249
Directory	/workspace/13.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_intr_test.1782423364
Short name	T469
Test name
Test status
Simulation time	15302676 ps
CPU time	0.73 seconds
Started	May 25 02:06:35 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	205216 kb
Host	smart-b1652bfe-b81c-4abc-99a1-39b56e011063
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782423364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1782423364
Directory	/workspace/13.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3246129958
Short name	T532
Test name
Test status
Simulation time	32194749 ps
CPU time	2.06 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	205424 kb
Host	smart-51d5d034-0f32-4dd5-9e58-e07960df617c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246129958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s ame_csr_outstanding.3246129958
Directory	/workspace/13.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1484973778
Short name	T505
Test name
Test status
Simulation time	329400020 ps
CPU time	3.54 seconds
Started	May 25 02:06:17 PM PDT 24
Finished	May 25 02:06:21 PM PDT 24
Peak memory	213964 kb
Host	smart-dde31f35-b891-4a37-a494-1c3f2aebd70b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484973778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad ow_reg_errors.1484973778
Directory	/workspace/13.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2667212160
Short name	T147
Test name
Test status
Simulation time	550808289 ps
CPU time	4.98 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	216796 kb
Host	smart-72ed2b76-458e-41c8-8a66-ab0f82d2e1ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667212160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2667212160
Directory	/workspace/13.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2355504251
Short name	T179
Test name
Test status
Simulation time	88567426 ps
CPU time	3.43 seconds
Started	May 25 02:06:35 PM PDT 24
Finished	May 25 02:06:39 PM PDT 24
Peak memory	208568 kb
Host	smart-06f12673-0b47-43e3-bf05-7a8abea01538
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355504251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er r.2355504251
Directory	/workspace/13.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1645263099
Short name	T500
Test name
Test status
Simulation time	22371099 ps
CPU time	1.11 seconds
Started	May 25 02:06:31 PM PDT 24
Finished	May 25 02:06:33 PM PDT 24
Peak memory	205440 kb
Host	smart-2c6c6446-6f0a-4ed7-b996-2d8a1b7900d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645263099 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1645263099
Directory	/workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_csr_rw.768718558
Short name	T508
Test name
Test status
Simulation time	43326157 ps
CPU time	1.01 seconds
Started	May 25 02:06:30 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	205348 kb
Host	smart-649d2887-954d-4ddb-bea6-6df022c7c4cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768718558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.768718558
Directory	/workspace/14.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_intr_test.2387897558
Short name	T509
Test name
Test status
Simulation time	34581184 ps
CPU time	0.72 seconds
Started	May 25 02:06:29 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	205292 kb
Host	smart-cc1accfc-0ba6-4974-b21d-dd0a0b9d77bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387897558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2387897558
Directory	/workspace/14.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.522923769
Short name	T186
Test name
Test status
Simulation time	61781902 ps
CPU time	1.82 seconds
Started	May 25 02:06:29 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	205508 kb
Host	smart-bf7f0ca6-29b1-47bc-9d22-a13d907625eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522923769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa me_csr_outstanding.522923769
Directory	/workspace/14.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3695459017
Short name	T189
Test name
Test status
Simulation time	742337930 ps
CPU time	3.82 seconds
Started	May 25 02:06:21 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	214136 kb
Host	smart-ba763304-95a9-40dd-b867-43a5a5781f77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695459017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad ow_reg_errors.3695459017
Directory	/workspace/14.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.173613101
Short name	T525
Test name
Test status
Simulation time	174544374 ps
CPU time	7.13 seconds
Started	May 25 02:06:21 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	214140 kb
Host	smart-18dd61f8-eaa2-4a0b-9b57-0449a550398b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173613101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. keymgr_shadow_reg_errors_with_csr_rw.173613101
Directory	/workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3136666722
Short name	T498
Test name
Test status
Simulation time	812956348 ps
CPU time	5.58 seconds
Started	May 25 02:06:29 PM PDT 24
Finished	May 25 02:06:35 PM PDT 24
Peak memory	217176 kb
Host	smart-84c1c8c4-5b94-4040-b367-a1a1beb1d619
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136666722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3136666722
Directory	/workspace/14.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.795235521
Short name	T518
Test name
Test status
Simulation time	30382336 ps
CPU time	1.31 seconds
Started	May 25 02:06:32 PM PDT 24
Finished	May 25 02:06:34 PM PDT 24
Peak memory	221944 kb
Host	smart-ae0d6d33-0488-43ad-a077-c1f9a51b3f67
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795235521 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.795235521
Directory	/workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3022726816
Short name	T479
Test name
Test status
Simulation time	66802379 ps
CPU time	0.95 seconds
Started	May 25 02:06:28 PM PDT 24
Finished	May 25 02:06:30 PM PDT 24
Peak memory	205384 kb
Host	smart-c9b85178-ee12-4c32-87e2-e1a2021f9a1b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022726816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3022726816
Directory	/workspace/15.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_intr_test.138140502
Short name	T473
Test name
Test status
Simulation time	25922830 ps
CPU time	0.77 seconds
Started	May 25 02:06:30 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	205260 kb
Host	smart-e7d5a22a-0341-4b40-a7a9-6a78288830e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138140502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.138140502
Directory	/workspace/15.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.306935143
Short name	T476
Test name
Test status
Simulation time	49650913 ps
CPU time	1.91 seconds
Started	May 25 02:06:33 PM PDT 24
Finished	May 25 02:06:35 PM PDT 24
Peak memory	205560 kb
Host	smart-c2622938-9b60-42f1-bac1-4c3222599096
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306935143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa me_csr_outstanding.306935143
Directory	/workspace/15.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1603020807
Short name	T513
Test name
Test status
Simulation time	206613761 ps
CPU time	5.4 seconds
Started	May 25 02:06:29 PM PDT 24
Finished	May 25 02:06:35 PM PDT 24
Peak memory	214116 kb
Host	smart-8e257077-b173-4674-8d1f-ebe9509dd983
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603020807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad ow_reg_errors.1603020807
Directory	/workspace/15.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3180772683
Short name	T122
Test name
Test status
Simulation time	1603333852 ps
CPU time	8.45 seconds
Started	May 25 02:06:31 PM PDT 24
Finished	May 25 02:06:40 PM PDT 24
Peak memory	214032 kb
Host	smart-e9fa5093-3901-4b30-9c09-884c943cccf5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180772683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .keymgr_shadow_reg_errors_with_csr_rw.3180772683
Directory	/workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2986826594
Short name	T193
Test name
Test status
Simulation time	186826365 ps
CPU time	5.56 seconds
Started	May 25 02:06:28 PM PDT 24
Finished	May 25 02:06:35 PM PDT 24
Peak memory	213836 kb
Host	smart-c3851f52-d436-4b47-96f7-9b89bedd5e0c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986826594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2986826594
Directory	/workspace/15.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3419657333
Short name	T526
Test name
Test status
Simulation time	28572678 ps
CPU time	1.54 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:46 PM PDT 24
Peak memory	213804 kb
Host	smart-80956f23-1f6c-4afb-96c6-0bf9308462ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419657333 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3419657333
Directory	/workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_intr_test.3602608863
Short name	T451
Test name
Test status
Simulation time	21241401 ps
CPU time	0.85 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:44 PM PDT 24
Peak memory	205364 kb
Host	smart-98906c43-7b19-47f7-942c-0aa0b8503631
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602608863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3602608863
Directory	/workspace/16.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.601706618
Short name	T151
Test name
Test status
Simulation time	1485783593 ps
CPU time	4.08 seconds
Started	May 25 02:06:41 PM PDT 24
Finished	May 25 02:06:46 PM PDT 24
Peak memory	205588 kb
Host	smart-961811a0-ecea-45bf-80d1-c6ae0765ce38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601706618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa me_csr_outstanding.601706618
Directory	/workspace/16.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1558448476
Short name	T516
Test name
Test status
Simulation time	110146277 ps
CPU time	2.74 seconds
Started	May 25 02:06:31 PM PDT 24
Finished	May 25 02:06:34 PM PDT 24
Peak memory	213996 kb
Host	smart-dd93bc97-319c-4637-b9b9-84cca2eaae9d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558448476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad ow_reg_errors.1558448476
Directory	/workspace/16.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3924790273
Short name	T558
Test name
Test status
Simulation time	286133467 ps
CPU time	10.34 seconds
Started	May 25 02:06:41 PM PDT 24
Finished	May 25 02:06:52 PM PDT 24
Peak memory	213972 kb
Host	smart-14a3bdaa-b742-483f-8606-08241b852e6d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924790273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .keymgr_shadow_reg_errors_with_csr_rw.3924790273
Directory	/workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2967515325
Short name	T537
Test name
Test status
Simulation time	28735095 ps
CPU time	1.84 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	213916 kb
Host	smart-092f134d-32d3-47d6-b0b0-698313f7693d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967515325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2967515325
Directory	/workspace/16.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4117752151
Short name	T140
Test name
Test status
Simulation time	218973819 ps
CPU time	5.86 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	213780 kb
Host	smart-ede0cfb2-f439-413d-a445-216da4c3b614
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117752151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er r.4117752151
Directory	/workspace/16.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1472898127
Short name	T464
Test name
Test status
Simulation time	42165563 ps
CPU time	0.96 seconds
Started	May 25 02:06:42 PM PDT 24
Finished	May 25 02:06:44 PM PDT 24
Peak memory	205456 kb
Host	smart-9c9fbd0d-7937-4364-8388-ddec3dafec14
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472898127 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1472898127
Directory	/workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_csr_rw.944314537
Short name	T507
Test name
Test status
Simulation time	127421284 ps
CPU time	0.92 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:45 PM PDT 24
Peak memory	205332 kb
Host	smart-b29fc0ec-d039-4882-93a9-1324b67c620e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944314537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.944314537
Directory	/workspace/17.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_intr_test.1223903092
Short name	T477
Test name
Test status
Simulation time	33546181 ps
CPU time	0.88 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	205260 kb
Host	smart-650af2ca-c5f3-4fdd-a59f-44583f625111
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223903092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1223903092
Directory	/workspace/17.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1704584765
Short name	T549
Test name
Test status
Simulation time	39150555 ps
CPU time	2.54 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	205452 kb
Host	smart-9de2f8d7-e6b7-43a7-affb-ccd2578b3947
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704584765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s ame_csr_outstanding.1704584765
Directory	/workspace/17.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1238065802
Short name	T522
Test name
Test status
Simulation time	303617723 ps
CPU time	5.92 seconds
Started	May 25 02:06:42 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	213960 kb
Host	smart-94ad9e5b-e04b-4390-bd29-d1e4d1b60ea8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238065802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad ow_reg_errors.1238065802
Directory	/workspace/17.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1100526464
Short name	T132
Test name
Test status
Simulation time	3904735639 ps
CPU time	7.99 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:52 PM PDT 24
Peak memory	214060 kb
Host	smart-592a6fa5-87ad-4f2b-bb13-b51c5fee17e6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100526464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .keymgr_shadow_reg_errors_with_csr_rw.1100526464
Directory	/workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_tl_errors.431684039
Short name	T492
Test name
Test status
Simulation time	151432459 ps
CPU time	3.46 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	215212 kb
Host	smart-e98356dd-6196-4806-a92c-2afbdaab3c8f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431684039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.431684039
Directory	/workspace/17.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1734262771
Short name	T552
Test name
Test status
Simulation time	213749783 ps
CPU time	5.06 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:50 PM PDT 24
Peak memory	208980 kb
Host	smart-f6145fe3-7f78-47e5-b390-d910da1b2084
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734262771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er r.1734262771
Directory	/workspace/17.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.938344503
Short name	T146
Test name
Test status
Simulation time	26745305 ps
CPU time	1.22 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:45 PM PDT 24
Peak memory	213812 kb
Host	smart-a83db2d3-7e3e-4efe-bc3c-abbd3576f1d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938344503 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.938344503
Directory	/workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_csr_rw.795360425
Short name	T494
Test name
Test status
Simulation time	16182505 ps
CPU time	0.92 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:46 PM PDT 24
Peak memory	205316 kb
Host	smart-c1b27224-64bf-4d5c-8934-b683be918cbd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795360425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.795360425
Directory	/workspace/18.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_intr_test.3344666690
Short name	T435
Test name
Test status
Simulation time	18589958 ps
CPU time	0.67 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:45 PM PDT 24
Peak memory	205336 kb
Host	smart-f5b97dcf-9b29-4357-94df-91cc0bf41bad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344666690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3344666690
Directory	/workspace/18.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3034336124
Short name	T559
Test name
Test status
Simulation time	53402801 ps
CPU time	2.13 seconds
Started	May 25 02:06:42 PM PDT 24
Finished	May 25 02:06:44 PM PDT 24
Peak memory	205468 kb
Host	smart-4bd9abe4-1d21-4085-a9ab-96c879ca4a31
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034336124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s ame_csr_outstanding.3034336124
Directory	/workspace/18.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3631333735
Short name	T475
Test name
Test status
Simulation time	128827246 ps
CPU time	4.45 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:50 PM PDT 24
Peak memory	214068 kb
Host	smart-2abafece-5330-4097-9fef-c2924ef7e415
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631333735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad ow_reg_errors.3631333735
Directory	/workspace/18.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.691824503
Short name	T524
Test name
Test status
Simulation time	180400140 ps
CPU time	5.31 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:52 PM PDT 24
Peak memory	219900 kb
Host	smart-f9dcc761-1e78-4638-86c9-35d1689a5a25
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691824503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. keymgr_shadow_reg_errors_with_csr_rw.691824503
Directory	/workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1591855437
Short name	T137
Test name
Test status
Simulation time	162836232 ps
CPU time	1.64 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	214868 kb
Host	smart-9c7ff67c-a907-4306-825e-67d9abfdc79e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591855437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1591855437
Directory	/workspace/18.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3248359290
Short name	T465
Test name
Test status
Simulation time	49665935 ps
CPU time	1.08 seconds
Started	May 25 02:06:44 PM PDT 24
Finished	May 25 02:06:46 PM PDT 24
Peak memory	205548 kb
Host	smart-02bbfe80-8f02-40ec-bd97-fa06ec658864
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248359290 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3248359290
Directory	/workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3913479304
Short name	T155
Test name
Test status
Simulation time	34413848 ps
CPU time	1.2 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	205480 kb
Host	smart-1b8fd551-020d-4bd3-a3a4-ec7c80ffed3e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913479304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3913479304
Directory	/workspace/19.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_intr_test.3625846043
Short name	T512
Test name
Test status
Simulation time	36752352 ps
CPU time	0.71 seconds
Started	May 25 02:06:48 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	205348 kb
Host	smart-c39690ba-a389-4a4b-9af4-c5df2c445177
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625846043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3625846043
Directory	/workspace/19.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2806722661
Short name	T455
Test name
Test status
Simulation time	215809976 ps
CPU time	1.48 seconds
Started	May 25 02:06:47 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	205492 kb
Host	smart-4aa1213e-2285-436c-beab-97f89125294a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806722661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s ame_csr_outstanding.2806722661
Directory	/workspace/19.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3331597060
Short name	T504
Test name
Test status
Simulation time	324435240 ps
CPU time	3.23 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:50 PM PDT 24
Peak memory	214108 kb
Host	smart-410a0e1c-880d-4538-8cfa-40dcdf928767
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331597060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad ow_reg_errors.3331597060
Directory	/workspace/19.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2780473676
Short name	T129
Test name
Test status
Simulation time	432303484 ps
CPU time	7.8 seconds
Started	May 25 02:06:43 PM PDT 24
Finished	May 25 02:06:52 PM PDT 24
Peak memory	213908 kb
Host	smart-7476c6ea-c37e-4d0d-aae4-04432fbfbb6c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780473676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .keymgr_shadow_reg_errors_with_csr_rw.2780473676
Directory	/workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2872360787
Short name	T486
Test name
Test status
Simulation time	231957265 ps
CPU time	3.98 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	216244 kb
Host	smart-5538d60e-0457-41c4-af94-d20fbcc0f9c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872360787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2872360787
Directory	/workspace/19.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1300702122
Short name	T530
Test name
Test status
Simulation time	493242741 ps
CPU time	8.77 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:19 PM PDT 24
Peak memory	205556 kb
Host	smart-63808a89-2094-40e8-9d84-877d598ec54a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300702122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1 300702122
Directory	/workspace/2.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.361964080
Short name	T438
Test name
Test status
Simulation time	257645778 ps
CPU time	6.38 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:19 PM PDT 24
Peak memory	205532 kb
Host	smart-1a834b01-d3f8-4445-91c9-63728a1003a4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361964080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.361964080
Directory	/workspace/2.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1969874075
Short name	T493
Test name
Test status
Simulation time	20209558 ps
CPU time	1.15 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:14 PM PDT 24
Peak memory	205456 kb
Host	smart-ec2dea5b-b5b3-4460-8f0d-911e9f1cd318
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969874075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1 969874075
Directory	/workspace/2.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.851184069
Short name	T192
Test name
Test status
Simulation time	73322739 ps
CPU time	1 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:13 PM PDT 24
Peak memory	205464 kb
Host	smart-6bab3446-f5e3-4d3a-a873-c62f4e686d71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851184069 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.851184069
Directory	/workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_intr_test.1612930140
Short name	T561
Test name
Test status
Simulation time	16073858 ps
CPU time	0.66 seconds
Started	May 25 02:06:14 PM PDT 24
Finished	May 25 02:06:16 PM PDT 24
Peak memory	205268 kb
Host	smart-35f494e2-dbf6-44d2-af15-1ce6f89709df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612930140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1612930140
Directory	/workspace/2.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.665353832
Short name	T482
Test name
Test status
Simulation time	81453649 ps
CPU time	2.5 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:17 PM PDT 24
Peak memory	214000 kb
Host	smart-46ebf0ed-f0fe-4aa9-9576-a5a587085371
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665353832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow _reg_errors.665353832
Directory	/workspace/2.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2352241071
Short name	T470
Test name
Test status
Simulation time	315855627 ps
CPU time	1.57 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	213848 kb
Host	smart-4c465331-126b-43d4-a0d0-abfb8803151b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352241071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2352241071
Directory	/workspace/2.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.keymgr_intr_test.1784920091
Short name	T489
Test name
Test status
Simulation time	12014406 ps
CPU time	0.81 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	205324 kb
Host	smart-03ef4060-05ad-4263-9339-74ef967bba41
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784920091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1784920091
Directory	/workspace/20.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.keymgr_intr_test.2751032019
Short name	T443
Test name
Test status
Simulation time	16540808 ps
CPU time	0.73 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	205428 kb
Host	smart-887ac9b0-fdda-4fbc-a8b6-cb574e0576ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751032019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2751032019
Directory	/workspace/21.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.keymgr_intr_test.3537157590
Short name	T523
Test name
Test status
Simulation time	57730045 ps
CPU time	0.76 seconds
Started	May 25 02:06:45 PM PDT 24
Finished	May 25 02:06:46 PM PDT 24
Peak memory	205336 kb
Host	smart-6a82ae9e-d224-421a-b204-69dcb19cb9ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537157590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3537157590
Directory	/workspace/22.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.keymgr_intr_test.1366176134
Short name	T490
Test name
Test status
Simulation time	191342178 ps
CPU time	0.71 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205280 kb
Host	smart-64cea346-b31a-469f-a80b-5563eafe6cdf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366176134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1366176134
Directory	/workspace/23.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.keymgr_intr_test.2036098628
Short name	T436
Test name
Test status
Simulation time	10745346 ps
CPU time	0.84 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205340 kb
Host	smart-eec5dd94-b628-422f-a963-6a2fac5738f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036098628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2036098628
Directory	/workspace/24.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.keymgr_intr_test.317776674
Short name	T468
Test name
Test status
Simulation time	11487225 ps
CPU time	0.83 seconds
Started	May 25 02:06:47 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205264 kb
Host	smart-4b903894-bd85-409e-b497-e28cf54cb058
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317776674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.317776674
Directory	/workspace/25.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.keymgr_intr_test.3162747208
Short name	T445
Test name
Test status
Simulation time	14587670 ps
CPU time	0.75 seconds
Started	May 25 02:06:47 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205308 kb
Host	smart-0852f6d4-b7ce-4909-89d9-c2e86eb6c682
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162747208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3162747208
Directory	/workspace/26.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.keymgr_intr_test.2574280736
Short name	T496
Test name
Test status
Simulation time	31869406 ps
CPU time	0.73 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:47 PM PDT 24
Peak memory	205304 kb
Host	smart-c0a55f7a-5c5c-4b90-9df6-5bbbce758669
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574280736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2574280736
Directory	/workspace/27.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.keymgr_intr_test.1124551242
Short name	T487
Test name
Test status
Simulation time	59454112 ps
CPU time	0.72 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205324 kb
Host	smart-d525fa6e-44d6-4ba8-bbfd-1d499d6dc6e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124551242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1124551242
Directory	/workspace/28.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.keymgr_intr_test.3360208560
Short name	T474
Test name
Test status
Simulation time	20999524 ps
CPU time	0.84 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205324 kb
Host	smart-e3efde9b-69bb-434b-8646-4006119ae7b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360208560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3360208560
Directory	/workspace/29.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2016271753
Short name	T153
Test name
Test status
Simulation time	144916417 ps
CPU time	6.51 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205580 kb
Host	smart-b3226133-9409-47fc-a8f6-3e91a67d94f8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016271753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2 016271753
Directory	/workspace/3.keymgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3933530486
Short name	T448
Test name
Test status
Simulation time	1039659624 ps
CPU time	14.44 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:24 PM PDT 24
Peak memory	205524 kb
Host	smart-82b4af16-a898-4450-a9dc-eba8815828ba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933530486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3 933530486
Directory	/workspace/3.keymgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2300979902
Short name	T501
Test name
Test status
Simulation time	117761611 ps
CPU time	1.23 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:14 PM PDT 24
Peak memory	205548 kb
Host	smart-59ef1ab8-e134-46b4-807b-9d041e416f7b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300979902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2 300979902
Directory	/workspace/3.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2456944716
Short name	T461
Test name
Test status
Simulation time	50562019 ps
CPU time	1.22 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:13 PM PDT 24
Peak memory	213840 kb
Host	smart-7b295830-2bd1-4bd4-b286-05d174d73759
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456944716 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2456944716
Directory	/workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1583850317
Short name	T457
Test name
Test status
Simulation time	47591234 ps
CPU time	0.89 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:13 PM PDT 24
Peak memory	205408 kb
Host	smart-fd764271-590e-4de6-ae3d-338e5f5ff9b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583850317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1583850317
Directory	/workspace/3.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_intr_test.3773178497
Short name	T152
Test name
Test status
Simulation time	43608011 ps
CPU time	0.72 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:12 PM PDT 24
Peak memory	205356 kb
Host	smart-13e7ddac-0448-4c55-9afc-734d2a81cfde
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773178497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3773178497
Directory	/workspace/3.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2579855504
Short name	T456
Test name
Test status
Simulation time	40260974 ps
CPU time	1.74 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:19 PM PDT 24
Peak memory	205264 kb
Host	smart-0703d9f3-a556-4225-ae54-a472c0c8cf46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579855504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa me_csr_outstanding.2579855504
Directory	/workspace/3.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.43465351
Short name	T188
Test name
Test status
Simulation time	329464767 ps
CPU time	5.45 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	214000 kb
Host	smart-df401280-e8c6-46a7-a1cf-a1dd35f71b36
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43465351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_ reg_errors.43465351
Directory	/workspace/3.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1351000854
Short name	T120
Test name
Test status
Simulation time	146709277 ps
CPU time	4.77 seconds
Started	May 25 02:06:08 PM PDT 24
Finished	May 25 02:06:14 PM PDT 24
Peak memory	213896 kb
Host	smart-695c9964-78c5-485f-ac3d-83307648c891
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351000854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. keymgr_shadow_reg_errors_with_csr_rw.1351000854
Directory	/workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4013637482
Short name	T491
Test name
Test status
Simulation time	113968128 ps
CPU time	1.65 seconds
Started	May 25 02:06:34 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	213812 kb
Host	smart-13c34e68-3cc0-4ce1-aa4b-058879c96ddc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013637482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4013637482
Directory	/workspace/3.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.keymgr_intr_test.894069279
Short name	T519
Test name
Test status
Simulation time	26504007 ps
CPU time	0.75 seconds
Started	May 25 02:06:46 PM PDT 24
Finished	May 25 02:06:48 PM PDT 24
Peak memory	205432 kb
Host	smart-5aede6bd-e7f0-4113-81bf-29b01f0fa320
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894069279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.894069279
Directory	/workspace/30.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.keymgr_intr_test.4141786791
Short name	T453
Test name
Test status
Simulation time	9013745 ps
CPU time	0.76 seconds
Started	May 25 02:06:47 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	205288 kb
Host	smart-6632acc4-9758-44a4-b92e-40f8a62495ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141786791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4141786791
Directory	/workspace/31.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.keymgr_intr_test.2650060029
Short name	T542
Test name
Test status
Simulation time	24513106 ps
CPU time	0.75 seconds
Started	May 25 02:06:55 PM PDT 24
Finished	May 25 02:06:57 PM PDT 24
Peak memory	205292 kb
Host	smart-e390664e-bd97-4bba-93e2-4ff0e3452d1b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650060029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2650060029
Directory	/workspace/32.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.keymgr_intr_test.974171920
Short name	T437
Test name
Test status
Simulation time	36553225 ps
CPU time	0.81 seconds
Started	May 25 02:06:47 PM PDT 24
Finished	May 25 02:06:49 PM PDT 24
Peak memory	205232 kb
Host	smart-deab4484-c090-4f9b-ba77-415db4815be5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974171920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.974171920
Directory	/workspace/33.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.keymgr_intr_test.2877375215
Short name	T535
Test name
Test status
Simulation time	10661476 ps
CPU time	0.81 seconds
Started	May 25 02:06:55 PM PDT 24
Finished	May 25 02:06:56 PM PDT 24
Peak memory	205368 kb
Host	smart-30a0a240-70c8-4192-ac9b-2da60bf2d9e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877375215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2877375215
Directory	/workspace/34.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.keymgr_intr_test.2011833037
Short name	T480
Test name
Test status
Simulation time	13496172 ps
CPU time	0.75 seconds
Started	May 25 02:06:49 PM PDT 24
Finished	May 25 02:06:50 PM PDT 24
Peak memory	205364 kb
Host	smart-fd304bf9-8c64-4c3f-b82e-7df5e641c511
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011833037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2011833037
Directory	/workspace/35.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.keymgr_intr_test.1911445177
Short name	T441
Test name
Test status
Simulation time	27620592 ps
CPU time	0.71 seconds
Started	May 25 02:06:55 PM PDT 24
Finished	May 25 02:06:56 PM PDT 24
Peak memory	205368 kb
Host	smart-3efedbdd-46f6-42d7-9908-c278d8c9e643
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911445177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1911445177
Directory	/workspace/36.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.keymgr_intr_test.4065019775
Short name	T471
Test name
Test status
Simulation time	40536762 ps
CPU time	0.79 seconds
Started	May 25 02:06:55 PM PDT 24
Finished	May 25 02:06:57 PM PDT 24
Peak memory	205368 kb
Host	smart-8ead6f75-f3db-4f6c-9f91-0ebab6eb8450
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065019775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4065019775
Directory	/workspace/37.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.keymgr_intr_test.3059016019
Short name	T511
Test name
Test status
Simulation time	12672906 ps
CPU time	0.85 seconds
Started	May 25 02:06:55 PM PDT 24
Finished	May 25 02:06:57 PM PDT 24
Peak memory	205368 kb
Host	smart-152e62a9-0584-4d5d-8a78-4e41b056f0b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059016019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3059016019
Directory	/workspace/38.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.keymgr_intr_test.939312535
Short name	T538
Test name
Test status
Simulation time	18387997 ps
CPU time	0.83 seconds
Started	May 25 02:06:56 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205268 kb
Host	smart-221e2f69-4026-4871-b96b-11606a080a94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939312535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.939312535
Directory	/workspace/39.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.174017849
Short name	T446
Test name
Test status
Simulation time	10507717 ps
CPU time	0.99 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205576 kb
Host	smart-8a2d4e5f-afd4-442d-bd71-9314520972f8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174017849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.174017849
Directory	/workspace/4.keymgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.546822771
Short name	T139
Test name
Test status
Simulation time	73935068 ps
CPU time	1.04 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	205112 kb
Host	smart-03e9c432-b23f-419c-af2f-4ebc258798dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546822771 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.546822771
Directory	/workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3851033384
Short name	T156
Test name
Test status
Simulation time	20978679 ps
CPU time	1.22 seconds
Started	May 25 02:06:13 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	205584 kb
Host	smart-197b0cde-98f3-43fa-9dfd-5d5b5d4738e4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851033384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3851033384
Directory	/workspace/4.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_intr_test.1435805067
Short name	T449
Test name
Test status
Simulation time	49630056 ps
CPU time	0.87 seconds
Started	May 25 02:06:11 PM PDT 24
Finished	May 25 02:06:12 PM PDT 24
Peak memory	205248 kb
Host	smart-1fc014b8-20fc-4c46-becd-1a50b3798395
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435805067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1435805067
Directory	/workspace/4.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1698260988
Short name	T534
Test name
Test status
Simulation time	959029204 ps
CPU time	4.7 seconds
Started	May 25 02:06:09 PM PDT 24
Finished	May 25 02:06:15 PM PDT 24
Peak memory	213960 kb
Host	smart-b8477ac4-ae5b-4910-95b4-786fd162d57e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698260988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado w_reg_errors.1698260988
Directory	/workspace/4.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.434682740
Short name	T554
Test name
Test status
Simulation time	1031779501 ps
CPU time	9.98 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:23 PM PDT 24
Peak memory	213948 kb
Host	smart-bdea87c4-92d5-45d2-b7e5-eefa2e99fe10
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434682740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST _SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k eymgr_shadow_reg_errors_with_csr_rw.434682740
Directory	/workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3543988221
Short name	T119
Test name
Test status
Simulation time	44149754 ps
CPU time	2.54 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:16 PM PDT 24
Peak memory	213780 kb
Host	smart-678eeb67-9d70-4064-856a-bb68284474f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543988221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3543988221
Directory	/workspace/4.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1552867584
Short name	T175
Test name
Test status
Simulation time	237368970 ps
CPU time	3.6 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:21 PM PDT 24
Peak memory	209112 kb
Host	smart-7d7c2c76-fc3c-4522-9434-b1da883c7903
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552867584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err .1552867584
Directory	/workspace/4.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.keymgr_intr_test.2669572255
Short name	T553
Test name
Test status
Simulation time	68378993 ps
CPU time	0.71 seconds
Started	May 25 02:06:54 PM PDT 24
Finished	May 25 02:06:55 PM PDT 24
Peak memory	205256 kb
Host	smart-57454e34-8b7d-46da-a39d-27f40c130b51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669572255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2669572255
Directory	/workspace/40.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.keymgr_intr_test.2931621318
Short name	T194
Test name
Test status
Simulation time	13312504 ps
CPU time	0.87 seconds
Started	May 25 02:06:56 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205572 kb
Host	smart-32650315-b572-40b6-a352-2e732f32ae6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931621318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2931621318
Directory	/workspace/41.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.keymgr_intr_test.3657812678
Short name	T541
Test name
Test status
Simulation time	7735941 ps
CPU time	0.71 seconds
Started	May 25 02:06:56 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205288 kb
Host	smart-35681823-69de-4200-b51c-30ae39a9d5e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657812678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3657812678
Directory	/workspace/42.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.keymgr_intr_test.607751274
Short name	T459
Test name
Test status
Simulation time	21438526 ps
CPU time	0.93 seconds
Started	May 25 02:06:57 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205392 kb
Host	smart-6cca7fb9-8025-468e-a203-abceeec99ddf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607751274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.607751274
Directory	/workspace/43.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.keymgr_intr_test.2136060645
Short name	T444
Test name
Test status
Simulation time	51232460 ps
CPU time	0.74 seconds
Started	May 25 02:06:58 PM PDT 24
Finished	May 25 02:06:59 PM PDT 24
Peak memory	205280 kb
Host	smart-c088e177-4f5b-4bd4-908f-a5387e2a8a05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136060645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2136060645
Directory	/workspace/44.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.keymgr_intr_test.2960961226
Short name	T440
Test name
Test status
Simulation time	34865126 ps
CPU time	0.82 seconds
Started	May 25 02:06:56 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205256 kb
Host	smart-4379e081-6c5c-4685-98fc-15de791705b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960961226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2960961226
Directory	/workspace/45.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.keymgr_intr_test.3122339405
Short name	T195
Test name
Test status
Simulation time	11754058 ps
CPU time	0.82 seconds
Started	May 25 02:06:57 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205280 kb
Host	smart-5d8a4f95-d1ed-4f76-9326-a36d1f071ba7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122339405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3122339405
Directory	/workspace/46.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.keymgr_intr_test.2420762731
Short name	T434
Test name
Test status
Simulation time	33465003 ps
CPU time	0.72 seconds
Started	May 25 02:06:54 PM PDT 24
Finished	May 25 02:06:55 PM PDT 24
Peak memory	205316 kb
Host	smart-9d592b84-cb65-476e-bd49-dd014e6c5bd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420762731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2420762731
Directory	/workspace/47.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.keymgr_intr_test.1230082834
Short name	T557
Test name
Test status
Simulation time	38060045 ps
CPU time	0.74 seconds
Started	May 25 02:06:58 PM PDT 24
Finished	May 25 02:06:59 PM PDT 24
Peak memory	205300 kb
Host	smart-83419b79-7917-4568-902b-159a5b7a76c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230082834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1230082834
Directory	/workspace/48.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.keymgr_intr_test.3410101142
Short name	T488
Test name
Test status
Simulation time	12480857 ps
CPU time	0.88 seconds
Started	May 25 02:06:56 PM PDT 24
Finished	May 25 02:06:58 PM PDT 24
Peak memory	205288 kb
Host	smart-3926a9a7-0200-4509-8c3c-b6c9ec346c02
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410101142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3410101142
Directory	/workspace/49.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.130857922
Short name	T551
Test name
Test status
Simulation time	89071395 ps
CPU time	1.08 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205528 kb
Host	smart-5ea90f8f-0fde-4a39-b3f1-812d5a8e1481
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130857922 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.130857922
Directory	/workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3518880151
Short name	T503
Test name
Test status
Simulation time	257487065 ps
CPU time	1.12 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205584 kb
Host	smart-d412fb9f-d11b-4235-a18c-1af9d2c12831
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518880151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3518880151
Directory	/workspace/5.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_intr_test.3607985352
Short name	T528
Test name
Test status
Simulation time	29946499 ps
CPU time	0.72 seconds
Started	May 25 02:06:14 PM PDT 24
Finished	May 25 02:06:16 PM PDT 24
Peak memory	205332 kb
Host	smart-93ec7b82-936a-4993-9a83-ffead7040aea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607985352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3607985352
Directory	/workspace/5.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.659664679
Short name	T127
Test name
Test status
Simulation time	1060218402 ps
CPU time	6.98 seconds
Started	May 25 02:06:14 PM PDT 24
Finished	May 25 02:06:22 PM PDT 24
Peak memory	213920 kb
Host	smart-aaa1e020-cd8a-40ad-ae44-f8c576fee5b5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659664679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow _reg_errors.659664679
Directory	/workspace/5.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2987962944
Short name	T472
Test name
Test status
Simulation time	350591445 ps
CPU time	8.32 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	214100 kb
Host	smart-d0e752fc-7406-413b-8fb6-543e9be30490
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987962944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. keymgr_shadow_reg_errors_with_csr_rw.2987962944
Directory	/workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3461938068
Short name	T562
Test name
Test status
Simulation time	108314029 ps
CPU time	1.87 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	215872 kb
Host	smart-01de9ca0-ff34-4acb-803a-735e88807929
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461938068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3461938068
Directory	/workspace/5.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2715149882
Short name	T550
Test name
Test status
Simulation time	34562680 ps
CPU time	1.32 seconds
Started	May 25 02:06:19 PM PDT 24
Finished	May 25 02:06:21 PM PDT 24
Peak memory	205652 kb
Host	smart-ce4bd04d-ab83-4c31-8a1c-1cc77fa629d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715149882 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2715149882
Directory	/workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_csr_rw.927141285
Short name	T458
Test name
Test status
Simulation time	23198328 ps
CPU time	0.81 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:18 PM PDT 24
Peak memory	205412 kb
Host	smart-edb03087-f84d-48b6-b146-41f7356e0a33
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927141285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.927141285
Directory	/workspace/6.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_intr_test.4250552215
Short name	T154
Test name
Test status
Simulation time	11111790 ps
CPU time	0.72 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205312 kb
Host	smart-3338a2c3-a1cb-4ece-bf33-7d358defe875
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250552215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4250552215
Directory	/workspace/6.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2875908209
Short name	T502
Test name
Test status
Simulation time	23861149 ps
CPU time	1.4 seconds
Started	May 25 02:06:34 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	205424 kb
Host	smart-a64e98df-619f-4a29-8159-50cfd2bde42a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875908209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa me_csr_outstanding.2875908209
Directory	/workspace/6.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1289257831
Short name	T533
Test name
Test status
Simulation time	1099819887 ps
CPU time	30.27 seconds
Started	May 25 02:06:12 PM PDT 24
Finished	May 25 02:06:44 PM PDT 24
Peak memory	222296 kb
Host	smart-7e1e6922-36f4-4f81-9809-cfb522ad4bbc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289257831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado w_reg_errors.1289257831
Directory	/workspace/6.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1943585304
Short name	T130
Test name
Test status
Simulation time	490693518 ps
CPU time	14.98 seconds
Started	May 25 02:06:15 PM PDT 24
Finished	May 25 02:06:31 PM PDT 24
Peak memory	213960 kb
Host	smart-99c88844-1616-476f-b8f7-9eb0dab89c9e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943585304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. keymgr_shadow_reg_errors_with_csr_rw.1943585304
Directory	/workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3932757320
Short name	T136
Test name
Test status
Simulation time	141233160 ps
CPU time	3.66 seconds
Started	May 25 02:06:16 PM PDT 24
Finished	May 25 02:06:21 PM PDT 24
Peak memory	217016 kb
Host	smart-9a1b576f-ac6d-479a-917f-cea4c0dce792
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932757320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3932757320
Directory	/workspace/6.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3293896619
Short name	T181
Test name
Test status
Simulation time	421973763 ps
CPU time	4.72 seconds
Started	May 25 02:06:27 PM PDT 24
Finished	May 25 02:06:32 PM PDT 24
Peak memory	213644 kb
Host	smart-858e3476-cabd-41e7-acd6-10ffc349667e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293896619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err .3293896619
Directory	/workspace/6.keymgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3079801032
Short name	T483
Test name
Test status
Simulation time	40163194 ps
CPU time	2.06 seconds
Started	May 25 02:06:35 PM PDT 24
Finished	May 25 02:06:38 PM PDT 24
Peak memory	213824 kb
Host	smart-2d8a9f1b-7a21-4088-87cb-736091c9cad6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079801032 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3079801032
Directory	/workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_intr_test.80817566
Short name	T521
Test name
Test status
Simulation time	14564490 ps
CPU time	0.9 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205588 kb
Host	smart-2804333b-a807-4429-90b2-1b6062b2df6b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80817566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.80817566
Directory	/workspace/7.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3819003446
Short name	T531
Test name
Test status
Simulation time	382246421 ps
CPU time	4.7 seconds
Started	May 25 02:06:35 PM PDT 24
Finished	May 25 02:06:40 PM PDT 24
Peak memory	222068 kb
Host	smart-f599fc0f-dd3a-44ca-b893-ba429b12b556
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819003446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado w_reg_errors.3819003446
Directory	/workspace/7.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3425796272
Short name	T463
Test name
Test status
Simulation time	18904852 ps
CPU time	1.44 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	213936 kb
Host	smart-226cd27a-ac1e-4525-b5d9-ef8d7610a186
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425796272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3425796272
Directory	/workspace/7.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1239446247
Short name	T527
Test name
Test status
Simulation time	132525765 ps
CPU time	1.6 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	213816 kb
Host	smart-d0adc0e0-8210-4b82-99f9-0708ab8ee689
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239446247 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1239446247
Directory	/workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3008450712
Short name	T536
Test name
Test status
Simulation time	53938829 ps
CPU time	1.5 seconds
Started	May 25 02:06:34 PM PDT 24
Finished	May 25 02:06:36 PM PDT 24
Peak memory	205440 kb
Host	smart-e55f6e82-5989-4047-9b3c-e05d27b745a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008450712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3008450712
Directory	/workspace/8.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_intr_test.3975404439
Short name	T520
Test name
Test status
Simulation time	9429970 ps
CPU time	0.75 seconds
Started	May 25 02:06:21 PM PDT 24
Finished	May 25 02:06:22 PM PDT 24
Peak memory	205328 kb
Host	smart-7c6a52e3-ec2b-45d6-b051-118df1fb19ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975404439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3975404439
Directory	/workspace/8.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1908597130
Short name	T497
Test name
Test status
Simulation time	63241124 ps
CPU time	2.1 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205572 kb
Host	smart-b3843aff-7ae2-4f05-9d5e-2ef4822b9f22
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908597130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa me_csr_outstanding.1908597130
Directory	/workspace/8.keymgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4237715673
Short name	T183
Test name
Test status
Simulation time	261009765 ps
CPU time	2.41 seconds
Started	May 25 02:06:19 PM PDT 24
Finished	May 25 02:06:22 PM PDT 24
Peak memory	214044 kb
Host	smart-8c5a6519-1f85-4392-a559-cd235e5ad948
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237715673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado w_reg_errors.4237715673
Directory	/workspace/8.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1262110622
Short name	T546
Test name
Test status
Simulation time	1648202603 ps
CPU time	15.79 seconds
Started	May 25 02:06:28 PM PDT 24
Finished	May 25 02:06:44 PM PDT 24
Peak memory	220136 kb
Host	smart-6548ee75-ea9e-47e9-a47e-238e2c3c1172
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262110622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. keymgr_shadow_reg_errors_with_csr_rw.1262110622
Directory	/workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2355792724
Short name	T460
Test name
Test status
Simulation time	143472859 ps
CPU time	2.9 seconds
Started	May 25 02:06:22 PM PDT 24
Finished	May 25 02:06:26 PM PDT 24
Peak memory	213928 kb
Host	smart-896c3312-1c92-40b6-95f9-cab686fae913
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355792724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2355792724
Directory	/workspace/8.keymgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1467496738
Short name	T184
Test name
Test status
Simulation time	28484108 ps
CPU time	1.07 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:25 PM PDT 24
Peak memory	205652 kb
Host	smart-0d37ccf2-0aa8-47b0-acda-4e68dfff707b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467496738 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1467496738
Directory	/workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4238499321
Short name	T543
Test name
Test status
Simulation time	53290007 ps
CPU time	1.06 seconds
Started	May 25 02:06:35 PM PDT 24
Finished	May 25 02:06:37 PM PDT 24
Peak memory	205352 kb
Host	smart-fa0b74df-f226-408c-84e5-0834fd4ed8be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238499321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4238499321
Directory	/workspace/9.keymgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_intr_test.3137651122
Short name	T478
Test name
Test status
Simulation time	15398436 ps
CPU time	0.73 seconds
Started	May 25 02:06:21 PM PDT 24
Finished	May 25 02:06:23 PM PDT 24
Peak memory	205328 kb
Host	smart-23c0babc-6999-41e4-8cf4-8575918cc32e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137651122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3137651122
Directory	/workspace/9.keymgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2145239036
Short name	T499
Test name
Test status
Simulation time	97508117 ps
CPU time	2.11 seconds
Started	May 25 02:06:34 PM PDT 24
Finished	May 25 02:06:37 PM PDT 24
Peak memory	213792 kb
Host	smart-8ac0e45b-32d5-444d-ad60-1069e2e66933
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145239036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado w_reg_errors.2145239036
Directory	/workspace/9.keymgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3998425407
Short name	T191
Test name
Test status
Simulation time	720975204 ps
CPU time	4.13 seconds
Started	May 25 02:06:23 PM PDT 24
Finished	May 25 02:06:29 PM PDT 24
Peak memory	213820 kb
Host	smart-baed635d-b629-4d37-b45c-0137258c8fc3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998425407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3998425407
Directory	/workspace/9.keymgr_tl_errors/latest

Test location	/workspace/coverage/default/0.keymgr_alert_test.2378360305
Short name	T606
Test name
Test status
Simulation time	22736611 ps
CPU time	0.86 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:52 PM PDT 24
Peak memory	205512 kb
Host	smart-49965b7a-e553-4563-89a2-17246d1383d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378360305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2378360305
Directory	/workspace/0.keymgr_alert_test/latest

Test location	/workspace/coverage/default/0.keymgr_cfg_regwen.396099819
Short name	T420
Test name
Test status
Simulation time	119594500 ps
CPU time	2.54 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	214104 kb
Host	smart-28f54b3f-248d-4f21-b0af-77888dcd33f9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=396099819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.396099819
Directory	/workspace/0.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/0.keymgr_direct_to_disabled.629494167
Short name	T86
Test name
Test status
Simulation time	259400600 ps
CPU time	2.56 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	209828 kb
Host	smart-14e711a5-dcb6-4d77-830a-8837cb078523
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629494167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.629494167
Directory	/workspace/0.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/0.keymgr_hwsw_invalid_input.3694624970
Short name	T98
Test name
Test status
Simulation time	1030387127 ps
CPU time	7.66 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	214024 kb
Host	smart-f039ae52-af70-4765-9874-f537c5a5c628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694624970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3694624970
Directory	/workspace/0.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/0.keymgr_kmac_rsp_err.2839628782
Short name	T207
Test name
Test status
Simulation time	930014183 ps
CPU time	6.96 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	222120 kb
Host	smart-db1a56d8-950a-4f2e-9852-a3aceff7be8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839628782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2839628782
Directory	/workspace/0.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/0.keymgr_random.3771099646
Short name	T860
Test name
Test status
Simulation time	1455429016 ps
CPU time	11.69 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:06 PM PDT 24
Peak memory	217916 kb
Host	smart-f9cd8084-93c0-4573-80e3-6db6d932f03e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771099646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3771099646
Directory	/workspace/0.keymgr_random/latest

Test location	/workspace/coverage/default/0.keymgr_sideload.165147087
Short name	T795
Test name
Test status
Simulation time	272915688 ps
CPU time	3.23 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:55 PM PDT 24
Peak memory	208264 kb
Host	smart-b598c2ad-2bf4-4b3f-9a17-0e35afb74b94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165147087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.165147087
Directory	/workspace/0.keymgr_sideload/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_aes.1997025136
Short name	T855
Test name
Test status
Simulation time	535131448 ps
CPU time	2.5 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:55 PM PDT 24
Peak memory	206536 kb
Host	smart-23597be9-1755-4391-8bfd-78f07370a2c1
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997025136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1997025136
Directory	/workspace/0.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_kmac.4109787387
Short name	T946
Test name
Test status
Simulation time	677509487 ps
CPU time	2.79 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:53 PM PDT 24
Peak memory	208364 kb
Host	smart-a48ce336-10e0-4ca3-8b16-f7d4b7043b08
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109787387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4109787387
Directory	/workspace/0.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_otbn.1078677940
Short name	T812
Test name
Test status
Simulation time	82204688 ps
CPU time	1.78 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:56 PM PDT 24
Peak memory	206544 kb
Host	smart-08fa1bf6-c0a9-4bb8-be5e-40f60d9d454b
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078677940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1078677940
Directory	/workspace/0.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.keymgr_sideload_protect.935121678
Short name	T1005
Test name
Test status
Simulation time	447137604 ps
CPU time	4.88 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	217720 kb
Host	smart-fdc87319-6a15-47b1-b6a0-87cde60fe568
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935121678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.935121678
Directory	/workspace/0.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/0.keymgr_smoke.3738321462
Short name	T144
Test name
Test status
Simulation time	437114050 ps
CPU time	4.17 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	206272 kb
Host	smart-fafa30da-227b-48f7-a073-80ac9dfce9bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738321462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3738321462
Directory	/workspace/0.keymgr_smoke/latest

Test location	/workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.509239711
Short name	T807
Test name
Test status
Simulation time	271470820 ps
CPU time	4.77 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	218360 kb
Host	smart-555648df-108b-4a1e-ac39-99cf488109fc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509239711 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.509239711
Directory	/workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.keymgr_sw_invalid_input.30957355
Short name	T714
Test name
Test status
Simulation time	422887063 ps
CPU time	4.81 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	214000 kb
Host	smart-8574859c-1ce6-447c-be9d-6a0d8ca0a618
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30957355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.30957355
Directory	/workspace/0.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_cfg_regwen.3404106333
Short name	T246
Test name
Test status
Simulation time	282391718 ps
CPU time	7.36 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	214068 kb
Host	smart-e927dd75-a15e-460b-8254-23ae6e83fd93
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3404106333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3404106333
Directory	/workspace/1.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/1.keymgr_custom_cm.3877227466
Short name	T846
Test name
Test status
Simulation time	144798299 ps
CPU time	3.99 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	213960 kb
Host	smart-2300ad97-ac7d-4a52-8b2b-dee2861f10a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877227466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3877227466
Directory	/workspace/1.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/1.keymgr_direct_to_disabled.2965092265
Short name	T574
Test name
Test status
Simulation time	111626380 ps
CPU time	2.11 seconds
Started	May 25 02:13:50 PM PDT 24
Finished	May 25 02:13:53 PM PDT 24
Peak memory	207452 kb
Host	smart-77303ba4-129f-4efd-85dd-07b70e9cf6fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965092265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2965092265
Directory	/workspace/1.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/1.keymgr_hwsw_invalid_input.112154748
Short name	T22
Test name
Test status
Simulation time	111820578 ps
CPU time	3.41 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	208896 kb
Host	smart-cf5320d6-22d8-40f2-b591-c35b555dbbf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112154748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.112154748
Directory	/workspace/1.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/1.keymgr_lc_disable.2174170031
Short name	T417
Test name
Test status
Simulation time	1904262015 ps
CPU time	3.92 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	216328 kb
Host	smart-5addc8f0-6f4b-4556-a922-c70143668b28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174170031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2174170031
Directory	/workspace/1.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/1.keymgr_random.2086255108
Short name	T201
Test name
Test status
Simulation time	143546164 ps
CPU time	5.8 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	218072 kb
Host	smart-a450787e-09db-480b-aa37-86f5901cfe8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086255108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2086255108
Directory	/workspace/1.keymgr_random/latest

Test location	/workspace/coverage/default/1.keymgr_sideload.3812874059
Short name	T710
Test name
Test status
Simulation time	368230876 ps
CPU time	4.73 seconds
Started	May 25 02:13:48 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	207784 kb
Host	smart-97150ce8-44f9-4a09-85af-d93dc3d47a21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812874059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3812874059
Directory	/workspace/1.keymgr_sideload/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_aes.1484342069
Short name	T792
Test name
Test status
Simulation time	690905035 ps
CPU time	7.79 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:04 PM PDT 24
Peak memory	208328 kb
Host	smart-49b4967b-5afa-41ad-b097-43257472df26
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484342069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1484342069
Directory	/workspace/1.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_kmac.1895009954
Short name	T662
Test name
Test status
Simulation time	370197449 ps
CPU time	2.64 seconds
Started	May 25 02:13:49 PM PDT 24
Finished	May 25 02:13:52 PM PDT 24
Peak memory	208180 kb
Host	smart-65384aab-1fef-4cc9-a40b-94edf9ef250d
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895009954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1895009954
Directory	/workspace/1.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_otbn.1157133261
Short name	T759
Test name
Test status
Simulation time	1037448813 ps
CPU time	5.21 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	207588 kb
Host	smart-225bb77c-5961-4b1f-8660-500e7f5eab05
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157133261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1157133261
Directory	/workspace/1.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.keymgr_sideload_protect.1666595917
Short name	T724
Test name
Test status
Simulation time	23141162 ps
CPU time	1.71 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	215936 kb
Host	smart-24947b15-9db6-4e1a-acc2-f92244f4dde9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666595917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1666595917
Directory	/workspace/1.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/1.keymgr_smoke.3186241988
Short name	T615
Test name
Test status
Simulation time	21059882 ps
CPU time	1.66 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	206436 kb
Host	smart-024d3485-2f11-4b52-950d-c392a0535e12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186241988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3186241988
Directory	/workspace/1.keymgr_smoke/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all.3648611980
Short name	T78
Test name
Test status
Simulation time	3173887324 ps
CPU time	30.17 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:27 PM PDT 24
Peak memory	216428 kb
Host	smart-5f43e3ac-358a-41b6-9473-acb9b1c5f374
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648611980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3648611980
Directory	/workspace/1.keymgr_stress_all/latest

Test location	/workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.59903420
Short name	T229
Test name
Test status
Simulation time	227116931 ps
CPU time	5.88 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	218788 kb
Host	smart-b12593dc-7c1e-4b3d-be89-80edae884145
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59903420 -assert nopostp roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.59903420
Directory	/workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.keymgr_sync_async_fault_cross.2866302738
Short name	T16
Test name
Test status
Simulation time	772488973 ps
CPU time	3.56 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	210592 kb
Host	smart-420de8fe-0c6f-4e89-ba21-5bd78313ecd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866302738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2866302738
Directory	/workspace/1.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/10.keymgr_alert_test.4073649053
Short name	T794
Test name
Test status
Simulation time	10384918 ps
CPU time	0.85 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:16 PM PDT 24
Peak memory	205408 kb
Host	smart-2834a2e0-eae8-4e78-a1ce-559495c0c17a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073649053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4073649053
Directory	/workspace/10.keymgr_alert_test/latest

Test location	/workspace/coverage/default/10.keymgr_custom_cm.2838563332
Short name	T37
Test name
Test status
Simulation time	241950439 ps
CPU time	4.19 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	209088 kb
Host	smart-fda0c9b0-d9e6-4193-904e-be7d8afaaf36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838563332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2838563332
Directory	/workspace/10.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/10.keymgr_direct_to_disabled.586138835
Short name	T940
Test name
Test status
Simulation time	84562308 ps
CPU time	3.45 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	213972 kb
Host	smart-34440aed-8fdd-428e-a94a-d501f1e5a175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586138835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.586138835
Directory	/workspace/10.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/10.keymgr_hwsw_invalid_input.41949176
Short name	T790
Test name
Test status
Simulation time	96380112 ps
CPU time	4.2 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	220044 kb
Host	smart-783e8f9a-77cb-4529-b9f0-3bc8a0369d6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41949176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.41949176
Directory	/workspace/10.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/10.keymgr_kmac_rsp_err.3400687517
Short name	T209
Test name
Test status
Simulation time	1074933008 ps
CPU time	6.8 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	222040 kb
Host	smart-b1c6f598-2deb-4c80-ad1a-6603d4ce04f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400687517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3400687517
Directory	/workspace/10.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/10.keymgr_random.171813319
Short name	T198
Test name
Test status
Simulation time	477754505 ps
CPU time	6.21 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:26 PM PDT 24
Peak memory	208864 kb
Host	smart-37ad43e4-1084-4ec8-8755-5f8be955afc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171813319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.171813319
Directory	/workspace/10.keymgr_random/latest

Test location	/workspace/coverage/default/10.keymgr_sideload.2310323166
Short name	T282
Test name
Test status
Simulation time	34693942 ps
CPU time	2.43 seconds
Started	May 25 02:14:20 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	206480 kb
Host	smart-e06ca8ed-6e0d-4ca2-b8b5-17163620013f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310323166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2310323166
Directory	/workspace/10.keymgr_sideload/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_kmac.1482941190
Short name	T1065
Test name
Test status
Simulation time	461233877 ps
CPU time	2.8 seconds
Started	May 25 02:14:20 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	206592 kb
Host	smart-15380dd6-6720-485c-a7f2-dfe31f6ae3b9
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482941190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1482941190
Directory	/workspace/10.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_otbn.990488274
Short name	T397
Test name
Test status
Simulation time	417189826 ps
CPU time	5.45 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:26 PM PDT 24
Peak memory	208392 kb
Host	smart-fab394ec-953d-4c27-b3d3-57e6439b257d
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990488274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.990488274
Directory	/workspace/10.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/10.keymgr_sideload_protect.3342100162
Short name	T749
Test name
Test status
Simulation time	189824600 ps
CPU time	2.8 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	208068 kb
Host	smart-2f135cd2-05a4-4468-a946-dc3c568e50d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342100162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3342100162
Directory	/workspace/10.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/10.keymgr_smoke.3615986935
Short name	T959
Test name
Test status
Simulation time	325626611 ps
CPU time	2.64 seconds
Started	May 25 02:14:14 PM PDT 24
Finished	May 25 02:14:17 PM PDT 24
Peak memory	207820 kb
Host	smart-be6807db-2542-44f9-ab18-78d7c0d7afc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615986935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3615986935
Directory	/workspace/10.keymgr_smoke/latest

Test location	/workspace/coverage/default/10.keymgr_sw_invalid_input.3042459482
Short name	T645
Test name
Test status
Simulation time	614101667 ps
CPU time	6.49 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	208436 kb
Host	smart-2011ffdf-8f90-42e2-8ed6-bbd3543d12e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042459482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3042459482
Directory	/workspace/10.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/10.keymgr_sync_async_fault_cross.3718585934
Short name	T678
Test name
Test status
Simulation time	115328502 ps
CPU time	2.62 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:19 PM PDT 24
Peak memory	209580 kb
Host	smart-4c2d2a7f-a860-4483-8bcb-c1ba24b8a4a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718585934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3718585934
Directory	/workspace/10.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/11.keymgr_alert_test.2376869726
Short name	T598
Test name
Test status
Simulation time	56730723 ps
CPU time	0.86 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:21 PM PDT 24
Peak memory	205524 kb
Host	smart-f95da186-0070-4c5e-83b6-c346f2a82155
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376869726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2376869726
Directory	/workspace/11.keymgr_alert_test/latest

Test location	/workspace/coverage/default/11.keymgr_hwsw_invalid_input.1904759467
Short name	T806
Test name
Test status
Simulation time	924174811 ps
CPU time	7.9 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:27 PM PDT 24
Peak memory	213996 kb
Host	smart-df4cdc87-fe14-48a1-b98a-5e80374b1020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904759467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1904759467
Directory	/workspace/11.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/11.keymgr_lc_disable.710844098
Short name	T729
Test name
Test status
Simulation time	155588353 ps
CPU time	6.1 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	219816 kb
Host	smart-e83e4c9e-8de9-4def-b876-ed75a2abe0b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710844098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.710844098
Directory	/workspace/11.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/11.keymgr_random.1573356492
Short name	T308
Test name
Test status
Simulation time	6365558648 ps
CPU time	34.19 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:49 PM PDT 24
Peak memory	208812 kb
Host	smart-4f6e7427-b9d1-40d6-9ec3-82868e8e7a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573356492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1573356492
Directory	/workspace/11.keymgr_random/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_aes.1042471898
Short name	T369
Test name
Test status
Simulation time	101773005 ps
CPU time	1.85 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:21 PM PDT 24
Peak memory	206400 kb
Host	smart-0ec904b2-f566-4a01-9083-be4164b71933
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042471898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1042471898
Directory	/workspace/11.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_kmac.3242315694
Short name	T773
Test name
Test status
Simulation time	203272386 ps
CPU time	3.01 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	206460 kb
Host	smart-95eb26d7-00c8-443e-96e5-af381138fcbc
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242315694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3242315694
Directory	/workspace/11.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_otbn.247850037
Short name	T891
Test name
Test status
Simulation time	157170732 ps
CPU time	4.39 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	208324 kb
Host	smart-6496118d-686c-4633-82bd-a0924df961cb
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247850037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.247850037
Directory	/workspace/11.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/11.keymgr_sideload_protect.1554710999
Short name	T567
Test name
Test status
Simulation time	97547684 ps
CPU time	2.19 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	207704 kb
Host	smart-d19b6a78-cfb1-449d-8963-878ae27179a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554710999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1554710999
Directory	/workspace/11.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/11.keymgr_smoke.886653312
Short name	T800
Test name
Test status
Simulation time	80128534 ps
CPU time	1.71 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:18 PM PDT 24
Peak memory	205828 kb
Host	smart-4d46bad5-1fcb-4222-a392-2e6be32770e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886653312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.886653312
Directory	/workspace/11.keymgr_smoke/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all.201608319
Short name	T60
Test name
Test status
Simulation time	176448545 ps
CPU time	7.19 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:26 PM PDT 24
Peak memory	221160 kb
Host	smart-050e17d4-8450-4193-915e-324d854acd3c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201608319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.201608319
Directory	/workspace/11.keymgr_stress_all/latest

Test location	/workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.458729110
Short name	T1037
Test name
Test status
Simulation time	374671639 ps
CPU time	7.56 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	222352 kb
Host	smart-41de84f4-c716-4732-a1ff-ea824a4843e4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458729110 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.458729110
Directory	/workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.keymgr_sw_invalid_input.1148583532
Short name	T805
Test name
Test status
Simulation time	527927010 ps
CPU time	2.53 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	207704 kb
Host	smart-08570f80-8714-4647-9045-968f3d61fa0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148583532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1148583532
Directory	/workspace/11.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_alert_test.2606523564
Short name	T639
Test name
Test status
Simulation time	25312574 ps
CPU time	0.83 seconds
Started	May 25 02:14:32 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	205628 kb
Host	smart-4b4236b7-df8f-452c-901d-e50995fb6419
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606523564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2606523564
Directory	/workspace/12.keymgr_alert_test/latest

Test location	/workspace/coverage/default/12.keymgr_direct_to_disabled.3764138837
Short name	T1046
Test name
Test status
Simulation time	10959292377 ps
CPU time	42.95 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:15:02 PM PDT 24
Peak memory	214160 kb
Host	smart-bc49ab1d-7d53-4f2e-bd17-8c7b62801511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764138837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3764138837
Directory	/workspace/12.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/12.keymgr_hwsw_invalid_input.3445792261
Short name	T99
Test name
Test status
Simulation time	1101969116 ps
CPU time	12.13 seconds
Started	May 25 02:14:33 PM PDT 24
Finished	May 25 02:14:46 PM PDT 24
Peak memory	219732 kb
Host	smart-7355210b-423a-4e8d-aaba-ceb024382d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445792261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3445792261
Directory	/workspace/12.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_random.136651826
Short name	T1014
Test name
Test status
Simulation time	130434187 ps
CPU time	5.66 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	207212 kb
Host	smart-0f74ccab-2ef4-48ec-8480-659b01750940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136651826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.136651826
Directory	/workspace/12.keymgr_random/latest

Test location	/workspace/coverage/default/12.keymgr_sideload.2321369388
Short name	T278
Test name
Test status
Simulation time	535358301 ps
CPU time	5.26 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	208232 kb
Host	smart-dc2551d9-99be-4ee5-81e3-0688555697bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321369388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2321369388
Directory	/workspace/12.keymgr_sideload/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_aes.3458371697
Short name	T1055
Test name
Test status
Simulation time	122477208 ps
CPU time	3.29 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	206576 kb
Host	smart-12d31573-d335-4818-b755-6e1128e3f279
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458371697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3458371697
Directory	/workspace/12.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_kmac.2532128605
Short name	T595
Test name
Test status
Simulation time	5013583620 ps
CPU time	10.58 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:30 PM PDT 24
Peak memory	208556 kb
Host	smart-44c6b57c-5c6e-4526-bdda-6d360d8de8d3
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532128605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2532128605
Directory	/workspace/12.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_otbn.2148310631
Short name	T841
Test name
Test status
Simulation time	264789627 ps
CPU time	3.36 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	208320 kb
Host	smart-80b6f48f-0881-4936-aebf-8bf7cbc2e35e
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148310631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2148310631
Directory	/workspace/12.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/12.keymgr_sideload_protect.1186181420
Short name	T306
Test name
Test status
Simulation time	213805048 ps
CPU time	2.49 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	207728 kb
Host	smart-5b782420-7547-4b1f-bff8-63b9f72bdb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186181420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1186181420
Directory	/workspace/12.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/12.keymgr_smoke.2100063839
Short name	T919
Test name
Test status
Simulation time	141035698 ps
CPU time	1.9 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	208188 kb
Host	smart-2d180a34-2327-420b-a92b-75a0ec7545dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100063839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2100063839
Directory	/workspace/12.keymgr_smoke/latest

Test location	/workspace/coverage/default/12.keymgr_stress_all.2911698848
Short name	T48
Test name
Test status
Simulation time	577268313 ps
CPU time	16.48 seconds
Started	May 25 02:14:35 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	222224 kb
Host	smart-7c1bd75b-8657-4e93-894d-b3adacc5bc5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911698848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2911698848
Directory	/workspace/12.keymgr_stress_all/latest

Test location	/workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.493193213
Short name	T986
Test name
Test status
Simulation time	775258898 ps
CPU time	5.96 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:36 PM PDT 24
Peak memory	219152 kb
Host	smart-f5899f54-2d28-49cf-aa33-d46df232fece
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493193213 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.493193213
Directory	/workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.keymgr_sw_invalid_input.2724916405
Short name	T915
Test name
Test status
Simulation time	112947038 ps
CPU time	3.56 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:33 PM PDT 24
Peak memory	209396 kb
Host	smart-72d6f51e-5b53-4a87-8126-5fc648b8d6da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724916405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2724916405
Directory	/workspace/12.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/12.keymgr_sync_async_fault_cross.1388994674
Short name	T696
Test name
Test status
Simulation time	82311060 ps
CPU time	1.82 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:36 PM PDT 24
Peak memory	209536 kb
Host	smart-a13ca605-6b1d-4ab3-9a61-23932a0ec7f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388994674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1388994674
Directory	/workspace/12.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/13.keymgr_alert_test.2196545712
Short name	T970
Test name
Test status
Simulation time	43235965 ps
CPU time	0.81 seconds
Started	May 25 02:14:33 PM PDT 24
Finished	May 25 02:14:35 PM PDT 24
Peak memory	205544 kb
Host	smart-f891399b-b707-458c-99eb-44fee1ead800
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196545712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2196545712
Directory	/workspace/13.keymgr_alert_test/latest

Test location	/workspace/coverage/default/13.keymgr_cfg_regwen.1009434079
Short name	T366
Test name
Test status
Simulation time	48191613 ps
CPU time	3.56 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	214764 kb
Host	smart-135b3ab8-4cfc-4154-a49c-26ab7f3c0686
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1009434079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1009434079
Directory	/workspace/13.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/13.keymgr_direct_to_disabled.1641100766
Short name	T682
Test name
Test status
Simulation time	278918157 ps
CPU time	3.24 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:41 PM PDT 24
Peak memory	208260 kb
Host	smart-c4ce247d-d5ac-4c91-a323-caf8a907d338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641100766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1641100766
Directory	/workspace/13.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/13.keymgr_hwsw_invalid_input.3237294873
Short name	T1059
Test name
Test status
Simulation time	211522192 ps
CPU time	5.55 seconds
Started	May 25 02:14:38 PM PDT 24
Finished	May 25 02:14:44 PM PDT 24
Peak memory	209328 kb
Host	smart-574229c7-0d12-4d24-8592-440821de5c99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3237294873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3237294873
Directory	/workspace/13.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/13.keymgr_kmac_rsp_err.414062394
Short name	T316
Test name
Test status
Simulation time	114181137 ps
CPU time	2.55 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	208696 kb
Host	smart-bc006a3f-ca3b-4574-b799-4b5d69e460ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414062394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.414062394
Directory	/workspace/13.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/13.keymgr_lc_disable.3322329544
Short name	T236
Test name
Test status
Simulation time	533909805 ps
CPU time	5.12 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:37 PM PDT 24
Peak memory	219972 kb
Host	smart-bd8f2a7c-9577-494e-874b-b65a176f776b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322329544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3322329544
Directory	/workspace/13.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/13.keymgr_random.785641967
Short name	T355
Test name
Test status
Simulation time	56946612 ps
CPU time	3.45 seconds
Started	May 25 02:14:28 PM PDT 24
Finished	May 25 02:14:32 PM PDT 24
Peak memory	207836 kb
Host	smart-fed864fc-846c-4109-bb91-88f3f7949817
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785641967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.785641967
Directory	/workspace/13.keymgr_random/latest

Test location	/workspace/coverage/default/13.keymgr_sideload.4080633088
Short name	T738
Test name
Test status
Simulation time	950976975 ps
CPU time	6.33 seconds
Started	May 25 02:14:32 PM PDT 24
Finished	May 25 02:14:39 PM PDT 24
Peak memory	206588 kb
Host	smart-9794039c-d3a6-4159-89d5-7ff178477866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080633088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4080633088
Directory	/workspace/13.keymgr_sideload/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_aes.1823448701
Short name	T82
Test name
Test status
Simulation time	183880957 ps
CPU time	5.44 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:43 PM PDT 24
Peak memory	207724 kb
Host	smart-1e896576-1cdd-46bf-8f84-3a3e822a40e5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823448701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1823448701
Directory	/workspace/13.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_kmac.4002925285
Short name	T629
Test name
Test status
Simulation time	1198846211 ps
CPU time	8.18 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:43 PM PDT 24
Peak memory	208284 kb
Host	smart-fdacbd28-3341-49e1-ab37-f30b45be1221
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002925285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4002925285
Directory	/workspace/13.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_otbn.3503901244
Short name	T375
Test name
Test status
Simulation time	322993852 ps
CPU time	4.76 seconds
Started	May 25 02:14:26 PM PDT 24
Finished	May 25 02:14:31 PM PDT 24
Peak memory	206528 kb
Host	smart-671637d4-8d2a-42c5-a133-922fee5701d5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503901244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3503901244
Directory	/workspace/13.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/13.keymgr_sideload_protect.992232659
Short name	T718
Test name
Test status
Simulation time	112238696 ps
CPU time	2.15 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:33 PM PDT 24
Peak memory	209252 kb
Host	smart-724d3a13-05c5-483d-9a5e-9b3596c48620
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992232659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.992232659
Directory	/workspace/13.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/13.keymgr_smoke.3302293220
Short name	T942
Test name
Test status
Simulation time	997678287 ps
CPU time	17.26 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	207580 kb
Host	smart-0d7b227b-44dd-46a4-9781-f39407a786be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302293220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3302293220
Directory	/workspace/13.keymgr_smoke/latest

Test location	/workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4222153859
Short name	T935
Test name
Test status
Simulation time	63017614 ps
CPU time	5.05 seconds
Started	May 25 02:14:33 PM PDT 24
Finished	May 25 02:14:38 PM PDT 24
Peak memory	222788 kb
Host	smart-55827992-c10d-4e40-97de-dd8e3beb6d4e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222153859 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4222153859
Directory	/workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.keymgr_sync_async_fault_cross.484609917
Short name	T176
Test name
Test status
Simulation time	220525265 ps
CPU time	2.71 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:33 PM PDT 24
Peak memory	209888 kb
Host	smart-c0e2163a-6c6a-4143-80b7-6f05b67ccfd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484609917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.484609917
Directory	/workspace/13.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/14.keymgr_alert_test.4209309711
Short name	T737
Test name
Test status
Simulation time	44399497 ps
CPU time	0.75 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:30 PM PDT 24
Peak memory	205596 kb
Host	smart-8a772ebb-3464-4d9f-a49d-c877eab4a5b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209309711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4209309711
Directory	/workspace/14.keymgr_alert_test/latest

Test location	/workspace/coverage/default/14.keymgr_cfg_regwen.1047258425
Short name	T422
Test name
Test status
Simulation time	2953782548 ps
CPU time	12.27 seconds
Started	May 25 02:14:33 PM PDT 24
Finished	May 25 02:14:46 PM PDT 24
Peak memory	214052 kb
Host	smart-c749a295-40c0-4cd9-8a23-6c143a935999
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1047258425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1047258425
Directory	/workspace/14.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/14.keymgr_custom_cm.996774790
Short name	T32
Test name
Test status
Simulation time	488541870 ps
CPU time	3.21 seconds
Started	May 25 02:14:35 PM PDT 24
Finished	May 25 02:14:39 PM PDT 24
Peak memory	219280 kb
Host	smart-b9a99bff-8401-4ea0-b794-abdc02c50746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996774790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.996774790
Directory	/workspace/14.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/14.keymgr_direct_to_disabled.3806283198
Short name	T967
Test name
Test status
Simulation time	83367065 ps
CPU time	1.75 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:36 PM PDT 24
Peak memory	206264 kb
Host	smart-66a6974b-9c5c-4dc7-9f8f-d3873543a38d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806283198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3806283198
Directory	/workspace/14.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/14.keymgr_hwsw_invalid_input.2419757274
Short name	T107
Test name
Test status
Simulation time	1159003906 ps
CPU time	5.82 seconds
Started	May 25 02:14:36 PM PDT 24
Finished	May 25 02:14:42 PM PDT 24
Peak memory	208936 kb
Host	smart-b5e1b1f9-7ee2-45bb-bfc7-32d546fe356f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419757274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2419757274
Directory	/workspace/14.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_kmac_rsp_err.4054090762
Short name	T338
Test name
Test status
Simulation time	1242018645 ps
CPU time	13.86 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:45 PM PDT 24
Peak memory	213948 kb
Host	smart-9c948feb-fcd4-456c-98b3-5257c1473a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054090762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4054090762
Directory	/workspace/14.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/14.keymgr_lc_disable.586260959
Short name	T352
Test name
Test status
Simulation time	319274511 ps
CPU time	2.94 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	209056 kb
Host	smart-a683ad7b-b108-4541-96f1-719a8c71744f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586260959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.586260959
Directory	/workspace/14.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/14.keymgr_random.2614886807
Short name	T210
Test name
Test status
Simulation time	767543556 ps
CPU time	4.89 seconds
Started	May 25 02:14:27 PM PDT 24
Finished	May 25 02:14:32 PM PDT 24
Peak memory	209736 kb
Host	smart-c3bc3d43-8dee-4c1a-8ce8-5f9e7b18793b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614886807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2614886807
Directory	/workspace/14.keymgr_random/latest

Test location	/workspace/coverage/default/14.keymgr_sideload.178673692
Short name	T323
Test name
Test status
Simulation time	3016447868 ps
CPU time	16.77 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	207684 kb
Host	smart-ef120010-524b-4d91-8f47-bb6ba5bb17d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178673692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.178673692
Directory	/workspace/14.keymgr_sideload/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_kmac.46208703
Short name	T701
Test name
Test status
Simulation time	1210529273 ps
CPU time	7.75 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:45 PM PDT 24
Peak memory	208772 kb
Host	smart-af83f3db-e566-4421-a69c-0e5b127880ad
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46208703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.46208703
Directory	/workspace/14.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_otbn.3502259077
Short name	T218
Test name
Test status
Simulation time	984235596 ps
CPU time	7.58 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:37 PM PDT 24
Peak memory	207776 kb
Host	smart-024924b4-0fe3-4d24-8b14-fd3d9cb38cf0
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502259077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3502259077
Directory	/workspace/14.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/14.keymgr_sideload_protect.1970544862
Short name	T996
Test name
Test status
Simulation time	56982958 ps
CPU time	2.46 seconds
Started	May 25 02:14:28 PM PDT 24
Finished	May 25 02:14:32 PM PDT 24
Peak memory	207568 kb
Host	smart-724d2632-6cd5-4d2c-b429-ceb51b124715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970544862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1970544862
Directory	/workspace/14.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/14.keymgr_smoke.3697006649
Short name	T564
Test name
Test status
Simulation time	674894471 ps
CPU time	15.37 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:45 PM PDT 24
Peak memory	207796 kb
Host	smart-070ab075-5ba2-46dd-8dc1-b716b55b046f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697006649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3697006649
Directory	/workspace/14.keymgr_smoke/latest

Test location	/workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2817368170
Short name	T863
Test name
Test status
Simulation time	1107411202 ps
CPU time	10.24 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:45 PM PDT 24
Peak memory	222344 kb
Host	smart-8821150d-3bc0-4451-a1eb-0f9b7ede003c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817368170 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2817368170
Directory	/workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.keymgr_sw_invalid_input.1506545058
Short name	T200
Test name
Test status
Simulation time	15495010265 ps
CPU time	97.21 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	213984 kb
Host	smart-11c923c8-ce37-49a2-964c-4814daa2e710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506545058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1506545058
Directory	/workspace/14.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/14.keymgr_sync_async_fault_cross.431561024
Short name	T761
Test name
Test status
Simulation time	221560740 ps
CPU time	2.53 seconds
Started	May 25 02:14:34 PM PDT 24
Finished	May 25 02:14:37 PM PDT 24
Peak memory	209648 kb
Host	smart-a6a1b4b0-f33b-4746-8dc3-40e05f5a6191
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431561024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.431561024
Directory	/workspace/14.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/15.keymgr_alert_test.655480098
Short name	T624
Test name
Test status
Simulation time	25248364 ps
CPU time	0.75 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:49 PM PDT 24
Peak memory	205572 kb
Host	smart-b155d6fb-eaf8-4c6e-a050-b48ed8bc7478
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655480098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.655480098
Directory	/workspace/15.keymgr_alert_test/latest

Test location	/workspace/coverage/default/15.keymgr_cfg_regwen.1664945674
Short name	T411
Test name
Test status
Simulation time	436511740 ps
CPU time	16.67 seconds
Started	May 25 02:14:27 PM PDT 24
Finished	May 25 02:14:44 PM PDT 24
Peak memory	213976 kb
Host	smart-676cd8e9-2ae3-459a-8b71-6bc91d6871af
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1664945674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1664945674
Directory	/workspace/15.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/15.keymgr_direct_to_disabled.35981846
Short name	T780
Test name
Test status
Simulation time	433435043 ps
CPU time	7.8 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:38 PM PDT 24
Peak memory	213952 kb
Host	smart-6687fc8d-03b3-4050-ab19-9fffd79e4f00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35981846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.35981846
Directory	/workspace/15.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/15.keymgr_hwsw_invalid_input.2429852261
Short name	T1036
Test name
Test status
Simulation time	188309612 ps
CPU time	2.91 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:32 PM PDT 24
Peak memory	213868 kb
Host	smart-2ce76ca3-f2d2-4e47-8b59-3584c0226969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429852261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2429852261
Directory	/workspace/15.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_kmac_rsp_err.1753770369
Short name	T378
Test name
Test status
Simulation time	289333946 ps
CPU time	5.85 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	222152 kb
Host	smart-967c6468-f5c7-4291-8be3-3bf1f2e2ac00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753770369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1753770369
Directory	/workspace/15.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/15.keymgr_lc_disable.3240407602
Short name	T268
Test name
Test status
Simulation time	125884303 ps
CPU time	5.56 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:37 PM PDT 24
Peak memory	214060 kb
Host	smart-22cd5cd3-ef5e-44ae-b01b-fc06e64cdc2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240407602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3240407602
Directory	/workspace/15.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/15.keymgr_random.2108321087
Short name	T354
Test name
Test status
Simulation time	336655340 ps
CPU time	4.54 seconds
Started	May 25 02:14:29 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	209372 kb
Host	smart-79c574b9-d1b6-456d-8a94-405edc4e408c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108321087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2108321087
Directory	/workspace/15.keymgr_random/latest

Test location	/workspace/coverage/default/15.keymgr_sideload.474302982
Short name	T889
Test name
Test status
Simulation time	220593691 ps
CPU time	2.91 seconds
Started	May 25 02:14:37 PM PDT 24
Finished	May 25 02:14:40 PM PDT 24
Peak memory	208204 kb
Host	smart-3edcc5f6-ed32-4eda-acdd-77c58f13f565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474302982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.474302982
Directory	/workspace/15.keymgr_sideload/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_aes.4244803186
Short name	T576
Test name
Test status
Simulation time	485750876 ps
CPU time	4.22 seconds
Started	May 25 02:14:38 PM PDT 24
Finished	May 25 02:14:42 PM PDT 24
Peak memory	206608 kb
Host	smart-8c65f425-6009-47e2-90a9-564cd39ec0e3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244803186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4244803186
Directory	/workspace/15.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_kmac.4200597384
Short name	T955
Test name
Test status
Simulation time	342613857 ps
CPU time	3.74 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	208148 kb
Host	smart-58959397-cbc2-4241-a20b-684a5ba961c5
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200597384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4200597384
Directory	/workspace/15.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_otbn.2383751917
Short name	T632
Test name
Test status
Simulation time	181912489 ps
CPU time	3.34 seconds
Started	May 25 02:14:30 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	208500 kb
Host	smart-0d4a700d-8bc6-489c-967b-b9980eac3262
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383751917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2383751917
Directory	/workspace/15.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/15.keymgr_sideload_protect.806734737
Short name	T697
Test name
Test status
Simulation time	54232989 ps
CPU time	2.2 seconds
Started	May 25 02:14:36 PM PDT 24
Finished	May 25 02:14:38 PM PDT 24
Peak memory	209524 kb
Host	smart-ed95369a-74fe-45fc-8185-aeb6b194fa4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806734737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.806734737
Directory	/workspace/15.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/15.keymgr_smoke.1028124445
Short name	T575
Test name
Test status
Simulation time	370854280 ps
CPU time	7.15 seconds
Started	May 25 02:14:35 PM PDT 24
Finished	May 25 02:14:43 PM PDT 24
Peak memory	208228 kb
Host	smart-de0fea83-0d63-4020-97b5-780a15584f1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028124445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1028124445
Directory	/workspace/15.keymgr_smoke/latest

Test location	/workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1445314895
Short name	T767
Test name
Test status
Simulation time	226223513 ps
CPU time	9 seconds
Started	May 25 02:14:47 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	222352 kb
Host	smart-ab78aefa-1ad6-4f2d-99aa-aaa1747d884d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445314895 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1445314895
Directory	/workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.keymgr_sw_invalid_input.1696854013
Short name	T1062
Test name
Test status
Simulation time	64443634 ps
CPU time	2.46 seconds
Started	May 25 02:14:31 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	206976 kb
Host	smart-70e856df-1f42-4e2c-921b-06344e259e11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696854013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1696854013
Directory	/workspace/15.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/15.keymgr_sync_async_fault_cross.351466814
Short name	T850
Test name
Test status
Simulation time	493633210 ps
CPU time	3.41 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	210116 kb
Host	smart-a2d6a8a1-413b-417e-9a6a-b50ac7defd56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351466814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.351466814
Directory	/workspace/15.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/16.keymgr_alert_test.2174409855
Short name	T949
Test name
Test status
Simulation time	29602220 ps
CPU time	0.79 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	205256 kb
Host	smart-a7001188-45fe-4af2-994c-baef4b88346f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174409855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2174409855
Directory	/workspace/16.keymgr_alert_test/latest

Test location	/workspace/coverage/default/16.keymgr_direct_to_disabled.446195708
Short name	T801
Test name
Test status
Simulation time	1062317187 ps
CPU time	8.05 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:15:00 PM PDT 24
Peak memory	208224 kb
Host	smart-f5989fa2-2e9c-4e18-a144-49ccdb671225
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446195708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.446195708
Directory	/workspace/16.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/16.keymgr_hwsw_invalid_input.3003858736
Short name	T394
Test name
Test status
Simulation time	781219905 ps
CPU time	3.81 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	214024 kb
Host	smart-db362258-7012-4ea0-9c68-de9669b2cc3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003858736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3003858736
Directory	/workspace/16.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_lc_disable.596180965
Short name	T695
Test name
Test status
Simulation time	59595214 ps
CPU time	3.06 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	208444 kb
Host	smart-2ff785e9-4188-4855-9696-85d73fd9056d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596180965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.596180965
Directory	/workspace/16.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/16.keymgr_random.3663432033
Short name	T399
Test name
Test status
Simulation time	87739251 ps
CPU time	3.99 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	208136 kb
Host	smart-b21ebbe1-fd2c-48c8-bc3d-e6116bd81c65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663432033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3663432033
Directory	/workspace/16.keymgr_random/latest

Test location	/workspace/coverage/default/16.keymgr_sideload.700208007
Short name	T655
Test name
Test status
Simulation time	760881917 ps
CPU time	6.19 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	207472 kb
Host	smart-dfd938ff-7a01-4c2b-a40d-aaea58ae9042
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700208007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.700208007
Directory	/workspace/16.keymgr_sideload/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_aes.3546507103
Short name	T1034
Test name
Test status
Simulation time	133657933 ps
CPU time	4.35 seconds
Started	May 25 02:14:46 PM PDT 24
Finished	May 25 02:14:51 PM PDT 24
Peak memory	208568 kb
Host	smart-4a8c8122-9cd0-4ec9-bb47-34c976d286ab
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546507103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3546507103
Directory	/workspace/16.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_kmac.1879723838
Short name	T877
Test name
Test status
Simulation time	40342789 ps
CPU time	2.26 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	206412 kb
Host	smart-bf7723ea-7b67-41e4-a70e-3ad7932ec73f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879723838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1879723838
Directory	/workspace/16.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_otbn.3207995303
Short name	T637
Test name
Test status
Simulation time	233965086 ps
CPU time	3.12 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	208644 kb
Host	smart-c897f9d6-19bd-422a-a9b2-8a7632fc3ac3
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207995303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3207995303
Directory	/workspace/16.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/16.keymgr_sideload_protect.3420944809
Short name	T648
Test name
Test status
Simulation time	26186492 ps
CPU time	1.87 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	206876 kb
Host	smart-e571743a-db65-4679-86e0-35d71e9fe4fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420944809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3420944809
Directory	/workspace/16.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/16.keymgr_smoke.411557124
Short name	T922
Test name
Test status
Simulation time	125864790 ps
CPU time	3.04 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	208036 kb
Host	smart-2fbe6a16-30b7-4681-bb6c-1c77e50efdce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411557124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.411557124
Directory	/workspace/16.keymgr_smoke/latest

Test location	/workspace/coverage/default/16.keymgr_sw_invalid_input.4286326924
Short name	T890
Test name
Test status
Simulation time	3547752933 ps
CPU time	60.08 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	214108 kb
Host	smart-849d8ca0-9b1d-4309-bf0c-70826a80612e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286326924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4286326924
Directory	/workspace/16.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/16.keymgr_sync_async_fault_cross.4152106306
Short name	T1053
Test name
Test status
Simulation time	228136005 ps
CPU time	3.88 seconds
Started	May 25 02:14:47 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	209640 kb
Host	smart-7e44eeae-e753-4b3f-9034-fdcfa7f63876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152106306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4152106306
Directory	/workspace/16.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/17.keymgr_alert_test.2247903734
Short name	T895
Test name
Test status
Simulation time	11077722 ps
CPU time	0.75 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:49 PM PDT 24
Peak memory	205420 kb
Host	smart-e4a21aa1-99c1-4426-a83c-c188f3036f6d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247903734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2247903734
Directory	/workspace/17.keymgr_alert_test/latest

Test location	/workspace/coverage/default/17.keymgr_cfg_regwen.1350751632
Short name	T327
Test name
Test status
Simulation time	31348346 ps
CPU time	2.59 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:51 PM PDT 24
Peak memory	214048 kb
Host	smart-2d7fbb71-1588-41b1-ac28-81baab19b00d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1350751632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1350751632
Directory	/workspace/17.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/17.keymgr_custom_cm.4232282444
Short name	T113
Test name
Test status
Simulation time	453719939 ps
CPU time	5.83 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	208356 kb
Host	smart-382adfac-0841-4bfe-8ce9-ebbaadd49016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232282444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4232282444
Directory	/workspace/17.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/17.keymgr_direct_to_disabled.157114672
Short name	T653
Test name
Test status
Simulation time	119287942 ps
CPU time	2.5 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	206796 kb
Host	smart-f231d9c0-9082-439f-bd12-ea439517a290
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157114672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.157114672
Directory	/workspace/17.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/17.keymgr_kmac_rsp_err.2854595974
Short name	T698
Test name
Test status
Simulation time	75952679 ps
CPU time	4.76 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	209876 kb
Host	smart-d7b8d6c2-49a0-41bf-9ae4-e491474d5a3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854595974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2854595974
Directory	/workspace/17.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/17.keymgr_lc_disable.3601876355
Short name	T969
Test name
Test status
Simulation time	395956610 ps
CPU time	4.5 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	219552 kb
Host	smart-94f7dd37-1b09-42a4-99b2-a4efa7e6fe47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601876355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3601876355
Directory	/workspace/17.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/17.keymgr_random.462611871
Short name	T367
Test name
Test status
Simulation time	1748965142 ps
CPU time	7.34 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:15:01 PM PDT 24
Peak memory	217908 kb
Host	smart-9b52ad71-d262-40b1-b35e-402dacb1fab7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462611871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.462611871
Directory	/workspace/17.keymgr_random/latest

Test location	/workspace/coverage/default/17.keymgr_sideload.3369862082
Short name	T342
Test name
Test status
Simulation time	90454270 ps
CPU time	1.99 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:50 PM PDT 24
Peak memory	208064 kb
Host	smart-31ae4338-a1a2-4d67-a307-e008cfc4a6dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369862082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3369862082
Directory	/workspace/17.keymgr_sideload/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_kmac.1865608388
Short name	T676
Test name
Test status
Simulation time	51370195 ps
CPU time	2.72 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	206404 kb
Host	smart-fbc10888-6e7a-4c82-ba97-2ca288d3c5de
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865608388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1865608388
Directory	/workspace/17.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_otbn.369161215
Short name	T825
Test name
Test status
Simulation time	74379002 ps
CPU time	3.12 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	208164 kb
Host	smart-09e55dab-6746-4bcc-a2aa-22bc826061b3
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369161215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.369161215
Directory	/workspace/17.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/17.keymgr_sideload_protect.1669059126
Short name	T747
Test name
Test status
Simulation time	121309844 ps
CPU time	1.67 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	208896 kb
Host	smart-d19035ed-59d5-4564-8fd0-5cd0cf35d7fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669059126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1669059126
Directory	/workspace/17.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/17.keymgr_smoke.2347280849
Short name	T694
Test name
Test status
Simulation time	619342311 ps
CPU time	10.34 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:15:00 PM PDT 24
Peak memory	207768 kb
Host	smart-aad2cf68-9cce-45b0-9a81-dcacf4d7fdd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347280849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2347280849
Directory	/workspace/17.keymgr_smoke/latest

Test location	/workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3476903778
Short name	T587
Test name
Test status
Simulation time	672847518 ps
CPU time	4.52 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	221944 kb
Host	smart-8e05cf42-b428-4116-a67c-1036bc6c578c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476903778 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3476903778
Directory	/workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.keymgr_sw_invalid_input.163221205
Short name	T878
Test name
Test status
Simulation time	310644161 ps
CPU time	8.35 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	208852 kb
Host	smart-9f8a9fba-902a-4ef4-b5a7-a8982cbc92f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163221205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.163221205
Directory	/workspace/17.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/17.keymgr_sync_async_fault_cross.1382469855
Short name	T972
Test name
Test status
Simulation time	68400320 ps
CPU time	1.93 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	209840 kb
Host	smart-340a25b6-4b70-405a-8ad7-cef3accbfab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382469855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1382469855
Directory	/workspace/17.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/18.keymgr_alert_test.1666628734
Short name	T1039
Test name
Test status
Simulation time	26587797 ps
CPU time	0.96 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	205744 kb
Host	smart-8373ff0f-6458-40c5-9214-888480d976d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666628734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1666628734
Directory	/workspace/18.keymgr_alert_test/latest

Test location	/workspace/coverage/default/18.keymgr_direct_to_disabled.1148238809
Short name	T313
Test name
Test status
Simulation time	1460098642 ps
CPU time	8.55 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	213976 kb
Host	smart-31ad734e-52d7-4faa-8287-23a5facd5496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148238809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1148238809
Directory	/workspace/18.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/18.keymgr_hwsw_invalid_input.965528734
Short name	T916
Test name
Test status
Simulation time	846560216 ps
CPU time	26.36 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:15:20 PM PDT 24
Peak memory	218864 kb
Host	smart-c93c4f5c-014b-4dd8-b0c7-d16432f94d6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965528734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.965528734
Directory	/workspace/18.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_kmac_rsp_err.2814331176
Short name	T24
Test name
Test status
Simulation time	1731618096 ps
CPU time	14.02 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	222104 kb
Host	smart-17ebf764-1ff6-4dd1-b207-b93e4aa36ad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814331176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2814331176
Directory	/workspace/18.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/18.keymgr_lc_disable.3485956928
Short name	T674
Test name
Test status
Simulation time	113813379 ps
CPU time	6.06 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	214016 kb
Host	smart-caed06dc-cbd6-4f5e-a074-200ee9d4b10f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485956928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3485956928
Directory	/workspace/18.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/18.keymgr_random.380333017
Short name	T881
Test name
Test status
Simulation time	779447045 ps
CPU time	7.85 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:00 PM PDT 24
Peak memory	209464 kb
Host	smart-11e51d90-3d82-4a91-9b06-072a1a3b25af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380333017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.380333017
Directory	/workspace/18.keymgr_random/latest

Test location	/workspace/coverage/default/18.keymgr_sideload.154086169
Short name	T675
Test name
Test status
Simulation time	53254283 ps
CPU time	2.86 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	208172 kb
Host	smart-2f943868-bcc5-4ad1-bb47-88510ae083dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154086169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.154086169
Directory	/workspace/18.keymgr_sideload/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_aes.3708663409
Short name	T685
Test name
Test status
Simulation time	308210221 ps
CPU time	4.1 seconds
Started	May 25 02:14:47 PM PDT 24
Finished	May 25 02:14:52 PM PDT 24
Peak memory	207040 kb
Host	smart-541df06b-57d4-47bd-8bbf-55597ff65e56
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708663409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3708663409
Directory	/workspace/18.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_kmac.1865564569
Short name	T644
Test name
Test status
Simulation time	815421315 ps
CPU time	6.83 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	207600 kb
Host	smart-e4b85648-44aa-4f06-8605-a3a69fe4d2cf
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865564569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1865564569
Directory	/workspace/18.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_otbn.1552522770
Short name	T842
Test name
Test status
Simulation time	23300060 ps
CPU time	1.98 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	206968 kb
Host	smart-e5457961-4ba1-4a01-82b4-f2d49ebfab90
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552522770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1552522770
Directory	/workspace/18.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/18.keymgr_sideload_protect.3471786859
Short name	T923
Test name
Test status
Simulation time	526999326 ps
CPU time	3.42 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	217684 kb
Host	smart-117e41cb-7ffb-4f25-a735-c15d4ffb4dbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471786859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3471786859
Directory	/workspace/18.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/18.keymgr_smoke.2582449969
Short name	T928
Test name
Test status
Simulation time	2210571117 ps
CPU time	5.42 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	208292 kb
Host	smart-c79740d6-7ac6-48f4-b4fe-ed4d8d3a3ada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582449969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2582449969
Directory	/workspace/18.keymgr_smoke/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all.608634559
Short name	T271
Test name
Test status
Simulation time	737892111 ps
CPU time	9.25 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:02 PM PDT 24
Peak memory	215256 kb
Host	smart-e0e6ee54-b29e-4e30-95e3-5b2e0fd3dbdd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608634559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.608634559
Directory	/workspace/18.keymgr_stress_all/latest

Test location	/workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.783091220
Short name	T225
Test name
Test status
Simulation time	213311252 ps
CPU time	5.94 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	222336 kb
Host	smart-981dbcc8-0ffe-4d8d-8909-1705c9af6db9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783091220 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.783091220
Directory	/workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.keymgr_sw_invalid_input.615514616
Short name	T205
Test name
Test status
Simulation time	62894336 ps
CPU time	3.99 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	206804 kb
Host	smart-47d6efb8-994d-43f6-b13f-dc29dfe38fc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615514616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.615514616
Directory	/workspace/18.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/18.keymgr_sync_async_fault_cross.2332955343
Short name	T631
Test name
Test status
Simulation time	85860122 ps
CPU time	2.74 seconds
Started	May 25 02:14:49 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	209520 kb
Host	smart-ee8c6564-a73e-4c0e-9a15-717ffbf75ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332955343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2332955343
Directory	/workspace/18.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/19.keymgr_alert_test.62139056
Short name	T616
Test name
Test status
Simulation time	37763387 ps
CPU time	0.69 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	205556 kb
Host	smart-2bd73c52-730a-40ec-82b8-617e265ed483
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62139056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.62139056
Directory	/workspace/19.keymgr_alert_test/latest

Test location	/workspace/coverage/default/19.keymgr_cfg_regwen.448741135
Short name	T421
Test name
Test status
Simulation time	859506787 ps
CPU time	13.32 seconds
Started	May 25 02:14:54 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	214048 kb
Host	smart-826dcf77-4ad5-4fc8-9d3f-10dd0b0a4253
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=448741135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.448741135
Directory	/workspace/19.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/19.keymgr_custom_cm.2082208265
Short name	T912
Test name
Test status
Simulation time	57815783 ps
CPU time	2.62 seconds
Started	May 25 02:14:54 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	216320 kb
Host	smart-57cc370c-9658-4891-98aa-fef9af1ef26b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082208265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2082208265
Directory	/workspace/19.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/19.keymgr_direct_to_disabled.3863246908
Short name	T830
Test name
Test status
Simulation time	4410847967 ps
CPU time	20.18 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	214024 kb
Host	smart-562a0cc2-a30a-4e8b-9d96-8642d431635f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863246908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3863246908
Directory	/workspace/19.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/19.keymgr_hwsw_invalid_input.3433789994
Short name	T875
Test name
Test status
Simulation time	474896255 ps
CPU time	16.52 seconds
Started	May 25 02:14:48 PM PDT 24
Finished	May 25 02:15:05 PM PDT 24
Peak memory	213904 kb
Host	smart-4928ceed-b7ae-4755-8ea9-ac37544a69a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433789994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3433789994
Directory	/workspace/19.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_kmac_rsp_err.2855065084
Short name	T276
Test name
Test status
Simulation time	211037193 ps
CPU time	6.25 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:59 PM PDT 24
Peak memory	222072 kb
Host	smart-3fb96bb5-3162-48cb-8ea4-2ae516c1e66c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855065084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2855065084
Directory	/workspace/19.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/19.keymgr_lc_disable.574339819
Short name	T1050
Test name
Test status
Simulation time	159447317 ps
CPU time	3.64 seconds
Started	May 25 02:14:54 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	222056 kb
Host	smart-2c96b9ea-bf5b-4bbd-b5fc-190a0bb57e87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574339819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.574339819
Directory	/workspace/19.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/19.keymgr_random.1328326959
Short name	T288
Test name
Test status
Simulation time	64446326 ps
CPU time	3.26 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	206812 kb
Host	smart-3bbfe3e0-43fd-49c0-8965-7be288856d58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1328326959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1328326959
Directory	/workspace/19.keymgr_random/latest

Test location	/workspace/coverage/default/19.keymgr_sideload.918578022
Short name	T814
Test name
Test status
Simulation time	1592079088 ps
CPU time	7.36 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	208060 kb
Host	smart-2e5b336d-67fb-41c4-8c66-fe709d7b1ebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918578022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.918578022
Directory	/workspace/19.keymgr_sideload/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_aes.1281441848
Short name	T111
Test name
Test status
Simulation time	37371166 ps
CPU time	2.19 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:54 PM PDT 24
Peak memory	206568 kb
Host	smart-0bac2f0a-c189-497b-a410-6f781baf2306
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281441848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1281441848
Directory	/workspace/19.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_kmac.4016624564
Short name	T630
Test name
Test status
Simulation time	118482035 ps
CPU time	2.92 seconds
Started	May 25 02:14:52 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	206500 kb
Host	smart-d079b57a-b624-4d43-a75b-f237651e0c0f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016624564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4016624564
Directory	/workspace/19.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_otbn.1905651255
Short name	T776
Test name
Test status
Simulation time	70760309 ps
CPU time	3.52 seconds
Started	May 25 02:14:53 PM PDT 24
Finished	May 25 02:14:57 PM PDT 24
Peak memory	208100 kb
Host	smart-764285ce-9762-4fc4-9fff-d5ad8e7ff824
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905651255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1905651255
Directory	/workspace/19.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/19.keymgr_sideload_protect.2136754586
Short name	T426
Test name
Test status
Simulation time	169189452 ps
CPU time	4.15 seconds
Started	May 25 02:14:54 PM PDT 24
Finished	May 25 02:14:59 PM PDT 24
Peak memory	217844 kb
Host	smart-985853c8-bcff-4ce6-9346-271475c7388c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136754586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2136754586
Directory	/workspace/19.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/19.keymgr_smoke.2264885106
Short name	T1028
Test name
Test status
Simulation time	1011498178 ps
CPU time	5.52 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:58 PM PDT 24
Peak memory	207980 kb
Host	smart-f462cca0-349e-4188-b658-568c0158623e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264885106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2264885106
Directory	/workspace/19.keymgr_smoke/latest

Test location	/workspace/coverage/default/19.keymgr_stress_all.1170354256
Short name	T64
Test name
Test status
Simulation time	352082623 ps
CPU time	8.3 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:00 PM PDT 24
Peak memory	219164 kb
Host	smart-ee9046bd-20c3-4b69-aff1-a3532d031bd3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170354256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1170354256
Directory	/workspace/19.keymgr_stress_all/latest

Test location	/workspace/coverage/default/19.keymgr_sw_invalid_input.616400410
Short name	T247
Test name
Test status
Simulation time	405659513 ps
CPU time	15.4 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	208472 kb
Host	smart-a77b2657-f174-4487-901e-24e41da3f632
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616400410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.616400410
Directory	/workspace/19.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/19.keymgr_sync_async_fault_cross.19483670
Short name	T182
Test name
Test status
Simulation time	864032766 ps
CPU time	2.28 seconds
Started	May 25 02:14:50 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	209900 kb
Host	smart-ec91e31f-8ca2-48ff-b093-aa08b17d275e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=19483670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.19483670
Directory	/workspace/19.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/2.keymgr_alert_test.3746227044
Short name	T810
Test name
Test status
Simulation time	14228039 ps
CPU time	0.74 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	205500 kb
Host	smart-bcb80fcf-505b-4dcb-8079-3fa296fe618e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746227044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3746227044
Directory	/workspace/2.keymgr_alert_test/latest

Test location	/workspace/coverage/default/2.keymgr_cfg_regwen.3708165322
Short name	T428
Test name
Test status
Simulation time	298713866 ps
CPU time	2.56 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	213952 kb
Host	smart-b7e1ca84-2085-4084-805f-e271a44d0489
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3708165322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3708165322
Directory	/workspace/2.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/2.keymgr_direct_to_disabled.3681934169
Short name	T69
Test name
Test status
Simulation time	50472359 ps
CPU time	1.36 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	207596 kb
Host	smart-3668811c-97bf-4bf5-b556-394ba86d8e75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681934169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3681934169
Directory	/workspace/2.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/2.keymgr_hwsw_invalid_input.2057616203
Short name	T813
Test name
Test status
Simulation time	117635367 ps
CPU time	4.81 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	218844 kb
Host	smart-30082a2c-160b-4c51-96e9-ed3ec3915906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057616203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2057616203
Directory	/workspace/2.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_kmac_rsp_err.750908069
Short name	T298
Test name
Test status
Simulation time	416651537 ps
CPU time	6.57 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	214048 kb
Host	smart-c665bce3-b7ca-4b06-9748-22f049a43650
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750908069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.750908069
Directory	/workspace/2.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/2.keymgr_random.4210280966
Short name	T835
Test name
Test status
Simulation time	298401564 ps
CPU time	4.08 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	207596 kb
Host	smart-57845d9b-ecab-44f5-8e14-ac5ba543bd37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4210280966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4210280966
Directory	/workspace/2.keymgr_random/latest

Test location	/workspace/coverage/default/2.keymgr_sec_cm.1685667512
Short name	T38
Test name
Test status
Simulation time	11719767613 ps
CPU time	65.03 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:15:00 PM PDT 24
Peak memory	243992 kb
Host	smart-8d90b91b-e636-4b67-9a6e-ec0180916c4c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685667512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1685667512
Directory	/workspace/2.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/2.keymgr_sideload.3025297425
Short name	T782
Test name
Test status
Simulation time	22314018 ps
CPU time	1.74 seconds
Started	May 25 02:13:51 PM PDT 24
Finished	May 25 02:13:54 PM PDT 24
Peak memory	206484 kb
Host	smart-2e82286e-8ee7-4617-baca-e26b53dd2d7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025297425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3025297425
Directory	/workspace/2.keymgr_sideload/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_aes.325897098
Short name	T319
Test name
Test status
Simulation time	4618660314 ps
CPU time	46.74 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:43 PM PDT 24
Peak memory	208320 kb
Host	smart-68d59250-4450-41f3-bea8-d2555368f4d7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325897098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.325897098
Directory	/workspace/2.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_kmac.4210769369
Short name	T903
Test name
Test status
Simulation time	36439510 ps
CPU time	2.82 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:02 PM PDT 24
Peak memory	208620 kb
Host	smart-2471c111-504a-45e0-9b69-5e010474bf3a
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210769369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4210769369
Directory	/workspace/2.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_otbn.1407978701
Short name	T755
Test name
Test status
Simulation time	278261203 ps
CPU time	3.74 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	208712 kb
Host	smart-a558aa2a-620f-48ff-8d87-0990595f5c54
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407978701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1407978701
Directory	/workspace/2.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.keymgr_sideload_protect.3510720457
Short name	T114
Test name
Test status
Simulation time	446392227 ps
CPU time	6.37 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	213944 kb
Host	smart-9ab6eb2e-21ba-41da-a513-63768a88b8a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510720457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3510720457
Directory	/workspace/2.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/2.keymgr_smoke.3121140892
Short name	T588
Test name
Test status
Simulation time	1187752921 ps
CPU time	3.31 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	207920 kb
Host	smart-78eadc45-be32-49db-bc67-66767fca8ad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121140892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3121140892
Directory	/workspace/2.keymgr_smoke/latest

Test location	/workspace/coverage/default/2.keymgr_stress_all.3858002593
Short name	T849
Test name
Test status
Simulation time	109684552 ps
CPU time	5.17 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	217884 kb
Host	smart-ed0eeae5-8a7e-4ae5-a461-a7461470ac74
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858002593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3858002593
Directory	/workspace/2.keymgr_stress_all/latest

Test location	/workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2302126457
Short name	T779
Test name
Test status
Simulation time	191293523 ps
CPU time	9.63 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	222488 kb
Host	smart-afd76115-8218-445e-af2c-c6f81146ec02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302126457 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2302126457
Directory	/workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.keymgr_sw_invalid_input.4076444156
Short name	T359
Test name
Test status
Simulation time	497763454 ps
CPU time	5.05 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	206924 kb
Host	smart-4f0081dc-50fe-492e-a4e9-6a0090a2648d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076444156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4076444156
Directory	/workspace/2.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/2.keymgr_sync_async_fault_cross.1608498221
Short name	T866
Test name
Test status
Simulation time	90799578 ps
CPU time	2.09 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	209328 kb
Host	smart-beb817c7-3f74-4b67-a772-3bac13aa80f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608498221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1608498221
Directory	/workspace/2.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/20.keymgr_alert_test.3614649530
Short name	T1017
Test name
Test status
Simulation time	40913381 ps
CPU time	0.76 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:01 PM PDT 24
Peak memory	205528 kb
Host	smart-1b95010c-c20c-424c-b9d3-d45362f7c98c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614649530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3614649530
Directory	/workspace/20.keymgr_alert_test/latest

Test location	/workspace/coverage/default/20.keymgr_cfg_regwen.3643299419
Short name	T414
Test name
Test status
Simulation time	100042141 ps
CPU time	3.74 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	214020 kb
Host	smart-983d7ad1-9fcc-4607-b9bf-1d1f5e5e0f34
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3643299419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3643299419
Directory	/workspace/20.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/20.keymgr_custom_cm.614251038
Short name	T861
Test name
Test status
Simulation time	443131547 ps
CPU time	9.48 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:10 PM PDT 24
Peak memory	218376 kb
Host	smart-841dd3b5-c3da-44ac-95ff-0512160cd89d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614251038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.614251038
Directory	/workspace/20.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/20.keymgr_direct_to_disabled.1080391098
Short name	T999
Test name
Test status
Simulation time	433606266 ps
CPU time	4.89 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	208648 kb
Host	smart-f9b858ac-d295-4746-b643-be33010b9e1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080391098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1080391098
Directory	/workspace/20.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/20.keymgr_hwsw_invalid_input.2776823061
Short name	T104
Test name
Test status
Simulation time	531604453 ps
CPU time	5.04 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	214044 kb
Host	smart-4b8fe208-4422-42ef-a9ea-e68c369550a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776823061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2776823061
Directory	/workspace/20.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_kmac_rsp_err.637286880
Short name	T295
Test name
Test status
Simulation time	198070641 ps
CPU time	4.75 seconds
Started	May 25 02:15:03 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	213956 kb
Host	smart-a9d7274e-b097-4efc-bd2c-b59091ea963c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637286880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.637286880
Directory	/workspace/20.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/20.keymgr_lc_disable.1690687756
Short name	T49
Test name
Test status
Simulation time	717230150 ps
CPU time	4.65 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	219192 kb
Host	smart-8916c927-0c7a-4add-9ce2-b95861bded23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1690687756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1690687756
Directory	/workspace/20.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/20.keymgr_random.1187919203
Short name	T424
Test name
Test status
Simulation time	740303518 ps
CPU time	9.81 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	219292 kb
Host	smart-62700657-07ab-4087-b5bb-826556a5e0df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187919203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1187919203
Directory	/workspace/20.keymgr_random/latest

Test location	/workspace/coverage/default/20.keymgr_sideload.3955518260
Short name	T309
Test name
Test status
Simulation time	77989205 ps
CPU time	3.88 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:56 PM PDT 24
Peak memory	208232 kb
Host	smart-07a15cba-1754-447d-808f-38c0dfb91b81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955518260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3955518260
Directory	/workspace/20.keymgr_sideload/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_aes.1325879025
Short name	T827
Test name
Test status
Simulation time	81958729 ps
CPU time	3.54 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	206620 kb
Host	smart-8e4368a2-86fd-4b9c-b68d-381b99b5c2e0
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325879025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1325879025
Directory	/workspace/20.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_kmac.1749286638
Short name	T815
Test name
Test status
Simulation time	31654538 ps
CPU time	2.3 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	206540 kb
Host	smart-e1a78ee7-7250-46c3-b358-00d9e6f1bf0c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749286638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1749286638
Directory	/workspace/20.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_otbn.2210241783
Short name	T633
Test name
Test status
Simulation time	124263833 ps
CPU time	4.55 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	206520 kb
Host	smart-456f7038-bff0-4efb-bc6d-1f5b5b9df6e8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210241783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2210241783
Directory	/workspace/20.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/20.keymgr_sideload_protect.144396043
Short name	T944
Test name
Test status
Simulation time	812652864 ps
CPU time	11.07 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	207736 kb
Host	smart-1b6dbc9f-8159-40c9-989f-751e589b2674
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144396043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.144396043
Directory	/workspace/20.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/20.keymgr_smoke.3867327203
Short name	T404
Test name
Test status
Simulation time	1980969946 ps
CPU time	18.02 seconds
Started	May 25 02:14:51 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	207904 kb
Host	smart-ad0d68f9-81cc-4ef9-a9da-3b73ba8cd84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867327203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3867327203
Directory	/workspace/20.keymgr_smoke/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all.1037475811
Short name	T957
Test name
Test status
Simulation time	1688443353 ps
CPU time	48.86 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:50 PM PDT 24
Peak memory	220456 kb
Host	smart-120a46da-8c8c-4479-bebb-fd3726b24323
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037475811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1037475811
Directory	/workspace/20.keymgr_stress_all/latest

Test location	/workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.275953184
Short name	T222
Test name
Test status
Simulation time	302036747 ps
CPU time	5.48 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	222400 kb
Host	smart-84d6905e-1781-44eb-809c-1740ab92e9d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275953184 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.275953184
Directory	/workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.keymgr_sw_invalid_input.64992559
Short name	T328
Test name
Test status
Simulation time	970734324 ps
CPU time	8.81 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	210076 kb
Host	smart-f2bdf292-dcee-48c3-8a5d-5dec28f2372e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64992559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.64992559
Directory	/workspace/20.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/20.keymgr_sync_async_fault_cross.103082632
Short name	T687
Test name
Test status
Simulation time	260898553 ps
CPU time	2.74 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:03 PM PDT 24
Peak memory	209448 kb
Host	smart-b0bc6e27-f8c9-4ffc-b5f8-b4be848c1c8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103082632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.103082632
Directory	/workspace/20.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/21.keymgr_alert_test.1748747471
Short name	T862
Test name
Test status
Simulation time	27053339 ps
CPU time	0.96 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:04 PM PDT 24
Peak memory	205488 kb
Host	smart-f528e5c5-5c68-4c5f-917e-99ce1971755e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748747471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1748747471
Directory	/workspace/21.keymgr_alert_test/latest

Test location	/workspace/coverage/default/21.keymgr_cfg_regwen.991869009
Short name	T431
Test name
Test status
Simulation time	63458924 ps
CPU time	3.1 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	214004 kb
Host	smart-47405d20-6dd1-4f44-8074-2c009e313277
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=991869009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.991869009
Directory	/workspace/21.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/21.keymgr_custom_cm.2149320412
Short name	T11
Test name
Test status
Simulation time	1048138922 ps
CPU time	3.86 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	222440 kb
Host	smart-31c25824-f746-496b-8c25-d03b9c7a4dcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2149320412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2149320412
Directory	/workspace/21.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/21.keymgr_direct_to_disabled.3201908988
Short name	T390
Test name
Test status
Simulation time	22295256 ps
CPU time	1.66 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	207628 kb
Host	smart-f51aa369-a09b-46a4-9a0b-bb74e05327a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201908988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3201908988
Directory	/workspace/21.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/21.keymgr_hwsw_invalid_input.1863557085
Short name	T96
Test name
Test status
Simulation time	60273171 ps
CPU time	3.17 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:04 PM PDT 24
Peak memory	208232 kb
Host	smart-87256428-79d2-433c-b1a4-2a61e16a5d0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863557085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1863557085
Directory	/workspace/21.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/21.keymgr_kmac_rsp_err.1230059549
Short name	T379
Test name
Test status
Simulation time	231377348 ps
CPU time	2.4 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:05 PM PDT 24
Peak memory	213976 kb
Host	smart-98f11d91-0dc2-4f80-b5c6-636ac618d79f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230059549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1230059549
Directory	/workspace/21.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/21.keymgr_lc_disable.4055421473
Short name	T874
Test name
Test status
Simulation time	58293266 ps
CPU time	2.92 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	215024 kb
Host	smart-a843171d-dbf3-4a85-ad5c-b33bb615ca96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055421473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4055421473
Directory	/workspace/21.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/21.keymgr_random.1797990092
Short name	T372
Test name
Test status
Simulation time	284077458 ps
CPU time	3.85 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	214024 kb
Host	smart-fdbaac79-bc9e-4e66-99b9-258401d50b9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797990092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1797990092
Directory	/workspace/21.keymgr_random/latest

Test location	/workspace/coverage/default/21.keymgr_sideload.803336694
Short name	T5
Test name
Test status
Simulation time	130517466 ps
CPU time	4.01 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:05 PM PDT 24
Peak memory	206504 kb
Host	smart-13fbe277-4425-43c0-8f45-2708c27eaa85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803336694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.803336694
Directory	/workspace/21.keymgr_sideload/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_aes.3658626938
Short name	T1001
Test name
Test status
Simulation time	23213367 ps
CPU time	1.88 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:03 PM PDT 24
Peak memory	206588 kb
Host	smart-6a33edd7-269c-4495-b978-47b8e9223e03
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658626938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3658626938
Directory	/workspace/21.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_kmac.2441283495
Short name	T148
Test name
Test status
Simulation time	82837338 ps
CPU time	3.97 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	208492 kb
Host	smart-6284a5eb-ba44-4da8-a88b-a4da6013f954
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441283495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2441283495
Directory	/workspace/21.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_otbn.1003656483
Short name	T909
Test name
Test status
Simulation time	128581254 ps
CPU time	3.69 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	208340 kb
Host	smart-bbc5f3e0-dbe2-4b5b-aa87-b20faff6f0d0
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003656483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1003656483
Directory	/workspace/21.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/21.keymgr_sideload_protect.2368473266
Short name	T673
Test name
Test status
Simulation time	3292295712 ps
CPU time	28.44 seconds
Started	May 25 02:15:00 PM PDT 24
Finished	May 25 02:15:29 PM PDT 24
Peak memory	208908 kb
Host	smart-1948ae18-cee3-418f-8c07-4bb48d913ae5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368473266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2368473266
Directory	/workspace/21.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/21.keymgr_smoke.2996280285
Short name	T945
Test name
Test status
Simulation time	180576609 ps
CPU time	3.82 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	207844 kb
Host	smart-3753a2a0-616c-443f-af7b-a0e5e63b04fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996280285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2996280285
Directory	/workspace/21.keymgr_smoke/latest

Test location	/workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2513112677
Short name	T668
Test name
Test status
Simulation time	149514214 ps
CPU time	2.57 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	214172 kb
Host	smart-b4424e84-8f38-470f-966e-e6a05a005a30
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513112677 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2513112677
Directory	/workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.keymgr_sync_async_fault_cross.2881485563
Short name	T808
Test name
Test status
Simulation time	678093546 ps
CPU time	4.19 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	210056 kb
Host	smart-ed26ac92-bddf-4aeb-b6f1-43647af35981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881485563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2881485563
Directory	/workspace/21.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/22.keymgr_alert_test.599311701
Short name	T727
Test name
Test status
Simulation time	19906980 ps
CPU time	0.83 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	205432 kb
Host	smart-bdb4026a-0f77-4c70-83c9-c9bb9192f2ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599311701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.599311701
Directory	/workspace/22.keymgr_alert_test/latest

Test location	/workspace/coverage/default/22.keymgr_direct_to_disabled.3760395887
Short name	T832
Test name
Test status
Simulation time	61739423 ps
CPU time	2.82 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	207080 kb
Host	smart-a183a588-31ca-41a0-ba66-d5e9a4ee3e8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760395887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3760395887
Directory	/workspace/22.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/22.keymgr_hwsw_invalid_input.2540663607
Short name	T651
Test name
Test status
Simulation time	671203285 ps
CPU time	5.82 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	213968 kb
Host	smart-820fb9a3-1353-4c24-9079-35f415654aad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540663607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2540663607
Directory	/workspace/22.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_lc_disable.930377024
Short name	T621
Test name
Test status
Simulation time	326390753 ps
CPU time	4.08 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	219828 kb
Host	smart-7a0b968e-eb18-43ed-bfc4-2d2d428cb3e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930377024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.930377024
Directory	/workspace/22.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/22.keymgr_random.812197425
Short name	T690
Test name
Test status
Simulation time	1220438102 ps
CPU time	8.1 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	209036 kb
Host	smart-f0e5f096-edae-4c26-bd4a-2de1a796e1e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812197425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.812197425
Directory	/workspace/22.keymgr_random/latest

Test location	/workspace/coverage/default/22.keymgr_sideload.2329333577
Short name	T1026
Test name
Test status
Simulation time	109080473 ps
CPU time	4.03 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	206544 kb
Host	smart-9f60bcd2-fe91-4fa6-b4a5-a28f4db33b74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329333577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2329333577
Directory	/workspace/22.keymgr_sideload/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_aes.1714329567
Short name	T748
Test name
Test status
Simulation time	912911608 ps
CPU time	11.23 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:18 PM PDT 24
Peak memory	207896 kb
Host	smart-b8f77b9d-ab9f-4eb3-9357-b5e3afd7bf47
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714329567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1714329567
Directory	/workspace/22.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_kmac.2958939689
Short name	T836
Test name
Test status
Simulation time	290439132 ps
CPU time	4.4 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:10 PM PDT 24
Peak memory	207112 kb
Host	smart-089a4d86-ca6c-45a3-9bd1-ca2342893d3a
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958939689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2958939689
Directory	/workspace/22.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_otbn.4002932969
Short name	T84
Test name
Test status
Simulation time	280105584 ps
CPU time	3.43 seconds
Started	May 25 02:15:01 PM PDT 24
Finished	May 25 02:15:05 PM PDT 24
Peak memory	206564 kb
Host	smart-95414cd3-5ed5-458d-aa3d-d4966beb2828
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002932969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4002932969
Directory	/workspace/22.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/22.keymgr_sideload_protect.376680647
Short name	T206
Test name
Test status
Simulation time	224170497 ps
CPU time	3.46 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	208744 kb
Host	smart-51fbeb41-5a22-4240-9d7c-93188a23cf9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376680647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.376680647
Directory	/workspace/22.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/22.keymgr_smoke.1829009522
Short name	T707
Test name
Test status
Simulation time	30784155 ps
CPU time	2.07 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:07 PM PDT 24
Peak memory	206412 kb
Host	smart-0d3db9b7-21a2-44c5-af19-b9e40633960f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829009522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1829009522
Directory	/workspace/22.keymgr_smoke/latest

Test location	/workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.230212928
Short name	T939
Test name
Test status
Simulation time	1258710827 ps
CPU time	7.25 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	219800 kb
Host	smart-a0fad64d-7fb0-4aaf-883b-ea6e45cfe500
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230212928 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.230212928
Directory	/workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.keymgr_sw_invalid_input.3220806378
Short name	T845
Test name
Test status
Simulation time	3733604625 ps
CPU time	22.25 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	208460 kb
Host	smart-d99c4691-09e7-4a35-a0be-bc9b9f0634f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220806378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3220806378
Directory	/workspace/22.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/22.keymgr_sync_async_fault_cross.1281070966
Short name	T608
Test name
Test status
Simulation time	68272639 ps
CPU time	1.83 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:08 PM PDT 24
Peak memory	209788 kb
Host	smart-f4bccb76-e77a-4804-b3fe-5c0623ea2cbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281070966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1281070966
Directory	/workspace/22.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/23.keymgr_alert_test.2600612393
Short name	T888
Test name
Test status
Simulation time	48484161 ps
CPU time	0.78 seconds
Started	May 25 02:15:09 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	205580 kb
Host	smart-9c5965d6-5b96-4e6c-b473-16b3b5f0adeb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600612393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2600612393
Directory	/workspace/23.keymgr_alert_test/latest

Test location	/workspace/coverage/default/23.keymgr_cfg_regwen.1887855986
Short name	T918
Test name
Test status
Simulation time	141419463 ps
CPU time	2.77 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	214828 kb
Host	smart-bfad131f-a046-4cc0-a23b-4996373f4706
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1887855986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1887855986
Directory	/workspace/23.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/23.keymgr_custom_cm.571080104
Short name	T29
Test name
Test status
Simulation time	154698958 ps
CPU time	6.22 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	221136 kb
Host	smart-bd9b268d-db99-40f2-8049-11cd706990cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571080104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.571080104
Directory	/workspace/23.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/23.keymgr_direct_to_disabled.361606514
Short name	T617
Test name
Test status
Simulation time	60231559 ps
CPU time	1.8 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:10 PM PDT 24
Peak memory	209060 kb
Host	smart-28be4c52-ed86-456d-b33e-a0b07e87370d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361606514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.361606514
Directory	/workspace/23.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/23.keymgr_hwsw_invalid_input.2672990559
Short name	T23
Test name
Test status
Simulation time	6936209916 ps
CPU time	29.44 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:36 PM PDT 24
Peak memory	209168 kb
Host	smart-7e6a6c44-9afa-4255-9c4b-16111c69804f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672990559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2672990559
Directory	/workspace/23.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_kmac_rsp_err.3683402150
Short name	T94
Test name
Test status
Simulation time	227277297 ps
CPU time	3.24 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	210400 kb
Host	smart-019b5e46-d823-4fa3-810e-065cf1bbf3b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683402150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3683402150
Directory	/workspace/23.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/23.keymgr_lc_disable.3372306829
Short name	T57
Test name
Test status
Simulation time	392558170 ps
CPU time	5.78 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	209268 kb
Host	smart-e29f4402-c89d-4513-a044-f66496d8de8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372306829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3372306829
Directory	/workspace/23.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/23.keymgr_random.1594826471
Short name	T793
Test name
Test status
Simulation time	568037565 ps
CPU time	7.87 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	207944 kb
Host	smart-0785d970-b966-49ad-8c34-97d771206061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594826471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1594826471
Directory	/workspace/23.keymgr_random/latest

Test location	/workspace/coverage/default/23.keymgr_sideload.12037600
Short name	T1020
Test name
Test status
Simulation time	83417608 ps
CPU time	3.45 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	206524 kb
Host	smart-e92d7eb1-3fee-4b7f-b9a1-e5ce23f9963f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12037600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.12037600
Directory	/workspace/23.keymgr_sideload/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_aes.589480996
Short name	T867
Test name
Test status
Simulation time	658646058 ps
CPU time	16.23 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	207960 kb
Host	smart-db73dab6-74b7-4c7e-93dd-540dafc6be48
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589480996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.589480996
Directory	/workspace/23.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_kmac.3811981281
Short name	T1048
Test name
Test status
Simulation time	877380073 ps
CPU time	9.15 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	208136 kb
Host	smart-0d8393e3-a78a-40be-a4cd-2f2dc55b66d7
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811981281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3811981281
Directory	/workspace/23.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_otbn.838643181
Short name	T770
Test name
Test status
Simulation time	552637822 ps
CPU time	10.5 seconds
Started	May 25 02:15:05 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	208464 kb
Host	smart-54870ca5-1a50-4e8b-9da6-403be594e3e7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838643181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.838643181
Directory	/workspace/23.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/23.keymgr_sideload_protect.3239706701
Short name	T572
Test name
Test status
Simulation time	50768303 ps
CPU time	2 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	215548 kb
Host	smart-a913c992-07ef-4a36-b261-24e71c505cbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239706701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3239706701
Directory	/workspace/23.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/23.keymgr_smoke.938454938
Short name	T1041
Test name
Test status
Simulation time	1349152662 ps
CPU time	20.48 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:26 PM PDT 24
Peak memory	207548 kb
Host	smart-58d19895-b2ca-49a5-8a50-096ff3b03477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938454938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.938454938
Directory	/workspace/23.keymgr_smoke/latest

Test location	/workspace/coverage/default/23.keymgr_stress_all.3050870037
Short name	T62
Test name
Test status
Simulation time	779759659 ps
CPU time	16.1 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	216560 kb
Host	smart-bfce5cd3-02cb-4966-8ebc-ed2f2d28c286
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050870037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3050870037
Directory	/workspace/23.keymgr_stress_all/latest

Test location	/workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.390531467
Short name	T723
Test name
Test status
Simulation time	154471705 ps
CPU time	6.64 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	214184 kb
Host	smart-c9441cb9-5336-4a99-8045-2bb66ecf1b58
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390531467 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.390531467
Directory	/workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.keymgr_sw_invalid_input.1504805571
Short name	T758
Test name
Test status
Simulation time	70706005 ps
CPU time	4.22 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	209664 kb
Host	smart-91e810e7-149c-4b3d-a9fc-5543e29e75a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504805571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1504805571
Directory	/workspace/23.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/23.keymgr_sync_async_fault_cross.784484218
Short name	T671
Test name
Test status
Simulation time	441976033 ps
CPU time	3.13 seconds
Started	May 25 02:15:02 PM PDT 24
Finished	May 25 02:15:06 PM PDT 24
Peak memory	210656 kb
Host	smart-c0dfa884-e88d-4e4b-b963-83f43fc88fce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784484218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.784484218
Directory	/workspace/23.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/24.keymgr_alert_test.3284355599
Short name	T885
Test name
Test status
Simulation time	50673852 ps
CPU time	0.73 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	205588 kb
Host	smart-ea496675-6227-4402-84ad-10f5af1b68d0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284355599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3284355599
Directory	/workspace/24.keymgr_alert_test/latest

Test location	/workspace/coverage/default/24.keymgr_cfg_regwen.530525971
Short name	T370
Test name
Test status
Simulation time	940264813 ps
CPU time	6.53 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	214032 kb
Host	smart-c41de763-0353-4b34-b36a-041da7e971c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=530525971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.530525971
Directory	/workspace/24.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/24.keymgr_direct_to_disabled.1006618714
Short name	T625
Test name
Test status
Simulation time	201699391 ps
CPU time	4.62 seconds
Started	May 25 02:15:09 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	214096 kb
Host	smart-42951d11-07e1-4a6f-980e-34d6570c45e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006618714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1006618714
Directory	/workspace/24.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/24.keymgr_hwsw_invalid_input.1741198628
Short name	T734
Test name
Test status
Simulation time	882138807 ps
CPU time	9.07 seconds
Started	May 25 02:15:09 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	208216 kb
Host	smart-894bb5d7-691c-4623-ace5-b2dc115be5ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741198628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1741198628
Directory	/workspace/24.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/24.keymgr_lc_disable.2894895758
Short name	T263
Test name
Test status
Simulation time	506391434 ps
CPU time	7.82 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:18 PM PDT 24
Peak memory	209764 kb
Host	smart-3a9ab728-0fb9-48d3-bffc-904604c70e83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894895758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2894895758
Directory	/workspace/24.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/24.keymgr_random.520290380
Short name	T672
Test name
Test status
Simulation time	250536628 ps
CPU time	7.56 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	206832 kb
Host	smart-cf933555-d4f6-4ab0-b36e-42841c5c9f2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520290380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.520290380
Directory	/workspace/24.keymgr_random/latest

Test location	/workspace/coverage/default/24.keymgr_sideload.2171376173
Short name	T112
Test name
Test status
Simulation time	322383527 ps
CPU time	5.78 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	207560 kb
Host	smart-15675b66-70df-45fe-926d-3d0b5894bdbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2171376173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2171376173
Directory	/workspace/24.keymgr_sideload/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_aes.281278086
Short name	T951
Test name
Test status
Simulation time	9478557649 ps
CPU time	65.45 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:16:15 PM PDT 24
Peak memory	208160 kb
Host	smart-4ac6115e-7308-45ce-8118-392b4e888eaa
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281278086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.281278086
Directory	/workspace/24.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_kmac.25316266
Short name	T731
Test name
Test status
Simulation time	133563786 ps
CPU time	2.61 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	206628 kb
Host	smart-5ed7193c-dbbb-4a3c-884d-1cfe28f4fd57
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25316266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.25316266
Directory	/workspace/24.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_otbn.1811550148
Short name	T1047
Test name
Test status
Simulation time	185477626 ps
CPU time	2.46 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	206592 kb
Host	smart-c90aed27-6ae7-41ae-943e-178a11548773
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811550148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1811550148
Directory	/workspace/24.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/24.keymgr_sideload_protect.25857266
Short name	T704
Test name
Test status
Simulation time	1482205245 ps
CPU time	7.68 seconds
Started	May 25 02:15:04 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	208936 kb
Host	smart-666f4c66-c326-40b8-8521-fbe4c51f2c08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25857266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.25857266
Directory	/workspace/24.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/24.keymgr_smoke.1671856194
Short name	T87
Test name
Test status
Simulation time	4310750083 ps
CPU time	28.87 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:38 PM PDT 24
Peak memory	207760 kb
Host	smart-c365714f-e3bf-4294-bdff-70e907b02de7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671856194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1671856194
Directory	/workspace/24.keymgr_smoke/latest

Test location	/workspace/coverage/default/24.keymgr_stress_all.4234592612
Short name	T329
Test name
Test status
Simulation time	5079595040 ps
CPU time	89.3 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:16:38 PM PDT 24
Peak memory	215568 kb
Host	smart-5ea25ecd-04e9-4518-9f59-89665ab15a7e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234592612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4234592612
Directory	/workspace/24.keymgr_stress_all/latest

Test location	/workspace/coverage/default/24.keymgr_sw_invalid_input.2156379810
Short name	T663
Test name
Test status
Simulation time	272324398 ps
CPU time	8.91 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	218088 kb
Host	smart-4ebb37bc-d6a9-4fd1-bdb0-754059146d81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156379810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2156379810
Directory	/workspace/24.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/24.keymgr_sync_async_fault_cross.202632690
Short name	T660
Test name
Test status
Simulation time	122469057 ps
CPU time	4.24 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	210208 kb
Host	smart-eb3887f8-a8d0-4d53-b55f-2b769167c728
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202632690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.202632690
Directory	/workspace/24.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/25.keymgr_alert_test.1366621411
Short name	T115
Test name
Test status
Simulation time	21455541 ps
CPU time	0.76 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	205548 kb
Host	smart-d30ea87d-2638-4bc4-b577-c33f5e74925a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366621411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1366621411
Directory	/workspace/25.keymgr_alert_test/latest

Test location	/workspace/coverage/default/25.keymgr_cfg_regwen.175651105
Short name	T416
Test name
Test status
Simulation time	23642611960 ps
CPU time	125.42 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:17:13 PM PDT 24
Peak memory	214028 kb
Host	smart-8cea4234-09e8-48a6-a328-380b885bc0ac
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=175651105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.175651105
Directory	/workspace/25.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/25.keymgr_custom_cm.3540396529
Short name	T706
Test name
Test status
Simulation time	1378216025 ps
CPU time	27.23 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	208588 kb
Host	smart-74fe4cc1-1c9e-44f4-9c5e-754d5da8c904
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540396529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3540396529
Directory	/workspace/25.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/25.keymgr_direct_to_disabled.1667437073
Short name	T947
Test name
Test status
Simulation time	69227824 ps
CPU time	3.15 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	219348 kb
Host	smart-97dd36d0-8306-4efd-8b7e-aed611d6d547
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667437073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1667437073
Directory	/workspace/25.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/25.keymgr_hwsw_invalid_input.3053001844
Short name	T91
Test name
Test status
Simulation time	245050641 ps
CPU time	6.12 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	208404 kb
Host	smart-3feebec8-8edd-4a3f-94e2-0c4fddc10167
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053001844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3053001844
Directory	/workspace/25.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_kmac_rsp_err.2396068244
Short name	T315
Test name
Test status
Simulation time	150063057 ps
CPU time	5.9 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	213896 kb
Host	smart-2401dd24-9bd9-4536-ba82-54d98f16b8ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396068244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2396068244
Directory	/workspace/25.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/25.keymgr_lc_disable.921597965
Short name	T43
Test name
Test status
Simulation time	136638256 ps
CPU time	5.08 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	210252 kb
Host	smart-a9e7a3a3-99c8-4ffa-9be2-363f620e1dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921597965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.921597965
Directory	/workspace/25.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/25.keymgr_random.767986762
Short name	T984
Test name
Test status
Simulation time	171412828 ps
CPU time	4.31 seconds
Started	May 25 02:15:08 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	208760 kb
Host	smart-b6c6de97-57a7-4b33-9789-d0b200b3800b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767986762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.767986762
Directory	/workspace/25.keymgr_random/latest

Test location	/workspace/coverage/default/25.keymgr_sideload.4237936605
Short name	T402
Test name
Test status
Simulation time	38156052 ps
CPU time	2.58 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	206576 kb
Host	smart-746ab6f6-96d1-4964-b7d9-82dde100ee93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237936605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4237936605
Directory	/workspace/25.keymgr_sideload/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_aes.4136139287
Short name	T212
Test name
Test status
Simulation time	155765405 ps
CPU time	3.95 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	208220 kb
Host	smart-74ed18e4-30b6-4223-af83-1dc88ea0fddd
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136139287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4136139287
Directory	/workspace/25.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_otbn.2511997972
Short name	T666
Test name
Test status
Simulation time	76742738 ps
CPU time	3.15 seconds
Started	May 25 02:15:06 PM PDT 24
Finished	May 25 02:15:11 PM PDT 24
Peak memory	208256 kb
Host	smart-8a4bcaff-217f-45f1-bcea-dad4b4cbbcc9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511997972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2511997972
Directory	/workspace/25.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/25.keymgr_sideload_protect.1371240694
Short name	T745
Test name
Test status
Simulation time	349673689 ps
CPU time	2.81 seconds
Started	May 25 02:15:16 PM PDT 24
Finished	May 25 02:15:20 PM PDT 24
Peak memory	217868 kb
Host	smart-e9c37ca6-0bcf-41ca-9109-e3b121c2da04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371240694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1371240694
Directory	/workspace/25.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/25.keymgr_smoke.1592854276
Short name	T18
Test name
Test status
Simulation time	636793054 ps
CPU time	7.96 seconds
Started	May 25 02:15:03 PM PDT 24
Finished	May 25 02:15:12 PM PDT 24
Peak memory	208000 kb
Host	smart-abf6aea5-36f1-438e-afd5-d52e1477625b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592854276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1592854276
Directory	/workspace/25.keymgr_smoke/latest

Test location	/workspace/coverage/default/25.keymgr_stress_all.2305385707
Short name	T1045
Test name
Test status
Simulation time	776922092 ps
CPU time	16.58 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:30 PM PDT 24
Peak memory	216328 kb
Host	smart-0db23cb9-7518-4b01-9640-2de2a6f80c61
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305385707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2305385707
Directory	/workspace/25.keymgr_stress_all/latest

Test location	/workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2241246739
Short name	T765
Test name
Test status
Simulation time	385616669 ps
CPU time	6.78 seconds
Started	May 25 02:15:15 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	222520 kb
Host	smart-2e11a24c-beb2-4959-aaa6-b58e0a684186
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241246739 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2241246739
Directory	/workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.keymgr_sw_invalid_input.1935809324
Short name	T743
Test name
Test status
Simulation time	1115420467 ps
CPU time	12.05 seconds
Started	May 25 02:15:07 PM PDT 24
Finished	May 25 02:15:21 PM PDT 24
Peak memory	207336 kb
Host	smart-14d27508-4db2-4ab4-b335-23b6bfc6fc07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935809324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1935809324
Directory	/workspace/25.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/25.keymgr_sync_async_fault_cross.1661666256
Short name	T820
Test name
Test status
Simulation time	68116004 ps
CPU time	3.02 seconds
Started	May 25 02:15:16 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	210152 kb
Host	smart-c8555171-8774-40f9-a6b5-685ae09baeec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661666256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1661666256
Directory	/workspace/25.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/26.keymgr_alert_test.3367249394
Short name	T1031
Test name
Test status
Simulation time	154909743 ps
CPU time	0.82 seconds
Started	May 25 02:15:14 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	205560 kb
Host	smart-3ef5b0a9-bae2-40ed-b884-f851cd1c8261
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367249394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3367249394
Directory	/workspace/26.keymgr_alert_test/latest

Test location	/workspace/coverage/default/26.keymgr_cfg_regwen.2749045960
Short name	T1058
Test name
Test status
Simulation time	47392245 ps
CPU time	3.29 seconds
Started	May 25 02:15:10 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	215128 kb
Host	smart-68a31c0d-8106-4e29-a49c-473f5402482d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2749045960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2749045960
Directory	/workspace/26.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/26.keymgr_direct_to_disabled.2743567704
Short name	T79
Test name
Test status
Simulation time	201374000 ps
CPU time	2.57 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:16 PM PDT 24
Peak memory	214040 kb
Host	smart-765a6c90-c208-4484-afd4-16eb3c4ded08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743567704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2743567704
Directory	/workspace/26.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/26.keymgr_hwsw_invalid_input.1719440034
Short name	T343
Test name
Test status
Simulation time	73556407 ps
CPU time	2.55 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	217948 kb
Host	smart-412497e2-4a4a-491a-bb1b-6c8d55214e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719440034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1719440034
Directory	/workspace/26.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_lc_disable.3956213773
Short name	T775
Test name
Test status
Simulation time	164956593 ps
CPU time	2.65 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	209204 kb
Host	smart-7d4c0019-d27b-44e9-beff-19afcf5e7df4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956213773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3956213773
Directory	/workspace/26.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/26.keymgr_random.1472295729
Short name	T872
Test name
Test status
Simulation time	869101530 ps
CPU time	5.49 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:18 PM PDT 24
Peak memory	207172 kb
Host	smart-27647d80-f737-440d-af3c-936ce7070366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472295729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1472295729
Directory	/workspace/26.keymgr_random/latest

Test location	/workspace/coverage/default/26.keymgr_sideload.3546450181
Short name	T716
Test name
Test status
Simulation time	26783798 ps
CPU time	2.18 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	208220 kb
Host	smart-c8aa3850-2fcc-4ca9-b12f-89bfb556f63b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546450181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3546450181
Directory	/workspace/26.keymgr_sideload/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_aes.3811434529
Short name	T715
Test name
Test status
Simulation time	187746730 ps
CPU time	4.17 seconds
Started	May 25 02:15:20 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	208436 kb
Host	smart-330bafae-721f-496d-b76f-a243ca116f4b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811434529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3811434529
Directory	/workspace/26.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_kmac.133271848
Short name	T39
Test name
Test status
Simulation time	133513136 ps
CPU time	2.88 seconds
Started	May 25 02:15:16 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	208520 kb
Host	smart-3e82e343-d457-4e1f-a857-15327d4954a9
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133271848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.133271848
Directory	/workspace/26.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_otbn.2821939133
Short name	T952
Test name
Test status
Simulation time	200655041 ps
CPU time	2.81 seconds
Started	May 25 02:15:15 PM PDT 24
Finished	May 25 02:15:18 PM PDT 24
Peak memory	206688 kb
Host	smart-1e153988-6508-446d-8ccc-47f8f92a0627
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821939133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2821939133
Directory	/workspace/26.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/26.keymgr_sideload_protect.455790747
Short name	T647
Test name
Test status
Simulation time	167667695 ps
CPU time	2.88 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	208744 kb
Host	smart-59976913-831a-45f2-ab51-e1774e7c9c56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455790747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.455790747
Directory	/workspace/26.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/26.keymgr_smoke.3144246917
Short name	T433
Test name
Test status
Simulation time	1871426049 ps
CPU time	29.47 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:49 PM PDT 24
Peak memory	207704 kb
Host	smart-89a94f75-2aa6-423c-bf32-1d2c6bb615a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144246917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3144246917
Directory	/workspace/26.keymgr_smoke/latest

Test location	/workspace/coverage/default/26.keymgr_stress_all.4071795494
Short name	T241
Test name
Test status
Simulation time	46195620139 ps
CPU time	215.74 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:18:49 PM PDT 24
Peak memory	222264 kb
Host	smart-c4b18d3e-845d-496d-ac6e-6a17bf593bb1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071795494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4071795494
Directory	/workspace/26.keymgr_stress_all/latest

Test location	/workspace/coverage/default/26.keymgr_sw_invalid_input.2866147631
Short name	T396
Test name
Test status
Simulation time	98271888 ps
CPU time	4.43 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:24 PM PDT 24
Peak memory	208184 kb
Host	smart-075ff2f6-bbec-4414-96ce-61d9f3fa4317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866147631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2866147631
Directory	/workspace/26.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/26.keymgr_sync_async_fault_cross.1677238846
Short name	T403
Test name
Test status
Simulation time	22372275 ps
CPU time	1.44 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	209572 kb
Host	smart-13d50cad-6391-4767-82b4-3126180d2c6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677238846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1677238846
Directory	/workspace/26.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/27.keymgr_alert_test.3382626584
Short name	T901
Test name
Test status
Simulation time	43460307 ps
CPU time	0.78 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	205596 kb
Host	smart-d2c1e91e-cfe9-4197-b32e-58b36ca1e647
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382626584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3382626584
Directory	/workspace/27.keymgr_alert_test/latest

Test location	/workspace/coverage/default/27.keymgr_direct_to_disabled.3110623020
Short name	T332
Test name
Test status
Simulation time	562665783 ps
CPU time	4.04 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	213980 kb
Host	smart-1ce1ba66-582c-4136-ba91-a5a6d2fdeded
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110623020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3110623020
Directory	/workspace/27.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/27.keymgr_hwsw_invalid_input.1187010739
Short name	T686
Test name
Test status
Simulation time	1089543725 ps
CPU time	4.64 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:15:29 PM PDT 24
Peak memory	208576 kb
Host	smart-886c5f14-ec20-4a4d-a244-5b951ce303c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187010739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1187010739
Directory	/workspace/27.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/27.keymgr_lc_disable.2994555515
Short name	T819
Test name
Test status
Simulation time	235267681 ps
CPU time	2.77 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	219608 kb
Host	smart-5f6b4eb5-0e77-415d-9905-887ca5d6e0f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994555515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2994555515
Directory	/workspace/27.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/27.keymgr_random.3764994441
Short name	T248
Test name
Test status
Simulation time	365820262 ps
CPU time	4.04 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	206632 kb
Host	smart-b23c57b7-1200-45bd-b682-0f9f68fee2ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764994441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3764994441
Directory	/workspace/27.keymgr_random/latest

Test location	/workspace/coverage/default/27.keymgr_sideload.382992867
Short name	T565
Test name
Test status
Simulation time	2153919758 ps
CPU time	19.81 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	208664 kb
Host	smart-039e9b10-d0be-40c0-8412-fedbfdae19cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382992867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.382992867
Directory	/workspace/27.keymgr_sideload/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_aes.3216000501
Short name	T211
Test name
Test status
Simulation time	456355064 ps
CPU time	6.34 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:18 PM PDT 24
Peak memory	207472 kb
Host	smart-173d2284-e661-41e8-bf80-3d603924a9a5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216000501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3216000501
Directory	/workspace/27.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_kmac.1869076606
Short name	T605
Test name
Test status
Simulation time	51532807 ps
CPU time	2.96 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	206556 kb
Host	smart-d4ed3249-6fa3-4ae3-8877-f9ab99abeba7
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869076606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1869076606
Directory	/workspace/27.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_otbn.424484452
Short name	T351
Test name
Test status
Simulation time	42534858 ps
CPU time	2.34 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:14 PM PDT 24
Peak memory	206464 kb
Host	smart-aed44002-76da-458a-9e40-bb64b8408298
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424484452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.424484452
Directory	/workspace/27.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/27.keymgr_sideload_protect.3400045091
Short name	T892
Test name
Test status
Simulation time	82822316 ps
CPU time	3.37 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	209824 kb
Host	smart-47979c0a-e1d1-4743-a841-1860e0ca595c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400045091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3400045091
Directory	/workspace/27.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/27.keymgr_smoke.1688479971
Short name	T1027
Test name
Test status
Simulation time	380408454 ps
CPU time	3.04 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	206488 kb
Host	smart-2939fb4d-9fff-4f9a-829d-5f70fc6ad8f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688479971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1688479971
Directory	/workspace/27.keymgr_smoke/latest

Test location	/workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3198678855
Short name	T227
Test name
Test status
Simulation time	234527710 ps
CPU time	8.97 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:15:27 PM PDT 24
Peak memory	222408 kb
Host	smart-feff06d5-11fd-4006-8586-c94e135ac12a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198678855 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3198678855
Directory	/workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.keymgr_sw_invalid_input.1262497507
Short name	T304
Test name
Test status
Simulation time	498512345 ps
CPU time	6.49 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:20 PM PDT 24
Peak memory	214000 kb
Host	smart-4b6a305f-292d-4bc6-b5ce-4a8ad55dc920
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262497507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1262497507
Directory	/workspace/27.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/27.keymgr_sync_async_fault_cross.1606443810
Short name	T579
Test name
Test status
Simulation time	255870909 ps
CPU time	2.1 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	209920 kb
Host	smart-4a6a72b9-79b7-4f46-b471-9f9f7208f62e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606443810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1606443810
Directory	/workspace/27.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/28.keymgr_alert_test.666793524
Short name	T683
Test name
Test status
Simulation time	14446338 ps
CPU time	0.76 seconds
Started	May 25 02:15:20 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	205592 kb
Host	smart-42cf9f23-45e5-4547-8e99-4636fe16a74e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666793524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.666793524
Directory	/workspace/28.keymgr_alert_test/latest

Test location	/workspace/coverage/default/28.keymgr_custom_cm.23231629
Short name	T67
Test name
Test status
Simulation time	109434336 ps
CPU time	4.59 seconds
Started	May 25 02:15:27 PM PDT 24
Finished	May 25 02:15:32 PM PDT 24
Peak memory	221940 kb
Host	smart-35c4cddc-e4e2-430a-a932-9628bc850b39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23231629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.23231629
Directory	/workspace/28.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/28.keymgr_direct_to_disabled.1724343080
Short name	T859
Test name
Test status
Simulation time	367652053 ps
CPU time	2.7 seconds
Started	May 25 02:15:11 PM PDT 24
Finished	May 25 02:15:15 PM PDT 24
Peak memory	207324 kb
Host	smart-5a5ad675-0ce2-46c8-a4c4-92b62c9166a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724343080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1724343080
Directory	/workspace/28.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/28.keymgr_kmac_rsp_err.3580695009
Short name	T35
Test name
Test status
Simulation time	1652210877 ps
CPU time	7.01 seconds
Started	May 25 02:15:20 PM PDT 24
Finished	May 25 02:15:28 PM PDT 24
Peak memory	222040 kb
Host	smart-9ddffda9-3e2c-490c-96f8-b9b9f42044ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580695009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3580695009
Directory	/workspace/28.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/28.keymgr_lc_disable.2733926246
Short name	T231
Test name
Test status
Simulation time	166333209 ps
CPU time	4.09 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	216612 kb
Host	smart-04b765a6-2fe0-4fd0-a1cf-2e8d50c1d7a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733926246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2733926246
Directory	/workspace/28.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/28.keymgr_random.4081208262
Short name	T607
Test name
Test status
Simulation time	325548520 ps
CPU time	3.89 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:23 PM PDT 24
Peak memory	206992 kb
Host	smart-a19b1096-30c8-4307-9bb4-9fd2c808039b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081208262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4081208262
Directory	/workspace/28.keymgr_random/latest

Test location	/workspace/coverage/default/28.keymgr_sideload.2753395785
Short name	T310
Test name
Test status
Simulation time	165167926 ps
CPU time	5.62 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:26 PM PDT 24
Peak memory	208592 kb
Host	smart-ab56765d-7e79-4e7a-9370-a1213aa9c229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2753395785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2753395785
Directory	/workspace/28.keymgr_sideload/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_aes.3510077602
Short name	T610
Test name
Test status
Simulation time	378112125 ps
CPU time	3.82 seconds
Started	May 25 02:15:15 PM PDT 24
Finished	May 25 02:15:19 PM PDT 24
Peak memory	208792 kb
Host	smart-be7c94f9-9199-47ce-9d6b-e7f0f7163069
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510077602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3510077602
Directory	/workspace/28.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_kmac.1623245738
Short name	T325
Test name
Test status
Simulation time	1033029608 ps
CPU time	8.04 seconds
Started	May 25 02:15:12 PM PDT 24
Finished	May 25 02:15:21 PM PDT 24
Peak memory	208404 kb
Host	smart-4ced7788-e728-42c7-a58f-7d3dd0731e98
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623245738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1623245738
Directory	/workspace/28.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_otbn.1501595811
Short name	T401
Test name
Test status
Simulation time	36167508 ps
CPU time	2.47 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:15:20 PM PDT 24
Peak memory	208264 kb
Host	smart-602a9639-4ddc-4487-914b-1ec3e115d8f9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501595811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1501595811
Directory	/workspace/28.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/28.keymgr_sideload_protect.1619311538
Short name	T1018
Test name
Test status
Simulation time	27376833 ps
CPU time	2.02 seconds
Started	May 25 02:15:21 PM PDT 24
Finished	May 25 02:15:24 PM PDT 24
Peak memory	209648 kb
Host	smart-efbc8fd7-ddcd-4bec-b193-21c8e44f22f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619311538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1619311538
Directory	/workspace/28.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/28.keymgr_smoke.1868660914
Short name	T994
Test name
Test status
Simulation time	1407597654 ps
CPU time	29.05 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:48 PM PDT 24
Peak memory	207752 kb
Host	smart-d1e535f2-344a-453a-96f6-f5aa28fc5a66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868660914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1868660914
Directory	/workspace/28.keymgr_smoke/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all.2908879615
Short name	T362
Test name
Test status
Simulation time	2598084444 ps
CPU time	48.47 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	220400 kb
Host	smart-c2f9bffd-9487-42d4-9667-70cfe68b61c4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908879615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2908879615
Directory	/workspace/28.keymgr_stress_all/latest

Test location	/workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2332794568
Short name	T243
Test name
Test status
Simulation time	781511197 ps
CPU time	13.94 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	222004 kb
Host	smart-71742d2f-f70d-4fe9-9320-f40b9d45ac8c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332794568 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2332794568
Directory	/workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.keymgr_sw_invalid_input.1176375693
Short name	T350
Test name
Test status
Simulation time	643050098 ps
CPU time	6.51 seconds
Started	May 25 02:15:17 PM PDT 24
Finished	May 25 02:15:24 PM PDT 24
Peak memory	209428 kb
Host	smart-42a72e5a-b25b-4321-ade2-20aee09668c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176375693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1176375693
Directory	/workspace/28.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/28.keymgr_sync_async_fault_cross.1473696422
Short name	T1056
Test name
Test status
Simulation time	1038624053 ps
CPU time	9.41 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:15:33 PM PDT 24
Peak memory	210656 kb
Host	smart-8287dca8-ebe2-4ba2-a698-b8d6a6f29229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473696422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1473696422
Directory	/workspace/28.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/29.keymgr_alert_test.1369929521
Short name	T1016
Test name
Test status
Simulation time	48805065 ps
CPU time	0.79 seconds
Started	May 25 02:15:24 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	205560 kb
Host	smart-e2dd821c-c644-4251-9c36-c1c26d5b4258
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369929521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1369929521
Directory	/workspace/29.keymgr_alert_test/latest

Test location	/workspace/coverage/default/29.keymgr_cfg_regwen.2067849831
Short name	T409
Test name
Test status
Simulation time	67642960 ps
CPU time	4.26 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:27 PM PDT 24
Peak memory	214236 kb
Host	smart-5ff47b89-bba1-4852-a5d7-247409a35bfc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2067849831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2067849831
Directory	/workspace/29.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/29.keymgr_custom_cm.1034714023
Short name	T771
Test name
Test status
Simulation time	48372063 ps
CPU time	2.18 seconds
Started	May 25 02:15:27 PM PDT 24
Finished	May 25 02:15:30 PM PDT 24
Peak memory	214332 kb
Host	smart-98c67a64-669d-418f-b863-05dc234227b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034714023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1034714023
Directory	/workspace/29.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/29.keymgr_direct_to_disabled.833114649
Short name	T373
Test name
Test status
Simulation time	110017488 ps
CPU time	2.49 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:22 PM PDT 24
Peak memory	222200 kb
Host	smart-cd4ec175-4df2-4aed-81f6-7578dffc06bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833114649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.833114649
Directory	/workspace/29.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/29.keymgr_hwsw_invalid_input.486065780
Short name	T89
Test name
Test status
Simulation time	882962705 ps
CPU time	6.13 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	214008 kb
Host	smart-68577e79-edcd-41d4-ae64-4b3a485eef70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486065780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.486065780
Directory	/workspace/29.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/29.keymgr_kmac_rsp_err.3772745526
Short name	T392
Test name
Test status
Simulation time	347913703 ps
CPU time	8.74 seconds
Started	May 25 02:15:18 PM PDT 24
Finished	May 25 02:15:28 PM PDT 24
Peak memory	213968 kb
Host	smart-2016a548-0c69-479c-8c25-10a3f07190de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772745526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3772745526
Directory	/workspace/29.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/29.keymgr_lc_disable.971679625
Short name	T979
Test name
Test status
Simulation time	185127661 ps
CPU time	5.03 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:25 PM PDT 24
Peak memory	207956 kb
Host	smart-d26622d1-6061-4b27-8459-6c0f94e6e791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971679625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.971679625
Directory	/workspace/29.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/29.keymgr_random.234290726
Short name	T964
Test name
Test status
Simulation time	595240176 ps
CPU time	7.92 seconds
Started	May 25 02:15:24 PM PDT 24
Finished	May 25 02:15:33 PM PDT 24
Peak memory	209512 kb
Host	smart-9fa907dc-6114-4f80-9f2d-9f583472bbb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234290726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.234290726
Directory	/workspace/29.keymgr_random/latest

Test location	/workspace/coverage/default/29.keymgr_sideload.3674293277
Short name	T784
Test name
Test status
Simulation time	310325286 ps
CPU time	6.08 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:20 PM PDT 24
Peak memory	208172 kb
Host	smart-a1471e20-838e-4192-b27a-76bb9793f085
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3674293277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3674293277
Directory	/workspace/29.keymgr_sideload/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_aes.2567583736
Short name	T934
Test name
Test status
Simulation time	206576009 ps
CPU time	5.53 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:28 PM PDT 24
Peak memory	208336 kb
Host	smart-7dc35c27-5170-46e8-a836-6e5aa59e9a0b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567583736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2567583736
Directory	/workspace/29.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_kmac.1893685384
Short name	T334
Test name
Test status
Simulation time	3984671646 ps
CPU time	30.35 seconds
Started	May 25 02:15:24 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	208604 kb
Host	smart-2c2f62b6-d814-4a88-8d01-04e01e4c7429
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893685384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1893685384
Directory	/workspace/29.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_otbn.2661073035
Short name	T705
Test name
Test status
Simulation time	64756969 ps
CPU time	3.15 seconds
Started	May 25 02:15:13 PM PDT 24
Finished	May 25 02:15:17 PM PDT 24
Peak memory	207180 kb
Host	smart-96e385f2-3e1f-4dbd-aac8-f3be79247bdb
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661073035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2661073035
Directory	/workspace/29.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/29.keymgr_sideload_protect.4252477984
Short name	T997
Test name
Test status
Simulation time	327538334 ps
CPU time	3.95 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:27 PM PDT 24
Peak memory	209692 kb
Host	smart-60a5ffa4-95a5-45d8-8b5d-b2d85115b900
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252477984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4252477984
Directory	/workspace/29.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/29.keymgr_smoke.462717371
Short name	T656
Test name
Test status
Simulation time	100387605 ps
CPU time	3.9 seconds
Started	May 25 02:15:19 PM PDT 24
Finished	May 25 02:15:24 PM PDT 24
Peak memory	206508 kb
Host	smart-c074210b-d950-4f71-bbba-5137b49b79f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462717371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.462717371
Directory	/workspace/29.keymgr_smoke/latest

Test location	/workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3895482615
Short name	T783
Test name
Test status
Simulation time	227385372 ps
CPU time	10.34 seconds
Started	May 25 02:15:20 PM PDT 24
Finished	May 25 02:15:31 PM PDT 24
Peak memory	222276 kb
Host	smart-a4de192a-6d4e-4ddb-8210-f07fabd042ba
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895482615 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3895482615
Directory	/workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.keymgr_sw_invalid_input.1377005752
Short name	T290
Test name
Test status
Simulation time	659911935 ps
CPU time	17.96 seconds
Started	May 25 02:15:21 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	207572 kb
Host	smart-e749980e-1bd8-4ec7-bdb8-fffd3668c524
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377005752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1377005752
Directory	/workspace/29.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/29.keymgr_sync_async_fault_cross.3712665623
Short name	T1015
Test name
Test status
Simulation time	487241679 ps
CPU time	2.62 seconds
Started	May 25 02:15:26 PM PDT 24
Finished	May 25 02:15:29 PM PDT 24
Peak memory	210108 kb
Host	smart-58ee0c7b-8fe7-461a-b42e-481353379d69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712665623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3712665623
Directory	/workspace/29.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/3.keymgr_alert_test.667141336
Short name	T868
Test name
Test status
Simulation time	17784960 ps
CPU time	0.7 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	204972 kb
Host	smart-d7429997-2d2b-4555-be48-94e3def26674
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667141336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.667141336
Directory	/workspace/3.keymgr_alert_test/latest

Test location	/workspace/coverage/default/3.keymgr_cfg_regwen.1007302093
Short name	T272
Test name
Test status
Simulation time	288079728 ps
CPU time	2.98 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:06 PM PDT 24
Peak memory	214048 kb
Host	smart-d10cf5dc-eb67-479e-b89d-3c63c65e7419
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1007302093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1007302093
Directory	/workspace/3.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/3.keymgr_direct_to_disabled.2615486864
Short name	T789
Test name
Test status
Simulation time	304492858 ps
CPU time	2.95 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	208412 kb
Host	smart-a383a24f-6ef4-438e-9f7f-2e61a00e2bb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615486864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2615486864
Directory	/workspace/3.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/3.keymgr_hwsw_invalid_input.2567161811
Short name	T280
Test name
Test status
Simulation time	143567859 ps
CPU time	5.28 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:02 PM PDT 24
Peak memory	219860 kb
Host	smart-fb1a1074-92e7-4e93-9f03-75b7cd114de7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567161811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2567161811
Directory	/workspace/3.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_lc_disable.3936444096
Short name	T363
Test name
Test status
Simulation time	286510436 ps
CPU time	4.54 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:14:02 PM PDT 24
Peak memory	219572 kb
Host	smart-5f3d5c0d-703f-4675-9f7b-6ce39665076a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936444096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3936444096
Directory	/workspace/3.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/3.keymgr_random.1859193011
Short name	T423
Test name
Test status
Simulation time	693259890 ps
CPU time	10.23 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	207560 kb
Host	smart-13a58d85-6f9d-46bd-aec0-cd1adec24050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859193011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1859193011
Directory	/workspace/3.keymgr_random/latest

Test location	/workspace/coverage/default/3.keymgr_sec_cm.2297256571
Short name	T108
Test name
Test status
Simulation time	1419279410 ps
CPU time	26.05 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	235740 kb
Host	smart-1c39c2d0-f4af-49ff-9a91-f7c6130ff31e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297256571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2297256571
Directory	/workspace/3.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/3.keymgr_sideload.1045092529
Short name	T958
Test name
Test status
Simulation time	102618286 ps
CPU time	2.91 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:56 PM PDT 24
Peak memory	208244 kb
Host	smart-185dc3b3-d420-4fcd-a8c9-9b2e64281140
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045092529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1045092529
Directory	/workspace/3.keymgr_sideload/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_aes.3215193758
Short name	T971
Test name
Test status
Simulation time	304263281 ps
CPU time	3.28 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	207188 kb
Host	smart-9b37f3f4-7b81-4fc1-b88f-46c692d91799
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215193758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3215193758
Directory	/workspace/3.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_kmac.2413492972
Short name	T735
Test name
Test status
Simulation time	92572509 ps
CPU time	1.91 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	208192 kb
Host	smart-27067f88-0363-4439-aac7-3d8b8ed53131
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413492972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2413492972
Directory	/workspace/3.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_otbn.3093902540
Short name	T1038
Test name
Test status
Simulation time	105963488 ps
CPU time	3.19 seconds
Started	May 25 02:14:01 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	206624 kb
Host	smart-fe0c1ab7-cbd9-4a7a-8f66-358b304bc6a5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093902540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3093902540
Directory	/workspace/3.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/3.keymgr_sideload_protect.2532795682
Short name	T110
Test name
Test status
Simulation time	166990468 ps
CPU time	2.82 seconds
Started	May 25 02:14:01 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	209516 kb
Host	smart-f41344fa-d126-42c5-80dd-c467b8b7cbef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532795682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2532795682
Directory	/workspace/3.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/3.keymgr_smoke.3330813161
Short name	T589
Test name
Test status
Simulation time	867419250 ps
CPU time	5.3 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	206408 kb
Host	smart-06b23113-bbad-419c-b006-359cecfe22f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330813161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3330813161
Directory	/workspace/3.keymgr_smoke/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all.2968496597
Short name	T285
Test name
Test status
Simulation time	285932233 ps
CPU time	13.26 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	222132 kb
Host	smart-4d2f0dcb-f6c9-46d0-87e5-7e03ced632af
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968496597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2968496597
Directory	/workspace/3.keymgr_stress_all/latest

Test location	/workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1311134231
Short name	T781
Test name
Test status
Simulation time	282047281 ps
CPU time	8.99 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:10 PM PDT 24
Peak memory	221588 kb
Host	smart-ba99f104-e2d9-4c57-873c-f299feabe8bc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311134231 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1311134231
Directory	/workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.keymgr_sw_invalid_input.1625404082
Short name	T848
Test name
Test status
Simulation time	530406579 ps
CPU time	5.39 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	213964 kb
Host	smart-00ec46c8-6d7b-4599-b0ed-d2aeded51d7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625404082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1625404082
Directory	/workspace/3.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/3.keymgr_sync_async_fault_cross.3499793871
Short name	T406
Test name
Test status
Simulation time	806290085 ps
CPU time	7.37 seconds
Started	May 25 02:14:03 PM PDT 24
Finished	May 25 02:14:11 PM PDT 24
Peak memory	209960 kb
Host	smart-551c75ea-24ae-4d7c-bfa2-a8ea8f7f85df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499793871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3499793871
Directory	/workspace/3.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/30.keymgr_alert_test.3242238528
Short name	T982
Test name
Test status
Simulation time	22499322 ps
CPU time	0.8 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	205604 kb
Host	smart-ec072a59-ada9-42d4-90cf-8ec75b19a442
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242238528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3242238528
Directory	/workspace/30.keymgr_alert_test/latest

Test location	/workspace/coverage/default/30.keymgr_custom_cm.4052028173
Short name	T361
Test name
Test status
Simulation time	63037188 ps
CPU time	3.35 seconds
Started	May 25 02:15:30 PM PDT 24
Finished	May 25 02:15:34 PM PDT 24
Peak memory	214296 kb
Host	smart-29b0b876-cfe1-4519-8ab7-22620c3ae399
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052028173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4052028173
Directory	/workspace/30.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/30.keymgr_direct_to_disabled.4054338263
Short name	T914
Test name
Test status
Simulation time	1052446521 ps
CPU time	5.78 seconds
Started	May 25 02:15:25 PM PDT 24
Finished	May 25 02:15:31 PM PDT 24
Peak memory	218008 kb
Host	smart-6c681f5b-56e4-4072-b277-0b6f1513a7b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054338263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4054338263
Directory	/workspace/30.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/30.keymgr_hwsw_invalid_input.394889948
Short name	T395
Test name
Test status
Simulation time	89622037 ps
CPU time	3.55 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:26 PM PDT 24
Peak memory	208344 kb
Host	smart-f77bef34-d065-43f0-9fd7-d7aa027d1df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394889948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.394889948
Directory	/workspace/30.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_random.3643429236
Short name	T345
Test name
Test status
Simulation time	2278102760 ps
CPU time	5.15 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:15:34 PM PDT 24
Peak memory	207352 kb
Host	smart-950b565b-bf57-417e-bce0-3ea095566111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643429236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3643429236
Directory	/workspace/30.keymgr_random/latest

Test location	/workspace/coverage/default/30.keymgr_sideload.550206663
Short name	T772
Test name
Test status
Simulation time	1028564540 ps
CPU time	31.36 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:16:00 PM PDT 24
Peak memory	208652 kb
Host	smart-2601ad09-69de-4fef-bc57-a161c6a6c80c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550206663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.550206663
Directory	/workspace/30.keymgr_sideload/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_aes.1204656546
Short name	T932
Test name
Test status
Simulation time	198494478 ps
CPU time	5.8 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:15:35 PM PDT 24
Peak memory	207612 kb
Host	smart-fb70a4be-ddc9-4d7d-876e-dcd8f22489a3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204656546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1204656546
Directory	/workspace/30.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_kmac.2343595211
Short name	T1024
Test name
Test status
Simulation time	358674655 ps
CPU time	5.85 seconds
Started	May 25 02:15:32 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	208496 kb
Host	smart-2402778f-d383-45e0-8ddb-5b305b64c9de
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343595211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2343595211
Directory	/workspace/30.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_otbn.3044329349
Short name	T83
Test name
Test status
Simulation time	108788330 ps
CPU time	1.97 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:15:31 PM PDT 24
Peak memory	208324 kb
Host	smart-50ce4459-1572-4d9f-9e91-4b461b322388
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044329349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3044329349
Directory	/workspace/30.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/30.keymgr_sideload_protect.3753892749
Short name	T213
Test name
Test status
Simulation time	67497250 ps
CPU time	3.18 seconds
Started	May 25 02:15:33 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	209288 kb
Host	smart-2e98b5cb-7987-43bd-b5ef-c73742ef4dd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753892749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3753892749
Directory	/workspace/30.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/30.keymgr_smoke.46138867
Short name	T925
Test name
Test status
Simulation time	95412590 ps
CPU time	3.2 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	206516 kb
Host	smart-924d68db-11d9-4f90-a2b3-adf11f2055ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46138867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.46138867
Directory	/workspace/30.keymgr_smoke/latest

Test location	/workspace/coverage/default/30.keymgr_stress_all.68729876
Short name	T301
Test name
Test status
Simulation time	12509152575 ps
CPU time	174.02 seconds
Started	May 25 02:15:27 PM PDT 24
Finished	May 25 02:18:21 PM PDT 24
Peak memory	217520 kb
Host	smart-01203ec7-83e3-49c3-a19e-17844f6c7872
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68729876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.68729876
Directory	/workspace/30.keymgr_stress_all/latest

Test location	/workspace/coverage/default/30.keymgr_sw_invalid_input.95862392
Short name	T804
Test name
Test status
Simulation time	91827761 ps
CPU time	3.84 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	207640 kb
Host	smart-5a8ba687-2f88-4dd5-955e-07a2f327e646
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95862392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.95862392
Directory	/workspace/30.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/30.keymgr_sync_async_fault_cross.4281485964
Short name	T920
Test name
Test status
Simulation time	61661488 ps
CPU time	1.82 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	209468 kb
Host	smart-48ae999a-b488-4046-9795-63e9e057dbf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281485964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4281485964
Directory	/workspace/30.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/31.keymgr_alert_test.824503763
Short name	T871
Test name
Test status
Simulation time	62442470 ps
CPU time	0.9 seconds
Started	May 25 02:15:29 PM PDT 24
Finished	May 25 02:15:31 PM PDT 24
Peak memory	205772 kb
Host	smart-2493dcd0-8dfd-4a4b-b5ee-2ae1b870cfe9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824503763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.824503763
Directory	/workspace/31.keymgr_alert_test/latest

Test location	/workspace/coverage/default/31.keymgr_direct_to_disabled.2252203806
Short name	T368
Test name
Test status
Simulation time	341149327 ps
CPU time	3.32 seconds
Started	May 25 02:15:32 PM PDT 24
Finished	May 25 02:15:36 PM PDT 24
Peak memory	208848 kb
Host	smart-dabb2ce1-8bf0-4281-a03c-2bada33aa32e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252203806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2252203806
Directory	/workspace/31.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/31.keymgr_hwsw_invalid_input.2362844202
Short name	T974
Test name
Test status
Simulation time	1929317791 ps
CPU time	4.18 seconds
Started	May 25 02:16:22 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	206940 kb
Host	smart-c446adc2-cf9a-402f-9a41-89cb56656b2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362844202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2362844202
Directory	/workspace/31.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_kmac_rsp_err.4016893120
Short name	T277
Test name
Test status
Simulation time	372239276 ps
CPU time	6.08 seconds
Started	May 25 02:15:32 PM PDT 24
Finished	May 25 02:15:38 PM PDT 24
Peak memory	213992 kb
Host	smart-f4db6dab-1a9e-404d-b33e-778d01be1de8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016893120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.4016893120
Directory	/workspace/31.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/31.keymgr_lc_disable.714637487
Short name	T224
Test name
Test status
Simulation time	169305916 ps
CPU time	2.46 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:15:30 PM PDT 24
Peak memory	214100 kb
Host	smart-c783f046-87b8-41d4-b20d-b0c4e1e8ce29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714637487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.714637487
Directory	/workspace/31.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/31.keymgr_random.3711042202
Short name	T609
Test name
Test status
Simulation time	114541425 ps
CPU time	4.97 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	210212 kb
Host	smart-f0ad6dca-eff7-4e8e-9f08-68882f74cbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711042202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3711042202
Directory	/workspace/31.keymgr_random/latest

Test location	/workspace/coverage/default/31.keymgr_sideload.3456893433
Short name	T294
Test name
Test status
Simulation time	123512803 ps
CPU time	4.64 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	206660 kb
Host	smart-f19d4e5a-fed0-412d-a128-f139f29f934d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456893433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3456893433
Directory	/workspace/31.keymgr_sideload/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_aes.3629067457
Short name	T1063
Test name
Test status
Simulation time	500478166 ps
CPU time	2.24 seconds
Started	May 25 02:15:30 PM PDT 24
Finished	May 25 02:15:33 PM PDT 24
Peak memory	206572 kb
Host	smart-584825ee-2808-4033-86f9-63be69aeec2c
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629067457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3629067457
Directory	/workspace/31.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_kmac.332040437
Short name	T713
Test name
Test status
Simulation time	309159134 ps
CPU time	8.47 seconds
Started	May 25 02:15:23 PM PDT 24
Finished	May 25 02:15:32 PM PDT 24
Peak memory	208476 kb
Host	smart-47f83f63-70a9-4679-81fe-33295e29226a
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332040437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.332040437
Directory	/workspace/31.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_otbn.209105753
Short name	T908
Test name
Test status
Simulation time	28474056 ps
CPU time	2.01 seconds
Started	May 25 02:15:29 PM PDT 24
Finished	May 25 02:15:32 PM PDT 24
Peak memory	208396 kb
Host	smart-64dd94b6-4312-4a0c-bc8d-329c3f59b1b5
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209105753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.209105753
Directory	/workspace/31.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/31.keymgr_sideload_protect.1401777920
Short name	T307
Test name
Test status
Simulation time	326488339 ps
CPU time	4.22 seconds
Started	May 25 02:15:30 PM PDT 24
Finished	May 25 02:15:34 PM PDT 24
Peak memory	213976 kb
Host	smart-d856177e-576b-4fd5-9f52-ea99726c70fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401777920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1401777920
Directory	/workspace/31.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/31.keymgr_smoke.1615758221
Short name	T1057
Test name
Test status
Simulation time	21463807 ps
CPU time	1.58 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	206596 kb
Host	smart-da23f255-11a5-45d7-8245-f5e3d766143b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615758221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1615758221
Directory	/workspace/31.keymgr_smoke/latest

Test location	/workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.282440441
Short name	T750
Test name
Test status
Simulation time	1625629847 ps
CPU time	6.11 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	222376 kb
Host	smart-36211f03-b8af-4df0-94cf-6ccfd1e2990a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282440441 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.282440441
Directory	/workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.keymgr_sw_invalid_input.244387330
Short name	T6
Test name
Test status
Simulation time	1587265085 ps
CPU time	10.1 seconds
Started	May 25 02:15:33 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	207284 kb
Host	smart-c16434b9-f6e1-4cd1-aa59-a7351981e872
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244387330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.244387330
Directory	/workspace/31.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/31.keymgr_sync_async_fault_cross.2958533559
Short name	T17
Test name
Test status
Simulation time	129062349 ps
CPU time	2.63 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	209556 kb
Host	smart-60c70c90-45d8-40e7-b05c-c2cb30357a0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958533559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2958533559
Directory	/workspace/31.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/32.keymgr_alert_test.2860485227
Short name	T712
Test name
Test status
Simulation time	10565932 ps
CPU time	0.68 seconds
Started	May 25 02:15:39 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	205488 kb
Host	smart-d085bca4-9bcf-4201-8b3b-48482e43c731
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860485227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2860485227
Directory	/workspace/32.keymgr_alert_test/latest

Test location	/workspace/coverage/default/32.keymgr_direct_to_disabled.2492694782
Short name	T1012
Test name
Test status
Simulation time	36285307 ps
CPU time	2.1 seconds
Started	May 25 02:15:24 PM PDT 24
Finished	May 25 02:15:27 PM PDT 24
Peak memory	207500 kb
Host	smart-e0ce606b-c6a4-4bf2-b793-9f2124163309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492694782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2492694782
Directory	/workspace/32.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/32.keymgr_hwsw_invalid_input.1417679670
Short name	T95
Test name
Test status
Simulation time	476184276 ps
CPU time	5.61 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:45 PM PDT 24
Peak memory	219892 kb
Host	smart-53f02b70-3638-4591-a9e0-ef791b47ff15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417679670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1417679670
Directory	/workspace/32.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_lc_disable.108383836
Short name	T42
Test name
Test status
Simulation time	164525357 ps
CPU time	3.88 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	209460 kb
Host	smart-b3033a0b-9506-41ed-8389-f4d6ee44ba3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108383836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.108383836
Directory	/workspace/32.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/32.keymgr_random.394070734
Short name	T1035
Test name
Test status
Simulation time	1698692964 ps
CPU time	8.76 seconds
Started	May 25 02:15:29 PM PDT 24
Finished	May 25 02:15:38 PM PDT 24
Peak memory	209540 kb
Host	smart-27eae3e7-535d-4dc1-8e88-7a94eb86cbc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394070734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.394070734
Directory	/workspace/32.keymgr_random/latest

Test location	/workspace/coverage/default/32.keymgr_sideload.3423339384
Short name	T322
Test name
Test status
Simulation time	183925734 ps
CPU time	4.62 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	206452 kb
Host	smart-ffa71b82-fd94-404a-be43-21b6f01c7b03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423339384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3423339384
Directory	/workspace/32.keymgr_sideload/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_aes.2107580663
Short name	T902
Test name
Test status
Simulation time	1130988758 ps
CPU time	7.78 seconds
Started	May 25 02:15:22 PM PDT 24
Finished	May 25 02:15:30 PM PDT 24
Peak memory	207660 kb
Host	smart-80e95c55-0aa1-45b9-9312-8439a47895ca
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107580663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2107580663
Directory	/workspace/32.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_kmac.4289544997
Short name	T627
Test name
Test status
Simulation time	1014221743 ps
CPU time	32.67 seconds
Started	May 25 02:15:29 PM PDT 24
Finished	May 25 02:16:02 PM PDT 24
Peak memory	208032 kb
Host	smart-e5415177-ce4a-46bf-adc2-18330a98d069
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289544997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.4289544997
Directory	/workspace/32.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_otbn.545745151
Short name	T283
Test name
Test status
Simulation time	232999730 ps
CPU time	6.11 seconds
Started	May 25 02:15:30 PM PDT 24
Finished	May 25 02:15:36 PM PDT 24
Peak memory	206692 kb
Host	smart-1097d375-cb44-4255-8735-40aa38d08c41
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545745151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.545745151
Directory	/workspace/32.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/32.keymgr_sideload_protect.787136725
Short name	T677
Test name
Test status
Simulation time	507460751 ps
CPU time	3.1 seconds
Started	May 25 02:15:33 PM PDT 24
Finished	May 25 02:15:37 PM PDT 24
Peak memory	218124 kb
Host	smart-68dc4f40-9624-4010-b110-7847e1aeff8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787136725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.787136725
Directory	/workspace/32.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/32.keymgr_smoke.3080962600
Short name	T802
Test name
Test status
Simulation time	135379494 ps
CPU time	4.36 seconds
Started	May 25 02:15:28 PM PDT 24
Finished	May 25 02:15:33 PM PDT 24
Peak memory	206888 kb
Host	smart-f3bf2912-3f9a-4d4e-86c8-5d86f300a679
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080962600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3080962600
Directory	/workspace/32.keymgr_smoke/latest

Test location	/workspace/coverage/default/32.keymgr_stress_all.106308310
Short name	T76
Test name
Test status
Simulation time	1287143050 ps
CPU time	26.58 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	215804 kb
Host	smart-18bf4faa-ea92-4628-835f-498c3756e818
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106308310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.106308310
Directory	/workspace/32.keymgr_stress_all/latest

Test location	/workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2774026394
Short name	T864
Test name
Test status
Simulation time	202715340 ps
CPU time	8.75 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:47 PM PDT 24
Peak memory	220316 kb
Host	smart-6630b14c-73e2-42e4-bc81-798361eace9c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774026394 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2774026394
Directory	/workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.keymgr_sw_invalid_input.2960086853
Short name	T880
Test name
Test status
Simulation time	958117619 ps
CPU time	11.51 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:51 PM PDT 24
Peak memory	218136 kb
Host	smart-95bf0183-a84d-4b56-8f4c-02c82d0e9798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960086853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2960086853
Directory	/workspace/32.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/32.keymgr_sync_async_fault_cross.2788042182
Short name	T976
Test name
Test status
Simulation time	44434128 ps
CPU time	1.85 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	209784 kb
Host	smart-8a6ff2df-0592-4579-8987-4b8ad24c7448
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788042182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2788042182
Directory	/workspace/32.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/33.keymgr_alert_test.2944412078
Short name	T594
Test name
Test status
Simulation time	57012667 ps
CPU time	0.81 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	205492 kb
Host	smart-ef6a4631-ed34-4680-b247-7fd141b86c68
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944412078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2944412078
Directory	/workspace/33.keymgr_alert_test/latest

Test location	/workspace/coverage/default/33.keymgr_cfg_regwen.2307055976
Short name	T413
Test name
Test status
Simulation time	74204675 ps
CPU time	5.17 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:44 PM PDT 24
Peak memory	214948 kb
Host	smart-fbd8f8a5-77e5-4781-bf0f-82d3d2228f53
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2307055976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2307055976
Directory	/workspace/33.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/33.keymgr_custom_cm.2153150613
Short name	T938
Test name
Test status
Simulation time	317373675 ps
CPU time	10.02 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:49 PM PDT 24
Peak memory	209212 kb
Host	smart-62e83e93-f366-4020-a136-2192962f1c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153150613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2153150613
Directory	/workspace/33.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/33.keymgr_direct_to_disabled.928309310
Short name	T896
Test name
Test status
Simulation time	89145067 ps
CPU time	2.68 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	218188 kb
Host	smart-c030d2b6-c85c-454b-9a27-dfe044732934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928309310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.928309310
Directory	/workspace/33.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/33.keymgr_hwsw_invalid_input.3315982435
Short name	T983
Test name
Test status
Simulation time	3160948893 ps
CPU time	28.03 seconds
Started	May 25 02:15:41 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	219960 kb
Host	smart-56d44c89-1b01-4ab2-a6ef-4dc2bfac1499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315982435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3315982435
Directory	/workspace/33.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/33.keymgr_lc_disable.70158796
Short name	T693
Test name
Test status
Simulation time	67474733 ps
CPU time	2.4 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	205804 kb
Host	smart-ac518d90-2864-43d8-91e2-6596ba3fc3d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=70158796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.70158796
Directory	/workspace/33.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/33.keymgr_random.327090383
Short name	T109
Test name
Test status
Simulation time	263352467 ps
CPU time	8.74 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:47 PM PDT 24
Peak memory	208444 kb
Host	smart-81d42f71-c0ad-4ef4-8902-c8f4267bbcb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327090383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.327090383
Directory	/workspace/33.keymgr_random/latest

Test location	/workspace/coverage/default/33.keymgr_sideload.1035402084
Short name	T88
Test name
Test status
Simulation time	241332296 ps
CPU time	2.95 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:44 PM PDT 24
Peak memory	208052 kb
Host	smart-3b366a5a-6b2a-47d4-9ec4-b8a0d000f028
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035402084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1035402084
Directory	/workspace/33.keymgr_sideload/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_aes.745644495
Short name	T667
Test name
Test status
Simulation time	1068385372 ps
CPU time	7.57 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:47 PM PDT 24
Peak memory	208620 kb
Host	smart-70840e49-17b4-43a3-8c30-7b01dcd89bc9
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745644495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.745644495
Directory	/workspace/33.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_kmac.4272427240
Short name	T839
Test name
Test status
Simulation time	1116801864 ps
CPU time	26.83 seconds
Started	May 25 02:15:39 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	207716 kb
Host	smart-8076c5fb-65b8-46d4-8840-7c4cad6df13f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272427240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4272427240
Directory	/workspace/33.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/33.keymgr_sideload_protect.3528001777
Short name	T777
Test name
Test status
Simulation time	2214878519 ps
CPU time	3.53 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	208280 kb
Host	smart-af10692a-270f-4b10-b6ea-989805af253b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528001777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3528001777
Directory	/workspace/33.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/33.keymgr_smoke.2054844304
Short name	T809
Test name
Test status
Simulation time	262949244 ps
CPU time	3.02 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	207600 kb
Host	smart-e1fc2b23-2dd9-4e2b-999c-4534adf78991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054844304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2054844304
Directory	/workspace/33.keymgr_smoke/latest

Test location	/workspace/coverage/default/33.keymgr_stress_all.2824258211
Short name	T834
Test name
Test status
Simulation time	2931136106 ps
CPU time	34.01 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	216864 kb
Host	smart-75e1d216-5ac0-4b50-a982-b7f298c6b941
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824258211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2824258211
Directory	/workspace/33.keymgr_stress_all/latest

Test location	/workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2631560893
Short name	T1002
Test name
Test status
Simulation time	2254912832 ps
CPU time	9.01 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:48 PM PDT 24
Peak memory	222408 kb
Host	smart-e6c44f79-079f-4b33-b868-dbd0c5b5f6bb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631560893 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2631560893
Directory	/workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.keymgr_sw_invalid_input.3126849819
Short name	T150
Test name
Test status
Simulation time	7865806907 ps
CPU time	77.14 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:16:55 PM PDT 24
Peak memory	209428 kb
Host	smart-88f5e132-ea10-43f7-941f-adf9a24ebbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126849819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3126849819
Directory	/workspace/33.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/33.keymgr_sync_async_fault_cross.1083200306
Short name	T691
Test name
Test status
Simulation time	163067259 ps
CPU time	2.45 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	209708 kb
Host	smart-f7e14af2-0156-4a31-a5fe-6ed539ef4595
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083200306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1083200306
Directory	/workspace/33.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/34.keymgr_alert_test.3897559093
Short name	T768
Test name
Test status
Simulation time	15349674 ps
CPU time	0.97 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:39 PM PDT 24
Peak memory	205772 kb
Host	smart-cfc16fbe-c6ee-4f3b-8411-791d951aae85
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897559093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3897559093
Directory	/workspace/34.keymgr_alert_test/latest

Test location	/workspace/coverage/default/34.keymgr_custom_cm.1645766672
Short name	T28
Test name
Test status
Simulation time	313013767 ps
CPU time	3.59 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	219472 kb
Host	smart-442e831e-473d-45e2-8a02-91238e9879f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645766672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1645766672
Directory	/workspace/34.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/34.keymgr_direct_to_disabled.3683372051
Short name	T740
Test name
Test status
Simulation time	88947127 ps
CPU time	1.63 seconds
Started	May 25 02:15:39 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	207144 kb
Host	smart-edf081fe-41b2-4ebd-aeae-396f510179e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683372051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3683372051
Directory	/workspace/34.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/34.keymgr_hwsw_invalid_input.840231603
Short name	T1023
Test name
Test status
Simulation time	644186028 ps
CPU time	13.65 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:53 PM PDT 24
Peak memory	218688 kb
Host	smart-c79e1b6c-2dd9-4be6-ada7-3b6f764b9c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840231603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.840231603
Directory	/workspace/34.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_kmac_rsp_err.1300046689
Short name	T216
Test name
Test status
Simulation time	570477078 ps
CPU time	6.17 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	222212 kb
Host	smart-8af16d8f-0dfe-40e8-86c5-78f5fd21f63c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300046689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1300046689
Directory	/workspace/34.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/34.keymgr_lc_disable.3324793519
Short name	T58
Test name
Test status
Simulation time	103650236 ps
CPU time	4.45 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	217764 kb
Host	smart-0c931d9a-59ca-48a0-a328-79f3b10bdd27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324793519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3324793519
Directory	/workspace/34.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/34.keymgr_random.3881952515
Short name	T963
Test name
Test status
Simulation time	466475398 ps
CPU time	7.46 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:48 PM PDT 24
Peak memory	217868 kb
Host	smart-fecb3b6c-f179-4ded-aa52-08a4d27f52dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881952515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3881952515
Directory	/workspace/34.keymgr_random/latest

Test location	/workspace/coverage/default/34.keymgr_sideload.988660625
Short name	T398
Test name
Test status
Simulation time	1081746398 ps
CPU time	8.72 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:48 PM PDT 24
Peak memory	208112 kb
Host	smart-f1326e75-85ab-46f9-925c-2729e489ce5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988660625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.988660625
Directory	/workspace/34.keymgr_sideload/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_aes.2589737468
Short name	T927
Test name
Test status
Simulation time	5579042394 ps
CPU time	34.61 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:16:14 PM PDT 24
Peak memory	208144 kb
Host	smart-c4625436-f5ca-42d2-8694-32d8e3e1f35e
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589737468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2589737468
Directory	/workspace/34.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_kmac.508509220
Short name	T879
Test name
Test status
Simulation time	93944785 ps
CPU time	4.56 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	208488 kb
Host	smart-21872b1d-be56-49cc-8266-e0e8e1506f85
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508509220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.508509220
Directory	/workspace/34.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_otbn.1622348003
Short name	T744
Test name
Test status
Simulation time	137797417 ps
CPU time	4.41 seconds
Started	May 25 02:15:35 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	206580 kb
Host	smart-8a265d11-4d1e-440d-a12c-bcc6df9cc9a6
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622348003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1622348003
Directory	/workspace/34.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/34.keymgr_sideload_protect.485776375
Short name	T838
Test name
Test status
Simulation time	303637931 ps
CPU time	3.43 seconds
Started	May 25 02:15:39 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	214040 kb
Host	smart-7f51c80e-7601-4304-94b6-a0da59f0d726
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485776375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.485776375
Directory	/workspace/34.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/34.keymgr_smoke.965234273
Short name	T208
Test name
Test status
Simulation time	25131656 ps
CPU time	1.79 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	206504 kb
Host	smart-f02daadc-fd7a-47a0-8650-37cf3bce7b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965234273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.965234273
Directory	/workspace/34.keymgr_smoke/latest

Test location	/workspace/coverage/default/34.keymgr_stress_all.2100566048
Short name	T357
Test name
Test status
Simulation time	6454588999 ps
CPU time	41.43 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	222260 kb
Host	smart-9024db14-e27a-4792-aa2f-c2a012534194
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100566048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2100566048
Directory	/workspace/34.keymgr_stress_all/latest

Test location	/workspace/coverage/default/34.keymgr_sw_invalid_input.743353956
Short name	T264
Test name
Test status
Simulation time	1431172789 ps
CPU time	9.24 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:47 PM PDT 24
Peak memory	207244 kb
Host	smart-739c12f2-2365-4225-b941-751914d1b3a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743353956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.743353956
Directory	/workspace/34.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/34.keymgr_sync_async_fault_cross.897644569
Short name	T51
Test name
Test status
Simulation time	90926928 ps
CPU time	1.51 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:40 PM PDT 24
Peak memory	208496 kb
Host	smart-5ca83483-1e98-4513-b5fb-1cf7ebdafafe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897644569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.897644569
Directory	/workspace/34.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/35.keymgr_alert_test.1975079955
Short name	T626
Test name
Test status
Simulation time	42082897 ps
CPU time	0.84 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	205604 kb
Host	smart-13bdca22-8e4f-498f-95ac-447c587f1cae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975079955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1975079955
Directory	/workspace/35.keymgr_alert_test/latest

Test location	/workspace/coverage/default/35.keymgr_cfg_regwen.209886629
Short name	T348
Test name
Test status
Simulation time	296390501 ps
CPU time	14.55 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	215180 kb
Host	smart-388f5ef3-536e-4a5c-ab73-c97147688b01
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=209886629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.209886629
Directory	/workspace/35.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/35.keymgr_custom_cm.2294642377
Short name	T19
Test name
Test status
Simulation time	410884126 ps
CPU time	4.56 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	220944 kb
Host	smart-66b1e034-6469-48a1-ba0c-0e45e0b4e93b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294642377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2294642377
Directory	/workspace/35.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/35.keymgr_direct_to_disabled.196381818
Short name	T266
Test name
Test status
Simulation time	91018587 ps
CPU time	3.7 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:44 PM PDT 24
Peak memory	209156 kb
Host	smart-8b5aef99-f5a8-4440-bd08-597b52d05342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=196381818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.196381818
Directory	/workspace/35.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/35.keymgr_hwsw_invalid_input.1977079296
Short name	T100
Test name
Test status
Simulation time	58492553 ps
CPU time	3.45 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	218876 kb
Host	smart-9117d8a2-2f72-4e9f-b03f-78316edf5999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977079296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1977079296
Directory	/workspace/35.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_lc_disable.1396854717
Short name	T791
Test name
Test status
Simulation time	138585083 ps
CPU time	4.89 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	209040 kb
Host	smart-d6568ccd-0374-4d75-a803-116220138837
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396854717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1396854717
Directory	/workspace/35.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/35.keymgr_random.632639684
Short name	T665
Test name
Test status
Simulation time	143477336 ps
CPU time	3.86 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:44 PM PDT 24
Peak memory	208496 kb
Host	smart-18a73a6d-bc78-4eb6-bf26-2482a76c739c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632639684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.632639684
Directory	/workspace/35.keymgr_random/latest

Test location	/workspace/coverage/default/35.keymgr_sideload.1684928016
Short name	T349
Test name
Test status
Simulation time	1135587331 ps
CPU time	4.47 seconds
Started	May 25 02:15:40 PM PDT 24
Finished	May 25 02:15:45 PM PDT 24
Peak memory	206520 kb
Host	smart-04d1dcf1-649a-434a-9159-84990bbb2eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684928016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1684928016
Directory	/workspace/35.keymgr_sideload/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_aes.2569995276
Short name	T386
Test name
Test status
Simulation time	452281340 ps
CPU time	3.59 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	208640 kb
Host	smart-8455905e-5003-40aa-904d-85c6ffd9025b
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569995276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2569995276
Directory	/workspace/35.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_kmac.3932824219
Short name	T803
Test name
Test status
Simulation time	214921987 ps
CPU time	2.8 seconds
Started	May 25 02:15:37 PM PDT 24
Finished	May 25 02:15:41 PM PDT 24
Peak memory	207744 kb
Host	smart-7da7b374-cdc6-4230-803c-3583531483b8
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932824219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3932824219
Directory	/workspace/35.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_otbn.2054170510
Short name	T612
Test name
Test status
Simulation time	203156226 ps
CPU time	2.77 seconds
Started	May 25 02:15:38 PM PDT 24
Finished	May 25 02:15:42 PM PDT 24
Peak memory	206484 kb
Host	smart-493d7a8f-e4f5-4bf7-9a11-af11c32fbe65
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054170510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2054170510
Directory	/workspace/35.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/35.keymgr_sideload_protect.2140200477
Short name	T1064
Test name
Test status
Simulation time	57048299 ps
CPU time	2.34 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:52 PM PDT 24
Peak memory	218032 kb
Host	smart-28ffc527-2c82-433c-9f79-4028ce8a540a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140200477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2140200477
Directory	/workspace/35.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/35.keymgr_smoke.3939283377
Short name	T573
Test name
Test status
Simulation time	39646812 ps
CPU time	2.16 seconds
Started	May 25 02:15:41 PM PDT 24
Finished	May 25 02:15:44 PM PDT 24
Peak memory	206468 kb
Host	smart-d1f99bcd-65a7-4956-86a5-e2dda3c09674
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939283377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3939283377
Directory	/workspace/35.keymgr_smoke/latest

Test location	/workspace/coverage/default/35.keymgr_stress_all.914505012
Short name	T623
Test name
Test status
Simulation time	29359970 ps
CPU time	0.82 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	205624 kb
Host	smart-22975547-85fe-41c7-bf1a-fb1ecc73f486
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914505012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.914505012
Directory	/workspace/35.keymgr_stress_all/latest

Test location	/workspace/coverage/default/35.keymgr_sw_invalid_input.2537529739
Short name	T730
Test name
Test status
Simulation time	173511405 ps
CPU time	5.51 seconds
Started	May 25 02:15:36 PM PDT 24
Finished	May 25 02:15:43 PM PDT 24
Peak memory	209308 kb
Host	smart-ae972572-b46c-4004-b8ae-bce897d9678a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537529739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2537529739
Directory	/workspace/35.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/35.keymgr_sync_async_fault_cross.2278344692
Short name	T636
Test name
Test status
Simulation time	76076880 ps
CPU time	1.81 seconds
Started	May 25 02:15:54 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	209656 kb
Host	smart-8be8153e-ff27-455d-8272-7cdc4319f8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278344692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2278344692
Directory	/workspace/35.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/36.keymgr_alert_test.3690545660
Short name	T746
Test name
Test status
Simulation time	50103813 ps
CPU time	0.85 seconds
Started	May 25 02:15:48 PM PDT 24
Finished	May 25 02:15:50 PM PDT 24
Peak memory	205580 kb
Host	smart-b0be23a3-3c4f-4c95-b6c1-1e8c03838707
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690545660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3690545660
Directory	/workspace/36.keymgr_alert_test/latest

Test location	/workspace/coverage/default/36.keymgr_cfg_regwen.2638945061
Short name	T387
Test name
Test status
Simulation time	788473732 ps
CPU time	4.15 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:59 PM PDT 24
Peak memory	214784 kb
Host	smart-5ce9902d-79dd-4ead-84d9-199a0df8e108
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2638945061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2638945061
Directory	/workspace/36.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/36.keymgr_custom_cm.3837772930
Short name	T36
Test name
Test status
Simulation time	643053068 ps
CPU time	4.55 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	220872 kb
Host	smart-6c7be640-4a3a-42fc-a9eb-91a9f1275918
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837772930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3837772930
Directory	/workspace/36.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/36.keymgr_direct_to_disabled.1659084170
Short name	T659
Test name
Test status
Simulation time	70277427 ps
CPU time	2.36 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	207508 kb
Host	smart-8a2440cf-10c8-4591-91ce-a7fe624b36a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659084170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1659084170
Directory	/workspace/36.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/36.keymgr_kmac_rsp_err.4194449061
Short name	T299
Test name
Test status
Simulation time	608558367 ps
CPU time	4.53 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	222028 kb
Host	smart-d674ce71-bd8f-430b-8993-48baaadc8351
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194449061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4194449061
Directory	/workspace/36.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/36.keymgr_lc_disable.3202744835
Short name	T911
Test name
Test status
Simulation time	154185543 ps
CPU time	2.78 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:53 PM PDT 24
Peak memory	207700 kb
Host	smart-f55784c0-6e50-4faf-9829-07c2dbbaa8fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202744835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3202744835
Directory	/workspace/36.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/36.keymgr_random.4053359637
Short name	T664
Test name
Test status
Simulation time	180586169 ps
CPU time	3.5 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	218076 kb
Host	smart-fcf9fb3f-29e2-4186-a96d-f982fbaf7001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053359637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4053359637
Directory	/workspace/36.keymgr_random/latest

Test location	/workspace/coverage/default/36.keymgr_sideload.729309623
Short name	T620
Test name
Test status
Simulation time	11481997860 ps
CPU time	42.79 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:16:35 PM PDT 24
Peak memory	208508 kb
Host	smart-a5c8d3a0-6fda-4bd1-823a-f89739b60169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729309623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.729309623
Directory	/workspace/36.keymgr_sideload/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_aes.3599907686
Short name	T906
Test name
Test status
Simulation time	134580827 ps
CPU time	4.44 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	206616 kb
Host	smart-988bc4d6-41db-492a-b398-2e8fa7413ea5
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599907686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3599907686
Directory	/workspace/36.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_kmac.2112077847
Short name	T384
Test name
Test status
Simulation time	161690152 ps
CPU time	4.88 seconds
Started	May 25 02:15:48 PM PDT 24
Finished	May 25 02:15:53 PM PDT 24
Peak memory	206600 kb
Host	smart-bd128cc1-8c8e-4b92-a9fb-645b4655d152
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112077847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2112077847
Directory	/workspace/36.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_otbn.1036430214
Short name	T80
Test name
Test status
Simulation time	222904955 ps
CPU time	2.7 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	206332 kb
Host	smart-784a45c3-8812-4090-8c29-a485facfa5a9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036430214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1036430214
Directory	/workspace/36.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/36.keymgr_sideload_protect.3418764385
Short name	T262
Test name
Test status
Simulation time	153438382 ps
CPU time	5.21 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	209460 kb
Host	smart-942621cf-cdf9-4ed0-bce7-07cfbf0757c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418764385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3418764385
Directory	/workspace/36.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/36.keymgr_smoke.1762522968
Short name	T569
Test name
Test status
Simulation time	40853556 ps
CPU time	2.09 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	206632 kb
Host	smart-737fafd6-066d-4c14-a011-b1462c34f86e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762522968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1762522968
Directory	/workspace/36.keymgr_smoke/latest

Test location	/workspace/coverage/default/36.keymgr_sw_invalid_input.3117196987
Short name	T669
Test name
Test status
Simulation time	451470263 ps
CPU time	5.48 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	217984 kb
Host	smart-07f8ce37-024e-4b9c-ac44-1148ac1ba55e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3117196987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3117196987
Directory	/workspace/36.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/36.keymgr_sync_async_fault_cross.2289802962
Short name	T816
Test name
Test status
Simulation time	346035023 ps
CPU time	2.45 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	209656 kb
Host	smart-3904ce8e-39d5-4a93-aa5c-8e704c02c8d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289802962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2289802962
Directory	/workspace/36.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/37.keymgr_alert_test.2362646976
Short name	T650
Test name
Test status
Simulation time	17107855 ps
CPU time	0.81 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	205444 kb
Host	smart-c9aef6c9-e022-4f40-8b04-4b2eb4624981
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362646976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2362646976
Directory	/workspace/37.keymgr_alert_test/latest

Test location	/workspace/coverage/default/37.keymgr_cfg_regwen.3420835112
Short name	T346
Test name
Test status
Simulation time	77761345 ps
CPU time	3.08 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	214880 kb
Host	smart-1dd5ca03-721b-47a7-8a50-717e945957d3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3420835112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3420835112
Directory	/workspace/37.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/37.keymgr_custom_cm.1010119261
Short name	T954
Test name
Test status
Simulation time	309345646 ps
CPU time	3.73 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	214380 kb
Host	smart-1bcffd6e-fae2-4516-ad22-f07c48115d64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010119261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1010119261
Directory	/workspace/37.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/37.keymgr_direct_to_disabled.3718472362
Short name	T45
Test name
Test status
Simulation time	36674402 ps
CPU time	1.57 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	207784 kb
Host	smart-189ea5cb-4fdb-46a0-b107-3f42681584af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718472362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3718472362
Directory	/workspace/37.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/37.keymgr_kmac_rsp_err.106041538
Short name	T102
Test name
Test status
Simulation time	776058757 ps
CPU time	7.02 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	210640 kb
Host	smart-e1ab76e3-c3b3-4e74-af1f-56cb1d274834
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106041538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.106041538
Directory	/workspace/37.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/37.keymgr_lc_disable.4197489074
Short name	T699
Test name
Test status
Simulation time	537065002 ps
CPU time	3.29 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	217924 kb
Host	smart-09d3f9dd-aeb7-48e7-b405-2bcbb2af6914
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197489074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4197489074
Directory	/workspace/37.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/37.keymgr_random.43784103
Short name	T1013
Test name
Test status
Simulation time	314396442 ps
CPU time	8.63 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:16:00 PM PDT 24
Peak memory	207464 kb
Host	smart-6636c328-b163-4fce-8944-6c7c622cca12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43784103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.43784103
Directory	/workspace/37.keymgr_random/latest

Test location	/workspace/coverage/default/37.keymgr_sideload.2126035691
Short name	T642
Test name
Test status
Simulation time	1022017086 ps
CPU time	7.78 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:59 PM PDT 24
Peak memory	207728 kb
Host	smart-12609ca9-6672-4857-8d80-8b7ce9f05920
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126035691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2126035691
Directory	/workspace/37.keymgr_sideload/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_aes.2162707566
Short name	T638
Test name
Test status
Simulation time	1154780121 ps
CPU time	9.02 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:16:02 PM PDT 24
Peak memory	208596 kb
Host	smart-78ff1f6f-1f62-4a85-8893-6e26dc31f8a4
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162707566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2162707566
Directory	/workspace/37.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_kmac.479726227
Short name	T961
Test name
Test status
Simulation time	98540168 ps
CPU time	3.96 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	208444 kb
Host	smart-55b8f99a-b6e9-4538-83f4-9e861ec39d35
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479726227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.479726227
Directory	/workspace/37.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_otbn.2652785651
Short name	T858
Test name
Test status
Simulation time	896443801 ps
CPU time	7.79 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	208792 kb
Host	smart-9364e423-861f-47f9-8d61-c7e42b99484b
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652785651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2652785651
Directory	/workspace/37.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/37.keymgr_sideload_protect.3424900183
Short name	T658
Test name
Test status
Simulation time	182493817 ps
CPU time	1.75 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:52 PM PDT 24
Peak memory	207896 kb
Host	smart-c162c8ec-b406-4793-a509-094a951f529f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424900183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3424900183
Directory	/workspace/37.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/37.keymgr_smoke.1886219147
Short name	T869
Test name
Test status
Simulation time	626467945 ps
CPU time	3.95 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	206444 kb
Host	smart-a0c618a7-e0ea-41de-81bb-1be4b4f9d1d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886219147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1886219147
Directory	/workspace/37.keymgr_smoke/latest

Test location	/workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3832959951
Short name	T990
Test name
Test status
Simulation time	325348128 ps
CPU time	13 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:16:06 PM PDT 24
Peak memory	220048 kb
Host	smart-6d3dd887-5bf5-469f-9249-2d07ecabd5db
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832959951 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3832959951
Directory	/workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.keymgr_sw_invalid_input.833194177
Short name	T893
Test name
Test status
Simulation time	690855426 ps
CPU time	12.94 seconds
Started	May 25 02:15:50 PM PDT 24
Finished	May 25 02:16:04 PM PDT 24
Peak memory	207740 kb
Host	smart-bea3c562-00f1-4878-8af2-06d1f06c5370
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833194177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.833194177
Directory	/workspace/37.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/37.keymgr_sync_async_fault_cross.2427558323
Short name	T670
Test name
Test status
Simulation time	50449900 ps
CPU time	1.62 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	209240 kb
Host	smart-e38c4dfd-cc0a-4e56-aeb3-571d94df7401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427558323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2427558323
Directory	/workspace/37.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/38.keymgr_alert_test.4169235716
Short name	T721
Test name
Test status
Simulation time	18231080 ps
CPU time	0.81 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:55 PM PDT 24
Peak memory	205636 kb
Host	smart-5b3dda09-af9b-420b-8257-a5456105e8fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169235716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4169235716
Directory	/workspace/38.keymgr_alert_test/latest

Test location	/workspace/coverage/default/38.keymgr_custom_cm.3470496652
Short name	T10
Test name
Test status
Simulation time	87167126 ps
CPU time	1.94 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	217124 kb
Host	smart-6e343085-2873-4021-a438-dfeecd20ca1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470496652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3470496652
Directory	/workspace/38.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/38.keymgr_direct_to_disabled.1476970011
Short name	T936
Test name
Test status
Simulation time	33598024 ps
CPU time	2.06 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	209960 kb
Host	smart-42c0eff4-44d8-4f95-b1b9-65594e3b815a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476970011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1476970011
Directory	/workspace/38.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/38.keymgr_hwsw_invalid_input.1398078112
Short name	T786
Test name
Test status
Simulation time	125319194 ps
CPU time	4.81 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	209124 kb
Host	smart-a2cdd724-f03c-4615-aedd-76dedb92065d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398078112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1398078112
Directory	/workspace/38.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_kmac_rsp_err.2782003739
Short name	T933
Test name
Test status
Simulation time	2258778168 ps
CPU time	24.4 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:16:18 PM PDT 24
Peak memory	215456 kb
Host	smart-e1f9a994-b8be-4352-9d61-fbf12040cfb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782003739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2782003739
Directory	/workspace/38.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/38.keymgr_random.1067926774
Short name	T1021
Test name
Test status
Simulation time	1511184933 ps
CPU time	5.42 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:59 PM PDT 24
Peak memory	208848 kb
Host	smart-f6a013e5-e1e5-446e-89c0-a408ad8e595b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067926774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1067926774
Directory	/workspace/38.keymgr_random/latest

Test location	/workspace/coverage/default/38.keymgr_sideload.876508134
Short name	T681
Test name
Test status
Simulation time	101754035 ps
CPU time	3.33 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	206332 kb
Host	smart-6869b4cc-15aa-4ca3-8202-d3ec40aed1e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876508134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.876508134
Directory	/workspace/38.keymgr_sideload/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_aes.1552535129
Short name	T250
Test name
Test status
Simulation time	860248787 ps
CPU time	9.66 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:59 PM PDT 24
Peak memory	208864 kb
Host	smart-da5b69f3-5617-4053-837a-b39d0a09fa66
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552535129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1552535129
Directory	/workspace/38.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_kmac.4161610770
Short name	T149
Test name
Test status
Simulation time	932838109 ps
CPU time	6.06 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	207644 kb
Host	smart-54a707b3-357c-4bec-8bcf-167cc37537ca
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161610770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4161610770
Directory	/workspace/38.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_otbn.1960115241
Short name	T708
Test name
Test status
Simulation time	261489986 ps
CPU time	7.03 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:16:00 PM PDT 24
Peak memory	207796 kb
Host	smart-a1e2845a-bde7-4039-8015-6d9a5657f92a
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960115241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1960115241
Directory	/workspace/38.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/38.keymgr_sideload_protect.2458901968
Short name	T937
Test name
Test status
Simulation time	484405585 ps
CPU time	10.93 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:16:05 PM PDT 24
Peak memory	208476 kb
Host	smart-6f406bf4-9c6f-4f70-b2ee-d37fc8dee090
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2458901968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2458901968
Directory	/workspace/38.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/38.keymgr_smoke.139580212
Short name	T873
Test name
Test status
Simulation time	199612362 ps
CPU time	3.56 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	207968 kb
Host	smart-27ddaf05-e639-43ca-8c8e-6b2d18073e53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139580212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.139580212
Directory	/workspace/38.keymgr_smoke/latest

Test location	/workspace/coverage/default/38.keymgr_stress_all.2721470610
Short name	T1003
Test name
Test status
Simulation time	740519725 ps
CPU time	14.1 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	216720 kb
Host	smart-da3df85b-f459-488f-9792-9dd52be2f466
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721470610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2721470610
Directory	/workspace/38.keymgr_stress_all/latest

Test location	/workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.949611757
Short name	T798
Test name
Test status
Simulation time	180091794 ps
CPU time	5.39 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:16:00 PM PDT 24
Peak memory	222460 kb
Host	smart-73b16e94-bd81-48f2-ad9e-2107b5b65057
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949611757 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.949611757
Directory	/workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.keymgr_sw_invalid_input.1370590749
Short name	T852
Test name
Test status
Simulation time	116695505 ps
CPU time	4.56 seconds
Started	May 25 02:15:49 PM PDT 24
Finished	May 25 02:15:54 PM PDT 24
Peak memory	217912 kb
Host	smart-48918d3c-6cf5-4877-86a7-5b82b1214cf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370590749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1370590749
Directory	/workspace/38.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/38.keymgr_sync_async_fault_cross.3048618796
Short name	T55
Test name
Test status
Simulation time	176589016 ps
CPU time	2.47 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	209644 kb
Host	smart-7e05b51e-9ec2-4f43-a864-4636769ad575
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048618796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3048618796
Directory	/workspace/38.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/39.keymgr_alert_test.2594764528
Short name	T980
Test name
Test status
Simulation time	32890105 ps
CPU time	0.75 seconds
Started	May 25 02:15:59 PM PDT 24
Finished	May 25 02:16:01 PM PDT 24
Peak memory	205584 kb
Host	smart-930694d0-8064-41f9-9a24-4d509c50e81d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594764528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2594764528
Directory	/workspace/39.keymgr_alert_test/latest

Test location	/workspace/coverage/default/39.keymgr_cfg_regwen.2824539125
Short name	T410
Test name
Test status
Simulation time	80678513 ps
CPU time	4.12 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:57 PM PDT 24
Peak memory	214016 kb
Host	smart-74854c4d-83ef-4f8e-9567-498dd77d0b53
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2824539125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2824539125
Directory	/workspace/39.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/39.keymgr_custom_cm.1164002389
Short name	T33
Test name
Test status
Simulation time	130385896 ps
CPU time	3.55 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	216744 kb
Host	smart-02454221-5670-4fce-8e68-49726cf278fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164002389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1164002389
Directory	/workspace/39.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/39.keymgr_direct_to_disabled.568073510
Short name	T843
Test name
Test status
Simulation time	508156538 ps
CPU time	4.3 seconds
Started	May 25 02:16:04 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	213956 kb
Host	smart-98d7d717-cbdd-49dc-807b-56dad9a241e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568073510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.568073510
Directory	/workspace/39.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/39.keymgr_hwsw_invalid_input.3584309693
Short name	T943
Test name
Test status
Simulation time	129455578 ps
CPU time	5.41 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	222028 kb
Host	smart-113e7d38-0a48-4173-9719-b4bc1c40c13f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584309693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3584309693
Directory	/workspace/39.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_lc_disable.3153640652
Short name	T643
Test name
Test status
Simulation time	202286322 ps
CPU time	3.77 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	207524 kb
Host	smart-eff38510-e5a1-4fa3-a498-8b08fa2c22c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153640652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3153640652
Directory	/workspace/39.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/39.keymgr_random.4062187560
Short name	T753
Test name
Test status
Simulation time	56693212 ps
CPU time	3.35 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	210052 kb
Host	smart-d667262c-c12c-4f73-aa99-521723bf372e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062187560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4062187560
Directory	/workspace/39.keymgr_random/latest

Test location	/workspace/coverage/default/39.keymgr_sideload.1553692335
Short name	T703
Test name
Test status
Simulation time	393769511 ps
CPU time	4.75 seconds
Started	May 25 02:15:52 PM PDT 24
Finished	May 25 02:15:58 PM PDT 24
Peak memory	207028 kb
Host	smart-47e99c7a-9c65-46a6-a7c1-06f26dc2dc9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553692335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1553692335
Directory	/workspace/39.keymgr_sideload/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_aes.3475740431
Short name	T905
Test name
Test status
Simulation time	124576433 ps
CPU time	3.97 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:59 PM PDT 24
Peak memory	208140 kb
Host	smart-de8e9a15-a93d-46cf-85e3-0672a6bf5d57
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475740431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3475740431
Directory	/workspace/39.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_kmac.1314389482
Short name	T1011
Test name
Test status
Simulation time	1673414077 ps
CPU time	49.38 seconds
Started	May 25 02:15:51 PM PDT 24
Finished	May 25 02:16:42 PM PDT 24
Peak memory	207744 kb
Host	smart-37c8165c-7c4e-4d23-99f5-9cc7c21c8c8f
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314389482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1314389482
Directory	/workspace/39.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_otbn.1260205849
Short name	T847
Test name
Test status
Simulation time	9194817386 ps
CPU time	52.44 seconds
Started	May 25 02:15:55 PM PDT 24
Finished	May 25 02:16:48 PM PDT 24
Peak memory	208748 kb
Host	smart-81447a18-fc8b-4ecb-a556-3c65cd9e0ab7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260205849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1260205849
Directory	/workspace/39.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/39.keymgr_sideload_protect.2644424636
Short name	T833
Test name
Test status
Simulation time	3011696579 ps
CPU time	5.98 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:14 PM PDT 24
Peak memory	210032 kb
Host	smart-b6f47d5d-9093-4871-821a-d09ec2c18d8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644424636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2644424636
Directory	/workspace/39.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/39.keymgr_smoke.3021976412
Short name	T679
Test name
Test status
Simulation time	74530694 ps
CPU time	1.7 seconds
Started	May 25 02:15:53 PM PDT 24
Finished	May 25 02:15:56 PM PDT 24
Peak memory	206776 kb
Host	smart-d9f6f051-706d-43fb-9e1f-6dc1513ef362
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021976412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3021976412
Directory	/workspace/39.keymgr_smoke/latest

Test location	/workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.278397255
Short name	T1006
Test name
Test status
Simulation time	87499850 ps
CPU time	3.21 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	222392 kb
Host	smart-7ea9cf7f-4a93-41fa-bba7-32f39c585e3c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278397255 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.278397255
Directory	/workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.keymgr_sw_invalid_input.807948502
Short name	T1054
Test name
Test status
Simulation time	39320469 ps
CPU time	3.05 seconds
Started	May 25 02:15:59 PM PDT 24
Finished	May 25 02:16:03 PM PDT 24
Peak memory	207004 kb
Host	smart-024419c7-ad43-4882-a9ba-276d167198c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807948502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.807948502
Directory	/workspace/39.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/39.keymgr_sync_async_fault_cross.2163403263
Short name	T785
Test name
Test status
Simulation time	41983212 ps
CPU time	2.08 seconds
Started	May 25 02:16:00 PM PDT 24
Finished	May 25 02:16:02 PM PDT 24
Peak memory	209660 kb
Host	smart-770f3ab6-f57e-4400-8324-21d12063a6b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163403263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2163403263
Directory	/workspace/39.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/4.keymgr_alert_test.2592786086
Short name	T580
Test name
Test status
Simulation time	31083262 ps
CPU time	0.67 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:04 PM PDT 24
Peak memory	205524 kb
Host	smart-5d36962d-e537-4286-9ac1-d7e0ff12c827
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592786086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2592786086
Directory	/workspace/4.keymgr_alert_test/latest

Test location	/workspace/coverage/default/4.keymgr_cfg_regwen.4257177124
Short name	T292
Test name
Test status
Simulation time	148552584 ps
CPU time	3.14 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	214020 kb
Host	smart-fd881b48-b669-4d52-be68-96b0d3d96930
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4257177124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4257177124
Directory	/workspace/4.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/4.keymgr_direct_to_disabled.776985969
Short name	T622
Test name
Test status
Simulation time	17866720 ps
CPU time	1.37 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	207632 kb
Host	smart-ee357acd-1762-43d1-96d7-186b3003a52c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776985969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.776985969
Directory	/workspace/4.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/4.keymgr_kmac_rsp_err.3958424089
Short name	T360
Test name
Test status
Simulation time	758131142 ps
CPU time	7.06 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:10 PM PDT 24
Peak memory	214124 kb
Host	smart-b2710a30-6406-4c06-b8cb-f9c1524099d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958424089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3958424089
Directory	/workspace/4.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/4.keymgr_lc_disable.3120968591
Short name	T851
Test name
Test status
Simulation time	99940998 ps
CPU time	4.58 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:04 PM PDT 24
Peak memory	220324 kb
Host	smart-b283162f-2684-4492-a819-9822273636e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120968591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3120968591
Directory	/workspace/4.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/4.keymgr_random.4093916169
Short name	T823
Test name
Test status
Simulation time	119449273 ps
CPU time	3.39 seconds
Started	May 25 02:13:59 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	209496 kb
Host	smart-cfe789ae-466b-4f07-83d8-6bec1eec4de9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093916169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4093916169
Directory	/workspace/4.keymgr_random/latest

Test location	/workspace/coverage/default/4.keymgr_sec_cm.2020835124
Short name	T14
Test name
Test status
Simulation time	8285000922 ps
CPU time	185.29 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:17:03 PM PDT 24
Peak memory	293892 kb
Host	smart-ae084461-8a5e-412f-afdf-f964a24daec4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020835124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2020835124
Directory	/workspace/4.keymgr_sec_cm/latest

Test location	/workspace/coverage/default/4.keymgr_sideload.1754609037
Short name	T725
Test name
Test status
Simulation time	455040586 ps
CPU time	2.45 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:02 PM PDT 24
Peak memory	208340 kb
Host	smart-cc5e035b-dded-4b0f-a89b-e7e8948a79e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754609037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1754609037
Directory	/workspace/4.keymgr_sideload/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_aes.3130126193
Short name	T1052
Test name
Test status
Simulation time	54625522 ps
CPU time	2.65 seconds
Started	May 25 02:13:59 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	208000 kb
Host	smart-ee798699-d67c-417b-96d9-aa5fccc97ebf
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130126193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3130126193
Directory	/workspace/4.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_kmac.3795791652
Short name	T1032
Test name
Test status
Simulation time	453101498 ps
CPU time	5.56 seconds
Started	May 25 02:13:59 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	208284 kb
Host	smart-efde7a02-8dae-433c-9c6b-d46b3e06d5ee
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795791652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3795791652
Directory	/workspace/4.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_otbn.3177005433
Short name	T856
Test name
Test status
Simulation time	11744732286 ps
CPU time	52.47 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:53 PM PDT 24
Peak memory	207852 kb
Host	smart-b4a16c01-8f58-46e5-a6ef-828afad549b7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177005433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3177005433
Directory	/workspace/4.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/4.keymgr_sideload_protect.1527942438
Short name	T646
Test name
Test status
Simulation time	388663969 ps
CPU time	7.9 seconds
Started	May 25 02:13:59 PM PDT 24
Finished	May 25 02:14:07 PM PDT 24
Peak memory	209392 kb
Host	smart-e0f243ad-35b0-46af-9a31-e1f40b8a1496
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527942438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1527942438
Directory	/workspace/4.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/4.keymgr_smoke.1207673171
Short name	T717
Test name
Test status
Simulation time	125047276 ps
CPU time	4.04 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	206616 kb
Host	smart-d947e2b3-887b-4cb4-b594-418e9100673b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207673171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1207673171
Directory	/workspace/4.keymgr_smoke/latest

Test location	/workspace/coverage/default/4.keymgr_stress_all.2789855771
Short name	T267
Test name
Test status
Simulation time	975933006 ps
CPU time	25.72 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:29 PM PDT 24
Peak memory	215460 kb
Host	smart-e0359e11-bbc8-43bc-9e69-becffa7675dd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789855771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2789855771
Directory	/workspace/4.keymgr_stress_all/latest

Test location	/workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.175274606
Short name	T948
Test name
Test status
Simulation time	2379216129 ps
CPU time	10.98 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	222412 kb
Host	smart-d71bd2f8-2636-422a-8873-473f4d17305c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175274606 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.175274606
Directory	/workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.keymgr_sw_invalid_input.1082132661
Short name	T418
Test name
Test status
Simulation time	11852005166 ps
CPU time	69.79 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:15:13 PM PDT 24
Peak memory	208744 kb
Host	smart-91853ed6-bb76-429e-85fe-4891a099bba4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082132661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1082132661
Directory	/workspace/4.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/4.keymgr_sync_async_fault_cross.2885816974
Short name	T769
Test name
Test status
Simulation time	73493447 ps
CPU time	1.79 seconds
Started	May 25 02:13:58 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	209436 kb
Host	smart-0c69e549-01fb-46c9-bb94-a5a75089f32d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885816974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2885816974
Directory	/workspace/4.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/40.keymgr_alert_test.1001071891
Short name	T760
Test name
Test status
Simulation time	10876893 ps
CPU time	0.74 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	205580 kb
Host	smart-0649599b-edbb-43d0-95d7-1492ca23fdde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001071891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1001071891
Directory	/workspace/40.keymgr_alert_test/latest

Test location	/workspace/coverage/default/40.keymgr_custom_cm.2367640338
Short name	T826
Test name
Test status
Simulation time	578687266 ps
CPU time	4.33 seconds
Started	May 25 02:16:00 PM PDT 24
Finished	May 25 02:16:05 PM PDT 24
Peak memory	209664 kb
Host	smart-362d468c-ce39-4f07-8fbb-b00f4f88c0df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367640338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2367640338
Directory	/workspace/40.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/40.keymgr_direct_to_disabled.2379349835
Short name	T70
Test name
Test status
Simulation time	656989110 ps
CPU time	1.73 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:06 PM PDT 24
Peak memory	206856 kb
Host	smart-fc82afd0-3736-424e-a1ff-c50265a36e70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379349835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2379349835
Directory	/workspace/40.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/40.keymgr_hwsw_invalid_input.3713878860
Short name	T101
Test name
Test status
Simulation time	198651730 ps
CPU time	3.45 seconds
Started	May 25 02:16:09 PM PDT 24
Finished	May 25 02:16:13 PM PDT 24
Peak memory	209116 kb
Host	smart-ce1b2be1-2148-4977-86be-6ad7d9aeaa57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713878860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3713878860
Directory	/workspace/40.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_lc_disable.2844349494
Short name	T419
Test name
Test status
Simulation time	155585716 ps
CPU time	3.46 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	219396 kb
Host	smart-c4ac27ae-adec-4c64-98c8-51c1b87fd937
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844349494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2844349494
Directory	/workspace/40.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/40.keymgr_random.4051176966
Short name	T799
Test name
Test status
Simulation time	102078225 ps
CPU time	3.33 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	208212 kb
Host	smart-556710c5-578c-48a4-bb1c-24cbd276470a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051176966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4051176966
Directory	/workspace/40.keymgr_random/latest

Test location	/workspace/coverage/default/40.keymgr_sideload.3871355306
Short name	T634
Test name
Test status
Simulation time	216709659 ps
CPU time	6.33 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:14 PM PDT 24
Peak memory	207656 kb
Host	smart-91f2f8e0-f6c9-49ac-bfd0-a3d5bc8e009b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871355306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3871355306
Directory	/workspace/40.keymgr_sideload/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_aes.2736383199
Short name	T993
Test name
Test status
Simulation time	52282639 ps
CPU time	3.2 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:05 PM PDT 24
Peak memory	206632 kb
Host	smart-72e99728-8f4f-4a6d-b5cd-843a8a43ac75
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736383199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2736383199
Directory	/workspace/40.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_kmac.10566152
Short name	T142
Test name
Test status
Simulation time	394465543 ps
CPU time	5.5 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	208416 kb
Host	smart-d8f027e1-719e-49e4-94b0-ad462f7b5c37
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.10566152
Directory	/workspace/40.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_otbn.4125341914
Short name	T217
Test name
Test status
Simulation time	80658024 ps
CPU time	3.96 seconds
Started	May 25 02:16:04 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	208272 kb
Host	smart-e5e3eda5-3af0-4e94-8c4c-f253cb18ddba
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125341914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4125341914
Directory	/workspace/40.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/40.keymgr_sideload_protect.1508798966
Short name	T757
Test name
Test status
Simulation time	90543198 ps
CPU time	3.28 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	218028 kb
Host	smart-71a8ff19-8478-43c8-b9ec-4769226543ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1508798966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1508798966
Directory	/workspace/40.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/40.keymgr_smoke.3789576121
Short name	T741
Test name
Test status
Simulation time	2082376576 ps
CPU time	46.76 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:50 PM PDT 24
Peak memory	207856 kb
Host	smart-6a1e2f56-0dff-477f-aff3-7408599e5171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789576121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3789576121
Directory	/workspace/40.keymgr_smoke/latest

Test location	/workspace/coverage/default/40.keymgr_stress_all.3619997125
Short name	T320
Test name
Test status
Simulation time	848614752 ps
CPU time	18.51 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:26 PM PDT 24
Peak memory	215540 kb
Host	smart-94ff70f7-f5c6-4f80-a966-13038fbfc871
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619997125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3619997125
Directory	/workspace/40.keymgr_stress_all/latest

Test location	/workspace/coverage/default/40.keymgr_sw_invalid_input.2926153116
Short name	T865
Test name
Test status
Simulation time	1714513934 ps
CPU time	7.82 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:15 PM PDT 24
Peak memory	209872 kb
Host	smart-dc3af5b1-e981-4065-a543-6b35046925c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926153116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2926153116
Directory	/workspace/40.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/40.keymgr_sync_async_fault_cross.215235477
Short name	T756
Test name
Test status
Simulation time	92059310 ps
CPU time	3.05 seconds
Started	May 25 02:16:09 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	210228 kb
Host	smart-095ebf50-d18f-406e-8290-84fd069adc6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215235477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.215235477
Directory	/workspace/40.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/41.keymgr_alert_test.284525830
Short name	T563
Test name
Test status
Simulation time	39878143 ps
CPU time	0.75 seconds
Started	May 25 02:16:00 PM PDT 24
Finished	May 25 02:16:02 PM PDT 24
Peak memory	205704 kb
Host	smart-f3470e10-30f6-42e7-8f09-f2e190e353e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284525830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.284525830
Directory	/workspace/41.keymgr_alert_test/latest

Test location	/workspace/coverage/default/41.keymgr_cfg_regwen.420256734
Short name	T429
Test name
Test status
Simulation time	201881910 ps
CPU time	4.25 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:06 PM PDT 24
Peak memory	214232 kb
Host	smart-59d078d8-f840-42a7-a78e-9911ae507dec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=420256734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.420256734
Directory	/workspace/41.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/41.keymgr_direct_to_disabled.3727666209
Short name	T279
Test name
Test status
Simulation time	124627211 ps
CPU time	2.31 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:04 PM PDT 24
Peak memory	209336 kb
Host	smart-1731d548-e6bd-48ff-b2d2-d67134cd58a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727666209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3727666209
Directory	/workspace/41.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/41.keymgr_hwsw_invalid_input.1782993306
Short name	T853
Test name
Test status
Simulation time	517017762 ps
CPU time	4.62 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:18 PM PDT 24
Peak memory	213792 kb
Host	smart-54625b11-1311-4398-9894-f32408ccf2c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782993306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1782993306
Directory	/workspace/41.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_kmac_rsp_err.2045392433
Short name	T274
Test name
Test status
Simulation time	3347623260 ps
CPU time	66 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:17:10 PM PDT 24
Peak memory	225792 kb
Host	smart-49e152ea-24f4-4c99-94b5-d7c2cce62fe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045392433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2045392433
Directory	/workspace/41.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/41.keymgr_lc_disable.2894366958
Short name	T821
Test name
Test status
Simulation time	380934707 ps
CPU time	1.83 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:06 PM PDT 24
Peak memory	205744 kb
Host	smart-89640ddf-2050-4bea-87c3-869d44579d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894366958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2894366958
Directory	/workspace/41.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/41.keymgr_random.1909373040
Short name	T270
Test name
Test status
Simulation time	912320069 ps
CPU time	27.98 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:34 PM PDT 24
Peak memory	209040 kb
Host	smart-7fe84650-8c9a-4556-9eb6-37b876f6a3fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909373040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1909373040
Directory	/workspace/41.keymgr_random/latest

Test location	/workspace/coverage/default/41.keymgr_sideload.3333490598
Short name	T840
Test name
Test status
Simulation time	272919765 ps
CPU time	3.33 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	208028 kb
Host	smart-dce039eb-a164-4741-ab1f-2a45dce1410c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333490598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3333490598
Directory	/workspace/41.keymgr_sideload/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_aes.3511297358
Short name	T619
Test name
Test status
Simulation time	239551285 ps
CPU time	3.56 seconds
Started	May 25 02:16:00 PM PDT 24
Finished	May 25 02:16:04 PM PDT 24
Peak memory	208324 kb
Host	smart-76afc378-ab16-4da7-87f0-739dcc5044ca
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511297358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3511297358
Directory	/workspace/41.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_kmac.1024720512
Short name	T751
Test name
Test status
Simulation time	152076713 ps
CPU time	2.19 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	206648 kb
Host	smart-81c715a0-7b89-464b-81ad-7046f11548e0
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024720512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1024720512
Directory	/workspace/41.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_otbn.4176264350
Short name	T220
Test name
Test status
Simulation time	99632849 ps
CPU time	2.78 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	206772 kb
Host	smart-50ff7303-0cd7-42b2-8f5d-d488e4eda124
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176264350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4176264350
Directory	/workspace/41.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/41.keymgr_sideload_protect.1191845747
Short name	T788
Test name
Test status
Simulation time	1096865194 ps
CPU time	25.92 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	210000 kb
Host	smart-b5d1f55e-6775-48bf-8e93-c674a166c0a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191845747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1191845747
Directory	/workspace/41.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/41.keymgr_smoke.71634410
Short name	T4
Test name
Test status
Simulation time	1871927261 ps
CPU time	4.92 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	206408 kb
Host	smart-66e4187c-e17c-47d7-8a25-05c69550117a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71634410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.71634410
Directory	/workspace/41.keymgr_smoke/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all.3159235433
Short name	T1030
Test name
Test status
Simulation time	1891066763 ps
CPU time	7.67 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	221084 kb
Host	smart-34171536-ffd4-4be0-8117-8f932705dd37
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159235433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3159235433
Directory	/workspace/41.keymgr_stress_all/latest

Test location	/workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2291458728
Short name	T702
Test name
Test status
Simulation time	215178558 ps
CPU time	5.18 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	220348 kb
Host	smart-c926bb28-7b82-46f0-a02d-a76d20e37917
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291458728 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2291458728
Directory	/workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.keymgr_sw_invalid_input.208175052
Short name	T199
Test name
Test status
Simulation time	116100126 ps
CPU time	5.32 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	209788 kb
Host	smart-f997b66d-7585-4fd8-a392-46f2f4c44bbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208175052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.208175052
Directory	/workspace/41.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/41.keymgr_sync_async_fault_cross.2049749557
Short name	T56
Test name
Test status
Simulation time	101356425 ps
CPU time	2.12 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	209836 kb
Host	smart-9def6197-d619-495d-927b-4672c84d2ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049749557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2049749557
Directory	/workspace/41.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/42.keymgr_alert_test.759700338
Short name	T106
Test name
Test status
Simulation time	12309458 ps
CPU time	0.88 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	205492 kb
Host	smart-7d60af0f-62ea-42d6-bc2d-85482376aee9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759700338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.759700338
Directory	/workspace/42.keymgr_alert_test/latest

Test location	/workspace/coverage/default/42.keymgr_cfg_regwen.2375981399
Short name	T930
Test name
Test status
Simulation time	68059570 ps
CPU time	4.03 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:13 PM PDT 24
Peak memory	213972 kb
Host	smart-080d4331-8a69-4db4-bca9-afbf72e92bb5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2375981399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2375981399
Directory	/workspace/42.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/42.keymgr_custom_cm.645786763
Short name	T34
Test name
Test status
Simulation time	152179942 ps
CPU time	5.03 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	209160 kb
Host	smart-fea2fbd7-8056-485a-8dc3-70110de649ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645786763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.645786763
Directory	/workspace/42.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/42.keymgr_direct_to_disabled.957944305
Short name	T900
Test name
Test status
Simulation time	133422634 ps
CPU time	3.24 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	214036 kb
Host	smart-39453871-75e4-4d7e-85aa-cb924dd057c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=957944305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.957944305
Directory	/workspace/42.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/42.keymgr_lc_disable.1817159169
Short name	T921
Test name
Test status
Simulation time	78273867 ps
CPU time	2.52 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	209704 kb
Host	smart-ea11832a-8ee7-4c8f-9f62-6cc946885d31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817159169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1817159169
Directory	/workspace/42.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/42.keymgr_random.3281324713
Short name	T341
Test name
Test status
Simulation time	553448905 ps
CPU time	4.71 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	214024 kb
Host	smart-a5a0c0fc-41d5-45dd-bd21-0e8d7d7475dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281324713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3281324713
Directory	/workspace/42.keymgr_random/latest

Test location	/workspace/coverage/default/42.keymgr_sideload.3295942395
Short name	T591
Test name
Test status
Simulation time	116174202 ps
CPU time	3.53 seconds
Started	May 25 02:16:04 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	206600 kb
Host	smart-3af62d9f-705b-4490-af98-3873bcdd8b7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295942395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3295942395
Directory	/workspace/42.keymgr_sideload/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_aes.3600842985
Short name	T1019
Test name
Test status
Simulation time	37297195 ps
CPU time	2.76 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	208220 kb
Host	smart-b76c75b5-9a27-4369-b552-93422ad9ca3f
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600842985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3600842985
Directory	/workspace/42.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_kmac.1339133159
Short name	T590
Test name
Test status
Simulation time	1029558528 ps
CPU time	5 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:18 PM PDT 24
Peak memory	206384 kb
Host	smart-fb392e1d-d86f-4c6d-a63c-26e0a6c07378
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339133159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1339133159
Directory	/workspace/42.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_otbn.1907485418
Short name	T628
Test name
Test status
Simulation time	606168513 ps
CPU time	20.18 seconds
Started	May 25 02:16:00 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	206852 kb
Host	smart-3f48a53f-4841-40a3-8262-4029df0a925f
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907485418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1907485418
Directory	/workspace/42.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/42.keymgr_sideload_protect.1471362299
Short name	T797
Test name
Test status
Simulation time	351040506 ps
CPU time	5.85 seconds
Started	May 25 02:16:09 PM PDT 24
Finished	May 25 02:16:15 PM PDT 24
Peak memory	208280 kb
Host	smart-4722d2aa-abd8-41e4-9e72-626908a29d74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471362299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1471362299
Directory	/workspace/42.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/42.keymgr_smoke.3351511933
Short name	T828
Test name
Test status
Simulation time	315919479 ps
CPU time	5.22 seconds
Started	May 25 02:16:01 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	208304 kb
Host	smart-650792d7-5bf5-4511-b9a2-e565a9f6e1eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351511933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3351511933
Directory	/workspace/42.keymgr_smoke/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all.2419549047
Short name	T1004
Test name
Test status
Simulation time	1740387779 ps
CPU time	23.53 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:37 PM PDT 24
Peak memory	221992 kb
Host	smart-e9e3438d-2ae1-4932-9d29-62559f80d603
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419549047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2419549047
Directory	/workspace/42.keymgr_stress_all/latest

Test location	/workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1850412739
Short name	T968
Test name
Test status
Simulation time	782429489 ps
CPU time	8.04 seconds
Started	May 25 02:16:12 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	222336 kb
Host	smart-f0694ad4-1ade-4141-87b1-5fc363c06b1e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850412739 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1850412739
Directory	/workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.keymgr_sw_invalid_input.3084141597
Short name	T764
Test name
Test status
Simulation time	238088607 ps
CPU time	4.56 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:13 PM PDT 24
Peak memory	207940 kb
Host	smart-3c4d91f7-f603-4e57-9aae-a1e633c96b63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084141597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3084141597
Directory	/workspace/42.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/42.keymgr_sync_async_fault_cross.2803104291
Short name	T950
Test name
Test status
Simulation time	694014555 ps
CPU time	4.04 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	210424 kb
Host	smart-5944509c-f536-4139-bc73-0971453bf23e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803104291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2803104291
Directory	/workspace/42.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/43.keymgr_alert_test.503256532
Short name	T613
Test name
Test status
Simulation time	135830296 ps
CPU time	0.86 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:08 PM PDT 24
Peak memory	205584 kb
Host	smart-764ee2fb-6467-4371-bcd8-d6d0585013ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503256532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.503256532
Directory	/workspace/43.keymgr_alert_test/latest

Test location	/workspace/coverage/default/43.keymgr_cfg_regwen.2343028808
Short name	T408
Test name
Test status
Simulation time	782125630 ps
CPU time	18.64 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:27 PM PDT 24
Peak memory	213900 kb
Host	smart-c953f20c-0713-4dba-b9f6-18b9b18d9286
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2343028808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2343028808
Directory	/workspace/43.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/43.keymgr_custom_cm.2259563140
Short name	T956
Test name
Test status
Simulation time	169512741 ps
CPU time	4.49 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	209020 kb
Host	smart-ba27aa66-220b-4fc2-91f4-e47b5d0b21c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259563140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2259563140
Directory	/workspace/43.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/43.keymgr_direct_to_disabled.1037906989
Short name	T336
Test name
Test status
Simulation time	91742406 ps
CPU time	2.26 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:05 PM PDT 24
Peak memory	209376 kb
Host	smart-aa4625f1-e52c-4754-893d-b788668d07d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037906989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1037906989
Directory	/workspace/43.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/43.keymgr_hwsw_invalid_input.559039951
Short name	T97
Test name
Test status
Simulation time	28140631 ps
CPU time	2.08 seconds
Started	May 25 02:16:02 PM PDT 24
Finished	May 25 02:16:05 PM PDT 24
Peak memory	208920 kb
Host	smart-71eef76e-241a-4334-ba02-1ffec726369e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559039951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.559039951
Directory	/workspace/43.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_lc_disable.1853593154
Short name	T63
Test name
Test status
Simulation time	71885909 ps
CPU time	3.5 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	217908 kb
Host	smart-c98441a5-8476-40ee-bae1-e27d694b301f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853593154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1853593154
Directory	/workspace/43.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/43.keymgr_random.987905714
Short name	T989
Test name
Test status
Simulation time	543015125 ps
CPU time	5.57 seconds
Started	May 25 02:16:05 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	218032 kb
Host	smart-b7a12816-1cfe-41af-b0a4-2623488bc58a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987905714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.987905714
Directory	/workspace/43.keymgr_random/latest

Test location	/workspace/coverage/default/43.keymgr_sideload.3726380676
Short name	T883
Test name
Test status
Simulation time	70140171 ps
CPU time	2.47 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:10 PM PDT 24
Peak memory	208280 kb
Host	smart-85f69e97-1790-422b-9506-b40ece71e172
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726380676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3726380676
Directory	/workspace/43.keymgr_sideload/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_aes.3177858609
Short name	T641
Test name
Test status
Simulation time	127718797 ps
CPU time	2.57 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:16 PM PDT 24
Peak memory	206952 kb
Host	smart-06ed2e41-5992-44ae-b395-e1296f5ee2d6
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177858609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3177858609
Directory	/workspace/43.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_kmac.4062214869
Short name	T1060
Test name
Test status
Simulation time	100207483 ps
CPU time	1.95 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:11 PM PDT 24
Peak memory	206464 kb
Host	smart-f6df8f58-bb8e-47ca-af79-a3627315f130
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062214869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4062214869
Directory	/workspace/43.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_otbn.2666679245
Short name	T931
Test name
Test status
Simulation time	435450549 ps
CPU time	5.11 seconds
Started	May 25 02:16:10 PM PDT 24
Finished	May 25 02:16:16 PM PDT 24
Peak memory	206788 kb
Host	smart-d1857c6d-3e53-43f7-a142-f6996d82b5fd
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666679245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2666679245
Directory	/workspace/43.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/43.keymgr_sideload_protect.187742580
Short name	T975
Test name
Test status
Simulation time	149762735 ps
CPU time	1.99 seconds
Started	May 25 02:16:10 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	215412 kb
Host	smart-c65d00ea-9c18-4889-a869-2a8ed7f217f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187742580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.187742580
Directory	/workspace/43.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/43.keymgr_smoke.1920847066
Short name	T680
Test name
Test status
Simulation time	1667998964 ps
CPU time	44.17 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:58 PM PDT 24
Peak memory	208188 kb
Host	smart-6afcc501-7866-48df-af93-3b5de41298fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920847066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1920847066
Directory	/workspace/43.keymgr_smoke/latest

Test location	/workspace/coverage/default/43.keymgr_stress_all.1704237642
Short name	T988
Test name
Test status
Simulation time	1454485724 ps
CPU time	34.45 seconds
Started	May 25 02:16:11 PM PDT 24
Finished	May 25 02:16:46 PM PDT 24
Peak memory	220664 kb
Host	smart-71d96bfd-cca6-42b8-9be2-74794982cd2a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704237642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1704237642
Directory	/workspace/43.keymgr_stress_all/latest

Test location	/workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.47312242
Short name	T235
Test name
Test status
Simulation time	1015391600 ps
CPU time	15.8 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	221960 kb
Host	smart-fd3c8afd-a171-47a5-b26f-a2bc413428a2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47312242 -assert nopostp roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.47312242
Directory	/workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.keymgr_sw_invalid_input.2421313162
Short name	T754
Test name
Test status
Simulation time	159764187 ps
CPU time	4.75 seconds
Started	May 25 02:16:07 PM PDT 24
Finished	May 25 02:16:13 PM PDT 24
Peak memory	218216 kb
Host	smart-c75175fd-abe6-40dd-bca0-cc4ac6928d40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421313162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2421313162
Directory	/workspace/43.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/43.keymgr_sync_async_fault_cross.317184180
Short name	T570
Test name
Test status
Simulation time	66322062 ps
CPU time	2.77 seconds
Started	May 25 02:16:06 PM PDT 24
Finished	May 25 02:16:09 PM PDT 24
Peak memory	209900 kb
Host	smart-f1d78fe8-3d74-4d4b-8b6d-135ace3faa90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317184180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.317184180
Directory	/workspace/43.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/44.keymgr_alert_test.1522744854
Short name	T1025
Test name
Test status
Simulation time	50755188 ps
CPU time	0.69 seconds
Started	May 25 02:16:11 PM PDT 24
Finished	May 25 02:16:13 PM PDT 24
Peak memory	205600 kb
Host	smart-f0a7706d-696f-4c4a-b82d-19cfdfaa4d20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522744854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1522744854
Directory	/workspace/44.keymgr_alert_test/latest

Test location	/workspace/coverage/default/44.keymgr_cfg_regwen.1482126908
Short name	T331
Test name
Test status
Simulation time	119805833 ps
CPU time	2.53 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:16 PM PDT 24
Peak memory	213956 kb
Host	smart-03961805-a9bb-4eb1-b1f0-c3c39215032d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1482126908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1482126908
Directory	/workspace/44.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/44.keymgr_custom_cm.1835003076
Short name	T1007
Test name
Test status
Simulation time	77370767 ps
CPU time	3.05 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	208272 kb
Host	smart-42f48f7e-2193-4d06-b691-7fe1a2d75553
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835003076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1835003076
Directory	/workspace/44.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/44.keymgr_direct_to_disabled.1578131565
Short name	T774
Test name
Test status
Simulation time	132323218 ps
CPU time	2.86 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	218032 kb
Host	smart-7c344589-24c2-4b90-888a-5b6ca0323436
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578131565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1578131565
Directory	/workspace/44.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/44.keymgr_hwsw_invalid_input.1344999715
Short name	T887
Test name
Test status
Simulation time	1330093298 ps
CPU time	14.32 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:32 PM PDT 24
Peak memory	220344 kb
Host	smart-8807307c-dd1a-42cc-a466-dfad9c7ed571
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344999715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1344999715
Directory	/workspace/44.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/44.keymgr_lc_disable.187695234
Short name	T778
Test name
Test status
Simulation time	374457218 ps
CPU time	3.12 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	219944 kb
Host	smart-2a648639-bb65-4e7a-be32-213532592e69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187695234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.187695234
Directory	/workspace/44.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/44.keymgr_random.3827160441
Short name	T251
Test name
Test status
Simulation time	3121950901 ps
CPU time	6.67 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	219572 kb
Host	smart-146964b4-7e15-4d4a-ba3c-f0372f986ea9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827160441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3827160441
Directory	/workspace/44.keymgr_random/latest

Test location	/workspace/coverage/default/44.keymgr_sideload.1466864090
Short name	T739
Test name
Test status
Simulation time	2335971452 ps
CPU time	28.01 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:37 PM PDT 24
Peak memory	206760 kb
Host	smart-25fcded8-a0fc-499e-bd1c-2630625062b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466864090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1466864090
Directory	/workspace/44.keymgr_sideload/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_aes.3235590542
Short name	T992
Test name
Test status
Simulation time	317973181 ps
CPU time	3.52 seconds
Started	May 25 02:16:08 PM PDT 24
Finished	May 25 02:16:12 PM PDT 24
Peak memory	208600 kb
Host	smart-6a890c82-f06d-46c0-bd64-bc2a140c6d85
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235590542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3235590542
Directory	/workspace/44.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_kmac.3278246338
Short name	T1040
Test name
Test status
Simulation time	5424212917 ps
CPU time	47.65 seconds
Started	May 25 02:16:09 PM PDT 24
Finished	May 25 02:16:57 PM PDT 24
Peak memory	207744 kb
Host	smart-58bfb0ae-ea1b-4b21-ae4c-cb9fdc21d221
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278246338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3278246338
Directory	/workspace/44.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_otbn.3734616256
Short name	T766
Test name
Test status
Simulation time	4608940586 ps
CPU time	44.27 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:17:05 PM PDT 24
Peak memory	208608 kb
Host	smart-9f2877ee-3c7c-4ed0-b084-7d5bc05fd082
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734616256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3734616256
Directory	/workspace/44.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/44.keymgr_sideload_protect.272200754
Short name	T640
Test name
Test status
Simulation time	36693428 ps
CPU time	2.45 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	209540 kb
Host	smart-30f6df70-0996-4308-99d5-702230679f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272200754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.272200754
Directory	/workspace/44.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/44.keymgr_smoke.3879373733
Short name	T568
Test name
Test status
Simulation time	291934507 ps
CPU time	2.97 seconds
Started	May 25 02:16:03 PM PDT 24
Finished	May 25 02:16:07 PM PDT 24
Peak memory	207860 kb
Host	smart-deaedaf8-196e-4fe7-bc02-37023cc25abc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879373733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3879373733
Directory	/workspace/44.keymgr_smoke/latest

Test location	/workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.207988078
Short name	T817
Test name
Test status
Simulation time	196766404 ps
CPU time	6.14 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	222316 kb
Host	smart-f69ab042-3e22-4d32-a77d-a76b0e344d51
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207988078 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.207988078
Directory	/workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.keymgr_sw_invalid_input.821528876
Short name	T219
Test name
Test status
Simulation time	137006304 ps
CPU time	5.15 seconds
Started	May 25 02:16:11 PM PDT 24
Finished	May 25 02:16:17 PM PDT 24
Peak memory	209024 kb
Host	smart-7d78acb5-4efb-4955-ab9c-24d6026fc9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821528876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.821528876
Directory	/workspace/44.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/44.keymgr_sync_async_fault_cross.1272063017
Short name	T854
Test name
Test status
Simulation time	52349115 ps
CPU time	1.37 seconds
Started	May 25 02:16:12 PM PDT 24
Finished	May 25 02:16:14 PM PDT 24
Peak memory	209420 kb
Host	smart-363357c1-a705-4860-a3d6-07bcff94c393
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272063017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1272063017
Directory	/workspace/44.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/45.keymgr_alert_test.2682788611
Short name	T692
Test name
Test status
Simulation time	16729341 ps
CPU time	0.8 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	205504 kb
Host	smart-c134839c-cd1f-4b04-bb8e-761852ad1d13
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682788611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2682788611
Directory	/workspace/45.keymgr_alert_test/latest

Test location	/workspace/coverage/default/45.keymgr_cfg_regwen.3919246356
Short name	T376
Test name
Test status
Simulation time	644919720 ps
CPU time	2.83 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:23 PM PDT 24
Peak memory	213976 kb
Host	smart-4cb954b0-5146-44a2-8459-37492977c61d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3919246356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3919246356
Directory	/workspace/45.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/45.keymgr_custom_cm.983485958
Short name	T822
Test name
Test status
Simulation time	299470394 ps
CPU time	2.98 seconds
Started	May 25 02:16:12 PM PDT 24
Finished	May 25 02:16:16 PM PDT 24
Peak memory	221392 kb
Host	smart-24350f91-b1b0-431f-94e5-cd80f1eaa7f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983485958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.983485958
Directory	/workspace/45.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/45.keymgr_direct_to_disabled.3679491226
Short name	T44
Test name
Test status
Simulation time	701617027 ps
CPU time	2.12 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	207856 kb
Host	smart-c5d77ec2-f08e-4a90-a2d7-459e07dcd9a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679491226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3679491226
Directory	/workspace/45.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/45.keymgr_hwsw_invalid_input.831787108
Short name	T593
Test name
Test status
Simulation time	107068193 ps
CPU time	4.21 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	217984 kb
Host	smart-bd78d150-8587-4096-a6d0-d9d82e9ff2f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831787108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.831787108
Directory	/workspace/45.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/45.keymgr_lc_disable.2751243616
Short name	T926
Test name
Test status
Simulation time	548240678 ps
CPU time	7.85 seconds
Started	May 25 02:16:16 PM PDT 24
Finished	May 25 02:16:24 PM PDT 24
Peak memory	222208 kb
Host	smart-ea124505-4eb0-4f41-b227-0a67bc869e90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751243616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2751243616
Directory	/workspace/45.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/45.keymgr_random.357711701
Short name	T356
Test name
Test status
Simulation time	76346450 ps
CPU time	3.14 seconds
Started	May 25 02:16:14 PM PDT 24
Finished	May 25 02:16:18 PM PDT 24
Peak memory	206916 kb
Host	smart-3f867a03-9335-4b5a-91cf-a81c53f69cc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357711701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.357711701
Directory	/workspace/45.keymgr_random/latest

Test location	/workspace/coverage/default/45.keymgr_sideload.3480294394
Short name	T252
Test name
Test status
Simulation time	36664663 ps
CPU time	2.18 seconds
Started	May 25 02:16:16 PM PDT 24
Finished	May 25 02:16:19 PM PDT 24
Peak memory	206536 kb
Host	smart-97c1d7c0-7f30-4393-91a9-e5a93b694c0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480294394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3480294394
Directory	/workspace/45.keymgr_sideload/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_aes.3416951042
Short name	T214
Test name
Test status
Simulation time	570626240 ps
CPU time	13.39 seconds
Started	May 25 02:16:16 PM PDT 24
Finished	May 25 02:16:29 PM PDT 24
Peak memory	207576 kb
Host	smart-c19b3097-96ea-4af0-8d84-122243a0ebb8
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416951042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3416951042
Directory	/workspace/45.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_kmac.3218507711
Short name	T876
Test name
Test status
Simulation time	1668669300 ps
CPU time	5.11 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:19 PM PDT 24
Peak memory	206964 kb
Host	smart-e0930275-d48a-44ac-9ad0-3487d8874248
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218507711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3218507711
Directory	/workspace/45.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_otbn.4074485726
Short name	T726
Test name
Test status
Simulation time	69968589 ps
CPU time	3.35 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	208584 kb
Host	smart-23b32322-9283-416e-bbf4-b1d3adef3fd8
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074485726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4074485726
Directory	/workspace/45.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/45.keymgr_sideload_protect.4006342097
Short name	T844
Test name
Test status
Simulation time	51261995 ps
CPU time	2.43 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	208808 kb
Host	smart-9d743130-8b59-495b-8c79-a2fc2a9fda08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006342097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4006342097
Directory	/workspace/45.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/45.keymgr_smoke.3025735720
Short name	T700
Test name
Test status
Simulation time	97358843 ps
CPU time	3.32 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:23 PM PDT 24
Peak memory	208292 kb
Host	smart-b321bf8f-d6e0-47f4-afe6-24e3ac52202b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025735720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3025735720
Directory	/workspace/45.keymgr_smoke/latest

Test location	/workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1205755938
Short name	T223
Test name
Test status
Simulation time	45273178 ps
CPU time	3.26 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:17 PM PDT 24
Peak memory	222408 kb
Host	smart-6715e804-4204-4913-bd90-aee0a11bcae5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205755938 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1205755938
Directory	/workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.keymgr_sw_invalid_input.477247719
Short name	T811
Test name
Test status
Simulation time	1151718965 ps
CPU time	9.09 seconds
Started	May 25 02:16:12 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	207892 kb
Host	smart-5991d8af-5882-4c4e-8200-7a11e442ea66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477247719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.477247719
Directory	/workspace/45.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_alert_test.3040894102
Short name	T709
Test name
Test status
Simulation time	11893820 ps
CPU time	0.74 seconds
Started	May 25 02:16:24 PM PDT 24
Finished	May 25 02:16:25 PM PDT 24
Peak memory	205484 kb
Host	smart-751b013b-3b85-427c-a744-1178af815498
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040894102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3040894102
Directory	/workspace/46.keymgr_alert_test/latest

Test location	/workspace/coverage/default/46.keymgr_direct_to_disabled.3079176841
Short name	T324
Test name
Test status
Simulation time	1548286937 ps
CPU time	43.24 seconds
Started	May 25 02:16:20 PM PDT 24
Finished	May 25 02:17:04 PM PDT 24
Peak memory	208844 kb
Host	smart-612c150f-8b28-418b-bd7a-b72807efb4fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079176841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3079176841
Directory	/workspace/46.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/46.keymgr_hwsw_invalid_input.3971441630
Short name	T913
Test name
Test status
Simulation time	10876936882 ps
CPU time	76.87 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:17:37 PM PDT 24
Peak memory	214100 kb
Host	smart-33e8c64e-9251-439a-ab13-5532afe0d432
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3971441630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3971441630
Directory	/workspace/46.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_kmac_rsp_err.1200346347
Short name	T257
Test name
Test status
Simulation time	951986328 ps
CPU time	8.24 seconds
Started	May 25 02:16:13 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	209848 kb
Host	smart-1e66b504-049a-463b-8a91-3ccb75961a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200346347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1200346347
Directory	/workspace/46.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/46.keymgr_lc_disable.993897369
Short name	T711
Test name
Test status
Simulation time	135685796 ps
CPU time	2.9 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	215592 kb
Host	smart-33e51905-a157-44c5-a525-c7e2992a2d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993897369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.993897369
Directory	/workspace/46.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/46.keymgr_random.24092338
Short name	T249
Test name
Test status
Simulation time	269587989 ps
CPU time	3.59 seconds
Started	May 25 02:16:24 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	207272 kb
Host	smart-40384cf1-0303-49ea-ac5b-c760ff7c6858
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24092338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.24092338
Directory	/workspace/46.keymgr_random/latest

Test location	/workspace/coverage/default/46.keymgr_sideload.6920416
Short name	T584
Test name
Test status
Simulation time	73591618 ps
CPU time	2.98 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:23 PM PDT 24
Peak memory	206480 kb
Host	smart-6edb4c30-c222-46f7-a8fc-b5923f08f8ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6920416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.6920416
Directory	/workspace/46.keymgr_sideload/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_aes.4065658860
Short name	T601
Test name
Test status
Simulation time	102812665 ps
CPU time	3.11 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	206512 kb
Host	smart-c997e30d-0f76-4681-a354-d0e6098faeaf
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065658860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4065658860
Directory	/workspace/46.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_kmac.1502334682
Short name	T973
Test name
Test status
Simulation time	5013488222 ps
CPU time	31.9 seconds
Started	May 25 02:16:33 PM PDT 24
Finished	May 25 02:17:06 PM PDT 24
Peak memory	208576 kb
Host	smart-1203258d-13ec-46aa-8f17-d54b82136362
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502334682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1502334682
Directory	/workspace/46.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_otbn.2444779237
Short name	T722
Test name
Test status
Simulation time	179632963 ps
CPU time	1.9 seconds
Started	May 25 02:16:16 PM PDT 24
Finished	May 25 02:16:19 PM PDT 24
Peak memory	206740 kb
Host	smart-03a7bf93-26ff-4e6a-add0-9f80a6831a45
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444779237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2444779237
Directory	/workspace/46.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/46.keymgr_sideload_protect.1811597092
Short name	T602
Test name
Test status
Simulation time	601123348 ps
CPU time	3.74 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	207360 kb
Host	smart-ff166001-d42b-4cfe-8027-644fa9ed3751
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811597092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1811597092
Directory	/workspace/46.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/46.keymgr_smoke.3895350311
Short name	T585
Test name
Test status
Simulation time	26116724 ps
CPU time	1.83 seconds
Started	May 25 02:16:19 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	208200 kb
Host	smart-6f55561d-c080-4910-af23-096c6383ea97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895350311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3895350311
Directory	/workspace/46.keymgr_smoke/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all.4114521422
Short name	T65
Test name
Test status
Simulation time	4750088749 ps
CPU time	34.35 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:53 PM PDT 24
Peak memory	215308 kb
Host	smart-664c39e6-07c9-484d-a2ce-bff629f1201c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114521422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4114521422
Directory	/workspace/46.keymgr_stress_all/latest

Test location	/workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.230281768
Short name	T787
Test name
Test status
Simulation time	147634758 ps
CPU time	3.31 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	220100 kb
Host	smart-52cfc15a-f1f8-42c5-a1b3-c1ad0d474650
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230281768 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.230281768
Directory	/workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.keymgr_sw_invalid_input.1422250961
Short name	T293
Test name
Test status
Simulation time	478751021 ps
CPU time	9.17 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:27 PM PDT 24
Peak memory	208472 kb
Host	smart-7bbd9d1e-c7e9-4e93-ac2d-880f64f8301c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422250961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1422250961
Directory	/workspace/46.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/46.keymgr_sync_async_fault_cross.539810516
Short name	T571
Test name
Test status
Simulation time	76736327 ps
CPU time	1.61 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:20 PM PDT 24
Peak memory	209584 kb
Host	smart-1a3f7002-cd75-4ba4-959f-8c48c3917ce7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539810516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.539810516
Directory	/workspace/46.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/47.keymgr_alert_test.1946888539
Short name	T1009
Test name
Test status
Simulation time	53933092 ps
CPU time	0.77 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:30 PM PDT 24
Peak memory	205628 kb
Host	smart-aa7e6014-8465-41f0-b7a4-a7fd4380c2ad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946888539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1946888539
Directory	/workspace/47.keymgr_alert_test/latest

Test location	/workspace/coverage/default/47.keymgr_direct_to_disabled.3023187630
Short name	T383
Test name
Test status
Simulation time	143718469 ps
CPU time	4.2 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:23 PM PDT 24
Peak memory	207816 kb
Host	smart-c5979fb9-76ec-496a-b63e-fcf3a2b61e7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023187630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3023187630
Directory	/workspace/47.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/47.keymgr_hwsw_invalid_input.856830188
Short name	T829
Test name
Test status
Simulation time	113729156 ps
CPU time	3.94 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	214048 kb
Host	smart-21364cd6-135c-45c7-bcdd-dcc3b6f5f86e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856830188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.856830188
Directory	/workspace/47.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_lc_disable.3472690210
Short name	T977
Test name
Test status
Simulation time	429766746 ps
CPU time	6.37 seconds
Started	May 25 02:16:18 PM PDT 24
Finished	May 25 02:16:25 PM PDT 24
Peak memory	219668 kb
Host	smart-9de696c6-1e62-49af-8cfb-922c1e793322
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472690210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3472690210
Directory	/workspace/47.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/47.keymgr_random.3817582222
Short name	T857
Test name
Test status
Simulation time	260927247 ps
CPU time	3.73 seconds
Started	May 25 02:16:17 PM PDT 24
Finished	May 25 02:16:21 PM PDT 24
Peak memory	207924 kb
Host	smart-107f1fbb-6dd7-4dea-bb1d-be0f64601028
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817582222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3817582222
Directory	/workspace/47.keymgr_random/latest

Test location	/workspace/coverage/default/47.keymgr_sideload.2210683868
Short name	T335
Test name
Test status
Simulation time	93476659 ps
CPU time	2.07 seconds
Started	May 25 02:16:23 PM PDT 24
Finished	May 25 02:16:25 PM PDT 24
Peak memory	208316 kb
Host	smart-bfe80d98-1497-4ee3-a84c-37da322b5659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210683868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2210683868
Directory	/workspace/47.keymgr_sideload/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_aes.799715265
Short name	T1061
Test name
Test status
Simulation time	275462576 ps
CPU time	6.82 seconds
Started	May 25 02:16:23 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	207656 kb
Host	smart-7a6419e2-52fe-4da3-b40a-ebd6d6faf216
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799715265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.799715265
Directory	/workspace/47.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_kmac.1765165636
Short name	T1008
Test name
Test status
Simulation time	419441338 ps
CPU time	3.64 seconds
Started	May 25 02:16:24 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	206424 kb
Host	smart-c2db1986-f780-4818-ab94-8033ea3c53ed
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765165636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1765165636
Directory	/workspace/47.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_otbn.525956818
Short name	T688
Test name
Test status
Simulation time	973018341 ps
CPU time	3.71 seconds
Started	May 25 02:16:24 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	208556 kb
Host	smart-3d8f2cf0-55c3-4655-90f2-59b86b152295
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525956818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.525956818
Directory	/workspace/47.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/47.keymgr_sideload_protect.748367628
Short name	T389
Test name
Test status
Simulation time	359008905 ps
CPU time	3.77 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:33 PM PDT 24
Peak memory	214040 kb
Host	smart-153d1acc-be54-4190-87b2-6b3c021575de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748367628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.748367628
Directory	/workspace/47.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/47.keymgr_smoke.1699867062
Short name	T604
Test name
Test status
Simulation time	1077376837 ps
CPU time	19.38 seconds
Started	May 25 02:16:11 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	208324 kb
Host	smart-4595e35d-7521-4213-9366-0d8515390eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699867062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1699867062
Directory	/workspace/47.keymgr_smoke/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all.928573842
Short name	T238
Test name
Test status
Simulation time	3632771116 ps
CPU time	36.05 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:17:04 PM PDT 24
Peak memory	216272 kb
Host	smart-be3e4332-28aa-44cd-acee-c35a7135cada
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928573842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.928573842
Directory	/workspace/47.keymgr_stress_all/latest

Test location	/workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.507127779
Short name	T226
Test name
Test status
Simulation time	118817388 ps
CPU time	6.27 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:36 PM PDT 24
Peak memory	222272 kb
Host	smart-2a466abc-447c-40d3-bce8-013f5c2c8c88
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507127779 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.507127779
Directory	/workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.keymgr_sw_invalid_input.834080340
Short name	T289
Test name
Test status
Simulation time	6305473160 ps
CPU time	57.94 seconds
Started	May 25 02:16:22 PM PDT 24
Finished	May 25 02:17:20 PM PDT 24
Peak memory	209024 kb
Host	smart-86ac7a2e-8305-4056-a50a-2cad203cd28f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834080340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.834080340
Directory	/workspace/47.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/47.keymgr_sync_async_fault_cross.1302436472
Short name	T2
Test name
Test status
Simulation time	466951486 ps
CPU time	4.5 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	210852 kb
Host	smart-9ac078d1-2432-423f-a79d-260b48e197f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302436472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1302436472
Directory	/workspace/47.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/48.keymgr_alert_test.582264251
Short name	T831
Test name
Test status
Simulation time	11829473 ps
CPU time	0.89 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:27 PM PDT 24
Peak memory	205588 kb
Host	smart-12407be7-3ce2-4365-ad26-3ab22033af19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582264251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.582264251
Directory	/workspace/48.keymgr_alert_test/latest

Test location	/workspace/coverage/default/48.keymgr_custom_cm.503074156
Short name	T30
Test name
Test status
Simulation time	136316588 ps
CPU time	4.76 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:34 PM PDT 24
Peak memory	217764 kb
Host	smart-86d3b572-7ad2-42c8-bc6d-0ba97f1ecd4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503074156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.503074156
Directory	/workspace/48.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/48.keymgr_direct_to_disabled.1793763916
Short name	T318
Test name
Test status
Simulation time	53637188 ps
CPU time	2.13 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	217928 kb
Host	smart-14c822ed-1083-4353-9906-8b883c5e8937
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793763916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1793763916
Directory	/workspace/48.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/48.keymgr_hwsw_invalid_input.308708489
Short name	T684
Test name
Test status
Simulation time	725782291 ps
CPU time	9.65 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:37 PM PDT 24
Peak memory	219228 kb
Host	smart-f842d5cd-9f02-4027-9752-3f9d0006d0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308708489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.308708489
Directory	/workspace/48.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/48.keymgr_kmac_rsp_err.4230982118
Short name	T339
Test name
Test status
Simulation time	11734114172 ps
CPU time	85.97 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:17:54 PM PDT 24
Peak memory	225820 kb
Host	smart-4464b3b3-df77-486f-9853-71b22ace4446
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230982118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4230982118
Directory	/workspace/48.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/48.keymgr_lc_disable.1418128178
Short name	T635
Test name
Test status
Simulation time	71854614 ps
CPU time	2.02 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:29 PM PDT 24
Peak memory	214328 kb
Host	smart-f5056020-0b11-4f14-b0a2-5a396c757d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418128178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1418128178
Directory	/workspace/48.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/48.keymgr_random.4201308684
Short name	T941
Test name
Test status
Simulation time	2809967471 ps
CPU time	30.22 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:57 PM PDT 24
Peak memory	208604 kb
Host	smart-7696b583-b7a7-4a9a-893e-613af890ed46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201308684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.4201308684
Directory	/workspace/48.keymgr_random/latest

Test location	/workspace/coverage/default/48.keymgr_sideload.1861440292
Short name	T611
Test name
Test status
Simulation time	124765667 ps
CPU time	4.67 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:30 PM PDT 24
Peak memory	208308 kb
Host	smart-8055d1e5-af45-494b-9cb5-4cb9f66bb51a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861440292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1861440292
Directory	/workspace/48.keymgr_sideload/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_aes.598508296
Short name	T960
Test name
Test status
Simulation time	66297626 ps
CPU time	3.33 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:29 PM PDT 24
Peak memory	206616 kb
Host	smart-fb7c5afe-03b0-4636-8a5b-a7adc3fc03ab
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598508296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.598508296
Directory	/workspace/48.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_kmac.1388027441
Short name	T1033
Test name
Test status
Simulation time	486709149 ps
CPU time	6.09 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:35 PM PDT 24
Peak memory	208572 kb
Host	smart-f72efcaa-dabe-45f3-bfed-c39c33ffcc9b
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388027441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1388027441
Directory	/workspace/48.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_otbn.2270494904
Short name	T752
Test name
Test status
Simulation time	3316407413 ps
CPU time	20.96 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:48 PM PDT 24
Peak memory	207892 kb
Host	smart-e806ee50-900e-485d-956a-67410ae63fd9
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270494904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2270494904
Directory	/workspace/48.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/48.keymgr_sideload_protect.1243090048
Short name	T1049
Test name
Test status
Simulation time	175682238 ps
CPU time	2.77 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:29 PM PDT 24
Peak memory	207280 kb
Host	smart-1bfed2c5-a301-4ecf-a56f-139bfd5b40f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243090048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1243090048
Directory	/workspace/48.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/48.keymgr_smoke.2810857868
Short name	T405
Test name
Test status
Simulation time	65631833 ps
CPU time	2.77 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	208628 kb
Host	smart-98ab3ab0-f2c8-4ceb-a001-caedf6361d63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2810857868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2810857868
Directory	/workspace/48.keymgr_smoke/latest

Test location	/workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3599797771
Short name	T228
Test name
Test status
Simulation time	1024850199 ps
CPU time	8.27 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:38 PM PDT 24
Peak memory	222344 kb
Host	smart-4ce447c7-b79d-42ce-ae07-7935076dac73
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599797771 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3599797771
Directory	/workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.keymgr_sw_invalid_input.2796538570
Short name	T962
Test name
Test status
Simulation time	625998433 ps
CPU time	9 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:35 PM PDT 24
Peak memory	207820 kb
Host	smart-ccae5546-7ea8-4b6d-8ece-23451aacb100
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796538570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2796538570
Directory	/workspace/48.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/48.keymgr_sync_async_fault_cross.1418034259
Short name	T581
Test name
Test status
Simulation time	141282241 ps
CPU time	2.72 seconds
Started	May 25 02:16:25 PM PDT 24
Finished	May 25 02:16:28 PM PDT 24
Peak memory	209916 kb
Host	smart-4387572f-9081-421b-be34-7d4cf3e0aa18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418034259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1418034259
Directory	/workspace/48.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/49.keymgr_alert_test.810411133
Short name	T985
Test name
Test status
Simulation time	50278714 ps
CPU time	0.77 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:30 PM PDT 24
Peak memory	205564 kb
Host	smart-b3984a55-47ff-46ff-be35-12789b7001cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810411133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.810411133
Directory	/workspace/49.keymgr_alert_test/latest

Test location	/workspace/coverage/default/49.keymgr_direct_to_disabled.1960349494
Short name	T882
Test name
Test status
Simulation time	377499561 ps
CPU time	11.6 seconds
Started	May 25 02:16:35 PM PDT 24
Finished	May 25 02:16:47 PM PDT 24
Peak memory	208948 kb
Host	smart-8b8b0390-b41c-409b-89c1-1ffe8e8ad797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960349494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1960349494
Directory	/workspace/49.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/49.keymgr_lc_disable.3873959097
Short name	T736
Test name
Test status
Simulation time	43845094 ps
CPU time	3.17 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:33 PM PDT 24
Peak memory	218448 kb
Host	smart-8e7cab20-f083-41a1-b2cb-501ddf0cc8f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873959097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3873959097
Directory	/workspace/49.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/49.keymgr_random.1974194949
Short name	T599
Test name
Test status
Simulation time	51155804 ps
CPU time	3.13 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:33 PM PDT 24
Peak memory	206592 kb
Host	smart-ac2af6d3-ec31-4890-a2f9-65fffe8b5366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974194949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1974194949
Directory	/workspace/49.keymgr_random/latest

Test location	/workspace/coverage/default/49.keymgr_sideload.1022190349
Short name	T796
Test name
Test status
Simulation time	253713512 ps
CPU time	3.32 seconds
Started	May 25 02:16:28 PM PDT 24
Finished	May 25 02:16:33 PM PDT 24
Peak memory	207084 kb
Host	smart-c1035d8b-9255-47c9-aac0-6b93d02d80ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022190349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1022190349
Directory	/workspace/49.keymgr_sideload/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_aes.148453995
Short name	T884
Test name
Test status
Simulation time	73807999 ps
CPU time	3.45 seconds
Started	May 25 02:16:29 PM PDT 24
Finished	May 25 02:16:34 PM PDT 24
Peak memory	208368 kb
Host	smart-afa9dadc-2139-40c8-93e4-852ee045a9f3
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148453995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.148453995
Directory	/workspace/49.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_otbn.319274355
Short name	T253
Test name
Test status
Simulation time	2394024230 ps
CPU time	27.14 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:56 PM PDT 24
Peak memory	208292 kb
Host	smart-a10bfaa6-48e5-4667-99b1-f77d6f144c18
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319274355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.319274355
Directory	/workspace/49.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/49.keymgr_sideload_protect.3066532619
Short name	T897
Test name
Test status
Simulation time	657090214 ps
CPU time	2.76 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:16:31 PM PDT 24
Peak memory	215312 kb
Host	smart-f1f54e78-4010-479d-81d5-6fb1c65fb6b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066532619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3066532619
Directory	/workspace/49.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/49.keymgr_smoke.282711596
Short name	T578
Test name
Test status
Simulation time	293206249 ps
CPU time	2.45 seconds
Started	May 25 02:16:26 PM PDT 24
Finished	May 25 02:16:30 PM PDT 24
Peak memory	206596 kb
Host	smart-ac7686e4-9cd7-4f7b-a74f-c8590f69bf31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282711596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.282711596
Directory	/workspace/49.keymgr_smoke/latest

Test location	/workspace/coverage/default/49.keymgr_stress_all.2298240610
Short name	T245
Test name
Test status
Simulation time	6774818735 ps
CPU time	206.05 seconds
Started	May 25 02:16:27 PM PDT 24
Finished	May 25 02:19:55 PM PDT 24
Peak memory	222200 kb
Host	smart-6a74f901-f569-4ed8-a842-d9e7cba6e66c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298240610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2298240610
Directory	/workspace/49.keymgr_stress_all/latest

Test location	/workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.769122642
Short name	T1010
Test name
Test status
Simulation time	219065395 ps
CPU time	6.71 seconds
Started	May 25 02:16:32 PM PDT 24
Finished	May 25 02:16:40 PM PDT 24
Peak memory	222256 kb
Host	smart-4c9715b4-b13e-492d-8b33-166b2a7af598
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769122642 -assert nopost proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.769122642
Directory	/workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.keymgr_sw_invalid_input.115577717
Short name	T657
Test name
Test status
Simulation time	131418631 ps
CPU time	5.05 seconds
Started	May 25 02:16:29 PM PDT 24
Finished	May 25 02:16:35 PM PDT 24
Peak memory	218124 kb
Host	smart-547f4fb2-6dbe-442f-9145-8618efdb3e96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115577717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.115577717
Directory	/workspace/49.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/49.keymgr_sync_async_fault_cross.2625801382
Short name	T762
Test name
Test status
Simulation time	68428834 ps
CPU time	2.5 seconds
Started	May 25 02:16:31 PM PDT 24
Finished	May 25 02:16:34 PM PDT 24
Peak memory	209952 kb
Host	smart-2f6111cd-3c8f-4446-8017-d1b010a95f1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625801382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2625801382
Directory	/workspace/49.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/5.keymgr_alert_test.1790462842
Short name	T597
Test name
Test status
Simulation time	26007064 ps
CPU time	0.73 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	205468 kb
Host	smart-9ecaaa7c-00c4-4e5f-b6cf-da517895f1dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790462842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1790462842
Directory	/workspace/5.keymgr_alert_test/latest

Test location	/workspace/coverage/default/5.keymgr_cfg_regwen.585723044
Short name	T432
Test name
Test status
Simulation time	80101308 ps
CPU time	2.95 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	215016 kb
Host	smart-7254099a-04e8-4a57-8bac-4f86d5200e32
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=585723044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.585723044
Directory	/workspace/5.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/5.keymgr_custom_cm.478621025
Short name	T26
Test name
Test status
Simulation time	51164146 ps
CPU time	3.06 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	210328 kb
Host	smart-dd518c36-4bf2-4c47-8023-f2b2d9d38824
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478621025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.478621025
Directory	/workspace/5.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/5.keymgr_direct_to_disabled.1698105133
Short name	T924
Test name
Test status
Simulation time	387501618 ps
CPU time	1.95 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	207968 kb
Host	smart-21e5c582-7120-4e8e-a38d-d86923082971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698105133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1698105133
Directory	/workspace/5.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/5.keymgr_hwsw_invalid_input.3918902524
Short name	T689
Test name
Test status
Simulation time	1286358048 ps
CPU time	27.68 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	214036 kb
Host	smart-45aff9a3-d749-457c-a1f1-4b8680414ea3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918902524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3918902524
Directory	/workspace/5.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_lc_disable.3796570346
Short name	T47
Test name
Test status
Simulation time	188253923 ps
CPU time	6.15 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	214664 kb
Host	smart-595cac14-ebe7-4b66-bacd-2ee4b4d10944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796570346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3796570346
Directory	/workspace/5.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/5.keymgr_random.1992847998
Short name	T728
Test name
Test status
Simulation time	93357431 ps
CPU time	4.46 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	207988 kb
Host	smart-ab3c1da6-d637-49af-a45c-327331cdb3d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992847998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1992847998
Directory	/workspace/5.keymgr_random/latest

Test location	/workspace/coverage/default/5.keymgr_sideload.2892278695
Short name	T141
Test name
Test status
Simulation time	59330607 ps
CPU time	2.95 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	207024 kb
Host	smart-da73ca4d-af5b-49b1-a1eb-0de11b571519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892278695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2892278695
Directory	/workspace/5.keymgr_sideload/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_aes.805301702
Short name	T287
Test name
Test status
Simulation time	475947513 ps
CPU time	3.84 seconds
Started	May 25 02:13:53 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	208272 kb
Host	smart-ed4b3ef6-0376-453d-aac3-1a6e4668bad7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805301702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.805301702
Directory	/workspace/5.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_kmac.4125589744
Short name	T586
Test name
Test status
Simulation time	87947180 ps
CPU time	3.84 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	208472 kb
Host	smart-da6dc3f8-cf42-4f97-b69e-fa946f001bbc
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125589744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4125589744
Directory	/workspace/5.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_otbn.2010505450
Short name	T365
Test name
Test status
Simulation time	199160702 ps
CPU time	5.49 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	208156 kb
Host	smart-48f65bd5-2ac4-41d1-a068-de05d313c976
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010505450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2010505450
Directory	/workspace/5.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/5.keymgr_sideload_protect.414174736
Short name	T425
Test name
Test status
Simulation time	271013164 ps
CPU time	3.35 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	208460 kb
Host	smart-05b09a44-d985-4131-a51b-d8f6eaab6378
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414174736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.414174736
Directory	/workspace/5.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/5.keymgr_smoke.1258313599
Short name	T837
Test name
Test status
Simulation time	196037933 ps
CPU time	2.79 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:14:00 PM PDT 24
Peak memory	205792 kb
Host	smart-c05b14b7-868a-466e-809a-c6aef54d361f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258313599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1258313599
Directory	/workspace/5.keymgr_smoke/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all.91533388
Short name	T1022
Test name
Test status
Simulation time	8875668149 ps
CPU time	216.75 seconds
Started	May 25 02:13:57 PM PDT 24
Finished	May 25 02:17:35 PM PDT 24
Peak memory	216808 kb
Host	smart-50ee6e5c-4b98-47dd-bc96-06d24f2c8e7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91533388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.91533388
Directory	/workspace/5.keymgr_stress_all/latest

Test location	/workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2434595637
Short name	T899
Test name
Test status
Simulation time	228111072 ps
CPU time	6.95 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:14:03 PM PDT 24
Peak memory	222588 kb
Host	smart-5dd228bc-9a7a-4c49-b7e2-211f70d3461f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434595637 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2434595637
Directory	/workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.keymgr_sw_invalid_input.4044651419
Short name	T733
Test name
Test status
Simulation time	2421415007 ps
CPU time	66.54 seconds
Started	May 25 02:13:56 PM PDT 24
Finished	May 25 02:15:04 PM PDT 24
Peak memory	208968 kb
Host	smart-cd6e1ba4-e5d5-491b-b1d2-18da169e5689
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044651419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4044651419
Directory	/workspace/5.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/5.keymgr_sync_async_fault_cross.2665207304
Short name	T180
Test name
Test status
Simulation time	74057249 ps
CPU time	1.51 seconds
Started	May 25 02:13:54 PM PDT 24
Finished	May 25 02:13:57 PM PDT 24
Peak memory	209620 kb
Host	smart-f11d95f4-4a38-4ac2-86cb-a420d6e40bc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665207304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2665207304
Directory	/workspace/5.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/6.keymgr_alert_test.4214167661
Short name	T105
Test name
Test status
Simulation time	16576774 ps
CPU time	0.78 seconds
Started	May 25 02:14:04 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	205596 kb
Host	smart-6536cc69-bf4a-4d75-a71e-21ce3a2e24a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214167661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4214167661
Directory	/workspace/6.keymgr_alert_test/latest

Test location	/workspace/coverage/default/6.keymgr_cfg_regwen.4221181624
Short name	T258
Test name
Test status
Simulation time	4500405066 ps
CPU time	119.87 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:16:03 PM PDT 24
Peak memory	215008 kb
Host	smart-d00c3ff7-8f8a-4280-8787-d5d42ed1a97a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4221181624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4221181624
Directory	/workspace/6.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/6.keymgr_custom_cm.3068617075
Short name	T20
Test name
Test status
Simulation time	348425299 ps
CPU time	4.49 seconds
Started	May 25 02:14:03 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	216368 kb
Host	smart-8806d294-b15d-48f2-bcae-e02e5017e430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068617075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3068617075
Directory	/workspace/6.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/6.keymgr_direct_to_disabled.4072137675
Short name	T74
Test name
Test status
Simulation time	77432410 ps
CPU time	2.46 seconds
Started	May 25 02:14:04 PM PDT 24
Finished	May 25 02:14:07 PM PDT 24
Peak memory	208468 kb
Host	smart-f67838cb-3d40-4216-a749-ec3384a8793e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072137675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4072137675
Directory	/workspace/6.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/6.keymgr_hwsw_invalid_input.1003169698
Short name	T732
Test name
Test status
Simulation time	241820535 ps
CPU time	4.62 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	207920 kb
Host	smart-f0d62bf1-5af6-4b77-b654-224880f1c524
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003169698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1003169698
Directory	/workspace/6.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/6.keymgr_lc_disable.7916949
Short name	T995
Test name
Test status
Simulation time	102125796 ps
CPU time	3.57 seconds
Started	May 25 02:14:09 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	207944 kb
Host	smart-c19aa5c2-eae8-432a-af37-50f7a0b13127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7916949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.7916949
Directory	/workspace/6.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/6.keymgr_random.2278920026
Short name	T291
Test name
Test status
Simulation time	1510277413 ps
CPU time	9.87 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:10 PM PDT 24
Peak memory	207700 kb
Host	smart-eb36ac93-8764-4c16-aeea-6f277bb390e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278920026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2278920026
Directory	/workspace/6.keymgr_random/latest

Test location	/workspace/coverage/default/6.keymgr_sideload.1212525180
Short name	T649
Test name
Test status
Simulation time	11620282195 ps
CPU time	30.12 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:14:27 PM PDT 24
Peak memory	208464 kb
Host	smart-4eab7c0e-af88-4c13-9273-34ecc872e63f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212525180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1212525180
Directory	/workspace/6.keymgr_sideload/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_aes.1606309606
Short name	T600
Test name
Test status
Simulation time	129416451 ps
CPU time	4.2 seconds
Started	May 25 02:14:01 PM PDT 24
Finished	May 25 02:14:07 PM PDT 24
Peak memory	206620 kb
Host	smart-5492ae5e-7933-499b-9b1e-5952601a7735
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606309606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1606309606
Directory	/workspace/6.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_kmac.1420419191
Short name	T330
Test name
Test status
Simulation time	193223073 ps
CPU time	5.56 seconds
Started	May 25 02:13:52 PM PDT 24
Finished	May 25 02:13:58 PM PDT 24
Peak memory	208160 kb
Host	smart-831de5fc-81a9-4249-9c09-001783fcf742
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420419191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1420419191
Directory	/workspace/6.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_otbn.1649351652
Short name	T654
Test name
Test status
Simulation time	94644575 ps
CPU time	4.43 seconds
Started	May 25 02:14:03 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	208696 kb
Host	smart-92f351b3-bd88-4e96-a430-4d18727bb091
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649351652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1649351652
Directory	/workspace/6.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/6.keymgr_sideload_protect.395378777
Short name	T763
Test name
Test status
Simulation time	169581893 ps
CPU time	3.92 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:12 PM PDT 24
Peak memory	208676 kb
Host	smart-e351e4cd-36fa-48a0-a5b5-366058c3f64b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395378777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.395378777
Directory	/workspace/6.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/6.keymgr_smoke.2191097127
Short name	T583
Test name
Test status
Simulation time	21727676 ps
CPU time	1.8 seconds
Started	May 25 02:13:55 PM PDT 24
Finished	May 25 02:13:59 PM PDT 24
Peak memory	206440 kb
Host	smart-7d01b444-909f-4538-bc28-14f6fbafc7a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191097127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2191097127
Directory	/workspace/6.keymgr_smoke/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all.4268846270
Short name	T312
Test name
Test status
Simulation time	4521086433 ps
CPU time	126.37 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:16:15 PM PDT 24
Peak memory	220932 kb
Host	smart-7d9fa47b-b240-44a7-822b-845bbfa55b56
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268846270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4268846270
Directory	/workspace/6.keymgr_stress_all/latest

Test location	/workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3047773122
Short name	T233
Test name
Test status
Simulation time	613110470 ps
CPU time	6.87 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:15 PM PDT 24
Peak memory	222348 kb
Host	smart-032b63f1-41ec-4d96-96b9-a0732a3720f5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047773122 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3047773122
Directory	/workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.keymgr_sw_invalid_input.1514864545
Short name	T894
Test name
Test status
Simulation time	1758613958 ps
CPU time	5.41 seconds
Started	May 25 02:14:13 PM PDT 24
Finished	May 25 02:14:19 PM PDT 24
Peak memory	206812 kb
Host	smart-7c24480a-1fc0-450c-bb83-91278a486775
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514864545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1514864545
Directory	/workspace/6.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_alert_test.1729568023
Short name	T3
Test name
Test status
Simulation time	12423989 ps
CPU time	0.73 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:01 PM PDT 24
Peak memory	205640 kb
Host	smart-2c979c9f-b96e-4abd-a185-f17b23b2c2da
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729568023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1729568023
Directory	/workspace/7.keymgr_alert_test/latest

Test location	/workspace/coverage/default/7.keymgr_cfg_regwen.3365438502
Short name	T381
Test name
Test status
Simulation time	192038365 ps
CPU time	2.93 seconds
Started	May 25 02:14:00 PM PDT 24
Finished	May 25 02:14:04 PM PDT 24
Peak memory	214072 kb
Host	smart-31170d37-39be-4689-b843-eaecbbd494cb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3365438502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3365438502
Directory	/workspace/7.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/7.keymgr_direct_to_disabled.2260582400
Short name	T255
Test name
Test status
Simulation time	121473614 ps
CPU time	2.29 seconds
Started	May 25 02:14:13 PM PDT 24
Finished	May 25 02:14:16 PM PDT 24
Peak memory	209384 kb
Host	smart-b4a6d591-069f-4f41-9c28-e0e403bd6317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260582400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2260582400
Directory	/workspace/7.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/7.keymgr_hwsw_invalid_input.3724055857
Short name	T907
Test name
Test status
Simulation time	224990106 ps
CPU time	5.18 seconds
Started	May 25 02:14:12 PM PDT 24
Finished	May 25 02:14:17 PM PDT 24
Peak memory	208820 kb
Host	smart-0e2c98bf-9ae8-4a01-a3b1-0e7e31795a81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724055857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3724055857
Directory	/workspace/7.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_lc_disable.2508983143
Short name	T1042
Test name
Test status
Simulation time	71210301 ps
CPU time	5.06 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:14:13 PM PDT 24
Peak memory	218784 kb
Host	smart-baf83385-555f-417e-a59e-230a2c2e1494
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508983143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2508983143
Directory	/workspace/7.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/7.keymgr_random.2430607896
Short name	T374
Test name
Test status
Simulation time	606484107 ps
CPU time	4.72 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	207236 kb
Host	smart-343b336a-16ac-4a36-b11a-5be9456bb240
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430607896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2430607896
Directory	/workspace/7.keymgr_random/latest

Test location	/workspace/coverage/default/7.keymgr_sideload.417620969
Short name	T388
Test name
Test status
Simulation time	80938066 ps
CPU time	1.77 seconds
Started	May 25 02:14:03 PM PDT 24
Finished	May 25 02:14:05 PM PDT 24
Peak memory	206632 kb
Host	smart-dec0ed6a-3866-4e74-b111-eb6b782a2f81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417620969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.417620969
Directory	/workspace/7.keymgr_sideload/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_aes.54511213
Short name	T898
Test name
Test status
Simulation time	1006774276 ps
CPU time	7.16 seconds
Started	May 25 02:14:04 PM PDT 24
Finished	May 25 02:14:11 PM PDT 24
Peak memory	208424 kb
Host	smart-ab7d8dc3-ff98-4875-9b26-4709967454b7
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54511213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.54511213
Directory	/workspace/7.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_kmac.1577193013
Short name	T987
Test name
Test status
Simulation time	386883452 ps
CPU time	5.35 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	208484 kb
Host	smart-ce148a36-c686-410b-987a-480bec3afb89
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577193013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1577193013
Directory	/workspace/7.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_otbn.686851756
Short name	T143
Test name
Test status
Simulation time	992283316 ps
CPU time	8.3 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:14:16 PM PDT 24
Peak memory	208324 kb
Host	smart-5802f49f-288d-40d2-856e-941cdfac8dc7
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686851756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.686851756
Directory	/workspace/7.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/7.keymgr_sideload_protect.4090860370
Short name	T618
Test name
Test status
Simulation time	606043271 ps
CPU time	13.01 seconds
Started	May 25 02:14:06 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	208156 kb
Host	smart-4629c730-76f8-4add-93f3-fc5a48175148
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090860370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4090860370
Directory	/workspace/7.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/7.keymgr_smoke.2730487220
Short name	T596
Test name
Test status
Simulation time	301677323 ps
CPU time	5.09 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:08 PM PDT 24
Peak memory	206320 kb
Host	smart-947ea7a8-489f-40e8-bd71-224435a9b60b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730487220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2730487220
Directory	/workspace/7.keymgr_smoke/latest

Test location	/workspace/coverage/default/7.keymgr_stress_all.4097925685
Short name	T603
Test name
Test status
Simulation time	67376124 ps
CPU time	3.12 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:11 PM PDT 24
Peak memory	206920 kb
Host	smart-d59e413d-bf34-4c60-9283-19c93b284bf6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097925685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4097925685
Directory	/workspace/7.keymgr_stress_all/latest

Test location	/workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3319299930
Short name	T953
Test name
Test status
Simulation time	1859403219 ps
CPU time	5.32 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:14:12 PM PDT 24
Peak memory	222260 kb
Host	smart-5b1ddfae-f803-4819-b7aa-d4df3ffb5443
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319299930 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3319299930
Directory	/workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.keymgr_sw_invalid_input.4232433777
Short name	T661
Test name
Test status
Simulation time	8435280258 ps
CPU time	61.71 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:15:09 PM PDT 24
Peak memory	208180 kb
Host	smart-aa0ec332-2a76-47d5-bfe9-0cb80ae7f404
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232433777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4232433777
Directory	/workspace/7.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/7.keymgr_sync_async_fault_cross.2042236782
Short name	T910
Test name
Test status
Simulation time	128089912 ps
CPU time	1.79 seconds
Started	May 25 02:14:07 PM PDT 24
Finished	May 25 02:14:09 PM PDT 24
Peak memory	209664 kb
Host	smart-42e8d9f8-4af0-4f56-b445-5daf580d1c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042236782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2042236782
Directory	/workspace/7.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/8.keymgr_alert_test.1031007936
Short name	T1000
Test name
Test status
Simulation time	34591751 ps
CPU time	0.7 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:17 PM PDT 24
Peak memory	205504 kb
Host	smart-3ff02494-a324-40a7-8570-e00b484dd470
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031007936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1031007936
Directory	/workspace/8.keymgr_alert_test/latest

Test location	/workspace/coverage/default/8.keymgr_direct_to_disabled.3901613501
Short name	T998
Test name
Test status
Simulation time	250534365 ps
CPU time	2.43 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	206944 kb
Host	smart-934a8deb-ef22-4760-b581-7c6a8ec8a29c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901613501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3901613501
Directory	/workspace/8.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/8.keymgr_hwsw_invalid_input.2277734148
Short name	T344
Test name
Test status
Simulation time	69753029 ps
CPU time	4.13 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	220104 kb
Host	smart-a4ef74e1-7334-4670-bcd9-dfa3cc67f91b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2277734148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2277734148
Directory	/workspace/8.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_kmac_rsp_err.1679762479
Short name	T275
Test name
Test status
Simulation time	3627843825 ps
CPU time	37.41 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:55 PM PDT 24
Peak memory	222116 kb
Host	smart-b6f91431-0a71-4b5f-b342-71e49d7a46e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679762479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1679762479
Directory	/workspace/8.keymgr_kmac_rsp_err/latest

Test location	/workspace/coverage/default/8.keymgr_lc_disable.223226401
Short name	T427
Test name
Test status
Simulation time	66104172 ps
CPU time	3.93 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	208760 kb
Host	smart-9f041ed4-ec30-40ba-960a-c6dea817a782
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223226401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.223226401
Directory	/workspace/8.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/8.keymgr_random.4186750202
Short name	T197
Test name
Test status
Simulation time	400692299 ps
CPU time	4.16 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	209240 kb
Host	smart-8529b2f6-b64d-4719-bf0f-54566e537ea4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186750202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4186750202
Directory	/workspace/8.keymgr_random/latest

Test location	/workspace/coverage/default/8.keymgr_sideload.2288555639
Short name	T965
Test name
Test status
Simulation time	132175360 ps
CPU time	5.35 seconds
Started	May 25 02:14:08 PM PDT 24
Finished	May 25 02:14:14 PM PDT 24
Peak memory	207924 kb
Host	smart-61518409-1cb1-45b3-b84c-9a236ac5b18b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288555639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2288555639
Directory	/workspace/8.keymgr_sideload/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_aes.1149312326
Short name	T1051
Test name
Test status
Simulation time	50590319 ps
CPU time	2.23 seconds
Started	May 25 02:14:06 PM PDT 24
Finished	May 25 02:14:09 PM PDT 24
Peak memory	208160 kb
Host	smart-a362ebd7-fe56-488b-83f3-8d7a29d8f60d
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149312326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1149312326
Directory	/workspace/8.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_kmac.2268458708
Short name	T652
Test name
Test status
Simulation time	217724569 ps
CPU time	8.5 seconds
Started	May 25 02:14:02 PM PDT 24
Finished	May 25 02:14:11 PM PDT 24
Peak memory	206488 kb
Host	smart-03b18762-92d9-4de2-bd02-c2983cf7c792
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268458708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2268458708
Directory	/workspace/8.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_otbn.1125166496
Short name	T870
Test name
Test status
Simulation time	40472466 ps
CPU time	2.47 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:18 PM PDT 24
Peak memory	208052 kb
Host	smart-c63f6300-8c47-4823-adfe-5a444bad2806
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125166496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1125166496
Directory	/workspace/8.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/8.keymgr_sideload_protect.3918837101
Short name	T259
Test name
Test status
Simulation time	210706724 ps
CPU time	4.6 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	217992 kb
Host	smart-3ab8018f-6420-462a-92a9-6efff0e77ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918837101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3918837101
Directory	/workspace/8.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/8.keymgr_smoke.678057296
Short name	T592
Test name
Test status
Simulation time	2420472097 ps
CPU time	3.4 seconds
Started	May 25 02:14:09 PM PDT 24
Finished	May 25 02:14:13 PM PDT 24
Peak memory	208124 kb
Host	smart-aab74e2e-1d07-45c2-b759-7bf1995340df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=678057296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.678057296
Directory	/workspace/8.keymgr_smoke/latest

Test location	/workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1588966684
Short name	T742
Test name
Test status
Simulation time	653480043 ps
CPU time	9.85 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:28 PM PDT 24
Peak memory	222328 kb
Host	smart-90626945-c5e3-41c5-990e-4dfd4ace610e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588966684 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1588966684
Directory	/workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.keymgr_sw_invalid_input.3317696916
Short name	T818
Test name
Test status
Simulation time	104517407 ps
CPU time	3.39 seconds
Started	May 25 02:14:22 PM PDT 24
Finished	May 25 02:14:26 PM PDT 24
Peak memory	207380 kb
Host	smart-2e4467f0-a895-48ba-ad03-477651c8ebe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317696916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3317696916
Directory	/workspace/8.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/8.keymgr_sync_async_fault_cross.1834112254
Short name	T719
Test name
Test status
Simulation time	55829049 ps
CPU time	1.97 seconds
Started	May 25 02:14:20 PM PDT 24
Finished	May 25 02:14:23 PM PDT 24
Peak memory	209964 kb
Host	smart-4d09892e-d76e-4687-b7a0-f3f3825c2e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834112254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1834112254
Directory	/workspace/8.keymgr_sync_async_fault_cross/latest

Test location	/workspace/coverage/default/9.keymgr_alert_test.2862826860
Short name	T991
Test name
Test status
Simulation time	62404786 ps
CPU time	0.85 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:19 PM PDT 24
Peak memory	205640 kb
Host	smart-9a20b0b0-c2da-48a7-906b-5da11c42829b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862826860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2862826860
Directory	/workspace/9.keymgr_alert_test/latest

Test location	/workspace/coverage/default/9.keymgr_cfg_regwen.2937069296
Short name	T302
Test name
Test status
Simulation time	1674211551 ps
CPU time	15.92 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:34 PM PDT 24
Peak memory	214876 kb
Host	smart-962171b1-a3be-45e4-8cfb-091b1362bcdf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2937069296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2937069296
Directory	/workspace/9.keymgr_cfg_regwen/latest

Test location	/workspace/coverage/default/9.keymgr_custom_cm.3004055502
Short name	T1043
Test name
Test status
Simulation time	335792788 ps
CPU time	2.9 seconds
Started	May 25 02:14:22 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	208492 kb
Host	smart-fcbb9d5c-0a4f-42fa-8285-41249708b5c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004055502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3004055502
Directory	/workspace/9.keymgr_custom_cm/latest

Test location	/workspace/coverage/default/9.keymgr_direct_to_disabled.4013955794
Short name	T1029
Test name
Test status
Simulation time	397757326 ps
CPU time	2.99 seconds
Started	May 25 02:14:22 PM PDT 24
Finished	May 25 02:14:25 PM PDT 24
Peak memory	208060 kb
Host	smart-b0cd8150-ae04-4386-8013-974248caf98a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013955794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4013955794
Directory	/workspace/9.keymgr_direct_to_disabled/latest

Test location	/workspace/coverage/default/9.keymgr_hwsw_invalid_input.3363841612
Short name	T393
Test name
Test status
Simulation time	604121522 ps
CPU time	4.54 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	207856 kb
Host	smart-b367c864-0fcc-4d5d-926a-e10151933a06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363841612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3363841612
Directory	/workspace/9.keymgr_hwsw_invalid_input/latest

Test location	/workspace/coverage/default/9.keymgr_lc_disable.2093207861
Short name	T40
Test name
Test status
Simulation time	185423306 ps
CPU time	4.48 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	209676 kb
Host	smart-50ff0565-88e5-48f0-b57d-75d509422511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093207861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2093207861
Directory	/workspace/9.keymgr_lc_disable/latest

Test location	/workspace/coverage/default/9.keymgr_random.3207469277
Short name	T284
Test name
Test status
Simulation time	194801611 ps
CPU time	4.39 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	217960 kb
Host	smart-1eb9f5ba-1e2e-4d2e-9486-1f187360294e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207469277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3207469277
Directory	/workspace/9.keymgr_random/latest

Test location	/workspace/coverage/default/9.keymgr_sideload.399396482
Short name	T886
Test name
Test status
Simulation time	780301600 ps
CPU time	2.86 seconds
Started	May 25 02:14:18 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	208104 kb
Host	smart-9e13dac1-9275-4739-a61c-24eebbd311fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399396482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.399396482
Directory	/workspace/9.keymgr_sideload/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_aes.2877083899
Short name	T261
Test name
Test status
Simulation time	124811355 ps
CPU time	3.66 seconds
Started	May 25 02:14:16 PM PDT 24
Finished	May 25 02:14:21 PM PDT 24
Peak memory	208188 kb
Host	smart-4697524a-3807-4490-961d-7e49f94cd5e2
User	root
Command	/workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877083899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2877083899
Directory	/workspace/9.keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_kmac.1959832463
Short name	T824
Test name
Test status
Simulation time	24606968 ps
CPU time	1.97 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:20 PM PDT 24
Peak memory	206540 kb
Host	smart-3d29bec6-c04c-4479-a8be-6a9fbf136a8c
User	root
Command	/workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959832463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1959832463
Directory	/workspace/9.keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_otbn.854725413
Short name	T904
Test name
Test status
Simulation time	100902909 ps
CPU time	3.39 seconds
Started	May 25 02:14:14 PM PDT 24
Finished	May 25 02:14:18 PM PDT 24
Peak memory	208036 kb
Host	smart-2b36ebb6-3464-4c36-91ff-f5e62fa35bfc
User	root
Command	/workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854725413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.854725413
Directory	/workspace/9.keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/9.keymgr_sideload_protect.3416092523
Short name	T1044
Test name
Test status
Simulation time	251311056 ps
CPU time	2.87 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:18 PM PDT 24
Peak memory	209836 kb
Host	smart-5992879f-a073-4cf1-a294-716ff6addfe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416092523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3416092523
Directory	/workspace/9.keymgr_sideload_protect/latest

Test location	/workspace/coverage/default/9.keymgr_smoke.1614339052
Short name	T116
Test name
Test status
Simulation time	96865975 ps
CPU time	3.6 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	208240 kb
Host	smart-609ba0f0-841a-4a2b-8c4e-9e9f5b932025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614339052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1614339052
Directory	/workspace/9.keymgr_smoke/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all.2081249835
Short name	T72
Test name
Test status
Simulation time	23964399240 ps
CPU time	127.94 seconds
Started	May 25 02:14:14 PM PDT 24
Finished	May 25 02:16:22 PM PDT 24
Peak memory	215976 kb
Host	smart-a958723e-bce7-4af6-805b-b135fe9cca76
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081249835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2081249835
Directory	/workspace/9.keymgr_stress_all/latest

Test location	/workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1419117242
Short name	T966
Test name
Test status
Simulation time	730551099 ps
CPU time	8.12 seconds
Started	May 25 02:14:15 PM PDT 24
Finished	May 25 02:14:24 PM PDT 24
Peak memory	222360 kb
Host	smart-1ea328df-459b-4952-9e66-86a457fa4014
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419117242 -assert nopos tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1419117242
Directory	/workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.keymgr_sw_invalid_input.3322518133
Short name	T720
Test name
Test status
Simulation time	3711623645 ps
CPU time	8.07 seconds
Started	May 25 02:14:17 PM PDT 24
Finished	May 25 02:14:26 PM PDT 24
Peak memory	217880 kb
Host	smart-fe4ec657-312b-44a2-ae7f-f26c9354cf5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322518133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3322518133
Directory	/workspace/9.keymgr_sw_invalid_input/latest

Test location	/workspace/coverage/default/9.keymgr_sync_async_fault_cross.4283358256
Short name	T61
Test name
Test status
Simulation time	93046747 ps
CPU time	1.85 seconds
Started	May 25 02:14:19 PM PDT 24
Finished	May 25 02:14:22 PM PDT 24
Peak memory	209432 kb
Host	smart-558d984d-4e63-4e2d-95f0-ab69890fe81d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283358256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4283358256
Directory	/workspace/9.keymgr_sync_async_fault_cross/latest