Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
76.19 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 0 14 100.00
Crosses 49 15 34 69.39


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 0 5 100.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 14 21 60.00 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 91 1 T7 1 T46 1 T47 1
auto[OpGenId] 15 1 T53 1 T104 1 T227 1
auto[OpGenSwOut] 33 1 T104 2 T70 1 T228 1
auto[OpGenHwOut] 20 1 T7 1 T104 2 T229 1
auto[OpDisable] 1 1 T230 1 - - - -


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1567 1 T7 2 T53 2 T231 1
auto[StInit] 185 1 T46 1 T26 1 T36 1
auto[StCreatorRootKey] 50 1 T103 1 T28 1 T232 1
auto[StOwnerIntKey] 29 1 T51 1 T32 1 T40 1
auto[StOwnerKey] 28 1 T7 1 T53 1 T67 1
auto[StDisabled] 319 1 T7 15 T53 12 T27 1
auto[StInvalid] 44 1 T24 1 T37 1 T38 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3126 1 T1 1 T2 1 T3 1
auto[1] 160 1 T7 2 T46 1 T53 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1555 1 T7 2 T53 2 T231 1
auto[StReset] auto[1] 12 1 T47 1 T104 1 T233 2
auto[StInit] auto[0] 85 1 T26 1 T36 1 T54 2
auto[StInit] auto[1] 100 1 T46 1 T39 1 T104 7
auto[StCreatorRootKey] auto[0] 32 1 T103 1 T232 1 T61 2
auto[StCreatorRootKey] auto[1] 18 1 T28 1 T228 1 T59 1
auto[StOwnerIntKey] auto[0] 18 1 T51 1 T40 1 T108 1
auto[StOwnerIntKey] auto[1] 11 1 T32 1 T63 1 T65 1
auto[StOwnerKey] auto[0] 19 1 T67 1 T69 1 T234 1
auto[StOwnerKey] auto[1] 9 1 T7 1 T53 1 T11 1
auto[StDisabled] auto[0] 309 1 T7 14 T53 12 T27 1
auto[StDisabled] auto[1] 10 1 T7 1 T70 1 T66 1
auto[StInvalid] auto[0] 44 1 T24 1 T37 1 T38 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 14 21 60.00 14


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 4
[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 3
[auto[StDisabled]] [auto[OpGenId]] 0 1 1
[auto[StDisabled]] [auto[OpDisable]] 0 1 1


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 12 1 T47 1 T104 1 T233 2
auto[StInit] auto[OpAdvance] 55 1 T46 1 T39 1 T104 2
auto[StInit] auto[OpGenId] 12 1 T104 1 T227 1 T228 1
auto[StInit] auto[OpGenSwOut] 21 1 T104 2 T233 1 T235 4
auto[StInit] auto[OpGenHwOut] 11 1 T104 2 T229 1 T48 1
auto[StInit] auto[OpDisable] 1 1 T230 1 - - - -
auto[StCreatorRootKey] auto[OpAdvance] 12 1 T28 1 T59 1 T236 1
auto[StCreatorRootKey] auto[OpGenId] 1 1 T237 1 - - - -
auto[StCreatorRootKey] auto[OpGenSwOut] 3 1 T228 1 T60 1 T238 1
auto[StCreatorRootKey] auto[OpGenHwOut] 2 1 T49 1 T239 1 - -
auto[StOwnerIntKey] auto[OpAdvance] 4 1 T63 1 T65 1 T162 1
auto[StOwnerIntKey] auto[OpGenId] 1 1 T32 1 - - - -
auto[StOwnerIntKey] auto[OpGenSwOut] 5 1 T66 1 T240 2 T241 1
auto[StOwnerIntKey] auto[OpGenHwOut] 1 1 T242 1 - - - -
auto[StOwnerKey] auto[OpAdvance] 3 1 T11 1 T169 1 T243 1
auto[StOwnerKey] auto[OpGenId] 1 1 T53 1 - - - -
auto[StOwnerKey] auto[OpGenSwOut] 1 1 T244 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 4 1 T7 1 T245 1 T246 1
auto[StDisabled] auto[OpAdvance] 5 1 T7 1 T66 1 T247 1
auto[StDisabled] auto[OpGenSwOut] 3 1 T70 1 T248 1 T249 1
auto[StDisabled] auto[OpGenHwOut] 2 1 T250 1 T251 1 - -