Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10850

1

T1

2

T2

5

T3

8

auto[Attestation]

7420

1

T1

6

T2

3

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2621	1			T3	1		T5	5		T6	1
auto[Aes]	3423	1			T2	8		T3	1		T4	23
auto[Kmac]	3296	1			T1	8		T3	3		T5	2
auto[Otbn]	3336	1			T3	1		T5	2		T6	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7157	1			T1	8		T2	8		T3	8
auto[OpGenId]	5594	1			T3	7		T5	11		T6	3
auto[OpGenSwOut]	5739	1			T3	6		T5	7		T6	6
auto[OpGenHwOut]	6937	1			T1	8		T2	8		T4	23
auto[OpDisable]	112	1			T6	1		T50	1		T7	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9225

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

16314

1

T1

8

T2

8

T3

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6231	1			T1	1		T2	1		T3	6
auto[StInit]	4150	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	2724	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2390	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2141	1			T1	2		T2	2		T3	2
auto[StDisabled]	6901	1			T1	7		T2	7		T3	7
auto[StInvalid]	1002	1			T24	18		T37	26		T38	30

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	317	1			T3	1		T214	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	95	1			T50	1		T22	2		T7	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T44	1		T7	1		T143	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T214	1		T7	2		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T216	1		T7	1		T145	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	171	1			T7	4		T145	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T24	1		T37	1		T217	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	319	1			T3	1		T24	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	116	1			T21	1		T50	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	76	1			T25	1		T146	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T44	1		T7	2		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	47	1			T5	1		T7	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	175	1			T5	1		T7	3		T143	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	26	1			T38	1		T58	1		T41	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	353	1			T20	2		T21	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T3	1		T5	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T219	1		T7	1		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T6	1		T216	1		T7	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	41	1			T20	1		T7	1		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	170	1			T3	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	29	1			T37	1		T41	1		T217	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	329	1			T24	3		T214	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	105	1			T20	1		T25	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T6	1		T44	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T7	2		T53	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T6	1		T7	3		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	217	1			T44	1		T50	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	38	1			T24	2		T37	2		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T7	3		T53	4		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T21	2		T22	2		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T20	1		T53	1		T136	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T44	1		T7	5		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T5	1		T219	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T5	1		T44	1		T7	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T24	1		T37	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T7	4		T53	8		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T5	1		T22	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	60	1			T20	1		T7	4		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T7	2		T142	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T7	2		T142	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	218	1			T20	1		T44	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	27	1			T58	1		T41	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T7	4		T53	5		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T24	1		T22	2		T23	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	58	1			T142	1		T145	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T3	1		T7	2		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	48	1			T6	1		T7	2		T53	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	175	1			T16	1		T216	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T24	1		T58	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T7	2		T53	7		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T6	1		T25	1		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	58	1			T6	1		T7	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	52	1			T7	2		T53	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T7	3		T220	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	193	1			T3	1		T44	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T24	1		T38	1		T58	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T5	1		T7	3		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T22	2		T23	2		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T15	1		T24	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	48	1			T53	1		T221	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	33	1			T44	1		T7	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	172	1			T5	1		T6	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T38	1		T217	2		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	486	1			T4	15		T14	7		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	147	1			T2	1		T16	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	113	1			T2	1		T25	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T14	1		T86	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T2	1		T4	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	270	1			T2	2		T4	2		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T37	1		T38	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	415	1			T24	1		T20	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	143	1			T1	1		T17	1		T223	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T44	1		T223	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T223	1		T53	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T1	1		T15	1		T53	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	267	1			T17	2		T20	1		T223	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	38	1			T38	2		T41	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	456	1			T5	1		T24	4		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T42	1		T20	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T43	1		T53	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T141	1		T144	1		T147	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T44	1		T7	3		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	265	1			T5	1		T42	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	33	1			T38	1		T58	1		T41	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T7	3		T53	2		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T214	1		T21	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T5	1		T20	1		T143	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T16	1		T7	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T7	1		T145	1		T225	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	149	1			T25	2		T214	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	25	1			T24	1		T37	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T7	4		T53	5		T54	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	138	1			T4	1		T14	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	95	1			T4	1		T14	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T2	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T5	3		T14	1		T226	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	250	1			T2	2		T4	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	28	1			T24	1		T37	1		T217	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T7	1		T53	6		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T20	1		T44	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T1	1		T17	1		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T1	1		T17	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T6	1		T17	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	259	1			T1	4		T17	2		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	40	1			T24	1		T37	1		T38	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T7	1		T53	4		T54	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T23	1		T7	1		T144	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T42	1		T7	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T42	1		T44	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T42	1		T44	1		T144	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	235	1			T42	3		T25	1		T7	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	27	1			T37	2		T38	2		T58	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	168	1			T44	1		T214	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	629	1			T3	1		T24	1		T214	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	172	1			T5	1		T44	1		T7	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	655	1			T3	1		T5	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	173	1			T6	1		T20	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	683	1			T3	2		T5	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	192	1			T6	2		T44	1		T7	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	702	1			T24	5		T20	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	166	1			T20	1		T44	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	426	1			T5	2		T24	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	167	1			T7	6		T142	2		T53	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	457	1			T5	1		T20	2		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	151	1			T3	1		T6	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	414	1			T16	1		T24	2		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	155	1			T6	1		T7	6		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	429	1			T3	1		T6	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	134	1			T15	1		T24	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	589	1			T5	2		T6	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	265	1			T2	2		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	963	1			T2	3		T4	17		T14	10
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	256	1			T1	1		T15	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	877	1			T1	1		T17	3		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T44	1		T43	1		T7	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	913	1			T5	2		T24	4		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	148	1			T5	1		T16	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	361	1			T24	1		T20	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	263	1			T2	1		T4	2		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	481	1			T2	2		T4	3		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	245	1			T1	2		T6	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	497	1			T1	4		T17	2		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T42	3		T44	3		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	463	1			T42	3		T25	1		T23	1