Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 29234 1 T1 20 T2 21 T3 28
auto[1] 271 1 T121 9 T123 6 T159 3



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 29240 1 T1 20 T2 21 T3 28
auto[134217728:268435455] 6 1 T121 1 T273 1 T298 1
auto[268435456:402653183] 5 1 T159 1 T436 1 T437 1
auto[402653184:536870911] 9 1 T159 1 T253 1 T273 1
auto[536870912:671088639] 12 1 T121 1 T123 1 T253 2
auto[671088640:805306367] 11 1 T293 2 T298 1 T438 1
auto[805306368:939524095] 6 1 T439 1 T342 1 T440 1
auto[939524096:1073741823] 10 1 T329 2 T437 1 T271 2
auto[1073741824:1207959551] 7 1 T273 1 T376 1 T271 2
auto[1207959552:1342177279] 9 1 T254 1 T272 1 T293 1
auto[1342177280:1476395007] 5 1 T121 1 T320 1 T441 1
auto[1476395008:1610612735] 8 1 T270 1 T329 1 T436 2
auto[1610612736:1744830463] 9 1 T159 1 T288 1 T254 1
auto[1744830464:1879048191] 9 1 T123 1 T329 1 T343 1
auto[1879048192:2013265919] 9 1 T121 1 T123 1 T329 1
auto[2013265920:2147483647] 9 1 T123 1 T254 2 T329 2
auto[2147483648:2281701375] 6 1 T273 1 T272 1 T271 1
auto[2281701376:2415919103] 11 1 T123 1 T253 1 T113 1
auto[2415919104:2550136831] 9 1 T343 1 T298 2 T294 1
auto[2550136832:2684354559] 5 1 T438 2 T386 2 T442 1
auto[2684354560:2818572287] 14 1 T293 1 T298 2 T437 1
auto[2818572288:2952790015] 13 1 T121 1 T253 1 T273 3
auto[2952790016:3087007743] 11 1 T121 2 T123 1 T253 1
auto[3087007744:3221225471] 13 1 T273 1 T254 1 T272 1
auto[3221225472:3355443199] 8 1 T329 1 T443 1 T364 2
auto[3355443200:3489660927] 9 1 T329 1 T113 1 T441 1
auto[3489660928:3623878655] 5 1 T293 1 T444 1 T356 1
auto[3623878656:3758096383] 5 1 T121 1 T436 1 T445 1
auto[3758096384:3892314111] 5 1 T294 1 T338 1 T386 1
auto[3892314112:4026531839] 10 1 T273 1 T113 1 T272 2
auto[4026531840:4160749567] 8 1 T253 1 T272 1 T363 1
auto[4160749568:4294967295] 9 1 T121 1 T253 1 T288 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 31 33 51.56 31


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins
sw_input_cpregwen_cpCOUNTAT LEASTNUMBERSTATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]] [auto[0]] -- -- 31


Covered bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 29234 1 T1 20 T2 21 T3 28
auto[0:134217727] auto[1] 6 1 T272 1 T436 1 T437 2
auto[134217728:268435455] auto[1] 6 1 T121 1 T273 1 T298 1
auto[268435456:402653183] auto[1] 5 1 T159 1 T436 1 T437 1
auto[402653184:536870911] auto[1] 9 1 T159 1 T253 1 T273 1
auto[536870912:671088639] auto[1] 12 1 T121 1 T123 1 T253 2
auto[671088640:805306367] auto[1] 11 1 T293 2 T298 1 T438 1
auto[805306368:939524095] auto[1] 6 1 T439 1 T342 1 T440 1
auto[939524096:1073741823] auto[1] 10 1 T329 2 T437 1 T271 2
auto[1073741824:1207959551] auto[1] 7 1 T273 1 T376 1 T271 2
auto[1207959552:1342177279] auto[1] 9 1 T254 1 T272 1 T293 1
auto[1342177280:1476395007] auto[1] 5 1 T121 1 T320 1 T441 1
auto[1476395008:1610612735] auto[1] 8 1 T270 1 T329 1 T436 2
auto[1610612736:1744830463] auto[1] 9 1 T159 1 T288 1 T254 1
auto[1744830464:1879048191] auto[1] 9 1 T123 1 T329 1 T343 1
auto[1879048192:2013265919] auto[1] 9 1 T121 1 T123 1 T329 1
auto[2013265920:2147483647] auto[1] 9 1 T123 1 T254 2 T329 2
auto[2147483648:2281701375] auto[1] 6 1 T273 1 T272 1 T271 1
auto[2281701376:2415919103] auto[1] 11 1 T123 1 T253 1 T113 1
auto[2415919104:2550136831] auto[1] 9 1 T343 1 T298 2 T294 1
auto[2550136832:2684354559] auto[1] 5 1 T438 2 T386 2 T442 1
auto[2684354560:2818572287] auto[1] 14 1 T293 1 T298 2 T437 1
auto[2818572288:2952790015] auto[1] 13 1 T121 1 T253 1 T273 3
auto[2952790016:3087007743] auto[1] 11 1 T121 2 T123 1 T253 1
auto[3087007744:3221225471] auto[1] 13 1 T273 1 T254 1 T272 1
auto[3221225472:3355443199] auto[1] 8 1 T329 1 T443 1 T364 2
auto[3355443200:3489660927] auto[1] 9 1 T329 1 T113 1 T441 1
auto[3489660928:3623878655] auto[1] 5 1 T293 1 T444 1 T356 1
auto[3623878656:3758096383] auto[1] 5 1 T121 1 T436 1 T445 1
auto[3758096384:3892314111] auto[1] 5 1 T294 1 T338 1 T386 1
auto[3892314112:4026531839] auto[1] 10 1 T273 1 T113 1 T272 2
auto[4026531840:4160749567] auto[1] 8 1 T253 1 T272 1 T363 1
auto[4160749568:4294967295] auto[1] 9 1 T121 1 T253 1 T288 1


Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1434 1 T5 2 T24 2 T20 7
auto[1] 1612 1 T5 4 T6 1 T24 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 86 1 T5 1 T7 1 T53 4
auto[134217728:268435455] 90 1 T44 1 T7 1 T53 3
auto[268435456:402653183] 100 1 T6 1 T20 1 T7 2
auto[402653184:536870911] 95 1 T24 2 T25 1 T23 1
auto[536870912:671088639] 109 1 T5 1 T20 1 T25 1
auto[671088640:805306367] 100 1 T25 1 T7 2 T53 1
auto[805306368:939524095] 108 1 T7 3 T53 3 T58 1
auto[939524096:1073741823] 91 1 T50 1 T22 1 T46 3
auto[1073741824:1207959551] 93 1 T24 1 T7 2 T46 1
auto[1207959552:1342177279] 102 1 T7 2 T145 1 T38 1
auto[1342177280:1476395007] 108 1 T5 1 T7 3 T146 1
auto[1476395008:1610612735] 104 1 T50 1 T53 2 T220 1
auto[1610612736:1744830463] 104 1 T43 1 T21 1 T7 2
auto[1744830464:1879048191] 124 1 T22 1 T7 4 T145 2
auto[1879048192:2013265919] 91 1 T21 1 T7 2 T53 1
auto[2013265920:2147483647] 94 1 T44 1 T25 1 T7 1
auto[2147483648:2281701375] 106 1 T25 1 T7 1 T46 1
auto[2281701376:2415919103] 93 1 T20 1 T25 1 T7 3
auto[2415919104:2550136831] 90 1 T5 2 T7 1 T53 1
auto[2550136832:2684354559] 104 1 T21 1 T7 3 T53 1
auto[2684354560:2818572287] 96 1 T25 2 T50 1 T7 1
auto[2818572288:2952790015] 87 1 T24 1 T20 2 T44 1
auto[2952790016:3087007743] 86 1 T53 2 T54 1 T104 1
auto[3087007744:3221225471] 97 1 T20 1 T23 1 T7 2
auto[3221225472:3355443199] 92 1 T43 1 T7 1 T53 2
auto[3355443200:3489660927] 83 1 T7 1 T53 1 T38 1
auto[3489660928:3623878655] 81 1 T24 1 T20 1 T23 1
auto[3623878656:3758096383] 81 1 T5 1 T24 1 T20 1
auto[3758096384:3892314111] 98 1 T7 1 T143 1 T53 2
auto[3892314112:4026531839] 86 1 T7 3 T145 1 T215 1
auto[4026531840:4160749567] 87 1 T7 1 T143 1 T53 1
auto[4160749568:4294967295] 80 1 T22 1 T7 1 T146 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 35 1 T5 1 T7 1 T53 2
auto[0:134217727] auto[1] 51 1 T53 2 T122 1 T105 1
auto[134217728:268435455] auto[0] 49 1 T44 1 T53 2 T253 1
auto[134217728:268435455] auto[1] 41 1 T7 1 T53 1 T10 1
auto[268435456:402653183] auto[0] 46 1 T20 1 T7 2 T53 1
auto[268435456:402653183] auto[1] 54 1 T6 1 T37 1 T62 1
auto[402653184:536870911] auto[0] 30 1 T24 1 T54 1 T55 1
auto[402653184:536870911] auto[1] 65 1 T24 1 T25 1 T23 1
auto[536870912:671088639] auto[0] 48 1 T20 1 T218 1 T280 1
auto[536870912:671088639] auto[1] 61 1 T5 1 T25 1 T23 1
auto[671088640:805306367] auto[0] 43 1 T121 1 T47 1 T54 1
auto[671088640:805306367] auto[1] 57 1 T25 1 T7 2 T53 1
auto[805306368:939524095] auto[0] 45 1 T7 3 T53 2 T159 1
auto[805306368:939524095] auto[1] 63 1 T53 1 T58 1 T231 1
auto[939524096:1073741823] auto[0] 48 1 T22 1 T46 2 T41 1
auto[939524096:1073741823] auto[1] 43 1 T50 1 T46 1 T56 1
auto[1073741824:1207959551] auto[0] 45 1 T24 1 T7 1 T46 1
auto[1073741824:1207959551] auto[1] 48 1 T7 1 T54 2 T369 1
auto[1207959552:1342177279] auto[0] 54 1 T38 1 T215 1 T28 1
auto[1207959552:1342177279] auto[1] 48 1 T7 2 T145 1 T215 1
auto[1342177280:1476395007] auto[0] 51 1 T5 1 T7 1 T146 1
auto[1342177280:1476395007] auto[1] 57 1 T7 2 T53 2 T104 1
auto[1476395008:1610612735] auto[0] 53 1 T50 1 T53 2 T89 2
auto[1476395008:1610612735] auto[1] 51 1 T220 1 T27 1 T54 1
auto[1610612736:1744830463] auto[0] 45 1 T43 1 T21 1 T7 1
auto[1610612736:1744830463] auto[1] 59 1 T7 1 T91 1 T58 1
auto[1744830464:1879048191] auto[0] 61 1 T7 3 T145 1 T36 1
auto[1744830464:1879048191] auto[1] 63 1 T22 1 T7 1 T145 1
auto[1879048192:2013265919] auto[0] 51 1 T21 1 T7 2 T53 1
auto[1879048192:2013265919] auto[1] 40 1 T122 1 T123 1 T54 1
auto[2013265920:2147483647] auto[0] 42 1 T44 1 T89 1 T90 1
auto[2013265920:2147483647] auto[1] 52 1 T25 1 T7 1 T56 1
auto[2147483648:2281701375] auto[0] 54 1 T7 1 T46 1 T53 3
auto[2147483648:2281701375] auto[1] 52 1 T25 1 T53 2 T122 1
auto[2281701376:2415919103] auto[0] 44 1 T20 1 T7 2 T146 1
auto[2281701376:2415919103] auto[1] 49 1 T25 1 T7 1 T145 1
auto[2415919104:2550136831] auto[0] 47 1 T53 1 T369 1 T417 1
auto[2415919104:2550136831] auto[1] 43 1 T5 2 T7 1 T159 1
auto[2550136832:2684354559] auto[0] 44 1 T7 1 T121 1 T429 1
auto[2550136832:2684354559] auto[1] 60 1 T21 1 T7 2 T53 1
auto[2684354560:2818572287] auto[0] 52 1 T25 2 T50 1 T220 1
auto[2684354560:2818572287] auto[1] 44 1 T7 1 T143 1 T218 1
auto[2818572288:2952790015] auto[0] 43 1 T20 2 T44 1 T37 2
auto[2818572288:2952790015] auto[1] 44 1 T24 1 T7 1 T91 1
auto[2952790016:3087007743] auto[0] 39 1 T53 2 T54 1 T352 1
auto[2952790016:3087007743] auto[1] 47 1 T104 1 T56 1 T70 1
auto[3087007744:3221225471] auto[0] 52 1 T20 1 T7 1 T37 1
auto[3087007744:3221225471] auto[1] 45 1 T23 1 T7 1 T231 1
auto[3221225472:3355443199] auto[0] 38 1 T43 1 T53 2 T159 1
auto[3221225472:3355443199] auto[1] 54 1 T7 1 T62 1 T369 1
auto[3355443200:3489660927] auto[0] 38 1 T54 1 T352 1 T417 1
auto[3355443200:3489660927] auto[1] 45 1 T7 1 T53 1 T38 1
auto[3489660928:3623878655] auto[0] 38 1 T20 1 T7 1 T159 1
auto[3489660928:3623878655] auto[1] 43 1 T24 1 T23 1 T38 1
auto[3623878656:3758096383] auto[0] 38 1 T7 1 T205 1 T311 1
auto[3623878656:3758096383] auto[1] 43 1 T5 1 T24 1 T20 1
auto[3758096384:3892314111] auto[0] 44 1 T89 1 T54 1 T218 1
auto[3758096384:3892314111] auto[1] 54 1 T7 1 T143 1 T53 2
auto[3892314112:4026531839] auto[0] 44 1 T215 1 T90 1 T93 1
auto[3892314112:4026531839] auto[1] 42 1 T7 3 T145 1 T10 1
auto[4026531840:4160749567] auto[0] 37 1 T7 1 T38 1 T231 1
auto[4026531840:4160749567] auto[1] 50 1 T143 1 T53 1 T123 1
auto[4160749568:4294967295] auto[0] 36 1 T22 1 T146 1 T47 1
auto[4160749568:4294967295] auto[1] 44 1 T7 1 T58 1 T159 1


Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1436 1 T5 2 T24 2 T20 6
auto[1] 1617 1 T5 4 T6 1 T24 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 94 1 T24 2 T20 1 T25 1
auto[134217728:268435455] 98 1 T5 1 T21 1 T7 2
auto[268435456:402653183] 107 1 T20 1 T22 1 T7 2
auto[402653184:536870911] 108 1 T20 1 T7 2 T146 1
auto[536870912:671088639] 95 1 T145 1 T53 3 T221 1
auto[671088640:805306367] 98 1 T7 2 T145 1 T53 2
auto[805306368:939524095] 87 1 T7 1 T143 1 T38 1
auto[939524096:1073741823] 98 1 T22 1 T7 2 T146 1
auto[1073741824:1207959551] 85 1 T20 1 T25 1 T23 1
auto[1207959552:1342177279] 83 1 T5 1 T43 1 T7 3
auto[1342177280:1476395007] 97 1 T7 3 T146 1 T53 1
auto[1476395008:1610612735] 108 1 T24 1 T25 1 T23 1
auto[1610612736:1744830463] 90 1 T20 1 T44 1 T7 3
auto[1744830464:1879048191] 93 1 T25 1 T7 2 T89 1
auto[1879048192:2013265919] 110 1 T7 1 T46 1 T53 1
auto[2013265920:2147483647] 101 1 T145 1 T58 1 T90 1
auto[2147483648:2281701375] 93 1 T24 1 T25 1 T7 3
auto[2281701376:2415919103] 94 1 T7 2 T46 1 T53 3
auto[2415919104:2550136831] 102 1 T5 1 T6 1 T43 1
auto[2550136832:2684354559] 96 1 T24 1 T21 1 T7 1
auto[2684354560:2818572287] 106 1 T44 1 T50 1 T7 1
auto[2818572288:2952790015] 87 1 T24 1 T91 1 T41 1
auto[2952790016:3087007743] 84 1 T5 1 T25 1 T7 1
auto[3087007744:3221225471] 88 1 T7 1 T53 2 T47 1
auto[3221225472:3355443199] 83 1 T7 1 T145 1 T27 2
auto[3355443200:3489660927] 97 1 T5 1 T20 2 T25 1
auto[3489660928:3623878655] 106 1 T50 1 T23 1 T53 4
auto[3623878656:3758096383] 89 1 T7 1 T53 1 T159 1
auto[3758096384:3892314111] 86 1 T7 2 T146 1 T53 1
auto[3892314112:4026531839] 102 1 T5 1 T20 1 T7 1
auto[4026531840:4160749567] 85 1 T44 1 T25 1 T7 2
auto[4160749568:4294967295] 103 1 T50 1 T22 1 T7 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 50 1 T20 1 T25 1 T21 1
auto[0:134217727] auto[1] 44 1 T24 2 T23 1 T7 1
auto[134217728:268435455] auto[0] 49 1 T21 1 T7 1 T53 2
auto[134217728:268435455] auto[1] 49 1 T5 1 T7 1 T53 1
auto[268435456:402653183] auto[0] 50 1 T22 1 T7 1 T46 1
auto[268435456:402653183] auto[1] 57 1 T20 1 T7 1 T53 1
auto[402653184:536870911] auto[0] 51 1 T20 1 T7 2 T146 1
auto[402653184:536870911] auto[1] 57 1 T53 1 T123 1 T27 1
auto[536870912:671088639] auto[0] 43 1 T53 2 T54 1 T41 1
auto[536870912:671088639] auto[1] 52 1 T145 1 T53 1 T221 1
auto[671088640:805306367] auto[0] 47 1 T53 1 T89 1 T221 1
auto[671088640:805306367] auto[1] 51 1 T7 2 T145 1 T53 1
auto[805306368:939524095] auto[0] 36 1 T7 1 T38 1 T105 1
auto[805306368:939524095] auto[1] 51 1 T143 1 T218 1 T104 1
auto[939524096:1073741823] auto[0] 48 1 T22 1 T146 1 T53 1
auto[939524096:1073741823] auto[1] 50 1 T7 2 T123 1 T215 1
auto[1073741824:1207959551] auto[0] 43 1 T20 1 T25 1 T53 1
auto[1073741824:1207959551] auto[1] 42 1 T23 1 T7 2 T220 1
auto[1207959552:1342177279] auto[0] 39 1 T43 1 T7 1 T53 1
auto[1207959552:1342177279] auto[1] 44 1 T5 1 T7 2 T53 1
auto[1342177280:1476395007] auto[0] 46 1 T7 1 T53 1 T54 1
auto[1342177280:1476395007] auto[1] 51 1 T7 2 T146 1 T91 1
auto[1476395008:1610612735] auto[0] 52 1 T24 1 T47 1 T215 1
auto[1476395008:1610612735] auto[1] 56 1 T25 1 T23 1 T7 2
auto[1610612736:1744830463] auto[0] 46 1 T20 1 T44 1 T7 1
auto[1610612736:1744830463] auto[1] 44 1 T7 2 T215 1 T253 1
auto[1744830464:1879048191] auto[0] 39 1 T7 1 T89 1 T280 2
auto[1744830464:1879048191] auto[1] 54 1 T25 1 T7 1 T122 1
auto[1879048192:2013265919] auto[0] 51 1 T46 1 T47 1 T446 1
auto[1879048192:2013265919] auto[1] 59 1 T7 1 T53 1 T58 1
auto[2013265920:2147483647] auto[0] 50 1 T90 1 T54 2 T41 1
auto[2013265920:2147483647] auto[1] 51 1 T145 1 T58 1 T280 1
auto[2147483648:2281701375] auto[0] 40 1 T25 1 T7 1 T105 1
auto[2147483648:2281701375] auto[1] 53 1 T24 1 T7 2 T146 1
auto[2281701376:2415919103] auto[0] 57 1 T7 1 T46 1 T53 2
auto[2281701376:2415919103] auto[1] 37 1 T7 1 T53 1 T123 1
auto[2415919104:2550136831] auto[0] 44 1 T43 1 T7 1 T53 1
auto[2415919104:2550136831] auto[1] 58 1 T5 1 T6 1 T7 2
auto[2550136832:2684354559] auto[0] 45 1 T24 1 T21 1 T7 1
auto[2550136832:2684354559] auto[1] 51 1 T53 2 T36 1 T231 1
auto[2684354560:2818572287] auto[0] 53 1 T44 1 T50 1 T37 1
auto[2684354560:2818572287] auto[1] 53 1 T7 1 T145 1 T53 1
auto[2818572288:2952790015] auto[0] 39 1 T227 1 T56 1 T217 1
auto[2818572288:2952790015] auto[1] 48 1 T24 1 T91 1 T41 1
auto[2952790016:3087007743] auto[0] 35 1 T5 1 T53 1 T89 1
auto[2952790016:3087007743] auto[1] 49 1 T25 1 T7 1 T122 1
auto[3087007744:3221225471] auto[0] 32 1 T53 1 T47 1 T41 1
auto[3087007744:3221225471] auto[1] 56 1 T7 1 T53 1 T54 1
auto[3221225472:3355443199] auto[0] 39 1 T7 1 T145 1 T54 1
auto[3221225472:3355443199] auto[1] 44 1 T27 2 T62 1 T447 1
auto[3355443200:3489660927] auto[0] 37 1 T5 1 T20 1 T53 1
auto[3355443200:3489660927] auto[1] 60 1 T20 1 T25 1 T143 1
auto[3489660928:3623878655] auto[0] 53 1 T50 1 T53 2 T231 1
auto[3489660928:3623878655] auto[1] 53 1 T23 1 T53 2 T122 1
auto[3623878656:3758096383] auto[0] 46 1 T53 1 T159 1 T218 1
auto[3623878656:3758096383] auto[1] 43 1 T7 1 T297 1 T318 1
auto[3758096384:3892314111] auto[0] 36 1 T7 1 T37 1 T57 1
auto[3758096384:3892314111] auto[1] 50 1 T7 1 T146 1 T53 1
auto[3892314112:4026531839] auto[0] 50 1 T20 1 T53 1 T37 1
auto[3892314112:4026531839] auto[1] 52 1 T5 1 T7 1 T62 1
auto[4026531840:4160749567] auto[0] 42 1 T44 1 T159 1 T54 2
auto[4026531840:4160749567] auto[1] 43 1 T25 1 T7 2 T159 1
auto[4160749568:4294967295] auto[0] 48 1 T50 1 T22 1 T231 1
auto[4160749568:4294967295] auto[1] 55 1 T7 2 T53 1 T38 1


Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1465 1 T5 2 T6 1 T24 2
auto[1] 1583 1 T5 4 T24 4 T20 1



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 88 1 T20 1 T7 2 T145 1
auto[134217728:268435455] 88 1 T46 1 T53 3 T91 1
auto[268435456:402653183] 94 1 T7 1 T37 1 T121 1
auto[402653184:536870911] 95 1 T24 1 T25 1 T7 1
auto[536870912:671088639] 95 1 T20 1 T7 1 T145 1
auto[671088640:805306367] 99 1 T5 1 T7 4 T53 1
auto[805306368:939524095] 92 1 T5 1 T43 1 T7 1
auto[939524096:1073741823] 84 1 T7 1 T143 1 T53 2
auto[1073741824:1207959551] 101 1 T24 1 T20 1 T7 1
auto[1207959552:1342177279] 90 1 T24 2 T7 1 T53 1
auto[1342177280:1476395007] 88 1 T20 1 T25 1 T53 1
auto[1476395008:1610612735] 74 1 T21 1 T22 1 T7 1
auto[1610612736:1744830463] 102 1 T50 2 T7 1 T53 1
auto[1744830464:1879048191] 82 1 T20 1 T22 2 T146 1
auto[1879048192:2013265919] 91 1 T25 1 T7 1 T53 3
auto[2013265920:2147483647] 103 1 T25 1 T7 2 T143 1
auto[2147483648:2281701375] 92 1 T5 1 T50 1 T7 4
auto[2281701376:2415919103] 101 1 T24 1 T25 1 T7 2
auto[2415919104:2550136831] 107 1 T5 1 T7 3 T143 1
auto[2550136832:2684354559] 118 1 T5 2 T25 1 T7 3
auto[2684354560:2818572287] 107 1 T24 1 T7 3 T46 1
auto[2818572288:2952790015] 105 1 T7 2 T46 1 T38 1
auto[2952790016:3087007743] 113 1 T21 1 T7 6 T145 1
auto[3087007744:3221225471] 81 1 T20 1 T21 1 T7 4
auto[3221225472:3355443199] 90 1 T46 1 T123 1 T58 1
auto[3355443200:3489660927] 84 1 T53 1 T273 1 T227 1
auto[3489660928:3623878655] 92 1 T44 1 T146 1 T89 2
auto[3623878656:3758096383] 94 1 T23 2 T7 2 T145 1
auto[3758096384:3892314111] 106 1 T25 1 T43 1 T23 1
auto[3892314112:4026531839] 86 1 T6 1 T25 1 T53 1
auto[4026531840:4160749567] 95 1 T20 1 T145 1 T53 1
auto[4160749568:4294967295] 111 1 T20 1 T44 2 T23 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 47 1 T20 1 T7 1 T146 1
auto[0:134217727] auto[1] 41 1 T7 1 T145 1 T53 1
auto[134217728:268435455] auto[0] 36 1 T46 1 T53 2 T54 1
auto[134217728:268435455] auto[1] 52 1 T53 1 T91 1 T105 1
auto[268435456:402653183] auto[0] 46 1 T7 1 T37 1 T121 1
auto[268435456:402653183] auto[1] 48 1 T222 1 T279 1 T326 1
auto[402653184:536870911] auto[0] 43 1 T146 1 T89 1 T54 2
auto[402653184:536870911] auto[1] 52 1 T24 1 T25 1 T7 1
auto[536870912:671088639] auto[0] 46 1 T53 2 T47 1 T215 1
auto[536870912:671088639] auto[1] 49 1 T20 1 T7 1 T145 1
auto[671088640:805306367] auto[0] 44 1 T5 1 T7 2 T53 1
auto[671088640:805306367] auto[1] 55 1 T7 2 T123 1 T273 1
auto[805306368:939524095] auto[0] 40 1 T5 1 T43 1 T159 1
auto[805306368:939524095] auto[1] 52 1 T7 1 T221 1 T122 1
auto[939524096:1073741823] auto[0] 32 1 T53 1 T221 1 T280 1
auto[939524096:1073741823] auto[1] 52 1 T7 1 T143 1 T53 1
auto[1073741824:1207959551] auto[0] 58 1 T24 1 T20 1 T121 1
auto[1073741824:1207959551] auto[1] 43 1 T7 1 T53 2 T159 1
auto[1207959552:1342177279] auto[0] 42 1 T24 1 T159 1 T105 1
auto[1207959552:1342177279] auto[1] 48 1 T24 1 T7 1 T53 1
auto[1342177280:1476395007] auto[0] 51 1 T20 1 T53 1 T215 1
auto[1342177280:1476395007] auto[1] 37 1 T25 1 T215 1 T222 1
auto[1476395008:1610612735] auto[0] 40 1 T21 1 T22 1 T7 1
auto[1476395008:1610612735] auto[1] 34 1 T53 1 T220 1 T122 1
auto[1610612736:1744830463] auto[0] 43 1 T50 1 T54 1 T322 1
auto[1610612736:1744830463] auto[1] 59 1 T50 1 T7 1 T53 1
auto[1744830464:1879048191] auto[0] 36 1 T20 1 T22 1 T146 1
auto[1744830464:1879048191] auto[1] 46 1 T22 1 T122 1 T91 1
auto[1879048192:2013265919] auto[0] 48 1 T7 1 T53 2 T37 1
auto[1879048192:2013265919] auto[1] 43 1 T25 1 T53 1 T38 1
auto[2013265920:2147483647] auto[0] 52 1 T54 1 T369 2 T56 1
auto[2013265920:2147483647] auto[1] 51 1 T25 1 T7 2 T143 1
auto[2147483648:2281701375] auto[0] 43 1 T50 1 T7 2 T53 2
auto[2147483648:2281701375] auto[1] 49 1 T5 1 T7 2 T38 1
auto[2281701376:2415919103] auto[0] 45 1 T25 1 T7 2 T53 2
auto[2281701376:2415919103] auto[1] 56 1 T24 1 T41 1 T104 1
auto[2415919104:2550136831] auto[0] 51 1 T7 2 T89 1 T38 1
auto[2415919104:2550136831] auto[1] 56 1 T5 1 T7 1 T143 1
auto[2550136832:2684354559] auto[0] 60 1 T25 1 T7 1 T53 1
auto[2550136832:2684354559] auto[1] 58 1 T5 2 T7 2 T159 1
auto[2684354560:2818572287] auto[0] 54 1 T7 1 T46 1 T38 1
auto[2684354560:2818572287] auto[1] 53 1 T24 1 T7 2 T36 1
auto[2818572288:2952790015] auto[0] 49 1 T46 1 T311 1 T322 1
auto[2818572288:2952790015] auto[1] 56 1 T7 2 T38 1 T122 1
auto[2952790016:3087007743] auto[0] 54 1 T21 1 T7 4 T231 1
auto[2952790016:3087007743] auto[1] 59 1 T7 2 T145 1 T146 1
auto[3087007744:3221225471] auto[0] 36 1 T20 1 T21 1 T7 2
auto[3087007744:3221225471] auto[1] 45 1 T7 2 T62 1 T56 1
auto[3221225472:3355443199] auto[0] 40 1 T46 1 T90 1 T54 1
auto[3221225472:3355443199] auto[1] 50 1 T123 1 T58 1 T54 1
auto[3355443200:3489660927] auto[0] 39 1 T227 1 T217 1 T322 1
auto[3355443200:3489660927] auto[1] 45 1 T53 1 T273 1 T429 1
auto[3489660928:3623878655] auto[0] 48 1 T44 1 T146 1 T89 2
auto[3489660928:3623878655] auto[1] 44 1 T218 1 T56 1 T93 1
auto[3623878656:3758096383] auto[0] 39 1 T7 1 T159 1 T54 1
auto[3623878656:3758096383] auto[1] 55 1 T23 2 T7 1 T145 1
auto[3758096384:3892314111] auto[0] 53 1 T43 1 T53 3 T54 1
auto[3758096384:3892314111] auto[1] 53 1 T25 1 T23 1 T7 2
auto[3892314112:4026531839] auto[0] 50 1 T6 1 T25 1 T53 1
auto[3892314112:4026531839] auto[1] 36 1 T218 1 T273 1 T93 1
auto[4026531840:4160749567] auto[0] 44 1 T20 1 T145 1 T53 1
auto[4026531840:4160749567] auto[1] 51 1 T91 1 T58 1 T215 1
auto[4160749568:4294967295] auto[0] 56 1 T20 1 T44 2 T46 1
auto[4160749568:4294967295] auto[1] 55 1 T23 1 T7 1 T53 2


Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1415 1 T5 2 T24 2 T20 6
auto[1] 1635 1 T5 4 T6 1 T24 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 117 1 T44 2 T43 1 T7 3
auto[134217728:268435455] 84 1 T23 1 T7 1 T53 1
auto[268435456:402653183] 98 1 T50 1 T7 2 T53 3
auto[402653184:536870911] 97 1 T24 2 T43 1 T7 1
auto[536870912:671088639] 87 1 T53 1 T220 1 T58 1
auto[671088640:805306367] 85 1 T24 1 T53 1 T122 1
auto[805306368:939524095] 118 1 T7 3 T53 1 T37 1
auto[939524096:1073741823] 90 1 T25 1 T7 3 T143 1
auto[1073741824:1207959551] 90 1 T22 2 T7 4 T145 1
auto[1207959552:1342177279] 76 1 T24 1 T7 4 T145 1
auto[1342177280:1476395007] 104 1 T25 1 T23 1 T7 3
auto[1476395008:1610612735] 103 1 T5 1 T25 2 T7 1
auto[1610612736:1744830463] 96 1 T53 2 T123 1 T215 1
auto[1744830464:1879048191] 109 1 T24 1 T23 1 T7 1
auto[1879048192:2013265919] 102 1 T7 2 T143 1 T146 2
auto[2013265920:2147483647] 82 1 T5 2 T7 1 T53 1
auto[2147483648:2281701375] 113 1 T20 1 T25 1 T145 1
auto[2281701376:2415919103] 96 1 T50 1 T7 3 T146 1
auto[2415919104:2550136831] 98 1 T20 2 T21 2 T53 1
auto[2550136832:2684354559] 89 1 T25 1 T7 1 T53 1
auto[2684354560:2818572287] 95 1 T21 1 T7 1 T53 1
auto[2818572288:2952790015] 87 1 T6 1 T22 1 T145 1
auto[2952790016:3087007743] 100 1 T5 2 T25 1 T50 1
auto[3087007744:3221225471] 81 1 T20 1 T44 1 T7 2
auto[3221225472:3355443199] 105 1 T5 1 T7 1 T53 2
auto[3355443200:3489660927] 76 1 T7 2 T46 1 T53 2
auto[3489660928:3623878655] 102 1 T20 2 T7 3 T46 1
auto[3623878656:3758096383] 87 1 T20 1 T7 1 T231 1
auto[3758096384:3892314111] 82 1 T20 1 T7 2 T53 2
auto[3892314112:4026531839] 95 1 T23 1 T7 1 T53 1
auto[4026531840:4160749567] 103 1 T25 1 T123 1 T91 2
auto[4160749568:4294967295] 103 1 T24 1 T7 1 T53 1