Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4129 1 T5 8 T24 4 T20 10
auto[1] 1971 1 T5 4 T6 2 T24 8



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 194 1 T5 2 T24 2 T21 2
auto[134217728:268435455] 164 1 T53 8 T54 2 T273 2
auto[268435456:402653183] 176 1 T7 8 T53 4 T36 2
auto[402653184:536870911] 210 1 T25 2 T22 2 T7 8
auto[536870912:671088639] 188 1 T25 2 T22 2 T7 6
auto[671088640:805306367] 192 1 T20 2 T50 2 T22 2
auto[805306368:939524095] 140 1 T24 2 T25 2 T7 2
auto[939524096:1073741823] 192 1 T20 2 T145 2 T146 2
auto[1073741824:1207959551] 228 1 T7 2 T46 2 T53 2
auto[1207959552:1342177279] 198 1 T7 4 T53 2 T36 2
auto[1342177280:1476395007] 208 1 T5 2 T21 2 T50 2
auto[1476395008:1610612735] 188 1 T20 2 T7 2 T53 4
auto[1610612736:1744830463] 188 1 T5 2 T7 2 T145 2
auto[1744830464:1879048191] 190 1 T24 2 T7 4 T46 2
auto[1879048192:2013265919] 194 1 T7 6 T146 2 T53 2
auto[2013265920:2147483647] 188 1 T6 2 T7 6 T91 2
auto[2147483648:2281701375] 213 1 T24 2 T7 10 T145 4
auto[2281701376:2415919103] 208 1 T5 2 T43 2 T7 2
auto[2415919104:2550136831] 204 1 T7 4 T53 4 T121 2
auto[2550136832:2684354559] 210 1 T44 2 T146 2 T220 2
auto[2684354560:2818572287] 230 1 T24 2 T23 2 T145 2
auto[2818572288:2952790015] 182 1 T43 2 T23 2 T7 4
auto[2952790016:3087007743] 172 1 T44 2 T53 2 T159 2
auto[3087007744:3221225471] 184 1 T53 2 T38 2 T54 2
auto[3221225472:3355443199] 146 1 T5 2 T25 2 T53 4
auto[3355443200:3489660927] 182 1 T5 2 T20 4 T25 2
auto[3489660928:3623878655] 192 1 T21 2 T7 2 T143 2
auto[3623878656:3758096383] 182 1 T20 4 T25 2 T7 4
auto[3758096384:3892314111] 188 1 T7 6 T37 2 T38 2
auto[3892314112:4026531839] 182 1 T24 2 T25 2 T23 2
auto[4026531840:4160749567] 204 1 T20 2 T25 2 T7 2
auto[4160749568:4294967295] 183 1 T44 2 T50 2 T7 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 126 1 T5 2 T7 4 T53 2
auto[0:134217727] auto[1] 68 1 T24 2 T21 2 T23 2
auto[134217728:268435455] auto[0] 116 1 T53 6 T273 2 T447 2
auto[134217728:268435455] auto[1] 48 1 T53 2 T54 2 T267 2
auto[268435456:402653183] auto[0] 122 1 T7 4 T36 2 T41 2
auto[268435456:402653183] auto[1] 54 1 T7 4 T53 4 T56 2
auto[402653184:536870911] auto[0] 144 1 T7 4 T143 2 T46 2
auto[402653184:536870911] auto[1] 66 1 T25 2 T22 2 T7 4
auto[536870912:671088639] auto[0] 122 1 T25 2 T7 4 T53 6
auto[536870912:671088639] auto[1] 66 1 T22 2 T7 2 T46 2
auto[671088640:805306367] auto[0] 116 1 T20 2 T50 2 T7 2
auto[671088640:805306367] auto[1] 76 1 T22 2 T56 2 T280 2
auto[805306368:939524095] auto[0] 96 1 T25 2 T7 2 T123 2
auto[805306368:939524095] auto[1] 44 1 T24 2 T53 2 T37 2
auto[939524096:1073741823] auto[0] 128 1 T20 2 T145 2 T146 2
auto[939524096:1073741823] auto[1] 64 1 T38 2 T159 2 T54 2
auto[1073741824:1207959551] auto[0] 162 1 T7 2 T46 2 T53 2
auto[1073741824:1207959551] auto[1] 66 1 T369 2 T55 4 T104 2
auto[1207959552:1342177279] auto[0] 128 1 T7 2 T53 2 T54 4
auto[1207959552:1342177279] auto[1] 70 1 T7 2 T36 2 T89 2
auto[1342177280:1476395007] auto[0] 136 1 T21 2 T50 2 T89 2
auto[1342177280:1476395007] auto[1] 72 1 T5 2 T7 4 T221 2
auto[1476395008:1610612735] auto[0] 150 1 T7 2 T53 4 T221 2
auto[1476395008:1610612735] auto[1] 38 1 T20 2 T58 2 T56 2
auto[1610612736:1744830463] auto[0] 120 1 T5 2 T145 2 T215 2
auto[1610612736:1744830463] auto[1] 68 1 T7 2 T273 2 T56 2
auto[1744830464:1879048191] auto[0] 120 1 T7 2 T46 2 T146 2
auto[1744830464:1879048191] auto[1] 70 1 T24 2 T7 2 T280 2
auto[1879048192:2013265919] auto[0] 132 1 T7 2 T146 2 T53 2
auto[1879048192:2013265919] auto[1] 62 1 T7 4 T446 2 T362 2
auto[2013265920:2147483647] auto[0] 130 1 T7 6 T91 2 T54 2
auto[2013265920:2147483647] auto[1] 58 1 T6 2 T291 2 T40 2
auto[2147483648:2281701375] auto[0] 155 1 T7 6 T145 4 T53 4
auto[2147483648:2281701375] auto[1] 58 1 T24 2 T7 4 T122 2
auto[2281701376:2415919103] auto[0] 120 1 T43 2 T7 2 T89 2
auto[2281701376:2415919103] auto[1] 88 1 T5 2 T58 2 T27 2
auto[2415919104:2550136831] auto[0] 132 1 T7 4 T53 4 T352 2
auto[2415919104:2550136831] auto[1] 72 1 T121 2 T54 2 T280 2
auto[2550136832:2684354559] auto[0] 158 1 T44 2 T36 2 T122 2
auto[2550136832:2684354559] auto[1] 52 1 T146 2 T220 2 T54 2
auto[2684354560:2818572287] auto[0] 160 1 T24 2 T53 2 T123 2
auto[2684354560:2818572287] auto[1] 70 1 T23 2 T145 2 T146 2
auto[2818572288:2952790015] auto[0] 122 1 T43 2 T46 2 T121 2
auto[2818572288:2952790015] auto[1] 60 1 T23 2 T7 4 T27 2
auto[2952790016:3087007743] auto[0] 100 1 T44 2 T53 2 T159 2
auto[2952790016:3087007743] auto[1] 72 1 T54 2 T28 2 T273 2
auto[3087007744:3221225471] auto[0] 130 1 T53 2 T38 2 T54 2
auto[3087007744:3221225471] auto[1] 54 1 T235 2 T98 2 T256 2
auto[3221225472:3355443199] auto[0] 100 1 T5 2 T25 2 T53 2
auto[3221225472:3355443199] auto[1] 46 1 T53 2 T64 2 T94 4
auto[3355443200:3489660927] auto[0] 130 1 T5 2 T20 4 T25 2
auto[3355443200:3489660927] auto[1] 52 1 T7 2 T54 2 T30 2
auto[3489660928:3623878655] auto[0] 130 1 T7 2 T143 2 T37 2
auto[3489660928:3623878655] auto[1] 62 1 T21 2 T56 4 T63 2
auto[3623878656:3758096383] auto[0] 122 1 T20 2 T25 2 T7 4
auto[3623878656:3758096383] auto[1] 60 1 T20 2 T53 2 T253 2
auto[3758096384:3892314111] auto[0] 132 1 T7 4 T37 2 T38 2
auto[3758096384:3892314111] auto[1] 56 1 T7 2 T27 2 T253 2
auto[3892314112:4026531839] auto[0] 120 1 T24 2 T25 2 T23 2
auto[3892314112:4026531839] auto[1] 62 1 T215 2 T41 4 T104 2
auto[4026531840:4160749567] auto[0] 142 1 T25 2 T53 6 T89 2
auto[4026531840:4160749567] auto[1] 62 1 T20 2 T7 2 T311 2
auto[4160749568:4294967295] auto[0] 128 1 T44 2 T7 2 T143 2
auto[4160749568:4294967295] auto[1] 55 1 T50 2 T53 2 T91 2