Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 57 1 T44 2 T43 1 T7 1
auto[0:134217727] auto[1] 60 1 T7 2 T53 2 T231 1
auto[134217728:268435455] auto[0] 32 1 T54 1 T352 1 T88 1
auto[134217728:268435455] auto[1] 52 1 T23 1 T7 1 T53 1
auto[268435456:402653183] auto[0] 43 1 T50 1 T7 1 T53 2
auto[268435456:402653183] auto[1] 55 1 T7 1 T53 1 T93 1
auto[402653184:536870911] auto[0] 45 1 T43 1 T7 1 T46 1
auto[402653184:536870911] auto[1] 52 1 T24 2 T221 1 T38 1
auto[536870912:671088639] auto[0] 47 1 T53 1 T54 2 T280 1
auto[536870912:671088639] auto[1] 40 1 T220 1 T58 1 T215 1
auto[671088640:805306367] auto[0] 41 1 T24 1 T90 1 T159 2
auto[671088640:805306367] auto[1] 44 1 T53 1 T122 1 T123 1
auto[805306368:939524095] auto[0] 57 1 T7 2 T53 1 T37 1
auto[805306368:939524095] auto[1] 61 1 T7 1 T221 1 T123 1
auto[939524096:1073741823] auto[0] 41 1 T7 2 T46 1 T322 1
auto[939524096:1073741823] auto[1] 49 1 T25 1 T7 1 T143 1
auto[1073741824:1207959551] auto[0] 36 1 T22 1 T253 1 T280 1
auto[1073741824:1207959551] auto[1] 54 1 T22 1 T7 4 T145 1
auto[1207959552:1342177279] auto[0] 46 1 T7 2 T41 1 T55 1
auto[1207959552:1342177279] auto[1] 30 1 T24 1 T7 2 T145 1
auto[1342177280:1476395007] auto[0] 45 1 T217 1 T446 1 T261 1
auto[1342177280:1476395007] auto[1] 59 1 T25 1 T23 1 T7 3
auto[1476395008:1610612735] auto[0] 41 1 T25 1 T7 1 T53 1
auto[1476395008:1610612735] auto[1] 62 1 T5 1 T25 1 T53 1
auto[1610612736:1744830463] auto[0] 40 1 T53 1 T54 1 T362 1
auto[1610612736:1744830463] auto[1] 56 1 T53 1 T123 1 T215 1
auto[1744830464:1879048191] auto[0] 51 1 T7 1 T53 1 T37 1
auto[1744830464:1879048191] auto[1] 58 1 T24 1 T23 1 T159 1
auto[1879048192:2013265919] auto[0] 49 1 T146 1 T53 1 T227 1
auto[1879048192:2013265919] auto[1] 53 1 T7 2 T143 1 T146 1
auto[2013265920:2147483647] auto[0] 34 1 T7 1 T38 1 T47 1
auto[2013265920:2147483647] auto[1] 48 1 T5 2 T53 1 T91 1
auto[2147483648:2281701375] auto[0] 56 1 T20 1 T54 2 T28 1
auto[2147483648:2281701375] auto[1] 57 1 T25 1 T145 1 T55 1
auto[2281701376:2415919103] auto[0] 39 1 T7 1 T146 1 T122 1
auto[2281701376:2415919103] auto[1] 57 1 T50 1 T7 2 T159 1
auto[2415919104:2550136831] auto[0] 55 1 T20 2 T21 1 T53 1
auto[2415919104:2550136831] auto[1] 43 1 T21 1 T122 1 T273 1
auto[2550136832:2684354559] auto[0] 40 1 T53 1 T215 1 T71 1
auto[2550136832:2684354559] auto[1] 49 1 T25 1 T7 1 T38 1
auto[2684354560:2818572287] auto[0] 43 1 T21 1 T53 1 T89 1
auto[2684354560:2818572287] auto[1] 52 1 T7 1 T159 1 T352 1
auto[2818572288:2952790015] auto[0] 36 1 T22 1 T145 1 T53 1
auto[2818572288:2952790015] auto[1] 51 1 T6 1 T253 1 T56 1
auto[2952790016:3087007743] auto[0] 50 1 T5 1 T50 1 T7 1
auto[2952790016:3087007743] auto[1] 50 1 T5 1 T25 1 T7 2
auto[3087007744:3221225471] auto[0] 40 1 T44 1 T7 1 T46 1
auto[3087007744:3221225471] auto[1] 41 1 T20 1 T7 1 T143 1
auto[3221225472:3355443199] auto[0] 51 1 T5 1 T7 1 T53 2
auto[3221225472:3355443199] auto[1] 54 1 T123 1 T58 2 T218 1
auto[3355443200:3489660927] auto[0] 39 1 T7 1 T46 1 T53 2
auto[3355443200:3489660927] auto[1] 37 1 T7 1 T36 1 T28 1
auto[3489660928:3623878655] auto[0] 53 1 T20 1 T7 2 T46 1
auto[3489660928:3623878655] auto[1] 49 1 T20 1 T7 1 T53 1
auto[3623878656:3758096383] auto[0] 41 1 T20 1 T231 1 T41 1
auto[3623878656:3758096383] auto[1] 46 1 T7 1 T47 1 T54 1
auto[3758096384:3892314111] auto[0] 33 1 T20 1 T7 1 T53 1
auto[3758096384:3892314111] auto[1] 49 1 T7 1 T53 1 T91 1
auto[3892314112:4026531839] auto[0] 52 1 T7 1 T53 1 T37 1
auto[3892314112:4026531839] auto[1] 43 1 T23 1 T38 1 T54 1
auto[4026531840:4160749567] auto[0] 43 1 T25 1 T231 1 T159 1
auto[4026531840:4160749567] auto[1] 60 1 T123 1 T91 2 T54 1
auto[4160749568:4294967295] auto[0] 39 1 T24 1 T7 1 T53 1
auto[4160749568:4294967295] auto[1] 64 1 T10 1 T56 1 T68 1