Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1441

1

T5

2

T24

2

T20

6

auto[1]

1608

1

T5

4

T6

1

T24

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T7	2		T123	2		T41	2
auto[134217728:268435455]	76	1			T25	1		T122	1		T58	1
auto[268435456:402653183]	89	1			T24	1		T53	3		T27	1
auto[402653184:536870911]	89	1			T22	1		T7	3		T145	1
auto[536870912:671088639]	90	1			T143	1		T146	1		T47	1
auto[671088640:805306367]	113	1			T24	1		T20	2		T7	2
auto[805306368:939524095]	94	1			T22	1		T23	1		T7	1
auto[939524096:1073741823]	90	1			T25	1		T7	1		T46	1
auto[1073741824:1207959551]	98	1			T44	1		T7	1		T221	1
auto[1207959552:1342177279]	96	1			T24	1		T7	2		T146	1
auto[1342177280:1476395007]	118	1			T5	1		T24	1		T20	1
auto[1476395008:1610612735]	87	1			T44	1		T25	1		T7	3
auto[1610612736:1744830463]	105	1			T5	1		T53	3		T37	1
auto[1744830464:1879048191]	96	1			T7	1		T53	5		T121	1
auto[1879048192:2013265919]	84	1			T5	1		T7	3		T122	1
auto[2013265920:2147483647]	97	1			T43	1		T7	1		T145	1
auto[2147483648:2281701375]	89	1			T50	1		T7	3		T146	1
auto[2281701376:2415919103]	98	1			T20	1		T7	2		T53	3
auto[2415919104:2550136831]	93	1			T25	1		T43	1		T7	2
auto[2550136832:2684354559]	96	1			T23	1		T53	1		T38	2
auto[2684354560:2818572287]	97	1			T5	1		T50	1		T7	3
auto[2818572288:2952790015]	69	1			T20	2		T7	1		T145	1
auto[2952790016:3087007743]	89	1			T25	1		T7	3		T46	1
auto[3087007744:3221225471]	113	1			T25	1		T21	1		T7	1
auto[3221225472:3355443199]	101	1			T24	1		T44	1		T25	1
auto[3355443200:3489660927]	95	1			T7	2		T53	1		T220	1
auto[3489660928:3623878655]	96	1			T7	2		T53	1		T41	1
auto[3623878656:3758096383]	91	1			T5	1		T46	1		T53	1
auto[3758096384:3892314111]	103	1			T6	1		T24	1		T20	2
auto[3892314112:4026531839]	106	1			T5	1		T53	2		T54	1
auto[4026531840:4160749567]	87	1			T21	1		T50	1		T23	1
auto[4160749568:4294967295]	115	1			T25	1		T23	1		T7	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T41	1		T253	1		T280	1
auto[0:134217727]	auto[1]	49	1			T7	2		T123	2		T41	1
auto[134217728:268435455]	auto[0]	29	1			T104	1		T217	1		T267	1
auto[134217728:268435455]	auto[1]	47	1			T25	1		T122	1		T58	1
auto[268435456:402653183]	auto[0]	40	1			T24	1		T53	3		T159	1
auto[268435456:402653183]	auto[1]	49	1			T27	1		T54	1		T55	1
auto[402653184:536870911]	auto[0]	46	1			T7	1		T53	1		T215	1
auto[402653184:536870911]	auto[1]	43	1			T22	1		T7	2		T145	1
auto[536870912:671088639]	auto[0]	34	1			T47	1		T218	1		T352	1
auto[536870912:671088639]	auto[1]	56	1			T143	1		T146	1		T54	2
auto[671088640:805306367]	auto[0]	59	1			T20	2		T89	1		T221	1
auto[671088640:805306367]	auto[1]	54	1			T24	1		T7	2		T91	1
auto[805306368:939524095]	auto[0]	52	1			T22	1		T7	1		T53	1
auto[805306368:939524095]	auto[1]	42	1			T23	1		T53	2		T62	1
auto[939524096:1073741823]	auto[0]	44	1			T25	1		T7	1		T46	1
auto[939524096:1073741823]	auto[1]	46	1			T53	1		T36	1		T369	1
auto[1073741824:1207959551]	auto[0]	52	1			T44	1		T56	1		T446	1
auto[1073741824:1207959551]	auto[1]	46	1			T7	1		T221	1		T62	1
auto[1207959552:1342177279]	auto[0]	45	1			T7	2		T146	1		T53	1
auto[1207959552:1342177279]	auto[1]	51	1			T24	1		T53	1		T215	1
auto[1342177280:1476395007]	auto[0]	50	1			T20	1		T7	1		T53	1
auto[1342177280:1476395007]	auto[1]	68	1			T5	1		T24	1		T7	1
auto[1476395008:1610612735]	auto[0]	43	1			T44	1		T7	2		T54	1
auto[1476395008:1610612735]	auto[1]	44	1			T25	1		T7	1		T220	1
auto[1610612736:1744830463]	auto[0]	61	1			T53	2		T37	1		T105	1
auto[1610612736:1744830463]	auto[1]	44	1			T5	1		T53	1		T41	1
auto[1744830464:1879048191]	auto[0]	43	1			T53	5		T121	1		T231	1
auto[1744830464:1879048191]	auto[1]	53	1			T7	1		T58	1		T369	1
auto[1879048192:2013265919]	auto[0]	40	1			T5	1		T7	1		T54	1
auto[1879048192:2013265919]	auto[1]	44	1			T7	2		T122	1		T91	1
auto[2013265920:2147483647]	auto[0]	44	1			T43	1		T146	1		T215	1
auto[2013265920:2147483647]	auto[1]	53	1			T7	1		T145	1		T123	1
auto[2147483648:2281701375]	auto[0]	43	1			T50	1		T7	2		T105	1
auto[2147483648:2281701375]	auto[1]	46	1			T7	1		T146	1		T53	1
auto[2281701376:2415919103]	auto[0]	50	1			T20	1		T7	2		T53	1
auto[2281701376:2415919103]	auto[1]	48	1			T53	2		T91	1		T93	1
auto[2415919104:2550136831]	auto[0]	50	1			T43	1		T46	1		T89	1
auto[2415919104:2550136831]	auto[1]	43	1			T25	1		T7	2		T105	1
auto[2550136832:2684354559]	auto[0]	47	1			T53	1		T38	1		T47	1
auto[2550136832:2684354559]	auto[1]	49	1			T23	1		T38	1		T54	1
auto[2684354560:2818572287]	auto[0]	40	1			T7	1		T46	1		T53	1
auto[2684354560:2818572287]	auto[1]	57	1			T5	1		T50	1		T7	2
auto[2818572288:2952790015]	auto[0]	37	1			T20	1		T7	1		T145	1
auto[2818572288:2952790015]	auto[1]	32	1			T20	1		T89	1		T215	1
auto[2952790016:3087007743]	auto[0]	41	1			T46	1		T53	1		T121	1
auto[2952790016:3087007743]	auto[1]	48	1			T25	1		T7	3		T91	1
auto[3087007744:3221225471]	auto[0]	47	1			T25	1		T21	1		T53	2
auto[3087007744:3221225471]	auto[1]	66	1			T7	1		T221	1		T122	1
auto[3221225472:3355443199]	auto[0]	43	1			T25	1		T53	1		T54	1
auto[3221225472:3355443199]	auto[1]	58	1			T24	1		T44	1		T21	1
auto[3355443200:3489660927]	auto[0]	43	1			T220	1		T41	1		T56	1
auto[3355443200:3489660927]	auto[1]	52	1			T7	2		T53	1		T54	2
auto[3489660928:3623878655]	auto[0]	46	1			T53	1		T41	1		T352	1
auto[3489660928:3623878655]	auto[1]	50	1			T7	2		T218	1		T104	1
auto[3623878656:3758096383]	auto[0]	42	1			T46	1		T53	1		T36	1
auto[3623878656:3758096383]	auto[1]	49	1			T5	1		T36	1		T38	1
auto[3758096384:3892314111]	auto[0]	51	1			T24	1		T20	1		T22	1
auto[3758096384:3892314111]	auto[1]	52	1			T6	1		T20	1		T146	1
auto[3892314112:4026531839]	auto[0]	44	1			T5	1		T53	1		T54	1
auto[3892314112:4026531839]	auto[1]	62	1			T53	1		T447	1		T280	1
auto[4026531840:4160749567]	auto[0]	40	1			T21	1		T50	1		T7	1
auto[4026531840:4160749567]	auto[1]	47	1			T23	1		T7	1		T145	1
auto[4160749568:4294967295]	auto[0]	55	1			T7	2		T143	1		T37	1
auto[4160749568:4294967295]	auto[1]	60	1			T25	1		T23	1		T7	2