Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.86 99.10 98.03 98.68 100.00 99.12 98.41 91.71


Total test records in report: 1064
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T1013 /workspace/coverage/default/46.keymgr_sideload_kmac.1679574021 Jun 01 03:06:38 PM PDT 24 Jun 01 03:06:40 PM PDT 24 226994310 ps
T1014 /workspace/coverage/default/22.keymgr_sideload_aes.3372428439 Jun 01 03:04:50 PM PDT 24 Jun 01 03:04:59 PM PDT 24 301407109 ps
T1015 /workspace/coverage/default/3.keymgr_sideload_otbn.741081105 Jun 01 03:03:16 PM PDT 24 Jun 01 03:03:19 PM PDT 24 96434724 ps
T19 /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3980284806 Jun 01 03:05:52 PM PDT 24 Jun 01 03:05:58 PM PDT 24 347444871 ps
T1016 /workspace/coverage/default/8.keymgr_sideload_protect.3482350937 Jun 01 03:03:38 PM PDT 24 Jun 01 03:03:42 PM PDT 24 133453389 ps
T1017 /workspace/coverage/default/43.keymgr_sideload.3532123878 Jun 01 03:06:21 PM PDT 24 Jun 01 03:06:24 PM PDT 24 74523622 ps
T1018 /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3206277406 Jun 01 03:03:38 PM PDT 24 Jun 01 03:03:41 PM PDT 24 405549682 ps
T1019 /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1811764404 Jun 01 03:05:27 PM PDT 24 Jun 01 03:05:41 PM PDT 24 1365634127 ps
T1020 /workspace/coverage/default/49.keymgr_sideload_otbn.4001095487 Jun 01 03:06:48 PM PDT 24 Jun 01 03:06:52 PM PDT 24 106781950 ps
T1021 /workspace/coverage/default/44.keymgr_sideload_protect.3342635134 Jun 01 03:06:28 PM PDT 24 Jun 01 03:06:32 PM PDT 24 410531199 ps
T1022 /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2912933925 Jun 01 03:06:40 PM PDT 24 Jun 01 03:06:47 PM PDT 24 1228484140 ps
T1023 /workspace/coverage/default/20.keymgr_sw_invalid_input.2222206514 Jun 01 03:04:49 PM PDT 24 Jun 01 03:04:52 PM PDT 24 195509794 ps
T1024 /workspace/coverage/default/41.keymgr_stress_all.2857698388 Jun 01 03:06:21 PM PDT 24 Jun 01 03:11:16 PM PDT 24 30329618593 ps
T1025 /workspace/coverage/default/31.keymgr_sideload_aes.3600294836 Jun 01 03:05:34 PM PDT 24 Jun 01 03:05:39 PM PDT 24 315769161 ps
T1026 /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2888911227 Jun 01 03:04:47 PM PDT 24 Jun 01 03:04:50 PM PDT 24 26677641 ps
T1027 /workspace/coverage/default/17.keymgr_hwsw_invalid_input.788598966 Jun 01 03:04:24 PM PDT 24 Jun 01 03:04:31 PM PDT 24 159375160 ps
T1028 /workspace/coverage/default/16.keymgr_sw_invalid_input.2816251952 Jun 01 03:04:20 PM PDT 24 Jun 01 03:04:24 PM PDT 24 129608315 ps
T1029 /workspace/coverage/default/18.keymgr_custom_cm.2623028307 Jun 01 03:04:27 PM PDT 24 Jun 01 03:04:31 PM PDT 24 124562733 ps
T1030 /workspace/coverage/default/14.keymgr_direct_to_disabled.1843316419 Jun 01 03:04:16 PM PDT 24 Jun 01 03:04:18 PM PDT 24 187927172 ps
T1031 /workspace/coverage/default/10.keymgr_direct_to_disabled.4156727373 Jun 01 03:03:47 PM PDT 24 Jun 01 03:03:50 PM PDT 24 82552359 ps
T319 /workspace/coverage/default/5.keymgr_cfg_regwen.3075372649 Jun 01 03:03:25 PM PDT 24 Jun 01 03:03:30 PM PDT 24 69019116 ps
T395 /workspace/coverage/default/44.keymgr_stress_all.1126513482 Jun 01 03:06:29 PM PDT 24 Jun 01 03:08:16 PM PDT 24 10762840880 ps
T1032 /workspace/coverage/default/42.keymgr_sideload.3711761295 Jun 01 03:06:22 PM PDT 24 Jun 01 03:06:25 PM PDT 24 63832543 ps
T1033 /workspace/coverage/default/41.keymgr_alert_test.2764746074 Jun 01 03:06:20 PM PDT 24 Jun 01 03:06:21 PM PDT 24 42898961 ps
T459 /workspace/coverage/default/40.keymgr_cfg_regwen.2113086909 Jun 01 03:06:21 PM PDT 24 Jun 01 03:06:26 PM PDT 24 100153537 ps
T1034 /workspace/coverage/default/13.keymgr_sideload.3066429533 Jun 01 03:04:04 PM PDT 24 Jun 01 03:04:07 PM PDT 24 211110473 ps
T1035 /workspace/coverage/default/24.keymgr_lc_disable.3753700721 Jun 01 03:04:56 PM PDT 24 Jun 01 03:04:59 PM PDT 24 136270283 ps
T167 /workspace/coverage/default/49.keymgr_custom_cm.1296172192 Jun 01 03:06:55 PM PDT 24 Jun 01 03:07:00 PM PDT 24 426818150 ps
T1036 /workspace/coverage/default/13.keymgr_sideload_protect.3094161130 Jun 01 03:04:11 PM PDT 24 Jun 01 03:04:14 PM PDT 24 226842266 ps
T1037 /workspace/coverage/default/46.keymgr_sideload_otbn.1900611351 Jun 01 03:06:39 PM PDT 24 Jun 01 03:06:44 PM PDT 24 1142847857 ps
T1038 /workspace/coverage/default/16.keymgr_sideload_kmac.3128118771 Jun 01 03:04:20 PM PDT 24 Jun 01 03:04:25 PM PDT 24 267449790 ps
T1039 /workspace/coverage/default/23.keymgr_sideload.2861690285 Jun 01 03:05:01 PM PDT 24 Jun 01 03:05:14 PM PDT 24 2724027619 ps
T1040 /workspace/coverage/default/48.keymgr_sideload_aes.3702652334 Jun 01 03:06:45 PM PDT 24 Jun 01 03:06:49 PM PDT 24 95460531 ps
T1041 /workspace/coverage/default/44.keymgr_sideload.2115125540 Jun 01 03:06:28 PM PDT 24 Jun 01 03:06:31 PM PDT 24 64656306 ps
T1042 /workspace/coverage/default/36.keymgr_alert_test.1036159196 Jun 01 03:05:59 PM PDT 24 Jun 01 03:06:00 PM PDT 24 27730631 ps
T106 /workspace/coverage/default/3.keymgr_sec_cm.2707029012 Jun 01 03:03:15 PM PDT 24 Jun 01 03:03:33 PM PDT 24 2775445832 ps
T1043 /workspace/coverage/default/43.keymgr_smoke.3682774209 Jun 01 03:06:20 PM PDT 24 Jun 01 03:06:25 PM PDT 24 335615077 ps
T1044 /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1008931286 Jun 01 03:04:14 PM PDT 24 Jun 01 03:04:52 PM PDT 24 1127888742 ps
T1045 /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1789267693 Jun 01 03:05:36 PM PDT 24 Jun 01 03:05:39 PM PDT 24 243729872 ps
T1046 /workspace/coverage/default/2.keymgr_sideload_kmac.3047506406 Jun 01 03:03:06 PM PDT 24 Jun 01 03:03:13 PM PDT 24 400102562 ps
T1047 /workspace/coverage/default/24.keymgr_sideload_protect.2288803340 Jun 01 03:05:06 PM PDT 24 Jun 01 03:05:13 PM PDT 24 1171970696 ps
T1048 /workspace/coverage/default/44.keymgr_sw_invalid_input.476404726 Jun 01 03:06:29 PM PDT 24 Jun 01 03:06:34 PM PDT 24 135077430 ps
T371 /workspace/coverage/default/22.keymgr_kmac_rsp_err.3938250934 Jun 01 03:04:50 PM PDT 24 Jun 01 03:04:56 PM PDT 24 741135724 ps
T377 /workspace/coverage/default/14.keymgr_lc_disable.1404339174 Jun 01 03:04:12 PM PDT 24 Jun 01 03:04:18 PM PDT 24 210922436 ps
T1049 /workspace/coverage/default/33.keymgr_sideload_otbn.1173460776 Jun 01 03:05:41 PM PDT 24 Jun 01 03:05:50 PM PDT 24 742389753 ps
T1050 /workspace/coverage/default/26.keymgr_sw_invalid_input.1957491497 Jun 01 03:05:07 PM PDT 24 Jun 01 03:05:12 PM PDT 24 81534541 ps
T1051 /workspace/coverage/default/7.keymgr_sideload_aes.2196360080 Jun 01 03:03:29 PM PDT 24 Jun 01 03:03:33 PM PDT 24 277585398 ps
T384 /workspace/coverage/default/5.keymgr_kmac_rsp_err.462630058 Jun 01 03:03:23 PM PDT 24 Jun 01 03:03:27 PM PDT 24 310500745 ps
T1052 /workspace/coverage/default/39.keymgr_sync_async_fault_cross.366371030 Jun 01 03:06:13 PM PDT 24 Jun 01 03:06:16 PM PDT 24 54500267 ps
T1053 /workspace/coverage/default/44.keymgr_sideload_kmac.79411829 Jun 01 03:06:28 PM PDT 24 Jun 01 03:06:31 PM PDT 24 34189069 ps
T1054 /workspace/coverage/default/46.keymgr_alert_test.578573921 Jun 01 03:06:36 PM PDT 24 Jun 01 03:06:37 PM PDT 24 12819846 ps
T1055 /workspace/coverage/default/18.keymgr_sideload.3219651693 Jun 01 03:04:29 PM PDT 24 Jun 01 03:04:35 PM PDT 24 142834784 ps
T334 /workspace/coverage/default/3.keymgr_stress_all.3668870715 Jun 01 03:03:15 PM PDT 24 Jun 01 03:03:20 PM PDT 24 358737377 ps
T1056 /workspace/coverage/default/6.keymgr_sideload.2306231317 Jun 01 03:03:24 PM PDT 24 Jun 01 03:03:31 PM PDT 24 803776969 ps
T415 /workspace/coverage/default/19.keymgr_hwsw_invalid_input.570634013 Jun 01 03:04:39 PM PDT 24 Jun 01 03:04:42 PM PDT 24 125079370 ps
T1057 /workspace/coverage/default/40.keymgr_sideload_kmac.1243440394 Jun 01 03:06:14 PM PDT 24 Jun 01 03:06:47 PM PDT 24 1150161606 ps
T1058 /workspace/coverage/default/32.keymgr_sw_invalid_input.2795379096 Jun 01 03:05:36 PM PDT 24 Jun 01 03:05:48 PM PDT 24 413780701 ps
T1059 /workspace/coverage/default/33.keymgr_smoke.465938352 Jun 01 03:05:42 PM PDT 24 Jun 01 03:05:45 PM PDT 24 122763317 ps
T1060 /workspace/coverage/default/16.keymgr_lc_disable.4154462641 Jun 01 03:04:21 PM PDT 24 Jun 01 03:04:24 PM PDT 24 141457808 ps
T1061 /workspace/coverage/default/30.keymgr_sideload_protect.618715716 Jun 01 03:05:38 PM PDT 24 Jun 01 03:05:41 PM PDT 24 121680702 ps
T1062 /workspace/coverage/default/13.keymgr_sw_invalid_input.1941881916 Jun 01 03:04:11 PM PDT 24 Jun 01 03:05:48 PM PDT 24 5225018105 ps
T249 /workspace/coverage/default/15.keymgr_lc_disable.4033317303 Jun 01 03:04:15 PM PDT 24 Jun 01 03:04:19 PM PDT 24 436534878 ps
T1063 /workspace/coverage/default/1.keymgr_random.689468120 Jun 01 03:03:04 PM PDT 24 Jun 01 03:03:30 PM PDT 24 997118408 ps
T1064 /workspace/coverage/default/24.keymgr_cfg_regwen.424391512 Jun 01 03:04:56 PM PDT 24 Jun 01 03:05:00 PM PDT 24 198229590 ps

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2479994385
Short name T5
Test name
Test status
Simulation time 402372189 ps
CPU time 10.4 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 213996 kb
Host smart-ee445d36-862f-4a23-bb7c-baa0f4502875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479994385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2479994385
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4036266343
Short name T7
Test name
Test status
Simulation time 2229618015 ps
CPU time 40.6 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:41 PM PDT 24
Peak memory 221688 kb
Host smart-c87e789e-1965-47ca-b1bb-41ef4422b662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036266343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4036266343
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2759362865
Short name T53
Test name
Test status
Simulation time 4033712076 ps
CPU time 41.73 seconds
Started Jun 01 03:05:58 PM PDT 24
Finished Jun 01 03:06:40 PM PDT 24
Peak memory 221988 kb
Host smart-bb6d6c35-3d5d-4d29-8d13-7b17807dfb6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759362865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2759362865
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.873371108
Short name T9
Test name
Test status
Simulation time 541750051 ps
CPU time 17.04 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:43 PM PDT 24
Peak memory 239708 kb
Host smart-f63e2c44-36ff-45e4-8d6d-feb6dd48e4b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873371108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.873371108
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1594342599
Short name T120
Test name
Test status
Simulation time 117293760 ps
CPU time 3.12 seconds
Started Jun 01 03:26:13 PM PDT 24
Finished Jun 01 03:26:17 PM PDT 24
Peak memory 213856 kb
Host smart-a5e8b264-8097-4998-a669-f87f9f3e4ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594342599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1594342599
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.630976055
Short name T61
Test name
Test status
Simulation time 7374208840 ps
CPU time 78.25 seconds
Started Jun 01 03:06:12 PM PDT 24
Finished Jun 01 03:07:30 PM PDT 24
Peak memory 216332 kb
Host smart-319bafb0-d517-4210-8aa5-8f46ded416a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630976055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.630976055
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2309051396
Short name T10
Test name
Test status
Simulation time 300535383 ps
CPU time 2.69 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 210404 kb
Host smart-681cc39b-91b2-4062-a9ed-8678b038d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309051396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2309051396
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2258422333
Short name T119
Test name
Test status
Simulation time 889340679 ps
CPU time 6.69 seconds
Started Jun 01 03:26:25 PM PDT 24
Finished Jun 01 03:26:32 PM PDT 24
Peak memory 214072 kb
Host smart-4cfc78d2-c678-45d3-b9d5-9f6fa330848b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258422333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2258422333
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.277501042
Short name T51
Test name
Test status
Simulation time 62926392 ps
CPU time 2.25 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 210028 kb
Host smart-04819cd4-24ff-4f26-8ff7-2edf0f3e5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277501042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.277501042
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.637658303
Short name T273
Test name
Test status
Simulation time 877774896 ps
CPU time 17.99 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:42 PM PDT 24
Peak memory 214672 kb
Host smart-9124b3a7-fa61-4265-8d1f-2b7abc6eba33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637658303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.637658303
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2653218159
Short name T6
Test name
Test status
Simulation time 256459888 ps
CPU time 4.53 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:03 PM PDT 24
Peak memory 208440 kb
Host smart-35370a46-ff4c-4f80-93e5-199938d7fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653218159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2653218159
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1683393162
Short name T54
Test name
Test status
Simulation time 1811866998 ps
CPU time 32.58 seconds
Started Jun 01 03:03:54 PM PDT 24
Finished Jun 01 03:04:27 PM PDT 24
Peak memory 221304 kb
Host smart-76699fdb-981e-4839-a9e9-c527f02a0f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683393162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1683393162
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3850236484
Short name T47
Test name
Test status
Simulation time 96502162 ps
CPU time 3.35 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:53 PM PDT 24
Peak memory 219564 kb
Host smart-82adb4f7-fa6e-462d-9e84-8733e6fc7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850236484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3850236484
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2718127100
Short name T437
Test name
Test status
Simulation time 652331427 ps
CPU time 9.33 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:15 PM PDT 24
Peak memory 215236 kb
Host smart-c32d69d9-395c-4dba-bcd2-f79d3e8b3caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718127100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2718127100
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3154546058
Short name T93
Test name
Test status
Simulation time 509901817 ps
CPU time 5.17 seconds
Started Jun 01 03:06:47 PM PDT 24
Finished Jun 01 03:06:53 PM PDT 24
Peak memory 214000 kb
Host smart-17028ed2-511a-4824-afbd-c4a02cbed095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154546058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3154546058
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2460723949
Short name T127
Test name
Test status
Simulation time 967210561 ps
CPU time 5.32 seconds
Started Jun 01 03:26:12 PM PDT 24
Finished Jun 01 03:26:18 PM PDT 24
Peak memory 214072 kb
Host smart-b557a3cc-10da-41b0-96ea-49c19f23978f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460723949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2460723949
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3641890810
Short name T329
Test name
Test status
Simulation time 5005958028 ps
CPU time 159.42 seconds
Started Jun 01 03:04:49 PM PDT 24
Finished Jun 01 03:07:29 PM PDT 24
Peak memory 214976 kb
Host smart-f70863f3-d446-4822-9556-bf644f234915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641890810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3641890810
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1764050527
Short name T41
Test name
Test status
Simulation time 792228456 ps
CPU time 9.06 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 213900 kb
Host smart-d662d5fd-d1e5-467f-b792-e588fb89d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764050527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1764050527
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4159605906
Short name T386
Test name
Test status
Simulation time 1402671582 ps
CPU time 18.17 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:47 PM PDT 24
Peak memory 215468 kb
Host smart-a6f6e7d0-8b26-48c2-bcb7-f3652275bff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159605906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4159605906
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3766908251
Short name T104
Test name
Test status
Simulation time 858152541 ps
CPU time 10.45 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:33 PM PDT 24
Peak memory 223256 kb
Host smart-4c9867af-cbc7-431a-907b-04954c15ddef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766908251 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3766908251
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1374647730
Short name T272
Test name
Test status
Simulation time 1403347104 ps
CPU time 18.3 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 214220 kb
Host smart-76ded51c-d340-4432-9469-e1b6d3987964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374647730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1374647730
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3615137495
Short name T24
Test name
Test status
Simulation time 80936358 ps
CPU time 3.06 seconds
Started Jun 01 03:06:08 PM PDT 24
Finished Jun 01 03:06:11 PM PDT 24
Peak memory 222128 kb
Host smart-209f1928-556f-4fc0-beac-6a44a86327f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615137495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3615137495
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4238776805
Short name T56
Test name
Test status
Simulation time 2298545537 ps
CPU time 25.69 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 216172 kb
Host smart-6569a51b-59e0-48c4-b643-6488ded81c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238776805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4238776805
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.739454492
Short name T364
Test name
Test status
Simulation time 818421473 ps
CPU time 10.66 seconds
Started Jun 01 03:05:14 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 214044 kb
Host smart-d181d213-8912-4b58-97eb-848a934e1e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739454492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.739454492
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1142755765
Short name T768
Test name
Test status
Simulation time 112951401 ps
CPU time 2.55 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:00 PM PDT 24
Peak memory 208428 kb
Host smart-6763a4f2-8e60-4576-a811-b534bd89f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142755765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1142755765
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1595119253
Short name T20
Test name
Test status
Simulation time 2288936548 ps
CPU time 77.28 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:05:30 PM PDT 24
Peak memory 213996 kb
Host smart-fedd3672-ec2c-40f7-8fde-43231b181cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595119253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1595119253
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1915145331
Short name T342
Test name
Test status
Simulation time 278676272 ps
CPU time 15.65 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 221940 kb
Host smart-97bda118-8591-44d2-98ed-62acc4a674b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915145331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1915145331
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3581299290
Short name T66
Test name
Test status
Simulation time 3013351414 ps
CPU time 60.65 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:05:31 PM PDT 24
Peak memory 215468 kb
Host smart-7e3189f6-1b98-43bc-9f6f-0038ca899f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581299290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3581299290
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3170196338
Short name T29
Test name
Test status
Simulation time 175819201 ps
CPU time 5.49 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 219568 kb
Host smart-f86ada0e-ef08-46fe-89da-a9513d7a4536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170196338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3170196338
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.192755956
Short name T38
Test name
Test status
Simulation time 323475352 ps
CPU time 10.03 seconds
Started Jun 01 03:05:03 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 214000 kb
Host smart-68d0a1b6-d04b-4fe4-be36-a2419f1ce9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192755956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.192755956
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1963201892
Short name T320
Test name
Test status
Simulation time 151573237 ps
CPU time 3.22 seconds
Started Jun 01 03:06:38 PM PDT 24
Finished Jun 01 03:06:42 PM PDT 24
Peak memory 214028 kb
Host smart-f18e849a-4aa3-4d43-bf20-76d4fc944403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963201892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1963201892
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4104550529
Short name T162
Test name
Test status
Simulation time 134094575 ps
CPU time 5.88 seconds
Started Jun 01 03:06:41 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 218164 kb
Host smart-a20d525b-b22d-4e48-b8dc-304d3d4c6784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104550529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4104550529
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1240827468
Short name T27
Test name
Test status
Simulation time 129706786 ps
CPU time 3.51 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:02 PM PDT 24
Peak memory 209044 kb
Host smart-635df7b0-59ac-42fe-932e-c1a6a3bd4582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240827468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1240827468
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.426925428
Short name T293
Test name
Test status
Simulation time 241146073 ps
CPU time 4.46 seconds
Started Jun 01 03:04:09 PM PDT 24
Finished Jun 01 03:04:14 PM PDT 24
Peak memory 222132 kb
Host smart-447025a3-69fb-44ed-a0f2-caa5c59a1722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426925428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.426925428
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1412580475
Short name T138
Test name
Test status
Simulation time 1093098725 ps
CPU time 11.53 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:50 PM PDT 24
Peak memory 213836 kb
Host smart-d848c654-230d-4afe-aa14-a59556e28bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412580475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1412580475
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1353327044
Short name T456
Test name
Test status
Simulation time 3971455506 ps
CPU time 52.56 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:07:21 PM PDT 24
Peak memory 222188 kb
Host smart-ed759fa3-5d1c-445a-99e1-329105a18f5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353327044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1353327044
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3878934481
Short name T236
Test name
Test status
Simulation time 3924429890 ps
CPU time 27.75 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 221500 kb
Host smart-3627d401-cc05-4c64-b9b1-053c6ab39d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878934481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3878934481
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3407902178
Short name T14
Test name
Test status
Simulation time 24940351 ps
CPU time 1.89 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 208412 kb
Host smart-859e2c5d-13cf-4da1-b2ff-ae4bac9c905d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407902178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3407902178
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3504849597
Short name T21
Test name
Test status
Simulation time 1197927576 ps
CPU time 8.07 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:06 PM PDT 24
Peak memory 218304 kb
Host smart-7e2662ce-6cf9-4f77-9428-7f43276d4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504849597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3504849597
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.367679773
Short name T58
Test name
Test status
Simulation time 7688287411 ps
CPU time 99.25 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:04:45 PM PDT 24
Peak memory 232716 kb
Host smart-7d917af6-84d8-46bd-959c-e0066d1cb5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367679773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.367679773
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1120665976
Short name T577
Test name
Test status
Simulation time 38590855 ps
CPU time 0.94 seconds
Started Jun 01 03:03:08 PM PDT 24
Finished Jun 01 03:03:09 PM PDT 24
Peak memory 205676 kb
Host smart-459bcb63-1d9b-4b2a-8382-eb3f92da374a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120665976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1120665976
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1589322530
Short name T174
Test name
Test status
Simulation time 733236395 ps
CPU time 6.72 seconds
Started Jun 01 03:24:58 PM PDT 24
Finished Jun 01 03:25:05 PM PDT 24
Peak memory 213796 kb
Host smart-5d17fd0e-6c51-43ae-9b20-dc7cdfd6f27a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589322530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1589322530
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2063869066
Short name T859
Test name
Test status
Simulation time 40479164 ps
CPU time 2.88 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:11 PM PDT 24
Peak memory 210716 kb
Host smart-640adca0-3e0b-44c6-a60f-31832f3f3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063869066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2063869066
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1129387312
Short name T298
Test name
Test status
Simulation time 396782086 ps
CPU time 5.98 seconds
Started Jun 01 03:02:59 PM PDT 24
Finished Jun 01 03:03:05 PM PDT 24
Peak memory 214044 kb
Host smart-1c4ca752-48a5-4695-b861-01b4a686eb31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129387312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1129387312
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4231398888
Short name T444
Test name
Test status
Simulation time 50603394 ps
CPU time 3.58 seconds
Started Jun 01 03:06:30 PM PDT 24
Finished Jun 01 03:06:34 PM PDT 24
Peak memory 214040 kb
Host smart-eace9e9f-e039-4267-aeda-ded364c02743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231398888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4231398888
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2137172433
Short name T278
Test name
Test status
Simulation time 1970256863 ps
CPU time 45.95 seconds
Started Jun 01 03:03:33 PM PDT 24
Finished Jun 01 03:04:19 PM PDT 24
Peak memory 222264 kb
Host smart-6a2d0fb4-bd18-4e46-8d88-2fd1bea47693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137172433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2137172433
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2348582213
Short name T165
Test name
Test status
Simulation time 46928440 ps
CPU time 2.25 seconds
Started Jun 01 03:03:10 PM PDT 24
Finished Jun 01 03:03:12 PM PDT 24
Peak memory 215020 kb
Host smart-98700b45-3f6b-4e64-8e37-20699597b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348582213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2348582213
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.786285273
Short name T166
Test name
Test status
Simulation time 170034474 ps
CPU time 4.24 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 222264 kb
Host smart-548fa55b-2e2e-46ae-b096-a9b90feb474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786285273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.786285273
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2306707538
Short name T173
Test name
Test status
Simulation time 274557490 ps
CPU time 10.11 seconds
Started Jun 01 03:25:37 PM PDT 24
Finished Jun 01 03:25:48 PM PDT 24
Peak memory 208620 kb
Host smart-ef7fd156-bc77-4387-a422-fcc8c4692c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306707538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2306707538
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2452753046
Short name T135
Test name
Test status
Simulation time 1287299383 ps
CPU time 22.33 seconds
Started Jun 01 03:25:47 PM PDT 24
Finished Jun 01 03:26:10 PM PDT 24
Peak memory 209380 kb
Host smart-d7a715aa-63f7-45d6-a063-b42b4e70f88e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452753046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2452753046
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3804171862
Short name T163
Test name
Test status
Simulation time 2486653237 ps
CPU time 19.7 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:26 PM PDT 24
Peak memory 217340 kb
Host smart-61f0db86-7fcd-4758-becb-6eeaca2b8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804171862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3804171862
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3655746130
Short name T281
Test name
Test status
Simulation time 422051418 ps
CPU time 16.93 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:16 PM PDT 24
Peak memory 216168 kb
Host smart-8c57bb69-5d30-47b8-a32d-67a9b77b40d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655746130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3655746130
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1220094098
Short name T328
Test name
Test status
Simulation time 63639035 ps
CPU time 3.61 seconds
Started Jun 01 03:04:10 PM PDT 24
Finished Jun 01 03:04:14 PM PDT 24
Peak memory 222084 kb
Host smart-52f236a2-6328-44cc-ae13-4eba8e68b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220094098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1220094098
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3166948621
Short name T452
Test name
Test status
Simulation time 57705695 ps
CPU time 4.57 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:27 PM PDT 24
Peak memory 214280 kb
Host smart-065abb76-0245-46b2-b4e1-34b33768ff06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166948621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3166948621
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_random.1441043394
Short name T352
Test name
Test status
Simulation time 257703264 ps
CPU time 4.85 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:05:01 PM PDT 24
Peak memory 217928 kb
Host smart-4bafb172-5a3e-490f-850b-6f3437ad6798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441043394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1441043394
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3939377003
Short name T123
Test name
Test status
Simulation time 4071650463 ps
CPU time 17.55 seconds
Started Jun 01 03:05:37 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 214912 kb
Host smart-a52d4af9-6aa7-405b-b771-28105b81956f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939377003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3939377003
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2413564834
Short name T1
Test name
Test status
Simulation time 231568256 ps
CPU time 3.27 seconds
Started Jun 01 03:06:36 PM PDT 24
Finished Jun 01 03:06:40 PM PDT 24
Peak memory 206624 kb
Host smart-763da9d3-1a8a-4957-8c9e-7b9938db66f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413564834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2413564834
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1021774711
Short name T67
Test name
Test status
Simulation time 110397571 ps
CPU time 2.68 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:24 PM PDT 24
Peak memory 209708 kb
Host smart-0f6a48bf-ab50-4a48-b855-796cffaf5b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021774711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1021774711
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1949563329
Short name T99
Test name
Test status
Simulation time 53670851 ps
CPU time 3.16 seconds
Started Jun 01 03:03:17 PM PDT 24
Finished Jun 01 03:03:21 PM PDT 24
Peak memory 219700 kb
Host smart-f3d10ade-9a72-4e87-b29e-aaae775afd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949563329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1949563329
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1890186240
Short name T168
Test name
Test status
Simulation time 197355912 ps
CPU time 4.82 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:33 PM PDT 24
Peak memory 222380 kb
Host smart-3541be03-8924-4e84-9a61-35458695aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890186240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1890186240
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1258182553
Short name T169
Test name
Test status
Simulation time 145289483 ps
CPU time 4.66 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 222336 kb
Host smart-31dc223b-1b2e-48dc-933f-311cf6501460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258182553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1258182553
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2073440039
Short name T70
Test name
Test status
Simulation time 245096831 ps
CPU time 3.21 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:01 PM PDT 24
Peak memory 214052 kb
Host smart-e22797c2-201e-44aa-9505-469f5bc67df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073440039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2073440039
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1746430415
Short name T351
Test name
Test status
Simulation time 195777079 ps
CPU time 7.57 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:04:04 PM PDT 24
Peak memory 213844 kb
Host smart-c1eef577-21f4-4c2c-89b9-6592404b6f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746430415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1746430415
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1981031172
Short name T445
Test name
Test status
Simulation time 537115304 ps
CPU time 8.05 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 214312 kb
Host smart-9145982c-e75e-41ca-80b9-8f1b9f3b0d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981031172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1981031172
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2917653752
Short name T401
Test name
Test status
Simulation time 6360886238 ps
CPU time 39.39 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 222252 kb
Host smart-dee99053-0957-47c6-b15f-06f5c4349c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917653752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2917653752
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.612747422
Short name T404
Test name
Test status
Simulation time 1133769497 ps
CPU time 5.24 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:34 PM PDT 24
Peak memory 209580 kb
Host smart-d41ee744-5588-491a-a5a3-374628a90dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612747422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.612747422
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4197169622
Short name T178
Test name
Test status
Simulation time 914867482 ps
CPU time 5.03 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:16 PM PDT 24
Peak memory 210856 kb
Host smart-65f37e9c-5f16-43b1-8f49-9afe11d7ec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197169622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4197169622
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3957167027
Short name T185
Test name
Test status
Simulation time 67439618 ps
CPU time 2.9 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 209648 kb
Host smart-086d8080-322e-472b-9354-9002e4aee067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957167027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3957167027
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4003176730
Short name T164
Test name
Test status
Simulation time 1480736905 ps
CPU time 17.11 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:23 PM PDT 24
Peak memory 215300 kb
Host smart-29ccce85-a375-46e1-9e96-7cd2109dfea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003176730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4003176730
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1296172192
Short name T167
Test name
Test status
Simulation time 426818150 ps
CPU time 4.84 seconds
Started Jun 01 03:06:55 PM PDT 24
Finished Jun 01 03:07:00 PM PDT 24
Peak memory 222244 kb
Host smart-185b8926-4916-4229-9673-7df0d70c2f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296172192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1296172192
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1433436473
Short name T785
Test name
Test status
Simulation time 979200191 ps
CPU time 38.13 seconds
Started Jun 01 03:03:57 PM PDT 24
Finished Jun 01 03:04:36 PM PDT 24
Peak memory 216696 kb
Host smart-55f1db7a-73d3-4638-a4b2-5b211fb92b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433436473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1433436473
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1265332275
Short name T267
Test name
Test status
Simulation time 2265763418 ps
CPU time 10.97 seconds
Started Jun 01 03:03:55 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 214048 kb
Host smart-1160ecaf-91dd-4430-9a53-20905a4d0802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265332275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1265332275
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.908482975
Short name T322
Test name
Test status
Simulation time 174105958 ps
CPU time 7.61 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:21 PM PDT 24
Peak memory 214020 kb
Host smart-d8fcb3d5-7fb1-4677-8f3b-b7fb4d542569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908482975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.908482975
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.647377569
Short name T237
Test name
Test status
Simulation time 3365335218 ps
CPU time 35.95 seconds
Started Jun 01 03:04:22 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 215780 kb
Host smart-fe55cc6d-6498-468a-8693-a829915a96eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647377569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.647377569
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.570634013
Short name T415
Test name
Test status
Simulation time 125079370 ps
CPU time 2.29 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:04:42 PM PDT 24
Peak memory 208304 kb
Host smart-392e7bc8-6bee-45f3-a113-6a646acfc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570634013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.570634013
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2817552221
Short name T217
Test name
Test status
Simulation time 88605547 ps
CPU time 4.39 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:02 PM PDT 24
Peak memory 209476 kb
Host smart-ca3fdfcf-3019-4285-8eea-442cfc1d8b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817552221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2817552221
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.713583705
Short name T230
Test name
Test status
Simulation time 344183264 ps
CPU time 5.43 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 219460 kb
Host smart-ca533f8e-c2e5-406d-91ad-9ffa2252a6b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713583705 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.713583705
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1533523911
Short name T199
Test name
Test status
Simulation time 97752566 ps
CPU time 3.19 seconds
Started Jun 01 03:25:14 PM PDT 24
Finished Jun 01 03:25:18 PM PDT 24
Peak memory 213828 kb
Host smart-e849fb8d-d435-424c-b52c-2dfdf03605f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533523911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1533523911
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.697888097
Short name T176
Test name
Test status
Simulation time 327761844 ps
CPU time 7.22 seconds
Started Jun 01 03:26:08 PM PDT 24
Finished Jun 01 03:26:16 PM PDT 24
Peak memory 208288 kb
Host smart-0f890547-37a1-4b08-b4bb-842a6ccc5dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697888097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.697888097
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.275029657
Short name T179
Test name
Test status
Simulation time 648215164 ps
CPU time 3.28 seconds
Started Jun 01 03:26:17 PM PDT 24
Finished Jun 01 03:26:21 PM PDT 24
Peak memory 213724 kb
Host smart-5808f2ff-354b-438a-abca-7237a452a5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275029657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.275029657
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.858349678
Short name T187
Test name
Test status
Simulation time 2354465147 ps
CPU time 15.98 seconds
Started Jun 01 03:26:27 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 209080 kb
Host smart-dbf9cc9c-dc40-4e8c-ac7b-f6150a87a08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858349678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.858349678
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2268714590
Short name T183
Test name
Test status
Simulation time 157379898 ps
CPU time 5.27 seconds
Started Jun 01 03:25:15 PM PDT 24
Finished Jun 01 03:25:21 PM PDT 24
Peak memory 208868 kb
Host smart-6a320f48-a401-4b8f-8e2e-0a96299053e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268714590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2268714590
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.847401055
Short name T182
Test name
Test status
Simulation time 180358540 ps
CPU time 1.64 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:03:58 PM PDT 24
Peak memory 209668 kb
Host smart-7abb2276-7dd5-442f-80a0-c4a7c952daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847401055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.847401055
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3243785694
Short name T180
Test name
Test status
Simulation time 1739784366 ps
CPU time 42.16 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:48 PM PDT 24
Peak memory 210596 kb
Host smart-ec1f0552-648d-4565-b95a-4b396190a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243785694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3243785694
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1367685830
Short name T570
Test name
Test status
Simulation time 2436500265 ps
CPU time 34.16 seconds
Started Jun 01 03:03:03 PM PDT 24
Finished Jun 01 03:03:38 PM PDT 24
Peak memory 207928 kb
Host smart-6dc331cd-7f58-4e27-93e7-fe9877112a0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367685830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1367685830
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3154707450
Short name T373
Test name
Test status
Simulation time 157374604 ps
CPU time 2.94 seconds
Started Jun 01 03:03:45 PM PDT 24
Finished Jun 01 03:03:49 PM PDT 24
Peak memory 215056 kb
Host smart-bb359729-b2ac-44d8-bd0a-ba15a21f9825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154707450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3154707450
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2890177483
Short name T303
Test name
Test status
Simulation time 2009057318 ps
CPU time 23.61 seconds
Started Jun 01 03:03:55 PM PDT 24
Finished Jun 01 03:04:19 PM PDT 24
Peak memory 220628 kb
Host smart-2c403bba-87bb-46eb-8033-0d7d6d684cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890177483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2890177483
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1145359707
Short name T248
Test name
Test status
Simulation time 50109499 ps
CPU time 3.86 seconds
Started Jun 01 03:04:01 PM PDT 24
Finished Jun 01 03:04:05 PM PDT 24
Peak memory 206964 kb
Host smart-ef69fb03-b1d3-4b01-9e63-40b10d4f5b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145359707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1145359707
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1106954927
Short name T271
Test name
Test status
Simulation time 299728198 ps
CPU time 15.77 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 215036 kb
Host smart-acc7e45b-ad37-4487-963a-22f8282926e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106954927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1106954927
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_random.2077126033
Short name T333
Test name
Test status
Simulation time 235828230 ps
CPU time 9.32 seconds
Started Jun 01 03:03:55 PM PDT 24
Finished Jun 01 03:04:04 PM PDT 24
Peak memory 219364 kb
Host smart-322b66f6-f7e6-4585-a720-f6e70cd1cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077126033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2077126033
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.478683751
Short name T316
Test name
Test status
Simulation time 199605244 ps
CPU time 4.67 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:04:01 PM PDT 24
Peak memory 209716 kb
Host smart-9813dfd5-f8d4-4b37-b45d-d909943d2975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478683751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.478683751
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1492498916
Short name T94
Test name
Test status
Simulation time 149843249 ps
CPU time 2.68 seconds
Started Jun 01 03:04:09 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 220088 kb
Host smart-79dab56a-5043-4f90-ab20-25fb3cc556cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492498916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1492498916
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2010547687
Short name T49
Test name
Test status
Simulation time 45588188 ps
CPU time 2.5 seconds
Started Jun 01 03:04:09 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 214060 kb
Host smart-cb5cbd82-09ec-4cf0-afe7-003ae05ffba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010547687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2010547687
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3573857496
Short name T375
Test name
Test status
Simulation time 5800929783 ps
CPU time 76.41 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:05:29 PM PDT 24
Peak memory 222240 kb
Host smart-4568fdde-923e-4187-aebd-5db8b0b843e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573857496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3573857496
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3394071919
Short name T363
Test name
Test status
Simulation time 61136655 ps
CPU time 2.55 seconds
Started Jun 01 03:04:10 PM PDT 24
Finished Jun 01 03:04:13 PM PDT 24
Peak memory 214052 kb
Host smart-03e51087-53bf-4097-8998-a2f38521526e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394071919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3394071919
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.603389672
Short name T355
Test name
Test status
Simulation time 284079885 ps
CPU time 14.26 seconds
Started Jun 01 03:04:23 PM PDT 24
Finished Jun 01 03:04:38 PM PDT 24
Peak memory 222248 kb
Host smart-359785e4-6546-4766-beb0-f9cf8919daf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603389672 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.603389672
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.393063774
Short name T294
Test name
Test status
Simulation time 1888783747 ps
CPU time 17.11 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 215316 kb
Host smart-b1ef582a-7b99-49c1-8f41-e720dfb64cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393063774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.393063774
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3233116503
Short name T388
Test name
Test status
Simulation time 132356842 ps
CPU time 2.49 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:04:41 PM PDT 24
Peak memory 213884 kb
Host smart-b309f733-ab94-4967-854e-1938e8859acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233116503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3233116503
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1796289084
Short name T440
Test name
Test status
Simulation time 442684149 ps
CPU time 6.04 seconds
Started Jun 01 03:03:10 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 213972 kb
Host smart-45102669-d0a0-4997-81e8-bca3d5cbb5f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796289084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1796289084
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1092280223
Short name T222
Test name
Test status
Simulation time 245804733 ps
CPU time 7.31 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 213952 kb
Host smart-3ca64e57-b649-493d-8a16-786f32ba3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092280223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1092280223
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2283028148
Short name T283
Test name
Test status
Simulation time 3647212720 ps
CPU time 12.43 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:05:03 PM PDT 24
Peak memory 214192 kb
Host smart-865c002a-b94b-4d50-9e64-16e6eba2fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283028148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2283028148
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2038485520
Short name T439
Test name
Test status
Simulation time 88370318 ps
CPU time 3.4 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 222120 kb
Host smart-0942a760-2348-4ee8-a686-5aea5a510a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038485520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2038485520
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3231260141
Short name T228
Test name
Test status
Simulation time 772028773 ps
CPU time 11.65 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:05:08 PM PDT 24
Peak memory 222356 kb
Host smart-cee19d17-5e8b-4f42-a52d-295d18ff9106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231260141 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3231260141
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.309961834
Short name T251
Test name
Test status
Simulation time 48885278 ps
CPU time 3.48 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 220336 kb
Host smart-00e883a5-354e-4462-b8cb-da74a2926dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309961834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.309961834
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1771683435
Short name T242
Test name
Test status
Simulation time 111422120 ps
CPU time 3.39 seconds
Started Jun 01 03:05:12 PM PDT 24
Finished Jun 01 03:05:16 PM PDT 24
Peak memory 214036 kb
Host smart-383762bf-35b0-48f6-807a-dc6e62646d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771683435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1771683435
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2098684722
Short name T382
Test name
Test status
Simulation time 39554973 ps
CPU time 2.73 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:30 PM PDT 24
Peak memory 220788 kb
Host smart-b8341542-296b-4807-9ce0-0d4b4bb83046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098684722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2098684722
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3437112725
Short name T253
Test name
Test status
Simulation time 2695949633 ps
CPU time 8.47 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 214116 kb
Host smart-132df3ec-3b8d-4096-a67d-8c75009d8a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437112725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3437112725
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1251768667
Short name T324
Test name
Test status
Simulation time 94207158 ps
CPU time 2.4 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:37 PM PDT 24
Peak memory 213932 kb
Host smart-4927410b-bd42-4e17-9a47-26586da7c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251768667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1251768667
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1191853514
Short name T343
Test name
Test status
Simulation time 78244510 ps
CPU time 4.68 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 214804 kb
Host smart-6e1cbbfd-64e0-4ddd-b3a1-d5280d1eda94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191853514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1191853514
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2231751832
Short name T244
Test name
Test status
Simulation time 96110722 ps
CPU time 3.48 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 218832 kb
Host smart-1dab3806-6a37-4b78-8df0-13c187adbcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231751832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2231751832
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2894761519
Short name T390
Test name
Test status
Simulation time 271761132 ps
CPU time 3.28 seconds
Started Jun 01 03:03:22 PM PDT 24
Finished Jun 01 03:03:25 PM PDT 24
Peak memory 209616 kb
Host smart-66dc05b3-dee8-4834-9164-4a95b651df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894761519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2894761519
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3483634421
Short name T32
Test name
Test status
Simulation time 117787357 ps
CPU time 5.09 seconds
Started Jun 01 03:03:33 PM PDT 24
Finished Jun 01 03:03:39 PM PDT 24
Peak memory 221324 kb
Host smart-b7ac2a6f-370d-4da7-8212-e7824f45ccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483634421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3483634421
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.740868198
Short name T353
Test name
Test status
Simulation time 1129903355 ps
CPU time 9.51 seconds
Started Jun 01 03:03:43 PM PDT 24
Finished Jun 01 03:03:53 PM PDT 24
Peak memory 216812 kb
Host smart-4ae0d9f6-c7d9-490c-9184-0cdcf72a7235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740868198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.740868198
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1434319703
Short name T161
Test name
Test status
Simulation time 296255925 ps
CPU time 3.63 seconds
Started Jun 01 03:05:53 PM PDT 24
Finished Jun 01 03:05:57 PM PDT 24
Peak memory 222340 kb
Host smart-12e9d33e-b321-4c4e-bde4-2f2bc9633e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434319703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1434319703
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2410529819
Short name T525
Test name
Test status
Simulation time 370793349 ps
CPU time 9.07 seconds
Started Jun 01 03:25:05 PM PDT 24
Finished Jun 01 03:25:15 PM PDT 24
Peak memory 205592 kb
Host smart-55c48458-f0c2-4310-b2ad-f4966f96e6af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410529819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
410529819
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2527030471
Short name T194
Test name
Test status
Simulation time 124766931 ps
CPU time 1.15 seconds
Started Jun 01 03:24:58 PM PDT 24
Finished Jun 01 03:24:59 PM PDT 24
Peak memory 205616 kb
Host smart-747b0386-9730-4bc7-b7d2-dfe4e222c837
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527030471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
527030471
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1489689139
Short name T505
Test name
Test status
Simulation time 15009310 ps
CPU time 1.15 seconds
Started Jun 01 03:25:03 PM PDT 24
Finished Jun 01 03:25:04 PM PDT 24
Peak memory 205664 kb
Host smart-a357a3b0-5893-4a39-9690-5f3c4bfd980a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489689139 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1489689139
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1521529751
Short name T508
Test name
Test status
Simulation time 10345719 ps
CPU time 1.02 seconds
Started Jun 01 03:24:58 PM PDT 24
Finished Jun 01 03:24:59 PM PDT 24
Peak memory 205600 kb
Host smart-8de34ccd-6de5-49a9-8653-020902c21da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521529751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1521529751
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1568516264
Short name T497
Test name
Test status
Simulation time 12239651 ps
CPU time 0.88 seconds
Started Jun 01 03:25:01 PM PDT 24
Finished Jun 01 03:25:02 PM PDT 24
Peak memory 205332 kb
Host smart-2340d224-0ace-464f-9921-a72b96f6254d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568516264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1568516264
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2168907455
Short name T537
Test name
Test status
Simulation time 186653681 ps
CPU time 2.35 seconds
Started Jun 01 03:25:06 PM PDT 24
Finished Jun 01 03:25:08 PM PDT 24
Peak memory 205592 kb
Host smart-f9dc5645-b056-460c-a59b-d69972aa5665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168907455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2168907455
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1622195421
Short name T192
Test name
Test status
Simulation time 245283124 ps
CPU time 2.93 seconds
Started Jun 01 03:24:59 PM PDT 24
Finished Jun 01 03:25:02 PM PDT 24
Peak memory 218844 kb
Host smart-fb7e7fb9-6eda-4da6-8d88-132d7150b26f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622195421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1622195421
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.102034452
Short name T133
Test name
Test status
Simulation time 224779158 ps
CPU time 2.03 seconds
Started Jun 01 03:25:01 PM PDT 24
Finished Jun 01 03:25:03 PM PDT 24
Peak memory 216012 kb
Host smart-dfdb1090-18b9-41d3-9a63-bdf85d05556e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102034452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.102034452
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1190916040
Short name T149
Test name
Test status
Simulation time 136976935 ps
CPU time 3.94 seconds
Started Jun 01 03:25:12 PM PDT 24
Finished Jun 01 03:25:17 PM PDT 24
Peak memory 205548 kb
Host smart-97b55b97-e160-412f-9541-b07e61d22b8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190916040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
190916040
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1548873163
Short name T193
Test name
Test status
Simulation time 39029686 ps
CPU time 1.16 seconds
Started Jun 01 03:25:10 PM PDT 24
Finished Jun 01 03:25:12 PM PDT 24
Peak memory 205572 kb
Host smart-414ae52f-492c-43e7-94a7-94346832a05b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548873163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
548873163
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2406472584
Short name T558
Test name
Test status
Simulation time 63658245 ps
CPU time 1.48 seconds
Started Jun 01 03:25:13 PM PDT 24
Finished Jun 01 03:25:15 PM PDT 24
Peak memory 213900 kb
Host smart-1055c9d4-4a8b-4693-826a-f5084f4919d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406472584 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2406472584
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3455710256
Short name T501
Test name
Test status
Simulation time 90263434 ps
CPU time 1.39 seconds
Started Jun 01 03:25:13 PM PDT 24
Finished Jun 01 03:25:15 PM PDT 24
Peak memory 205588 kb
Host smart-c825d318-6570-485f-8846-cbf40de04a24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455710256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3455710256
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2492839034
Short name T481
Test name
Test status
Simulation time 47248578 ps
CPU time 0.71 seconds
Started Jun 01 03:25:13 PM PDT 24
Finished Jun 01 03:25:14 PM PDT 24
Peak memory 205340 kb
Host smart-8f60870c-b86d-4c0c-b5df-b9086e1fcae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492839034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2492839034
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3001796595
Short name T209
Test name
Test status
Simulation time 238660659 ps
CPU time 2.07 seconds
Started Jun 01 03:25:05 PM PDT 24
Finished Jun 01 03:25:07 PM PDT 24
Peak memory 213992 kb
Host smart-1424106b-174f-4020-a829-704de62093ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001796595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3001796595
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2302412907
Short name T502
Test name
Test status
Simulation time 392752166 ps
CPU time 4.75 seconds
Started Jun 01 03:25:03 PM PDT 24
Finished Jun 01 03:25:08 PM PDT 24
Peak memory 214068 kb
Host smart-afffd70e-c7ef-4d35-949d-992e4ff2aceb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302412907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2302412907
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4025553227
Short name T522
Test name
Test status
Simulation time 55896677 ps
CPU time 1.34 seconds
Started Jun 01 03:26:02 PM PDT 24
Finished Jun 01 03:26:04 PM PDT 24
Peak memory 213904 kb
Host smart-e9ae2d99-25de-4316-a943-d75c8da728a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025553227 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4025553227
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2064757818
Short name T540
Test name
Test status
Simulation time 8265504 ps
CPU time 0.77 seconds
Started Jun 01 03:25:55 PM PDT 24
Finished Jun 01 03:25:56 PM PDT 24
Peak memory 205236 kb
Host smart-6e1a5890-e878-40ed-9ea9-e42b18fe5e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064757818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2064757818
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3898367291
Short name T158
Test name
Test status
Simulation time 99344116 ps
CPU time 1.99 seconds
Started Jun 01 03:25:55 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 205524 kb
Host smart-0fe02d47-680d-4f4e-a927-218d4d77df6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898367291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3898367291
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1425924195
Short name T544
Test name
Test status
Simulation time 465092729 ps
CPU time 5.69 seconds
Started Jun 01 03:25:54 PM PDT 24
Finished Jun 01 03:26:00 PM PDT 24
Peak memory 214148 kb
Host smart-f41a0648-a1c5-457f-9058-6c22ae6112e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425924195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1425924195
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.190280645
Short name T550
Test name
Test status
Simulation time 378408881 ps
CPU time 5.01 seconds
Started Jun 01 03:25:53 PM PDT 24
Finished Jun 01 03:25:59 PM PDT 24
Peak memory 214028 kb
Host smart-58fc2d90-b4e3-4db9-aa88-4dada40ed866
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190280645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.190280645
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2103361591
Short name T130
Test name
Test status
Simulation time 205965494 ps
CPU time 2.99 seconds
Started Jun 01 03:25:53 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 213884 kb
Host smart-f5341fb0-5a92-491d-91fb-30055e61336c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103361591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2103361591
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1647771991
Short name T206
Test name
Test status
Simulation time 34736625 ps
CPU time 1.3 seconds
Started Jun 01 03:26:10 PM PDT 24
Finished Jun 01 03:26:11 PM PDT 24
Peak memory 213776 kb
Host smart-1f5d7ec5-0e98-4c8f-8997-f3c063f624c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647771991 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1647771991
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4227215606
Short name T479
Test name
Test status
Simulation time 12290391 ps
CPU time 1.04 seconds
Started Jun 01 03:26:01 PM PDT 24
Finished Jun 01 03:26:02 PM PDT 24
Peak memory 205588 kb
Host smart-45dd19d7-80bf-4ea5-b565-ceb4a638d9d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227215606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4227215606
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1905197823
Short name T484
Test name
Test status
Simulation time 75370979 ps
CPU time 0.89 seconds
Started Jun 01 03:26:01 PM PDT 24
Finished Jun 01 03:26:03 PM PDT 24
Peak memory 205400 kb
Host smart-a65a9fd1-8c08-45c1-a9db-317465dd57c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905197823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1905197823
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1241210500
Short name T157
Test name
Test status
Simulation time 97808443 ps
CPU time 2.54 seconds
Started Jun 01 03:26:09 PM PDT 24
Finished Jun 01 03:26:12 PM PDT 24
Peak memory 205488 kb
Host smart-d823cef8-73f6-44d5-9fb8-bd24b20c31ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241210500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1241210500
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1070961921
Short name T526
Test name
Test status
Simulation time 3914590618 ps
CPU time 33.31 seconds
Started Jun 01 03:26:01 PM PDT 24
Finished Jun 01 03:26:35 PM PDT 24
Peak memory 218624 kb
Host smart-8e6ab33e-c1a5-4954-8a67-b9e1e556dee4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070961921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1070961921
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3523055509
Short name T170
Test name
Test status
Simulation time 820045132 ps
CPU time 4.1 seconds
Started Jun 01 03:26:02 PM PDT 24
Finished Jun 01 03:26:07 PM PDT 24
Peak memory 215084 kb
Host smart-93d94ef9-ecae-4fc8-8e1f-dfa0de3d9cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523055509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3523055509
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1407262516
Short name T210
Test name
Test status
Simulation time 126866906 ps
CPU time 1.91 seconds
Started Jun 01 03:26:10 PM PDT 24
Finished Jun 01 03:26:12 PM PDT 24
Peak memory 213840 kb
Host smart-943a99e8-0fec-4622-bd5d-664b64825112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407262516 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1407262516
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1091625904
Short name T485
Test name
Test status
Simulation time 45676013 ps
CPU time 0.84 seconds
Started Jun 01 03:26:11 PM PDT 24
Finished Jun 01 03:26:12 PM PDT 24
Peak memory 205320 kb
Host smart-7793677a-7823-4483-a809-32feb7c18b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091625904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1091625904
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3742529013
Short name T527
Test name
Test status
Simulation time 21935062 ps
CPU time 1.36 seconds
Started Jun 01 03:26:10 PM PDT 24
Finished Jun 01 03:26:12 PM PDT 24
Peak memory 205588 kb
Host smart-a3f93c92-c35f-4dff-84c5-9cf5cd5e2019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742529013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3742529013
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3684863534
Short name T556
Test name
Test status
Simulation time 37490559 ps
CPU time 1.99 seconds
Started Jun 01 03:26:12 PM PDT 24
Finished Jun 01 03:26:15 PM PDT 24
Peak memory 213900 kb
Host smart-08579cd8-ced4-4712-8990-1ffe46b97ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684863534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3684863534
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4018329507
Short name T472
Test name
Test status
Simulation time 28182786 ps
CPU time 1.15 seconds
Started Jun 01 03:26:08 PM PDT 24
Finished Jun 01 03:26:09 PM PDT 24
Peak memory 205612 kb
Host smart-51e5193f-32fe-4198-a998-93a1a94717f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018329507 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4018329507
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3135210131
Short name T492
Test name
Test status
Simulation time 97823152 ps
CPU time 1.26 seconds
Started Jun 01 03:26:09 PM PDT 24
Finished Jun 01 03:26:11 PM PDT 24
Peak memory 205492 kb
Host smart-05c2de7f-5842-4445-94b1-8dd3f84a7029
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135210131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3135210131
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2799822120
Short name T554
Test name
Test status
Simulation time 13134584 ps
CPU time 0.77 seconds
Started Jun 01 03:26:12 PM PDT 24
Finished Jun 01 03:26:13 PM PDT 24
Peak memory 205392 kb
Host smart-d0dd391c-f9f7-420a-bd26-a1edd6e473d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799822120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2799822120
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3672757397
Short name T470
Test name
Test status
Simulation time 301515558 ps
CPU time 1.8 seconds
Started Jun 01 03:26:12 PM PDT 24
Finished Jun 01 03:26:14 PM PDT 24
Peak memory 205732 kb
Host smart-237d5cc3-0376-4ed0-99ef-751b1f109553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672757397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3672757397
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.673416713
Short name T530
Test name
Test status
Simulation time 526841018 ps
CPU time 3.98 seconds
Started Jun 01 03:26:10 PM PDT 24
Finished Jun 01 03:26:15 PM PDT 24
Peak memory 214052 kb
Host smart-63e8bb93-a111-4ec9-8694-7f9653e0e533
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673416713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.673416713
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1583646498
Short name T476
Test name
Test status
Simulation time 691286744 ps
CPU time 9.54 seconds
Started Jun 01 03:26:13 PM PDT 24
Finished Jun 01 03:26:23 PM PDT 24
Peak memory 213996 kb
Host smart-010296d8-4117-40cd-8d8b-7c34ea42b69f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583646498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1583646498
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.489955519
Short name T557
Test name
Test status
Simulation time 201693357 ps
CPU time 1.99 seconds
Started Jun 01 03:26:11 PM PDT 24
Finished Jun 01 03:26:13 PM PDT 24
Peak memory 213864 kb
Host smart-4600ed8f-d9ca-4327-9ab9-f96d5492ad11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489955519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.489955519
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1845248225
Short name T134
Test name
Test status
Simulation time 28677505 ps
CPU time 2.1 seconds
Started Jun 01 03:26:22 PM PDT 24
Finished Jun 01 03:26:25 PM PDT 24
Peak memory 213868 kb
Host smart-f9514171-5fa0-4f51-86c3-7453b44d180b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845248225 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1845248225
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2438722978
Short name T148
Test name
Test status
Simulation time 16585359 ps
CPU time 1.1 seconds
Started Jun 01 03:26:22 PM PDT 24
Finished Jun 01 03:26:24 PM PDT 24
Peak memory 205668 kb
Host smart-4f19080b-4d76-436f-b4bd-f87939c14ea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438722978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2438722978
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3423878511
Short name T546
Test name
Test status
Simulation time 195780125 ps
CPU time 0.88 seconds
Started Jun 01 03:26:20 PM PDT 24
Finished Jun 01 03:26:21 PM PDT 24
Peak memory 205396 kb
Host smart-fee599e7-ca3b-4a33-9b47-dd7d2587a268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423878511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3423878511
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3353177107
Short name T521
Test name
Test status
Simulation time 296729882 ps
CPU time 4.77 seconds
Started Jun 01 03:26:10 PM PDT 24
Finished Jun 01 03:26:15 PM PDT 24
Peak memory 213956 kb
Host smart-459db362-5cb8-4ef3-b399-713c582dbed5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353177107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3353177107
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3135162896
Short name T124
Test name
Test status
Simulation time 370940302 ps
CPU time 4.73 seconds
Started Jun 01 03:26:11 PM PDT 24
Finished Jun 01 03:26:16 PM PDT 24
Peak memory 213956 kb
Host smart-4dcecf2f-c95a-4688-9c21-578eb41f8389
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135162896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3135162896
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1130725773
Short name T189
Test name
Test status
Simulation time 228381987 ps
CPU time 4.84 seconds
Started Jun 01 03:26:12 PM PDT 24
Finished Jun 01 03:26:18 PM PDT 24
Peak memory 213800 kb
Host smart-973254e1-8325-4059-94ca-2c439bcacade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130725773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1130725773
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2956335445
Short name T115
Test name
Test status
Simulation time 48598173 ps
CPU time 1.06 seconds
Started Jun 01 03:26:17 PM PDT 24
Finished Jun 01 03:26:19 PM PDT 24
Peak memory 205540 kb
Host smart-91d15ef0-0e02-4aef-8723-77023b86f075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956335445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2956335445
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3585943268
Short name T153
Test name
Test status
Simulation time 22222282 ps
CPU time 0.86 seconds
Started Jun 01 03:26:20 PM PDT 24
Finished Jun 01 03:26:21 PM PDT 24
Peak memory 205352 kb
Host smart-e3fb512e-f62c-4535-bae9-298bee7561d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585943268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3585943268
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3189553106
Short name T539
Test name
Test status
Simulation time 267141586 ps
CPU time 2.13 seconds
Started Jun 01 03:26:17 PM PDT 24
Finished Jun 01 03:26:19 PM PDT 24
Peak memory 205628 kb
Host smart-445c650f-86bb-4246-ba10-ab8324e58cbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189553106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3189553106
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4045860932
Short name T560
Test name
Test status
Simulation time 780503452 ps
CPU time 5.48 seconds
Started Jun 01 03:26:17 PM PDT 24
Finished Jun 01 03:26:23 PM PDT 24
Peak memory 214040 kb
Host smart-e169de24-a60c-488b-9a7e-24cfc7be2dfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045860932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4045860932
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.265610580
Short name T172
Test name
Test status
Simulation time 319070054 ps
CPU time 3.23 seconds
Started Jun 01 03:26:19 PM PDT 24
Finished Jun 01 03:26:22 PM PDT 24
Peak memory 217044 kb
Host smart-9cf0f2c3-5e85-4bbe-a318-cd79b21b3547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265610580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.265610580
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2591372112
Short name T151
Test name
Test status
Simulation time 67325908 ps
CPU time 1.41 seconds
Started Jun 01 03:26:26 PM PDT 24
Finished Jun 01 03:26:28 PM PDT 24
Peak memory 216900 kb
Host smart-2e88fd4d-8198-421c-812c-70cc895bab75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591372112 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2591372112
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3963491716
Short name T561
Test name
Test status
Simulation time 26274543 ps
CPU time 1.21 seconds
Started Jun 01 03:26:18 PM PDT 24
Finished Jun 01 03:26:20 PM PDT 24
Peak memory 205584 kb
Host smart-f318ab3e-6d36-48e7-9d7c-02f20f0df4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963491716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3963491716
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.582021521
Short name T541
Test name
Test status
Simulation time 26865605 ps
CPU time 0.78 seconds
Started Jun 01 03:26:19 PM PDT 24
Finished Jun 01 03:26:21 PM PDT 24
Peak memory 205356 kb
Host smart-bd86e0db-65cb-47ce-8217-0e021fbcbd7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582021521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.582021521
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2774490067
Short name T500
Test name
Test status
Simulation time 595291316 ps
CPU time 3.53 seconds
Started Jun 01 03:26:17 PM PDT 24
Finished Jun 01 03:26:21 PM PDT 24
Peak memory 214088 kb
Host smart-a8ce185b-a53a-436a-ba20-0697791b5cc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774490067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2774490067
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3707485754
Short name T480
Test name
Test status
Simulation time 284695463 ps
CPU time 4.63 seconds
Started Jun 01 03:26:20 PM PDT 24
Finished Jun 01 03:26:25 PM PDT 24
Peak memory 214136 kb
Host smart-6f9dff3a-05a2-4429-b5ff-b6594663a26f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707485754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3707485754
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2416546970
Short name T531
Test name
Test status
Simulation time 353487410 ps
CPU time 2.76 seconds
Started Jun 01 03:26:19 PM PDT 24
Finished Jun 01 03:26:22 PM PDT 24
Peak memory 213940 kb
Host smart-1617bd43-d9a0-4420-ae3f-d759bcc07c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416546970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2416546970
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3798176518
Short name T559
Test name
Test status
Simulation time 38897273 ps
CPU time 1.37 seconds
Started Jun 01 03:26:27 PM PDT 24
Finished Jun 01 03:26:29 PM PDT 24
Peak memory 213836 kb
Host smart-3e86cc7d-6deb-419e-8c3b-41968bcbec63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798176518 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3798176518
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2477016726
Short name T139
Test name
Test status
Simulation time 66686658 ps
CPU time 1 seconds
Started Jun 01 03:26:25 PM PDT 24
Finished Jun 01 03:26:26 PM PDT 24
Peak memory 205456 kb
Host smart-e0cfaeb7-ef18-4238-a577-e34eea44610d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477016726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2477016726
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2610459179
Short name T468
Test name
Test status
Simulation time 54906604 ps
CPU time 0.77 seconds
Started Jun 01 03:26:25 PM PDT 24
Finished Jun 01 03:26:26 PM PDT 24
Peak memory 205388 kb
Host smart-6deaf790-4913-4eaf-9acb-efbf2fc6516d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610459179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2610459179
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2594538466
Short name T519
Test name
Test status
Simulation time 49954961 ps
CPU time 1.75 seconds
Started Jun 01 03:26:26 PM PDT 24
Finished Jun 01 03:26:28 PM PDT 24
Peak memory 205616 kb
Host smart-40de7d51-45bf-4526-9467-0ffa6e913326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594538466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2594538466
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2710848148
Short name T126
Test name
Test status
Simulation time 208327807 ps
CPU time 3.97 seconds
Started Jun 01 03:26:23 PM PDT 24
Finished Jun 01 03:26:27 PM PDT 24
Peak memory 218832 kb
Host smart-e4556ec3-69f2-4de7-9f76-6904f921b377
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710848148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2710848148
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2604072576
Short name T545
Test name
Test status
Simulation time 64479590 ps
CPU time 2.17 seconds
Started Jun 01 03:26:26 PM PDT 24
Finished Jun 01 03:26:28 PM PDT 24
Peak memory 213812 kb
Host smart-4fd77250-a841-4134-a6d7-927fc0ffd02d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604072576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2604072576
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.9161604
Short name T494
Test name
Test status
Simulation time 290655301 ps
CPU time 4.57 seconds
Started Jun 01 03:26:27 PM PDT 24
Finished Jun 01 03:26:33 PM PDT 24
Peak memory 213716 kb
Host smart-5ca2fe8f-1905-492a-8c7a-e0e3ff722154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9161604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.9161604
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1942605498
Short name T131
Test name
Test status
Simulation time 69229987 ps
CPU time 1.65 seconds
Started Jun 01 03:26:27 PM PDT 24
Finished Jun 01 03:26:29 PM PDT 24
Peak memory 217680 kb
Host smart-11ce50af-de56-49dd-b049-8a6a73159362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942605498 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1942605498
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4039084007
Short name T542
Test name
Test status
Simulation time 16356813 ps
CPU time 0.91 seconds
Started Jun 01 03:26:26 PM PDT 24
Finished Jun 01 03:26:27 PM PDT 24
Peak memory 205196 kb
Host smart-beff90a7-74b1-4962-82b1-9cc2ef816038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039084007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4039084007
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2339620779
Short name T532
Test name
Test status
Simulation time 471399535 ps
CPU time 1.61 seconds
Started Jun 01 03:26:28 PM PDT 24
Finished Jun 01 03:26:30 PM PDT 24
Peak memory 205624 kb
Host smart-37646204-3bcf-40be-b419-261744d56653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339620779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2339620779
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1724381177
Short name T128
Test name
Test status
Simulation time 241918488 ps
CPU time 2.69 seconds
Started Jun 01 03:26:29 PM PDT 24
Finished Jun 01 03:26:32 PM PDT 24
Peak memory 222240 kb
Host smart-ca4a4e85-fa1d-48b0-8c99-b12745473741
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724381177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1724381177
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3800205673
Short name T543
Test name
Test status
Simulation time 256255008 ps
CPU time 6.24 seconds
Started Jun 01 03:26:28 PM PDT 24
Finished Jun 01 03:26:35 PM PDT 24
Peak memory 214004 kb
Host smart-32175dc2-7831-45b5-826b-c84162b3f352
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800205673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3800205673
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1091009302
Short name T499
Test name
Test status
Simulation time 288061826 ps
CPU time 3.29 seconds
Started Jun 01 03:26:26 PM PDT 24
Finished Jun 01 03:26:30 PM PDT 24
Peak memory 214148 kb
Host smart-4fbe70e8-1b0e-4f2f-bd1d-01e1819e7e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091009302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1091009302
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2588614830
Short name T490
Test name
Test status
Simulation time 34162828 ps
CPU time 1.5 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:39 PM PDT 24
Peak memory 213916 kb
Host smart-9fb6de17-dbee-4290-beae-8092d1d27bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588614830 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2588614830
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3091015594
Short name T150
Test name
Test status
Simulation time 70290818 ps
CPU time 1.32 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205720 kb
Host smart-383d229a-4b41-4535-9858-72b6413705a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091015594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3091015594
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2665450589
Short name T564
Test name
Test status
Simulation time 14121367 ps
CPU time 0.91 seconds
Started Jun 01 03:26:34 PM PDT 24
Finished Jun 01 03:26:36 PM PDT 24
Peak memory 205476 kb
Host smart-34c759c0-67d4-4943-89bb-af4a82385b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665450589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2665450589
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3644885047
Short name T496
Test name
Test status
Simulation time 84769151 ps
CPU time 1.43 seconds
Started Jun 01 03:26:34 PM PDT 24
Finished Jun 01 03:26:36 PM PDT 24
Peak memory 205700 kb
Host smart-6b82549e-24c9-4fb0-85b2-25ab774951af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644885047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3644885047
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.174459741
Short name T200
Test name
Test status
Simulation time 1215984674 ps
CPU time 2.24 seconds
Started Jun 01 03:26:24 PM PDT 24
Finished Jun 01 03:26:26 PM PDT 24
Peak memory 214072 kb
Host smart-747a18f9-7322-4c7f-ad89-d56db3d2d93d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174459741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.174459741
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1934840046
Short name T177
Test name
Test status
Simulation time 142364499 ps
CPU time 2.7 seconds
Started Jun 01 03:26:27 PM PDT 24
Finished Jun 01 03:26:30 PM PDT 24
Peak memory 213932 kb
Host smart-9132ee9d-e993-4ded-bbe1-30c402db0227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934840046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1934840046
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1926284281
Short name T186
Test name
Test status
Simulation time 101239513 ps
CPU time 3.54 seconds
Started Jun 01 03:26:28 PM PDT 24
Finished Jun 01 03:26:32 PM PDT 24
Peak memory 208896 kb
Host smart-1daef7c0-00df-45f2-93e5-d8cb8d73bb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926284281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1926284281
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.608187323
Short name T195
Test name
Test status
Simulation time 1247490574 ps
CPU time 9.04 seconds
Started Jun 01 03:25:21 PM PDT 24
Finished Jun 01 03:25:31 PM PDT 24
Peak memory 205596 kb
Host smart-e5cd2294-c7c1-4743-b3c7-2f33fd8ded96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608187323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.608187323
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3206880128
Short name T407
Test name
Test status
Simulation time 429264649 ps
CPU time 9.04 seconds
Started Jun 01 03:25:24 PM PDT 24
Finished Jun 01 03:25:33 PM PDT 24
Peak memory 205652 kb
Host smart-c27c4200-b551-4b48-ac11-ce3cd655e9a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206880128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
206880128
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.641822979
Short name T529
Test name
Test status
Simulation time 89627885 ps
CPU time 1.13 seconds
Started Jun 01 03:25:24 PM PDT 24
Finished Jun 01 03:25:26 PM PDT 24
Peak memory 205592 kb
Host smart-2eabcee5-a752-4a20-b0cd-40837aaac7df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641822979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.641822979
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1751308214
Short name T208
Test name
Test status
Simulation time 96697313 ps
CPU time 1.46 seconds
Started Jun 01 03:25:25 PM PDT 24
Finished Jun 01 03:25:27 PM PDT 24
Peak memory 213780 kb
Host smart-607c3e69-296e-4924-83f7-e837a17f7686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751308214 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1751308214
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1771002005
Short name T510
Test name
Test status
Simulation time 15569390 ps
CPU time 0.7 seconds
Started Jun 01 03:25:13 PM PDT 24
Finished Jun 01 03:25:14 PM PDT 24
Peak memory 205296 kb
Host smart-55467240-8fd0-4eaf-866a-47f9b222e68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771002005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1771002005
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4106015924
Short name T156
Test name
Test status
Simulation time 50476841 ps
CPU time 2.26 seconds
Started Jun 01 03:25:23 PM PDT 24
Finished Jun 01 03:25:25 PM PDT 24
Peak memory 205632 kb
Host smart-74d7e203-ccf9-4073-bde2-fb22ba88356f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106015924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4106015924
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2201142250
Short name T118
Test name
Test status
Simulation time 722932980 ps
CPU time 6.28 seconds
Started Jun 01 03:25:11 PM PDT 24
Finished Jun 01 03:25:18 PM PDT 24
Peak memory 214048 kb
Host smart-58ca08f4-4a9a-4861-8dd1-831547ab1c4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201142250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2201142250
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3964003172
Short name T523
Test name
Test status
Simulation time 158688688 ps
CPU time 1.93 seconds
Started Jun 01 03:25:13 PM PDT 24
Finished Jun 01 03:25:16 PM PDT 24
Peak memory 213912 kb
Host smart-f7f26dde-5c6b-4680-8631-657ef6c980cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964003172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3964003172
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.435631806
Short name T504
Test name
Test status
Simulation time 19181927 ps
CPU time 0.88 seconds
Started Jun 01 03:26:34 PM PDT 24
Finished Jun 01 03:26:36 PM PDT 24
Peak memory 205388 kb
Host smart-121bdd27-7dc2-4022-a693-c52fcdbc99a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435631806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.435631806
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.406140964
Short name T137
Test name
Test status
Simulation time 19049170 ps
CPU time 0.81 seconds
Started Jun 01 03:26:38 PM PDT 24
Finished Jun 01 03:26:39 PM PDT 24
Peak memory 205376 kb
Host smart-431d02ac-7cf3-41d0-8192-5781f166897e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406140964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.406140964
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1931885783
Short name T483
Test name
Test status
Simulation time 35883435 ps
CPU time 0.87 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205308 kb
Host smart-ee8ea366-85d6-4be2-b5a4-4a7bfc264918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931885783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1931885783
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2233069806
Short name T473
Test name
Test status
Simulation time 37695426 ps
CPU time 0.73 seconds
Started Jun 01 03:26:33 PM PDT 24
Finished Jun 01 03:26:34 PM PDT 24
Peak memory 205376 kb
Host smart-d7635210-eca8-43df-9c9c-0e8b81fe68ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233069806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2233069806
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2471805817
Short name T154
Test name
Test status
Simulation time 10488910 ps
CPU time 0.84 seconds
Started Jun 01 03:26:36 PM PDT 24
Finished Jun 01 03:26:37 PM PDT 24
Peak memory 205408 kb
Host smart-3e928257-8d7c-4206-963c-373f1d8accbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471805817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2471805817
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.75025237
Short name T507
Test name
Test status
Simulation time 66862511 ps
CPU time 0.81 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205256 kb
Host smart-da2c7b9e-ddb8-4ca9-b39b-bb75473f3f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75025237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.75025237
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.710069112
Short name T477
Test name
Test status
Simulation time 18988411 ps
CPU time 0.76 seconds
Started Jun 01 03:26:36 PM PDT 24
Finished Jun 01 03:26:37 PM PDT 24
Peak memory 205372 kb
Host smart-8e0b1a91-533d-4188-8c09-feab0d9bc6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710069112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.710069112
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.331378040
Short name T513
Test name
Test status
Simulation time 33090693 ps
CPU time 0.72 seconds
Started Jun 01 03:26:34 PM PDT 24
Finished Jun 01 03:26:35 PM PDT 24
Peak memory 205376 kb
Host smart-9eebcb80-3183-4735-a856-a2e8aa3c6e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331378040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.331378040
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.712675912
Short name T506
Test name
Test status
Simulation time 29144809 ps
CPU time 0.81 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205296 kb
Host smart-faea96f5-5cb3-4bfe-bd2d-2f2141f8c4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712675912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.712675912
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3138157125
Short name T475
Test name
Test status
Simulation time 36609458 ps
CPU time 0.85 seconds
Started Jun 01 03:26:36 PM PDT 24
Finished Jun 01 03:26:37 PM PDT 24
Peak memory 205364 kb
Host smart-0b0596d7-e6d8-4772-a482-11d00979a769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138157125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3138157125
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4122223160
Short name T487
Test name
Test status
Simulation time 140630628 ps
CPU time 4.17 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:25:36 PM PDT 24
Peak memory 205476 kb
Host smart-6c146da1-8df8-4a1b-a0c5-3c188e39a867
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122223160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
122223160
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2891118153
Short name T482
Test name
Test status
Simulation time 454171491 ps
CPU time 13.45 seconds
Started Jun 01 03:25:33 PM PDT 24
Finished Jun 01 03:25:47 PM PDT 24
Peak memory 205592 kb
Host smart-71bb4f0a-a381-40fb-90ab-1170e1c59608
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891118153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
891118153
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3501491633
Short name T160
Test name
Test status
Simulation time 43345930 ps
CPU time 1.01 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:25:33 PM PDT 24
Peak memory 205416 kb
Host smart-284a52d2-c3fa-442d-925d-d44d9fd2d3d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501491633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
501491633
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4028833250
Short name T201
Test name
Test status
Simulation time 18744920 ps
CPU time 1.02 seconds
Started Jun 01 03:25:31 PM PDT 24
Finished Jun 01 03:25:32 PM PDT 24
Peak memory 205484 kb
Host smart-f640da5c-8a80-40d3-a29b-9625909def89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028833250 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4028833250
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.698640991
Short name T515
Test name
Test status
Simulation time 21032158 ps
CPU time 1.13 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:25:34 PM PDT 24
Peak memory 205720 kb
Host smart-dfafcab3-8825-4a60-883a-13fc0edece26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698640991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.698640991
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1882343435
Short name T551
Test name
Test status
Simulation time 9957111 ps
CPU time 0.8 seconds
Started Jun 01 03:25:31 PM PDT 24
Finished Jun 01 03:25:33 PM PDT 24
Peak memory 205264 kb
Host smart-db2a2598-f42f-4809-9cc7-b26664a96e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882343435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1882343435
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1700589337
Short name T191
Test name
Test status
Simulation time 706916021 ps
CPU time 2.8 seconds
Started Jun 01 03:25:26 PM PDT 24
Finished Jun 01 03:25:29 PM PDT 24
Peak memory 213976 kb
Host smart-4cabced9-50f5-4aa9-994e-12e9d57aa535
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700589337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1700589337
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2436100482
Short name T117
Test name
Test status
Simulation time 379797629 ps
CPU time 5.74 seconds
Started Jun 01 03:25:23 PM PDT 24
Finished Jun 01 03:25:29 PM PDT 24
Peak memory 214048 kb
Host smart-94869b49-8fbf-436b-b81d-7a33a95f180a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436100482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2436100482
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2383196606
Short name T171
Test name
Test status
Simulation time 33231176 ps
CPU time 2.45 seconds
Started Jun 01 03:25:25 PM PDT 24
Finished Jun 01 03:25:28 PM PDT 24
Peak memory 213800 kb
Host smart-a2f80ae3-2f6f-46e3-910f-a2f588cf9809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383196606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2383196606
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1795847333
Short name T464
Test name
Test status
Simulation time 34367858 ps
CPU time 0.7 seconds
Started Jun 01 03:26:37 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205340 kb
Host smart-11c74565-b97f-4c68-93b3-348ea566486d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795847333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1795847333
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.876364355
Short name T478
Test name
Test status
Simulation time 8298398 ps
CPU time 0.81 seconds
Started Jun 01 03:26:38 PM PDT 24
Finished Jun 01 03:26:39 PM PDT 24
Peak memory 205376 kb
Host smart-9fe9d6c5-92c7-4b30-bf9e-4e4b10876f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876364355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.876364355
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1447711107
Short name T406
Test name
Test status
Simulation time 11899268 ps
CPU time 0.69 seconds
Started Jun 01 03:26:36 PM PDT 24
Finished Jun 01 03:26:38 PM PDT 24
Peak memory 205384 kb
Host smart-83628594-510e-47b9-b3cc-e38d2164c01d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447711107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1447711107
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1161278812
Short name T524
Test name
Test status
Simulation time 10995568 ps
CPU time 0.7 seconds
Started Jun 01 03:26:42 PM PDT 24
Finished Jun 01 03:26:43 PM PDT 24
Peak memory 205316 kb
Host smart-9a8ee001-8474-47ce-96e9-b4aced327d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161278812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1161278812
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1941413571
Short name T155
Test name
Test status
Simulation time 145571178 ps
CPU time 0.77 seconds
Started Jun 01 03:26:50 PM PDT 24
Finished Jun 01 03:26:51 PM PDT 24
Peak memory 205352 kb
Host smart-062639a0-4cef-43eb-bf53-0dc57bb220d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941413571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1941413571
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1433422323
Short name T517
Test name
Test status
Simulation time 10190056 ps
CPU time 0.73 seconds
Started Jun 01 03:26:42 PM PDT 24
Finished Jun 01 03:26:43 PM PDT 24
Peak memory 205384 kb
Host smart-c0a34885-72e2-44cd-9087-98d83dd22208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433422323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1433422323
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2339931312
Short name T509
Test name
Test status
Simulation time 27421887 ps
CPU time 0.91 seconds
Started Jun 01 03:26:45 PM PDT 24
Finished Jun 01 03:26:46 PM PDT 24
Peak memory 205400 kb
Host smart-d329a347-d6b3-4997-9896-dcc80a51c46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339931312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2339931312
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3733081681
Short name T466
Test name
Test status
Simulation time 10856244 ps
CPU time 0.73 seconds
Started Jun 01 03:26:43 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205328 kb
Host smart-029c5487-de48-426c-9740-59006d90cd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733081681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3733081681
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2619905743
Short name T489
Test name
Test status
Simulation time 100331487 ps
CPU time 0.88 seconds
Started Jun 01 03:26:43 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205396 kb
Host smart-cea1c170-1215-45e0-be29-fec649851401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619905743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2619905743
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.115051332
Short name T152
Test name
Test status
Simulation time 14675976 ps
CPU time 0.93 seconds
Started Jun 01 03:26:43 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205336 kb
Host smart-27eb1c48-3b46-4833-959a-31f0b95ec579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115051332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.115051332
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2811591657
Short name T552
Test name
Test status
Simulation time 121604506 ps
CPU time 8.37 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:25:40 PM PDT 24
Peak memory 205472 kb
Host smart-f2cd3862-40d2-417e-b3cb-3af3fdccee8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811591657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
811591657
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3136467003
Short name T535
Test name
Test status
Simulation time 1193175988 ps
CPU time 27.12 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:26:00 PM PDT 24
Peak memory 205520 kb
Host smart-86c40860-703f-446f-8317-fa6d5e404475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136467003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
136467003
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2432575285
Short name T547
Test name
Test status
Simulation time 14656535 ps
CPU time 0.9 seconds
Started Jun 01 03:25:31 PM PDT 24
Finished Jun 01 03:25:32 PM PDT 24
Peak memory 205368 kb
Host smart-bb57e1ce-1723-40c4-9a3b-366d1ae050da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432575285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
432575285
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3413561704
Short name T549
Test name
Test status
Simulation time 96819667 ps
CPU time 1.22 seconds
Started Jun 01 03:25:27 PM PDT 24
Finished Jun 01 03:25:28 PM PDT 24
Peak memory 213896 kb
Host smart-5c3d17c2-5ef5-44d1-950e-fd54514d010e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413561704 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3413561704
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2701268035
Short name T538
Test name
Test status
Simulation time 25913506 ps
CPU time 1.17 seconds
Started Jun 01 03:25:29 PM PDT 24
Finished Jun 01 03:25:31 PM PDT 24
Peak memory 205516 kb
Host smart-7126b2cf-d26d-49d3-bdec-7eb568db27b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701268035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2701268035
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1394000585
Short name T465
Test name
Test status
Simulation time 21096603 ps
CPU time 0.83 seconds
Started Jun 01 03:25:31 PM PDT 24
Finished Jun 01 03:25:32 PM PDT 24
Peak memory 205304 kb
Host smart-5455f590-6f6c-48ff-a5fb-e1f0b8b43f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394000585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1394000585
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2804027515
Short name T190
Test name
Test status
Simulation time 94754249 ps
CPU time 3.07 seconds
Started Jun 01 03:25:31 PM PDT 24
Finished Jun 01 03:25:35 PM PDT 24
Peak memory 214080 kb
Host smart-4b1dfd6a-74cc-437c-a482-391ffe36b359
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804027515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2804027515
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2400602872
Short name T198
Test name
Test status
Simulation time 658405086 ps
CPU time 3.86 seconds
Started Jun 01 03:25:32 PM PDT 24
Finished Jun 01 03:25:37 PM PDT 24
Peak memory 213864 kb
Host smart-6cc6ccb6-ee99-436b-a7ed-9b19fa930f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400602872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2400602872
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.870667479
Short name T467
Test name
Test status
Simulation time 35012824 ps
CPU time 0.73 seconds
Started Jun 01 03:26:42 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205396 kb
Host smart-6db288e2-0fdf-487f-bbb4-a44515364a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870667479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.870667479
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3239127731
Short name T553
Test name
Test status
Simulation time 11295691 ps
CPU time 0.84 seconds
Started Jun 01 03:26:44 PM PDT 24
Finished Jun 01 03:26:45 PM PDT 24
Peak memory 205340 kb
Host smart-cd921a18-7b38-4b31-9786-1968613877b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239127731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3239127731
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4280862390
Short name T202
Test name
Test status
Simulation time 9706887 ps
CPU time 0.69 seconds
Started Jun 01 03:26:42 PM PDT 24
Finished Jun 01 03:26:43 PM PDT 24
Peak memory 205304 kb
Host smart-0b9885bf-1cee-4e8f-bb65-6a4b6b9f4e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280862390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4280862390
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2075205914
Short name T212
Test name
Test status
Simulation time 33767344 ps
CPU time 0.73 seconds
Started Jun 01 03:26:42 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205384 kb
Host smart-2eec893c-6049-47b1-8dc1-649921de79a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075205914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2075205914
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1765916736
Short name T503
Test name
Test status
Simulation time 37421656 ps
CPU time 0.72 seconds
Started Jun 01 03:26:43 PM PDT 24
Finished Jun 01 03:26:44 PM PDT 24
Peak memory 205352 kb
Host smart-7bb312ee-c378-4098-9102-ee59507043ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765916736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1765916736
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2232549780
Short name T488
Test name
Test status
Simulation time 35286005 ps
CPU time 0.7 seconds
Started Jun 01 03:26:50 PM PDT 24
Finished Jun 01 03:26:51 PM PDT 24
Peak memory 205392 kb
Host smart-2f70218b-527b-4ec9-b495-fab74f99c5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232549780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2232549780
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2446424122
Short name T555
Test name
Test status
Simulation time 10303646 ps
CPU time 0.74 seconds
Started Jun 01 03:26:49 PM PDT 24
Finished Jun 01 03:26:50 PM PDT 24
Peak memory 205396 kb
Host smart-0c82e330-9533-4376-9c1c-5fcda75494e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446424122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2446424122
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.80087526
Short name T520
Test name
Test status
Simulation time 11837395 ps
CPU time 0.76 seconds
Started Jun 01 03:26:50 PM PDT 24
Finished Jun 01 03:26:51 PM PDT 24
Peak memory 205356 kb
Host smart-9932ec4a-2f00-41b0-8727-9d6c4ca7531a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80087526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.80087526
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1901350158
Short name T140
Test name
Test status
Simulation time 15537906 ps
CPU time 0.83 seconds
Started Jun 01 03:26:50 PM PDT 24
Finished Jun 01 03:26:51 PM PDT 24
Peak memory 205340 kb
Host smart-de182059-c3af-4ac8-accb-3c8d1141e2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901350158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1901350158
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3121603644
Short name T491
Test name
Test status
Simulation time 47943921 ps
CPU time 0.74 seconds
Started Jun 01 03:26:53 PM PDT 24
Finished Jun 01 03:26:54 PM PDT 24
Peak memory 205352 kb
Host smart-10cd2ce0-80d9-440e-a955-73ddd0e6e21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121603644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3121603644
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1488967865
Short name T514
Test name
Test status
Simulation time 183953429 ps
CPU time 1.1 seconds
Started Jun 01 03:25:40 PM PDT 24
Finished Jun 01 03:25:42 PM PDT 24
Peak memory 205524 kb
Host smart-8d87ae94-3d59-4f4d-9768-9832267360b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488967865 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1488967865
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.352196634
Short name T533
Test name
Test status
Simulation time 53638965 ps
CPU time 1.26 seconds
Started Jun 01 03:25:41 PM PDT 24
Finished Jun 01 03:25:43 PM PDT 24
Peak memory 205612 kb
Host smart-5e83f38c-82df-4c21-829d-8d8e398c1591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352196634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.352196634
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3016512759
Short name T471
Test name
Test status
Simulation time 12151160 ps
CPU time 0.88 seconds
Started Jun 01 03:25:41 PM PDT 24
Finished Jun 01 03:25:43 PM PDT 24
Peak memory 205400 kb
Host smart-483b3e8f-520b-4611-bc45-efa404cabb9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016512759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3016512759
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2137229871
Short name T495
Test name
Test status
Simulation time 20286541 ps
CPU time 1.43 seconds
Started Jun 01 03:25:39 PM PDT 24
Finished Jun 01 03:25:41 PM PDT 24
Peak memory 205680 kb
Host smart-c67b9b58-a014-483c-99c8-906c6bce013b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137229871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2137229871
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3673378308
Short name T188
Test name
Test status
Simulation time 838519568 ps
CPU time 6.85 seconds
Started Jun 01 03:25:29 PM PDT 24
Finished Jun 01 03:25:36 PM PDT 24
Peak memory 213992 kb
Host smart-2013377c-fa94-42d3-9a3b-565d5eb794b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673378308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3673378308
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2375670159
Short name T125
Test name
Test status
Simulation time 246086839 ps
CPU time 11.3 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:50 PM PDT 24
Peak memory 213916 kb
Host smart-cf9f4f10-1e8e-45d6-96b4-85f7fb4e6ecb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375670159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2375670159
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3201610451
Short name T511
Test name
Test status
Simulation time 358878503 ps
CPU time 2.87 seconds
Started Jun 01 03:25:40 PM PDT 24
Finished Jun 01 03:25:44 PM PDT 24
Peak memory 221972 kb
Host smart-8f3dc938-fee5-4aca-ab14-7486f10385bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201610451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3201610451
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1376648626
Short name T132
Test name
Test status
Simulation time 121221865 ps
CPU time 2.11 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:41 PM PDT 24
Peak memory 213880 kb
Host smart-6d8bc823-5074-40fe-8ab1-23f5b5c2a9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376648626 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1376648626
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2212014101
Short name T565
Test name
Test status
Simulation time 10957295 ps
CPU time 0.78 seconds
Started Jun 01 03:25:40 PM PDT 24
Finished Jun 01 03:25:42 PM PDT 24
Peak memory 205280 kb
Host smart-48f28765-b307-43bb-a5b8-f213ff0ce0e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212014101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2212014101
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4154635217
Short name T493
Test name
Test status
Simulation time 42529571 ps
CPU time 1.72 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:40 PM PDT 24
Peak memory 213800 kb
Host smart-e5e6a8f9-d62d-4cc1-b5d1-382a8da05367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154635217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4154635217
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.523221007
Short name T534
Test name
Test status
Simulation time 345996323 ps
CPU time 2.56 seconds
Started Jun 01 03:25:37 PM PDT 24
Finished Jun 01 03:25:40 PM PDT 24
Peak memory 222180 kb
Host smart-2ce32546-e55c-4f66-b573-63605a150bb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523221007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.523221007
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1424276982
Short name T518
Test name
Test status
Simulation time 829049121 ps
CPU time 12.17 seconds
Started Jun 01 03:25:40 PM PDT 24
Finished Jun 01 03:25:53 PM PDT 24
Peak memory 213964 kb
Host smart-9427200f-bef9-463f-8c23-3784db7f4220
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424276982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1424276982
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1179448580
Short name T197
Test name
Test status
Simulation time 505232651 ps
CPU time 3.91 seconds
Started Jun 01 03:25:39 PM PDT 24
Finished Jun 01 03:25:44 PM PDT 24
Peak memory 214060 kb
Host smart-613e510c-18e5-4693-8712-cc27e0251f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179448580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1179448580
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1006214018
Short name T175
Test name
Test status
Simulation time 695492482 ps
CPU time 7.71 seconds
Started Jun 01 03:25:40 PM PDT 24
Finished Jun 01 03:25:49 PM PDT 24
Peak memory 208908 kb
Host smart-8a37a716-c867-498a-9699-e9a30ebd1688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006214018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1006214018
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.92251936
Short name T196
Test name
Test status
Simulation time 22709569 ps
CPU time 1.36 seconds
Started Jun 01 03:25:47 PM PDT 24
Finished Jun 01 03:25:49 PM PDT 24
Peak memory 213840 kb
Host smart-6c1e0892-ec48-43cb-9d01-a9847f1f9945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92251936 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.92251936
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.914333765
Short name T528
Test name
Test status
Simulation time 64537631 ps
CPU time 1.13 seconds
Started Jun 01 03:25:37 PM PDT 24
Finished Jun 01 03:25:39 PM PDT 24
Peak memory 205576 kb
Host smart-5d5d3c51-fb31-426f-b3aa-e944fd2311df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914333765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.914333765
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1065903998
Short name T486
Test name
Test status
Simulation time 39366498 ps
CPU time 0.84 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:40 PM PDT 24
Peak memory 205408 kb
Host smart-39f55918-5ab0-4922-8e5d-062aef02e3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065903998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1065903998
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1433433937
Short name T213
Test name
Test status
Simulation time 532232399 ps
CPU time 2.28 seconds
Started Jun 01 03:25:38 PM PDT 24
Finished Jun 01 03:25:41 PM PDT 24
Peak memory 214064 kb
Host smart-7fa5dc1c-643c-4e34-b5a3-00b5faab738b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433433937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1433433937
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.691896599
Short name T536
Test name
Test status
Simulation time 250929941 ps
CPU time 1.72 seconds
Started Jun 01 03:25:37 PM PDT 24
Finished Jun 01 03:25:39 PM PDT 24
Peak memory 214896 kb
Host smart-df13f787-3047-4cf0-abe7-7e9369cdd7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691896599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.691896599
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2398499596
Short name T563
Test name
Test status
Simulation time 32832287 ps
CPU time 1.69 seconds
Started Jun 01 03:25:55 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 213832 kb
Host smart-62756597-3a47-4fe2-a60d-169c8d87b35a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398499596 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2398499596
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1153366059
Short name T512
Test name
Test status
Simulation time 15504941 ps
CPU time 1.02 seconds
Started Jun 01 03:25:44 PM PDT 24
Finished Jun 01 03:25:46 PM PDT 24
Peak memory 205448 kb
Host smart-7d8ffa46-08c0-4df5-bdc4-d79676d3e68e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153366059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1153366059
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3071362186
Short name T211
Test name
Test status
Simulation time 9754087 ps
CPU time 0.69 seconds
Started Jun 01 03:25:44 PM PDT 24
Finished Jun 01 03:25:46 PM PDT 24
Peak memory 205400 kb
Host smart-33d00140-9921-40fa-b4d7-e4a156a88d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071362186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3071362186
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.66478845
Short name T469
Test name
Test status
Simulation time 139045840 ps
CPU time 2.53 seconds
Started Jun 01 03:25:55 PM PDT 24
Finished Jun 01 03:25:58 PM PDT 24
Peak memory 205676 kb
Host smart-d31ccad0-f42c-406d-b93e-cd4e279c696f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66478845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same
_csr_outstanding.66478845
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.847628192
Short name T548
Test name
Test status
Simulation time 704267857 ps
CPU time 9.67 seconds
Started Jun 01 03:25:46 PM PDT 24
Finished Jun 01 03:25:56 PM PDT 24
Peak memory 214048 kb
Host smart-9741626b-b257-4e74-80cd-b1515010814c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847628192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.847628192
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.615398072
Short name T116
Test name
Test status
Simulation time 1447166134 ps
CPU time 3.57 seconds
Started Jun 01 03:25:44 PM PDT 24
Finished Jun 01 03:25:48 PM PDT 24
Peak memory 213796 kb
Host smart-ace34b00-be04-4e5b-9cb3-40bf57a4766d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615398072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.615398072
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4213700336
Short name T498
Test name
Test status
Simulation time 36407073 ps
CPU time 1.68 seconds
Started Jun 01 03:25:54 PM PDT 24
Finished Jun 01 03:25:56 PM PDT 24
Peak memory 213928 kb
Host smart-22a4feea-3a16-4492-979f-2e6abf0eba8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213700336 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4213700336
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3697140478
Short name T474
Test name
Test status
Simulation time 27665873 ps
CPU time 1.02 seconds
Started Jun 01 03:25:56 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 205324 kb
Host smart-2efa4a80-26c7-483e-b3c1-5a72801371c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697140478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3697140478
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.513697482
Short name T203
Test name
Test status
Simulation time 9569499 ps
CPU time 0.71 seconds
Started Jun 01 03:25:54 PM PDT 24
Finished Jun 01 03:25:55 PM PDT 24
Peak memory 205368 kb
Host smart-203dd60f-5430-4091-9ef6-0fea1d875166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513697482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.513697482
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.894354065
Short name T516
Test name
Test status
Simulation time 205593003 ps
CPU time 1.74 seconds
Started Jun 01 03:25:57 PM PDT 24
Finished Jun 01 03:25:59 PM PDT 24
Peak memory 205608 kb
Host smart-52682c48-84ec-4549-abd2-c5cd62129fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894354065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.894354065
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4202204304
Short name T207
Test name
Test status
Simulation time 349828870 ps
CPU time 2.23 seconds
Started Jun 01 03:25:54 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 214072 kb
Host smart-9d09b767-bc9c-425b-8a91-4699bce62875
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202204304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4202204304
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2098439461
Short name T562
Test name
Test status
Simulation time 878614521 ps
CPU time 4.16 seconds
Started Jun 01 03:25:52 PM PDT 24
Finished Jun 01 03:25:57 PM PDT 24
Peak memory 213888 kb
Host smart-c5311c41-574f-492a-8a04-fdeada0462f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098439461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2098439461
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2857340875
Short name T782
Test name
Test status
Simulation time 27746210 ps
CPU time 0.72 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:02:59 PM PDT 24
Peak memory 205492 kb
Host smart-d4faa161-404a-4421-8558-1255b291339a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857340875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2857340875
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3171967990
Short name T12
Test name
Test status
Simulation time 258336949 ps
CPU time 5.33 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:03 PM PDT 24
Peak memory 214444 kb
Host smart-d4464627-6c24-45c9-b4d8-e320c3094f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171967990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3171967990
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2835139559
Short name T87
Test name
Test status
Simulation time 1181009751 ps
CPU time 12 seconds
Started Jun 01 03:02:56 PM PDT 24
Finished Jun 01 03:03:09 PM PDT 24
Peak memory 214008 kb
Host smart-9b121834-c293-4470-af8a-e335324deca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835139559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2835139559
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1269047315
Short name T68
Test name
Test status
Simulation time 233875095 ps
CPU time 9.29 seconds
Started Jun 01 03:02:59 PM PDT 24
Finished Jun 01 03:03:09 PM PDT 24
Peak memory 211092 kb
Host smart-cabd78cb-0acc-4983-a880-8de815fe4551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269047315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1269047315
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2069801952
Short name T241
Test name
Test status
Simulation time 74647406 ps
CPU time 3.26 seconds
Started Jun 01 03:03:02 PM PDT 24
Finished Jun 01 03:03:06 PM PDT 24
Peak memory 208644 kb
Host smart-fd475479-e996-4c94-a867-4c30f2d89d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069801952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2069801952
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.246746854
Short name T904
Test name
Test status
Simulation time 89300641 ps
CPU time 3.67 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:08 PM PDT 24
Peak memory 207916 kb
Host smart-a08871b4-9488-4f88-b619-57c70afcfd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246746854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.246746854
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3212199716
Short name T45
Test name
Test status
Simulation time 9100173237 ps
CPU time 87.11 seconds
Started Jun 01 03:02:59 PM PDT 24
Finished Jun 01 03:04:26 PM PDT 24
Peak memory 237796 kb
Host smart-cae50ad5-ef18-48ba-b698-6872be81b61a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212199716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3212199716
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2749281954
Short name T317
Test name
Test status
Simulation time 192861056 ps
CPU time 4.84 seconds
Started Jun 01 03:02:55 PM PDT 24
Finished Jun 01 03:03:00 PM PDT 24
Peak memory 208132 kb
Host smart-fa1cdcb2-28f7-4f5f-b32f-7f25282a51f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749281954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2749281954
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1051965954
Short name T594
Test name
Test status
Simulation time 661505500 ps
CPU time 4.93 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:02 PM PDT 24
Peak memory 208404 kb
Host smart-1edd2a53-5648-46c3-8105-cdd4235d0c3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051965954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1051965954
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2449012574
Short name T775
Test name
Test status
Simulation time 339881999 ps
CPU time 2.39 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:00 PM PDT 24
Peak memory 208252 kb
Host smart-55dba15c-10bf-4da4-b666-b78256aca3ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449012574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2449012574
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.243691495
Short name T843
Test name
Test status
Simulation time 295584978 ps
CPU time 3.73 seconds
Started Jun 01 03:03:00 PM PDT 24
Finished Jun 01 03:03:04 PM PDT 24
Peak memory 208124 kb
Host smart-aab6b21f-3464-4315-8a8d-7677dc5269d0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243691495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.243691495
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4208471834
Short name T654
Test name
Test status
Simulation time 980004885 ps
CPU time 5.6 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:03 PM PDT 24
Peak memory 213828 kb
Host smart-e74a2b9a-48ed-47b9-86b3-cb75e9f675bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208471834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4208471834
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2352329738
Short name T3
Test name
Test status
Simulation time 90857705 ps
CPU time 2.57 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:07 PM PDT 24
Peak memory 207848 kb
Host smart-46935bda-20f8-40da-9107-0270eaf031ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352329738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2352329738
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1505576785
Short name T877
Test name
Test status
Simulation time 177275869 ps
CPU time 7.65 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:06 PM PDT 24
Peak memory 219220 kb
Host smart-7e4723da-ed6a-456f-9e1a-b02c45a25bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505576785 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1505576785
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.701229408
Short name T416
Test name
Test status
Simulation time 277116358 ps
CPU time 2.27 seconds
Started Jun 01 03:03:01 PM PDT 24
Finished Jun 01 03:03:03 PM PDT 24
Peak memory 206844 kb
Host smart-926525a9-a9b4-4149-92f8-e3721d095758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701229408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.701229408
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2178510447
Short name T84
Test name
Test status
Simulation time 79549876 ps
CPU time 2.31 seconds
Started Jun 01 03:02:59 PM PDT 24
Finished Jun 01 03:03:01 PM PDT 24
Peak memory 209716 kb
Host smart-f4978ac4-2b19-4a21-8c28-0a682bd7c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178510447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2178510447
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.51367143
Short name T314
Test name
Test status
Simulation time 138465561 ps
CPU time 7.51 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:06 PM PDT 24
Peak memory 215376 kb
Host smart-46a3f438-b6a0-41b1-a56c-4e0619ae0912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51367143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.51367143
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1422574689
Short name T817
Test name
Test status
Simulation time 4815413703 ps
CPU time 49.57 seconds
Started Jun 01 03:03:02 PM PDT 24
Finished Jun 01 03:03:51 PM PDT 24
Peak memory 214328 kb
Host smart-6faf9111-73d1-4835-86bf-dc2ee5b5b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422574689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1422574689
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.366386496
Short name T350
Test name
Test status
Simulation time 365997743 ps
CPU time 4.59 seconds
Started Jun 01 03:03:07 PM PDT 24
Finished Jun 01 03:03:12 PM PDT 24
Peak memory 213968 kb
Host smart-e4b2c88c-f8f3-4af7-9e61-f2fabc4d3a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366386496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.366386496
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_random.689468120
Short name T1063
Test name
Test status
Simulation time 997118408 ps
CPU time 25.12 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:30 PM PDT 24
Peak memory 218736 kb
Host smart-efe7653d-45bd-41e6-a3d0-e5fe690b8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689468120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.689468120
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2207498929
Short name T8
Test name
Test status
Simulation time 1519748279 ps
CPU time 12.08 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:19 PM PDT 24
Peak memory 230636 kb
Host smart-98f3f454-61b1-437f-8205-b6c065835bbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207498929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2207498929
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2212506550
Short name T661
Test name
Test status
Simulation time 84643863 ps
CPU time 2.96 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:02 PM PDT 24
Peak memory 206448 kb
Host smart-1619cdd6-2088-40ca-99ac-bba53d4e1d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212506550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2212506550
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2766989231
Short name T1008
Test name
Test status
Simulation time 38556352 ps
CPU time 1.77 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:06 PM PDT 24
Peak memory 206368 kb
Host smart-7ab27b6e-1911-4587-97dd-9bc89c4d7e9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766989231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2766989231
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3053872748
Short name T574
Test name
Test status
Simulation time 11524825552 ps
CPU time 26.19 seconds
Started Jun 01 03:02:57 PM PDT 24
Finished Jun 01 03:03:24 PM PDT 24
Peak memory 208664 kb
Host smart-2a508143-c212-45d4-8660-ce365010e882
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053872748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3053872748
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3197677309
Short name T311
Test name
Test status
Simulation time 272782864 ps
CPU time 8.09 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 209368 kb
Host smart-a9c362cd-ec93-46ed-8ff1-887137e5fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197677309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3197677309
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2075111969
Short name T846
Test name
Test status
Simulation time 214490070 ps
CPU time 1.68 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:00 PM PDT 24
Peak memory 206496 kb
Host smart-98cb922c-1707-4767-887e-07df57751929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075111969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2075111969
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.373684350
Short name T677
Test name
Test status
Simulation time 491662448 ps
CPU time 10.06 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:15 PM PDT 24
Peak memory 222352 kb
Host smart-58784215-3e9d-405c-8f93-0d90f181ba4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373684350 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.373684350
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3897619380
Short name T968
Test name
Test status
Simulation time 304510322 ps
CPU time 5.08 seconds
Started Jun 01 03:02:58 PM PDT 24
Finished Jun 01 03:03:04 PM PDT 24
Peak memory 208828 kb
Host smart-1a6205f1-1906-4bfe-88e2-adaf68d75322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897619380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3897619380
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1835309305
Short name T944
Test name
Test status
Simulation time 156189795 ps
CPU time 3.59 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:13 PM PDT 24
Peak memory 209980 kb
Host smart-22e901a8-f73c-4443-9738-3a995fb03d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835309305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1835309305
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2696144368
Short name T994
Test name
Test status
Simulation time 21053274 ps
CPU time 0.87 seconds
Started Jun 01 03:03:57 PM PDT 24
Finished Jun 01 03:03:58 PM PDT 24
Peak memory 205484 kb
Host smart-e53c471b-87f1-46da-aea8-edaffa62f165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696144368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2696144368
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3361299970
Short name T886
Test name
Test status
Simulation time 66814254 ps
CPU time 3.46 seconds
Started Jun 01 03:03:53 PM PDT 24
Finished Jun 01 03:03:57 PM PDT 24
Peak memory 209464 kb
Host smart-00a2bf5b-f72b-4c5d-a0f1-f8ea7e746b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361299970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3361299970
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4156727373
Short name T1031
Test name
Test status
Simulation time 82552359 ps
CPU time 2.17 seconds
Started Jun 01 03:03:47 PM PDT 24
Finished Jun 01 03:03:50 PM PDT 24
Peak memory 207256 kb
Host smart-3c623559-fffa-4502-bab0-4d3caea92b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156727373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4156727373
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2277250037
Short name T665
Test name
Test status
Simulation time 157110183 ps
CPU time 2.47 seconds
Started Jun 01 03:04:00 PM PDT 24
Finished Jun 01 03:04:03 PM PDT 24
Peak memory 208364 kb
Host smart-d2809a25-eeef-435c-a93d-c7a2cfdf39cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277250037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2277250037
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_random.4239851330
Short name T664
Test name
Test status
Simulation time 130051610 ps
CPU time 5.83 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:53 PM PDT 24
Peak memory 218188 kb
Host smart-870bf4b6-df22-4061-b94b-363e7b6c5af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239851330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4239851330
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1976302505
Short name T912
Test name
Test status
Simulation time 71429693 ps
CPU time 1.94 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:48 PM PDT 24
Peak memory 206956 kb
Host smart-4ddbaa6c-eaa4-4f5c-92fe-670975c5126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976302505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1976302505
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3661075984
Short name T398
Test name
Test status
Simulation time 115942247 ps
CPU time 1.88 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:48 PM PDT 24
Peak memory 206428 kb
Host smart-4099650f-850c-4a63-b0ca-d8e5228aad2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661075984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3661075984
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.289451987
Short name T269
Test name
Test status
Simulation time 587260598 ps
CPU time 14.72 seconds
Started Jun 01 03:03:47 PM PDT 24
Finished Jun 01 03:04:02 PM PDT 24
Peak memory 208120 kb
Host smart-19ef3db8-e15a-4cc3-b8bc-2facc6f17f88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289451987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.289451987
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3240191219
Short name T260
Test name
Test status
Simulation time 28942957 ps
CPU time 2.06 seconds
Started Jun 01 03:03:45 PM PDT 24
Finished Jun 01 03:03:47 PM PDT 24
Peak memory 207912 kb
Host smart-7d1dec8f-1f34-4578-a08c-71648f171c6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240191219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3240191219
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2998247135
Short name T732
Test name
Test status
Simulation time 1010923545 ps
CPU time 15.26 seconds
Started Jun 01 03:03:55 PM PDT 24
Finished Jun 01 03:04:11 PM PDT 24
Peak memory 208280 kb
Host smart-87015a9d-1743-49d8-8e0d-07e7ff068e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998247135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2998247135
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1339428569
Short name T696
Test name
Test status
Simulation time 909508750 ps
CPU time 9.51 seconds
Started Jun 01 03:03:47 PM PDT 24
Finished Jun 01 03:03:57 PM PDT 24
Peak memory 208284 kb
Host smart-e96a6248-7914-49ed-a741-7a89891138eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339428569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1339428569
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3548164672
Short name T424
Test name
Test status
Simulation time 309428497 ps
CPU time 13.71 seconds
Started Jun 01 03:03:54 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 222520 kb
Host smart-4c1ff0db-e1ea-43f7-8526-a92d43e484f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548164672 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3548164672
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1968598425
Short name T297
Test name
Test status
Simulation time 769029737 ps
CPU time 12.77 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:04:09 PM PDT 24
Peak memory 209116 kb
Host smart-c11910dc-f9c8-472d-890e-c4abc625ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968598425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1968598425
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.226872534
Short name T663
Test name
Test status
Simulation time 95128911 ps
CPU time 2.91 seconds
Started Jun 01 03:03:54 PM PDT 24
Finished Jun 01 03:03:58 PM PDT 24
Peak memory 209556 kb
Host smart-2a7b8236-f5da-4146-b792-b16e07e90e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226872534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.226872534
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.687849539
Short name T720
Test name
Test status
Simulation time 13317393 ps
CPU time 0.73 seconds
Started Jun 01 03:04:07 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 205580 kb
Host smart-032c40bd-290b-4c90-8ff6-d0b4a3d70864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687849539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.687849539
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1081718058
Short name T612
Test name
Test status
Simulation time 479200859 ps
CPU time 13.53 seconds
Started Jun 01 03:03:55 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 209800 kb
Host smart-651281bf-087f-48c7-a7ad-8719c5d03512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081718058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1081718058
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3413982210
Short name T252
Test name
Test status
Simulation time 132868632 ps
CPU time 3.81 seconds
Started Jun 01 03:03:53 PM PDT 24
Finished Jun 01 03:03:58 PM PDT 24
Peak memory 208628 kb
Host smart-d2f2ee16-371b-4790-a829-520a6e77e8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413982210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3413982210
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3502514608
Short name T336
Test name
Test status
Simulation time 269049799 ps
CPU time 3.79 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:04:00 PM PDT 24
Peak memory 213952 kb
Host smart-26c35339-b222-4108-96fb-fa000ad498b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502514608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3502514608
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2779932715
Short name T823
Test name
Test status
Simulation time 188101323 ps
CPU time 7.2 seconds
Started Jun 01 03:04:00 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 208120 kb
Host smart-08b2fdd7-1c49-4c3e-916b-cf84b83e41ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779932715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2779932715
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2898531967
Short name T2
Test name
Test status
Simulation time 267315746 ps
CPU time 1.98 seconds
Started Jun 01 03:03:57 PM PDT 24
Finished Jun 01 03:04:00 PM PDT 24
Peak memory 206656 kb
Host smart-36d5fb28-badc-496f-9cce-3634852e6d32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898531967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2898531967
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.137288692
Short name T224
Test name
Test status
Simulation time 56662014 ps
CPU time 2.77 seconds
Started Jun 01 03:03:54 PM PDT 24
Finished Jun 01 03:03:57 PM PDT 24
Peak memory 207744 kb
Host smart-96c1b2ae-a203-4fa6-ad3a-c089979cba14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137288692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.137288692
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2949042599
Short name T573
Test name
Test status
Simulation time 124731016 ps
CPU time 2.5 seconds
Started Jun 01 03:03:56 PM PDT 24
Finished Jun 01 03:03:58 PM PDT 24
Peak memory 206652 kb
Host smart-7e4ed76e-2407-4a3a-8d46-babd8f3e1153
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949042599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2949042599
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3788721754
Short name T1000
Test name
Test status
Simulation time 57700484 ps
CPU time 1.43 seconds
Started Jun 01 03:04:00 PM PDT 24
Finished Jun 01 03:04:02 PM PDT 24
Peak memory 207580 kb
Host smart-8a116314-718d-425b-88b4-9133dae3438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788721754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3788721754
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4268243545
Short name T772
Test name
Test status
Simulation time 14922538704 ps
CPU time 72.35 seconds
Started Jun 01 03:03:58 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 208416 kb
Host smart-50e7f327-3891-44e0-84db-f76fd614959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268243545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4268243545
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.73270236
Short name T652
Test name
Test status
Simulation time 621581105 ps
CPU time 5.26 seconds
Started Jun 01 03:04:01 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 222340 kb
Host smart-a784345b-519c-41be-94eb-4caa7a8b3940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73270236 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.73270236
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.827032664
Short name T568
Test name
Test status
Simulation time 25555802 ps
CPU time 0.76 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:05 PM PDT 24
Peak memory 205368 kb
Host smart-e4632d9b-378b-4ad3-a797-4d5d8a76032b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827032664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.827032664
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1081524874
Short name T121
Test name
Test status
Simulation time 325941402 ps
CPU time 4.68 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:09 PM PDT 24
Peak memory 214964 kb
Host smart-88697bd0-aa10-4b16-bca8-3f678f2e88d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081524874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1081524874
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.651836292
Short name T866
Test name
Test status
Simulation time 296777454 ps
CPU time 5.69 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:11 PM PDT 24
Peak memory 209236 kb
Host smart-cb95d8ab-1cf8-42cd-b5a8-99efb3148fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651836292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.651836292
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1979772727
Short name T76
Test name
Test status
Simulation time 171728729 ps
CPU time 3.66 seconds
Started Jun 01 03:04:03 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 208864 kb
Host smart-74be57ce-11e0-4916-b1e9-51397c99cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979772727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1979772727
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2938537501
Short name T408
Test name
Test status
Simulation time 58955928 ps
CPU time 3.43 seconds
Started Jun 01 03:04:05 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 219832 kb
Host smart-4b8ee672-0803-4207-9679-527aab8b0142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938537501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2938537501
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4277835776
Short name T964
Test name
Test status
Simulation time 112070818 ps
CPU time 3.69 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 214984 kb
Host smart-2ce377f3-0f46-4050-bc1c-b94078549b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277835776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4277835776
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3196127977
Short name T690
Test name
Test status
Simulation time 149986574 ps
CPU time 3.23 seconds
Started Jun 01 03:04:08 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 206600 kb
Host smart-4b5be6ed-aad0-404c-9838-46dda4d935af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196127977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3196127977
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.96876932
Short name T578
Test name
Test status
Simulation time 2351420489 ps
CPU time 4.05 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:08 PM PDT 24
Peak memory 206580 kb
Host smart-d8dc527c-2510-4fbf-b20f-4821dcd13b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96876932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.96876932
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2667391145
Short name T226
Test name
Test status
Simulation time 2207198467 ps
CPU time 52.92 seconds
Started Jun 01 03:04:07 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 207928 kb
Host smart-37a544b7-ef62-4112-bd52-eb89d5b5a680
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667391145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2667391145
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2088063631
Short name T266
Test name
Test status
Simulation time 73234629 ps
CPU time 4.04 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:09 PM PDT 24
Peak memory 208528 kb
Host smart-b5a7066f-2d47-4566-a397-74b47821d73c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088063631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2088063631
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4108902295
Short name T571
Test name
Test status
Simulation time 118115402 ps
CPU time 5.06 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:10 PM PDT 24
Peak memory 208452 kb
Host smart-22fbb061-7d78-4c25-89d7-ae2c6ed44260
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108902295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4108902295
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3659659829
Short name T277
Test name
Test status
Simulation time 68958744 ps
CPU time 3.19 seconds
Started Jun 01 03:04:06 PM PDT 24
Finished Jun 01 03:04:10 PM PDT 24
Peak memory 215632 kb
Host smart-2f08893f-5c45-4676-9818-3c401a5c04ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659659829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3659659829
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3109832426
Short name T426
Test name
Test status
Simulation time 152867343 ps
CPU time 4.61 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:09 PM PDT 24
Peak memory 206464 kb
Host smart-39df25ee-a2da-41ef-b814-b6f0bfef2434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109832426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3109832426
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1834174908
Short name T245
Test name
Test status
Simulation time 13281672004 ps
CPU time 257.35 seconds
Started Jun 01 03:04:05 PM PDT 24
Finished Jun 01 03:08:23 PM PDT 24
Peak memory 216540 kb
Host smart-9b2c0b5d-fb29-46be-b39b-0116be5c6f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834174908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1834174908
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3649901126
Short name T932
Test name
Test status
Simulation time 300321663 ps
CPU time 4.84 seconds
Started Jun 01 03:04:05 PM PDT 24
Finished Jun 01 03:04:10 PM PDT 24
Peak memory 207560 kb
Host smart-3e3625f6-20fa-45ef-abae-9feef848d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649901126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3649901126
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3370739104
Short name T591
Test name
Test status
Simulation time 59708405 ps
CPU time 0.78 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:13 PM PDT 24
Peak memory 205524 kb
Host smart-5f777607-5fc8-45e5-8d12-32f6e17cdf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370739104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3370739104
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.478378705
Short name T28
Test name
Test status
Simulation time 393699640 ps
CPU time 8.02 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:22 PM PDT 24
Peak memory 214328 kb
Host smart-001f286e-4653-4495-b47e-2a688d993e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478378705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.478378705
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2556918054
Short name T781
Test name
Test status
Simulation time 71883287 ps
CPU time 1.91 seconds
Started Jun 01 03:04:03 PM PDT 24
Finished Jun 01 03:04:05 PM PDT 24
Peak memory 207848 kb
Host smart-d1cf1ca0-5c10-4519-9db3-792d771a1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556918054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2556918054
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1917680838
Short name T89
Test name
Test status
Simulation time 339589179 ps
CPU time 4.25 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:16 PM PDT 24
Peak memory 218136 kb
Host smart-b2865b27-e6f1-47d7-add2-2305a2a832b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917680838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1917680838
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3888488264
Short name T845
Test name
Test status
Simulation time 3626114590 ps
CPU time 39.6 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 222200 kb
Host smart-357ea529-85d8-4383-b570-6cac1aa0ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888488264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3888488264
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.3222943524
Short name T774
Test name
Test status
Simulation time 404909434 ps
CPU time 15.37 seconds
Started Jun 01 03:04:03 PM PDT 24
Finished Jun 01 03:04:19 PM PDT 24
Peak memory 207688 kb
Host smart-d9cbb518-a7a6-45e1-9223-58f050370ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222943524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3222943524
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3066429533
Short name T1034
Test name
Test status
Simulation time 211110473 ps
CPU time 3.23 seconds
Started Jun 01 03:04:04 PM PDT 24
Finished Jun 01 03:04:07 PM PDT 24
Peak memory 207940 kb
Host smart-7c51ba7e-725f-4ee1-9725-160d3b4eacd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066429533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3066429533
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3688785756
Short name T301
Test name
Test status
Simulation time 564074005 ps
CPU time 4.94 seconds
Started Jun 01 03:04:05 PM PDT 24
Finished Jun 01 03:04:11 PM PDT 24
Peak memory 206736 kb
Host smart-a3feebfd-f84b-424f-a48d-0aba483164a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688785756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3688785756
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4131625732
Short name T621
Test name
Test status
Simulation time 1051335091 ps
CPU time 12.44 seconds
Started Jun 01 03:04:07 PM PDT 24
Finished Jun 01 03:04:20 PM PDT 24
Peak memory 207748 kb
Host smart-8f31f64c-77a8-4661-ae56-e5312ca7c689
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131625732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4131625732
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.62742608
Short name T992
Test name
Test status
Simulation time 979569432 ps
CPU time 3.34 seconds
Started Jun 01 03:04:06 PM PDT 24
Finished Jun 01 03:04:10 PM PDT 24
Peak memory 208500 kb
Host smart-a16ab30d-991b-476c-91f2-5d5553fc3cd2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62742608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.62742608
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3094161130
Short name T1036
Test name
Test status
Simulation time 226842266 ps
CPU time 2.16 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:14 PM PDT 24
Peak memory 208756 kb
Host smart-fc57fa77-5444-4be2-bd49-e0381077104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094161130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3094161130
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.735457086
Short name T965
Test name
Test status
Simulation time 74303003 ps
CPU time 2.62 seconds
Started Jun 01 03:04:03 PM PDT 24
Finished Jun 01 03:04:06 PM PDT 24
Peak memory 206476 kb
Host smart-9cb016c6-87b6-4082-85c5-ac5c6a1958ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735457086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.735457086
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1231484208
Short name T750
Test name
Test status
Simulation time 85414326 ps
CPU time 3.75 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 222400 kb
Host smart-ba0fd859-d32b-4e92-8d0e-5e45beea9409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231484208 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1231484208
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1941881916
Short name T1062
Test name
Test status
Simulation time 5225018105 ps
CPU time 96.28 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 209332 kb
Host smart-a060fb7e-c647-48fa-ae1c-15d895ba9010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941881916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1941881916
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2717208812
Short name T996
Test name
Test status
Simulation time 572562451 ps
CPU time 3.87 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:04:19 PM PDT 24
Peak memory 209444 kb
Host smart-0aaacc60-6eeb-47ca-b423-591b7ec7ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717208812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2717208812
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.690535122
Short name T575
Test name
Test status
Simulation time 88768931 ps
CPU time 0.74 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 205528 kb
Host smart-87480112-b15b-4019-b3c8-bdaa732f942a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690535122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.690535122
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2109127621
Short name T39
Test name
Test status
Simulation time 1649057935 ps
CPU time 18.6 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:04:33 PM PDT 24
Peak memory 208308 kb
Host smart-0d43a312-5869-4de6-8df6-d16f58c57c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109127621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2109127621
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1843316419
Short name T1030
Test name
Test status
Simulation time 187927172 ps
CPU time 2.39 seconds
Started Jun 01 03:04:16 PM PDT 24
Finished Jun 01 03:04:18 PM PDT 24
Peak memory 222204 kb
Host smart-862104ac-190b-4977-af9b-af6751c6fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843316419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1843316419
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1008931286
Short name T1044
Test name
Test status
Simulation time 1127888742 ps
CPU time 36.88 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 213992 kb
Host smart-8ef4b38a-abd6-4394-83ea-242c57c57e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008931286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1008931286
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1404339174
Short name T377
Test name
Test status
Simulation time 210922436 ps
CPU time 5.36 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:18 PM PDT 24
Peak memory 208652 kb
Host smart-73b92101-e49b-4eab-9bc9-29cbf0fd1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404339174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1404339174
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.350521429
Short name T82
Test name
Test status
Simulation time 1899234403 ps
CPU time 56 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:05:11 PM PDT 24
Peak memory 208668 kb
Host smart-c812ad87-bc67-4b46-9479-73adcade4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350521429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.350521429
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4289064507
Short name T833
Test name
Test status
Simulation time 147653529 ps
CPU time 2.39 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 206552 kb
Host smart-d4405d6f-08d4-47f3-b6da-37f523cc41bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289064507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4289064507
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1505265119
Short name T611
Test name
Test status
Simulation time 33485552 ps
CPU time 2.35 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:04:17 PM PDT 24
Peak memory 206492 kb
Host smart-bf2e1f43-c197-4833-badf-d82742ab037d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505265119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1505265119
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3383155979
Short name T793
Test name
Test status
Simulation time 122835269 ps
CPU time 2.42 seconds
Started Jun 01 03:04:11 PM PDT 24
Finished Jun 01 03:04:14 PM PDT 24
Peak memory 206952 kb
Host smart-f40000d6-ab10-463a-96a1-dfdb7d5b37c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383155979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3383155979
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3192463928
Short name T42
Test name
Test status
Simulation time 113413524 ps
CPU time 2.49 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:16 PM PDT 24
Peak memory 206576 kb
Host smart-af307c58-10a2-4a83-8d1c-6e8613deb89f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192463928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3192463928
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1762972976
Short name T255
Test name
Test status
Simulation time 74879505 ps
CPU time 2.27 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 207604 kb
Host smart-85ab050b-89db-4649-bb4f-1b5800739c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762972976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1762972976
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2102048132
Short name T111
Test name
Test status
Simulation time 257972749 ps
CPU time 7.46 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:21 PM PDT 24
Peak memory 206680 kb
Host smart-13f16e12-0a35-47aa-8371-7be1cadc5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102048132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2102048132
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2442956690
Short name T920
Test name
Test status
Simulation time 231105906 ps
CPU time 6.14 seconds
Started Jun 01 03:04:15 PM PDT 24
Finished Jun 01 03:04:22 PM PDT 24
Peak memory 218088 kb
Host smart-b3f48ba4-cdc9-489d-8b76-b48d7cc72366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442956690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2442956690
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2095438564
Short name T776
Test name
Test status
Simulation time 11995612 ps
CPU time 0.75 seconds
Started Jun 01 03:04:19 PM PDT 24
Finished Jun 01 03:04:21 PM PDT 24
Peak memory 205572 kb
Host smart-c98b6853-5d6e-4650-9209-d7600eeeb2e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095438564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2095438564
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.128353378
Short name T443
Test name
Test status
Simulation time 185534516 ps
CPU time 3.05 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:17 PM PDT 24
Peak memory 214892 kb
Host smart-24aeb329-3f45-4906-97ef-8d98118c75b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128353378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.128353378
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.568711866
Short name T30
Test name
Test status
Simulation time 1676299609 ps
CPU time 9.18 seconds
Started Jun 01 03:04:22 PM PDT 24
Finished Jun 01 03:04:32 PM PDT 24
Peak memory 221248 kb
Host smart-956bcf08-072a-4a4f-941b-dd606a82b1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568711866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.568711866
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1312188207
Short name T263
Test name
Test status
Simulation time 39425603 ps
CPU time 2.19 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:16 PM PDT 24
Peak memory 207780 kb
Host smart-1395b50d-666c-4527-b426-ada41553f9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312188207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1312188207
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4033317303
Short name T249
Test name
Test status
Simulation time 436534878 ps
CPU time 3.23 seconds
Started Jun 01 03:04:15 PM PDT 24
Finished Jun 01 03:04:19 PM PDT 24
Peak memory 207716 kb
Host smart-05978c85-ebd2-4dd2-a5d2-c7978c46d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033317303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4033317303
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3536578585
Short name T744
Test name
Test status
Simulation time 472600190 ps
CPU time 9.56 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:23 PM PDT 24
Peak memory 207100 kb
Host smart-33bab7fc-0528-4f56-9cc8-b82a762e1114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536578585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3536578585
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1805937157
Short name T381
Test name
Test status
Simulation time 249335575 ps
CPU time 6.38 seconds
Started Jun 01 03:04:15 PM PDT 24
Finished Jun 01 03:04:22 PM PDT 24
Peak memory 207612 kb
Host smart-6c8a0537-b1a6-4d2e-accc-95e0712db98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805937157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1805937157
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1624823026
Short name T738
Test name
Test status
Simulation time 205715101 ps
CPU time 3.25 seconds
Started Jun 01 03:04:14 PM PDT 24
Finished Jun 01 03:04:18 PM PDT 24
Peak memory 206488 kb
Host smart-570fb426-778e-48d7-8073-060f0e6cf6bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624823026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1624823026
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2072125730
Short name T824
Test name
Test status
Simulation time 26810660 ps
CPU time 2 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 206680 kb
Host smart-f5c8b648-b3c2-4589-b002-86ab90876b15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072125730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2072125730
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1106967219
Short name T894
Test name
Test status
Simulation time 140556179 ps
CPU time 2.32 seconds
Started Jun 01 03:04:12 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 206608 kb
Host smart-648fff58-3f10-4e8a-bfdf-b5b7ebaa8daf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106967219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1106967219
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.497969205
Short name T706
Test name
Test status
Simulation time 225004603 ps
CPU time 4.46 seconds
Started Jun 01 03:04:22 PM PDT 24
Finished Jun 01 03:04:27 PM PDT 24
Peak memory 218012 kb
Host smart-692dec99-1ca6-4a7f-9671-1a40c908ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497969205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.497969205
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1656932725
Short name T809
Test name
Test status
Simulation time 141520053 ps
CPU time 3.78 seconds
Started Jun 01 03:04:10 PM PDT 24
Finished Jun 01 03:04:15 PM PDT 24
Peak memory 206384 kb
Host smart-af2761c4-ce10-413d-98f0-8b5ac3fd9f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656932725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1656932725
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3769732149
Short name T331
Test name
Test status
Simulation time 36129547903 ps
CPU time 335.21 seconds
Started Jun 01 03:04:19 PM PDT 24
Finished Jun 01 03:09:55 PM PDT 24
Peak memory 217344 kb
Host smart-5c196973-ef38-41b7-8d7e-b89ee6033eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769732149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3769732149
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3072238183
Short name T330
Test name
Test status
Simulation time 135330509 ps
CPU time 3.01 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 222364 kb
Host smart-350b1ff8-a764-47f4-b3f3-852b49970aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072238183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3072238183
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2569707693
Short name T220
Test name
Test status
Simulation time 284130403 ps
CPU time 3.56 seconds
Started Jun 01 03:04:13 PM PDT 24
Finished Jun 01 03:04:17 PM PDT 24
Peak memory 206992 kb
Host smart-428fe56d-0d5f-4988-8b87-4bbe6bafc12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569707693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2569707693
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4083866178
Short name T849
Test name
Test status
Simulation time 142501392 ps
CPU time 2.03 seconds
Started Jun 01 03:04:22 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 209784 kb
Host smart-a9a3fb13-65f3-48bb-87e2-e58b736f9374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083866178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4083866178
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2919845382
Short name T572
Test name
Test status
Simulation time 75013843 ps
CPU time 0.75 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:23 PM PDT 24
Peak memory 205572 kb
Host smart-0046b508-a91c-4790-913e-cc79d86693ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919845382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2919845382
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3171703332
Short name T756
Test name
Test status
Simulation time 95249296 ps
CPU time 2.04 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:27 PM PDT 24
Peak memory 209188 kb
Host smart-3f3ddb08-9b04-43e3-bd2b-9d6f92a5d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171703332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3171703332
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3012543787
Short name T74
Test name
Test status
Simulation time 87896880 ps
CPU time 3.56 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:26 PM PDT 24
Peak memory 214032 kb
Host smart-e8f750a4-610b-4a9f-ab10-94fe92d92ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012543787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3012543787
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3613601984
Short name T18
Test name
Test status
Simulation time 259141253 ps
CPU time 5.99 seconds
Started Jun 01 03:04:23 PM PDT 24
Finished Jun 01 03:04:29 PM PDT 24
Peak memory 213992 kb
Host smart-a121be23-9dad-4ad9-a491-b24c4daf10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613601984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3613601984
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.748686217
Short name T346
Test name
Test status
Simulation time 53453698 ps
CPU time 3.46 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:23 PM PDT 24
Peak memory 211404 kb
Host smart-57d8fdb1-5f7c-46e7-a44e-1d2d129a433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748686217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.748686217
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4154462641
Short name T1060
Test name
Test status
Simulation time 141457808 ps
CPU time 2.97 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:24 PM PDT 24
Peak memory 206868 kb
Host smart-1441744f-5895-481d-af03-eaee75e08242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154462641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4154462641
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3284171460
Short name T1010
Test name
Test status
Simulation time 299054169 ps
CPU time 5.16 seconds
Started Jun 01 03:04:18 PM PDT 24
Finished Jun 01 03:04:24 PM PDT 24
Peak memory 207232 kb
Host smart-6f2261be-1e5c-42f1-95e5-b9aadabd4006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284171460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3284171460
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1230308204
Short name T585
Test name
Test status
Simulation time 52137718 ps
CPU time 2.43 seconds
Started Jun 01 03:04:23 PM PDT 24
Finished Jun 01 03:04:26 PM PDT 24
Peak memory 206588 kb
Host smart-164df175-fc29-44cb-8c9d-eb9a0c423a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230308204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1230308204
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.281025824
Short name T681
Test name
Test status
Simulation time 63509858 ps
CPU time 3.23 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:28 PM PDT 24
Peak memory 206544 kb
Host smart-0e757be5-9282-4b9f-a261-fc563dc2f386
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281025824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.281025824
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3128118771
Short name T1038
Test name
Test status
Simulation time 267449790 ps
CPU time 4.14 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 208144 kb
Host smart-eccd295f-2919-4da3-90f1-f16a682493a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128118771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3128118771
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.527995491
Short name T425
Test name
Test status
Simulation time 3802734983 ps
CPU time 38.38 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 208068 kb
Host smart-9d87eacd-5365-4501-a30d-0fd06e238b9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527995491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.527995491
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3784235783
Short name T1012
Test name
Test status
Simulation time 206883752 ps
CPU time 2.67 seconds
Started Jun 01 03:04:23 PM PDT 24
Finished Jun 01 03:04:26 PM PDT 24
Peak memory 208660 kb
Host smart-1da01d31-cfe4-4483-84ae-26b68c769352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784235783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3784235783
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1044583559
Short name T921
Test name
Test status
Simulation time 200934453 ps
CPU time 2.45 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:27 PM PDT 24
Peak memory 208040 kb
Host smart-6bbff8ad-d999-4c4a-8687-d30103732c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044583559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1044583559
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2816251952
Short name T1028
Test name
Test status
Simulation time 129608315 ps
CPU time 3.13 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:24 PM PDT 24
Peak memory 207968 kb
Host smart-871d2368-dfc8-4c13-91a8-1bd20279c880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816251952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2816251952
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2222058077
Short name T807
Test name
Test status
Simulation time 16222321 ps
CPU time 0.77 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:29 PM PDT 24
Peak memory 205488 kb
Host smart-88d9b1b8-c3de-47bd-bbe0-00b33fa1d58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222058077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2222058077
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3244883947
Short name T940
Test name
Test status
Simulation time 431724364 ps
CPU time 15.36 seconds
Started Jun 01 03:04:35 PM PDT 24
Finished Jun 01 03:04:50 PM PDT 24
Peak memory 222516 kb
Host smart-676059b9-93d0-41a5-ab65-0ae938e88f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244883947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3244883947
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3586829403
Short name T590
Test name
Test status
Simulation time 247968964 ps
CPU time 1.75 seconds
Started Jun 01 03:04:23 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 207560 kb
Host smart-cd1559db-5462-4f97-850c-b1e95316dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586829403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3586829403
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.788598966
Short name T1027
Test name
Test status
Simulation time 159375160 ps
CPU time 6.94 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:31 PM PDT 24
Peak memory 213996 kb
Host smart-3dd0583c-781e-423c-937c-92637774733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788598966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.788598966
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.805685638
Short name T812
Test name
Test status
Simulation time 251514149 ps
CPU time 9.01 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:31 PM PDT 24
Peak memory 209208 kb
Host smart-8a1a0c60-8f72-46b8-8016-3ae22da65597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805685638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.805685638
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.576306592
Short name T998
Test name
Test status
Simulation time 616485322 ps
CPU time 4.92 seconds
Started Jun 01 03:04:24 PM PDT 24
Finished Jun 01 03:04:29 PM PDT 24
Peak memory 210300 kb
Host smart-cc634f68-296d-4628-9e2b-f6dc01f7c794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576306592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.576306592
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.604626736
Short name T748
Test name
Test status
Simulation time 100970436 ps
CPU time 3.91 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 207504 kb
Host smart-52463044-469d-47a0-8c3e-700bfc6559bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604626736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.604626736
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1206477558
Short name T743
Test name
Test status
Simulation time 263515302 ps
CPU time 3.84 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:24 PM PDT 24
Peak memory 208568 kb
Host smart-61c9f3e1-4403-407f-ae93-675ca9c2f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206477558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1206477558
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.22247597
Short name T639
Test name
Test status
Simulation time 132026258 ps
CPU time 2.75 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 208264 kb
Host smart-139f7f1e-5141-4435-80de-757741dd863b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.22247597
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2565046420
Short name T620
Test name
Test status
Simulation time 66172302 ps
CPU time 3.39 seconds
Started Jun 01 03:04:21 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 208428 kb
Host smart-8482eb23-b76f-4bba-80f5-1a615ecec4f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565046420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2565046420
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4235099620
Short name T642
Test name
Test status
Simulation time 103090438 ps
CPU time 3.62 seconds
Started Jun 01 03:04:22 PM PDT 24
Finished Jun 01 03:04:26 PM PDT 24
Peak memory 206464 kb
Host smart-9c6ad6e0-56cd-40b7-a1a4-e108bb3a3c66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235099620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4235099620
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3702732389
Short name T623
Test name
Test status
Simulation time 49892432 ps
CPU time 1.79 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:30 PM PDT 24
Peak memory 209436 kb
Host smart-c64aacf2-62ea-40bf-a35a-1e2b42b588ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702732389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3702732389
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2079043493
Short name T769
Test name
Test status
Simulation time 362276708 ps
CPU time 5.82 seconds
Started Jun 01 03:04:19 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 208272 kb
Host smart-da3ecaa3-f20c-4830-8161-eaa096764549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079043493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2079043493
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3096700151
Short name T762
Test name
Test status
Simulation time 293077988 ps
CPU time 2.92 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:33 PM PDT 24
Peak memory 217732 kb
Host smart-81eece56-223f-46cf-9b0f-bff61eedc827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096700151 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3096700151
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3647822793
Short name T847
Test name
Test status
Simulation time 78963260 ps
CPU time 4.22 seconds
Started Jun 01 03:04:20 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 208936 kb
Host smart-ff67a6e3-f0b3-412d-961e-9dd063813d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647822793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3647822793
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2447534313
Short name T861
Test name
Test status
Simulation time 56023155 ps
CPU time 2.85 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:32 PM PDT 24
Peak memory 210028 kb
Host smart-42496ae1-7031-4529-bde6-18f70e9fc1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447534313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2447534313
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1379959803
Short name T604
Test name
Test status
Simulation time 11616882 ps
CPU time 0.71 seconds
Started Jun 01 03:04:30 PM PDT 24
Finished Jun 01 03:04:31 PM PDT 24
Peak memory 205524 kb
Host smart-e1990256-88b8-45ac-8a22-2f3451444704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379959803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1379959803
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2623028307
Short name T1029
Test name
Test status
Simulation time 124562733 ps
CPU time 4.21 seconds
Started Jun 01 03:04:27 PM PDT 24
Finished Jun 01 03:04:31 PM PDT 24
Peak memory 208424 kb
Host smart-ece546c9-cb41-4725-a878-4abe0f8bd5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623028307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2623028307
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1529470625
Short name T79
Test name
Test status
Simulation time 23049501 ps
CPU time 1.75 seconds
Started Jun 01 03:04:30 PM PDT 24
Finished Jun 01 03:04:32 PM PDT 24
Peak memory 206796 kb
Host smart-37e30b4c-32cd-4faa-87b7-58a04181b17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529470625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1529470625
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2797219580
Short name T908
Test name
Test status
Simulation time 87319645 ps
CPU time 4.37 seconds
Started Jun 01 03:04:27 PM PDT 24
Finished Jun 01 03:04:32 PM PDT 24
Peak memory 213960 kb
Host smart-40cde1e5-97d6-4bd1-9c08-6457fca755a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797219580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2797219580
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3539370245
Short name T896
Test name
Test status
Simulation time 642983858 ps
CPU time 3.62 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:33 PM PDT 24
Peak memory 210312 kb
Host smart-3eb9134f-7be8-4910-9c70-4582959a6660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539370245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3539370245
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.784143710
Short name T751
Test name
Test status
Simulation time 734516307 ps
CPU time 11.23 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:40 PM PDT 24
Peak memory 207552 kb
Host smart-7504b1bd-f773-473b-a351-2b03f33a6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784143710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.784143710
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3219651693
Short name T1055
Test name
Test status
Simulation time 142834784 ps
CPU time 4.79 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:35 PM PDT 24
Peak memory 207636 kb
Host smart-a454e11f-9cce-4a18-b704-fe5ca9b9c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219651693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3219651693
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.995155758
Short name T400
Test name
Test status
Simulation time 537290267 ps
CPU time 4.05 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:32 PM PDT 24
Peak memory 206568 kb
Host smart-8b0eafc2-731a-4693-86e4-5f04c4ccf8de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995155758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.995155758
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.687858393
Short name T204
Test name
Test status
Simulation time 476977986 ps
CPU time 5.86 seconds
Started Jun 01 03:04:35 PM PDT 24
Finished Jun 01 03:04:41 PM PDT 24
Peak memory 206556 kb
Host smart-b655d822-fdbb-49a7-90c7-e038436fda68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687858393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.687858393
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2071559209
Short name T951
Test name
Test status
Simulation time 57409769 ps
CPU time 3.07 seconds
Started Jun 01 03:04:30 PM PDT 24
Finished Jun 01 03:04:33 PM PDT 24
Peak memory 208564 kb
Host smart-7c249a25-0de8-4884-bd9e-027adc7c9de7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071559209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2071559209
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3845809955
Short name T830
Test name
Test status
Simulation time 125663030 ps
CPU time 4.68 seconds
Started Jun 01 03:04:49 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 207244 kb
Host smart-b378d167-4498-4b4b-b1c7-65703d153a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845809955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3845809955
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3002831519
Short name T576
Test name
Test status
Simulation time 301315132 ps
CPU time 2.53 seconds
Started Jun 01 03:04:32 PM PDT 24
Finished Jun 01 03:04:35 PM PDT 24
Peak memory 206592 kb
Host smart-30e50455-8f12-4ab6-bc97-7c51aaad9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002831519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3002831519
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3115411277
Short name T580
Test name
Test status
Simulation time 609919585 ps
CPU time 6.19 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:36 PM PDT 24
Peak memory 222340 kb
Host smart-f625c7a6-4c60-45f0-94dc-d680798c06a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115411277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3115411277
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2164592233
Short name T895
Test name
Test status
Simulation time 138883745 ps
CPU time 5.53 seconds
Started Jun 01 03:04:29 PM PDT 24
Finished Jun 01 03:04:35 PM PDT 24
Peak memory 217964 kb
Host smart-9d927fba-443a-4637-bc4d-3f283f7b03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164592233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2164592233
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.4225391707
Short name T698
Test name
Test status
Simulation time 55288135 ps
CPU time 1.62 seconds
Started Jun 01 03:04:28 PM PDT 24
Finished Jun 01 03:04:30 PM PDT 24
Peak memory 209452 kb
Host smart-a02ff709-0ff4-4f52-9d4b-38f291a654a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225391707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.4225391707
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3330236977
Short name T922
Test name
Test status
Simulation time 61000549 ps
CPU time 0.71 seconds
Started Jun 01 03:04:38 PM PDT 24
Finished Jun 01 03:04:39 PM PDT 24
Peak memory 205364 kb
Host smart-c9a5ffe1-4c21-488c-b1eb-6f8f00d1fa77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330236977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3330236977
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2850525938
Short name T370
Test name
Test status
Simulation time 27870009 ps
CPU time 1.48 seconds
Started Jun 01 03:04:37 PM PDT 24
Finished Jun 01 03:04:39 PM PDT 24
Peak memory 207844 kb
Host smart-8fcdb166-edfc-4781-8239-decc3347f901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850525938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2850525938
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1082245931
Short name T345
Test name
Test status
Simulation time 35032145434 ps
CPU time 46.1 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:05:28 PM PDT 24
Peak memory 213932 kb
Host smart-aec4748d-1739-4728-93ac-e67293123f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082245931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1082245931
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4239531461
Short name T754
Test name
Test status
Simulation time 152458891 ps
CPU time 5.39 seconds
Started Jun 01 03:04:38 PM PDT 24
Finished Jun 01 03:04:44 PM PDT 24
Peak memory 209148 kb
Host smart-dc1c5165-0dbd-4ae8-b4bc-c53cfc5f2384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239531461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4239531461
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.342569050
Short name T679
Test name
Test status
Simulation time 111228147 ps
CPU time 4.37 seconds
Started Jun 01 03:04:40 PM PDT 24
Finished Jun 01 03:04:44 PM PDT 24
Peak memory 208408 kb
Host smart-de1bc3fe-2d12-44aa-abbd-03d8e44ce766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342569050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.342569050
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1414273679
Short name T630
Test name
Test status
Simulation time 62437665 ps
CPU time 3.15 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:04:45 PM PDT 24
Peak memory 208520 kb
Host smart-de93c006-59dd-4576-9a9e-47648c299f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414273679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1414273679
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.746347609
Short name T86
Test name
Test status
Simulation time 199801428 ps
CPU time 3.1 seconds
Started Jun 01 03:04:38 PM PDT 24
Finished Jun 01 03:04:41 PM PDT 24
Peak memory 206636 kb
Host smart-d37c9836-0d42-40bd-a6d5-4163eef63a24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746347609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.746347609
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.250178142
Short name T857
Test name
Test status
Simulation time 1094473002 ps
CPU time 22.16 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:05:02 PM PDT 24
Peak memory 207944 kb
Host smart-43b7803a-1575-45ee-ac95-dc2a4934c970
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250178142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.250178142
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3082307598
Short name T974
Test name
Test status
Simulation time 66742061 ps
CPU time 3.41 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:04:44 PM PDT 24
Peak memory 208680 kb
Host smart-a1278313-a1d0-4674-b0e2-ced1a9600011
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082307598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3082307598
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1066337866
Short name T902
Test name
Test status
Simulation time 73940130 ps
CPU time 2.52 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:04:42 PM PDT 24
Peak memory 209340 kb
Host smart-d3f73432-8e27-43f6-ac1b-a89f14c7bf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066337866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1066337866
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2572330756
Short name T761
Test name
Test status
Simulation time 129806242 ps
CPU time 2.92 seconds
Started Jun 01 03:04:30 PM PDT 24
Finished Jun 01 03:04:33 PM PDT 24
Peak memory 208024 kb
Host smart-d95f25bd-5bf4-466d-a765-463dc74942af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572330756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2572330756
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1011538379
Short name T454
Test name
Test status
Simulation time 951997440 ps
CPU time 19.4 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:05:01 PM PDT 24
Peak memory 216024 kb
Host smart-4a7af784-a744-43d8-ab03-ed64105e29cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011538379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1011538379
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2453927900
Short name T48
Test name
Test status
Simulation time 882680471 ps
CPU time 9.79 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 222264 kb
Host smart-9c96c401-8286-44f9-b2dc-0ad9753a71b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453927900 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2453927900
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2203886514
Short name T688
Test name
Test status
Simulation time 889497862 ps
CPU time 8.07 seconds
Started Jun 01 03:04:41 PM PDT 24
Finished Jun 01 03:04:50 PM PDT 24
Peak memory 208856 kb
Host smart-35346921-f5c8-4d52-af52-a23da86791a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203886514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2203886514
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2091840945
Short name T783
Test name
Test status
Simulation time 78510130 ps
CPU time 2.98 seconds
Started Jun 01 03:04:39 PM PDT 24
Finished Jun 01 03:04:43 PM PDT 24
Peak memory 210440 kb
Host smart-e96a90e4-a86b-45be-8bf2-7c5374d4de13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091840945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2091840945
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1864094662
Short name T463
Test name
Test status
Simulation time 69052077 ps
CPU time 0.72 seconds
Started Jun 01 03:03:14 PM PDT 24
Finished Jun 01 03:03:15 PM PDT 24
Peak memory 205524 kb
Host smart-61953ae5-0faf-4759-a644-54b1e007cc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864094662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1864094662
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.818657780
Short name T808
Test name
Test status
Simulation time 4017549975 ps
CPU time 47.61 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:54 PM PDT 24
Peak memory 214212 kb
Host smart-ab35cb7d-5b5d-4e9e-94a2-11c4c9171b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818657780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.818657780
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2570405836
Short name T916
Test name
Test status
Simulation time 31381741 ps
CPU time 2.01 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:12 PM PDT 24
Peak memory 213912 kb
Host smart-ecded7c6-1c8f-4285-a0bc-6d923b3039aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570405836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2570405836
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.819676744
Short name T349
Test name
Test status
Simulation time 6056261262 ps
CPU time 47.81 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:57 PM PDT 24
Peak memory 222180 kb
Host smart-eb50bad5-fa50-47ef-8559-32d8a7a8e48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819676744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.819676744
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1122145364
Short name T913
Test name
Test status
Simulation time 198451096 ps
CPU time 2.46 seconds
Started Jun 01 03:03:10 PM PDT 24
Finished Jun 01 03:03:13 PM PDT 24
Peak memory 215176 kb
Host smart-00e6875b-8f8b-4794-ac9e-4ce72dc1bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122145364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1122145364
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3666752811
Short name T644
Test name
Test status
Simulation time 153823108 ps
CPU time 5.27 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:12 PM PDT 24
Peak memory 213996 kb
Host smart-18bd6e18-9209-475a-8338-40bea825b8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666752811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3666752811
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.523802857
Short name T13
Test name
Test status
Simulation time 18203175662 ps
CPU time 42.47 seconds
Started Jun 01 03:03:18 PM PDT 24
Finished Jun 01 03:04:01 PM PDT 24
Peak memory 243628 kb
Host smart-ec95308e-7306-49c7-94e3-3a1838dbd957
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523802857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.523802857
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3278831122
Short name T592
Test name
Test status
Simulation time 279809925 ps
CPU time 2.56 seconds
Started Jun 01 03:03:07 PM PDT 24
Finished Jun 01 03:03:10 PM PDT 24
Peak memory 206316 kb
Host smart-fb6993b5-85e1-4ad0-9dc8-078c62403d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278831122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3278831122
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3124856011
Short name T672
Test name
Test status
Simulation time 163003379 ps
CPU time 6.79 seconds
Started Jun 01 03:03:09 PM PDT 24
Finished Jun 01 03:03:16 PM PDT 24
Peak memory 208412 kb
Host smart-665c03b5-cbcf-4d98-8aca-e2ac0ccf327f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124856011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3124856011
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3047506406
Short name T1046
Test name
Test status
Simulation time 400102562 ps
CPU time 6.58 seconds
Started Jun 01 03:03:06 PM PDT 24
Finished Jun 01 03:03:13 PM PDT 24
Peak memory 207976 kb
Host smart-a983e6c8-4231-41c1-9950-dd6c3620c5c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047506406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3047506406
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3464195227
Short name T684
Test name
Test status
Simulation time 1022376537 ps
CPU time 9.34 seconds
Started Jun 01 03:03:08 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 208076 kb
Host smart-7291b9b3-5570-4d1f-aa13-9ec85aeac42e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464195227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3464195227
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3057278009
Short name T712
Test name
Test status
Simulation time 430627775 ps
CPU time 3.22 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:20 PM PDT 24
Peak memory 208164 kb
Host smart-040fde60-1f48-40eb-b56c-26bf73263f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057278009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3057278009
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2181484893
Short name T899
Test name
Test status
Simulation time 53966655 ps
CPU time 2.69 seconds
Started Jun 01 03:03:04 PM PDT 24
Finished Jun 01 03:03:07 PM PDT 24
Peak memory 207676 kb
Host smart-36bda2e7-5073-4d01-ae58-a00c5edbbf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181484893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2181484893
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.230948692
Short name T423
Test name
Test status
Simulation time 292097733 ps
CPU time 8.26 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:25 PM PDT 24
Peak memory 213740 kb
Host smart-cf9918f5-35ad-4eba-a009-e94fd1ea071d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230948692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.230948692
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1392186325
Short name T821
Test name
Test status
Simulation time 930617965 ps
CPU time 17.1 seconds
Started Jun 01 03:03:14 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 219956 kb
Host smart-860c3ddf-868f-4952-8c82-26aa1e5676ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392186325 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1392186325
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.616651479
Short name T583
Test name
Test status
Simulation time 91282737 ps
CPU time 1.87 seconds
Started Jun 01 03:03:13 PM PDT 24
Finished Jun 01 03:03:15 PM PDT 24
Peak memory 209396 kb
Host smart-bf24bf87-e74a-42ae-bfb4-04baf7ca85b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616651479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.616651479
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3662346475
Short name T942
Test name
Test status
Simulation time 30262968 ps
CPU time 0.88 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:49 PM PDT 24
Peak memory 205544 kb
Host smart-89ce7bd4-2247-4ae1-8e43-10cdb155eaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662346475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3662346475
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2598359669
Short name T461
Test name
Test status
Simulation time 344790828 ps
CPU time 3.47 seconds
Started Jun 01 03:04:52 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 222588 kb
Host smart-9a54daca-7abc-4805-bbba-e15a1bdf458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598359669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2598359669
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3082264682
Short name T795
Test name
Test status
Simulation time 249140567 ps
CPU time 5.03 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 213960 kb
Host smart-c839fbf0-5a62-48e7-9aac-9e90dcbebc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082264682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3082264682
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3538355055
Short name T725
Test name
Test status
Simulation time 744266615 ps
CPU time 5.11 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 214016 kb
Host smart-35f3f65f-943b-4528-ae9b-ec05602dde02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538355055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3538355055
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1734579870
Short name T231
Test name
Test status
Simulation time 585614052 ps
CPU time 2.84 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 206168 kb
Host smart-1a36c941-16fc-4bfe-a582-873c7ad937a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734579870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1734579870
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3127099857
Short name T662
Test name
Test status
Simulation time 73781890 ps
CPU time 3.79 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 206992 kb
Host smart-c5ab5a52-2059-485b-9b7d-cd09578b442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127099857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3127099857
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.426705435
Short name T216
Test name
Test status
Simulation time 59106557 ps
CPU time 2.27 seconds
Started Jun 01 03:04:40 PM PDT 24
Finished Jun 01 03:04:43 PM PDT 24
Peak memory 206556 kb
Host smart-f7f46efb-329c-46a9-a400-c824de743c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426705435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.426705435
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2218424848
Short name T312
Test name
Test status
Simulation time 1388890414 ps
CPU time 30.23 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 208480 kb
Host smart-e5152a45-77e6-406d-8ed4-aa2f3465c655
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218424848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2218424848
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.440820550
Short name T419
Test name
Test status
Simulation time 143798369 ps
CPU time 4.01 seconds
Started Jun 01 03:04:49 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 206564 kb
Host smart-a7cacc8d-f8ce-487b-8cda-f27de5f39367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440820550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.440820550
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3081661256
Short name T934
Test name
Test status
Simulation time 6967631167 ps
CPU time 72.51 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:06:00 PM PDT 24
Peak memory 208056 kb
Host smart-9ff7c166-e680-4a3d-99ea-31ca0c67e69c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081661256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3081661256
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4167859386
Short name T287
Test name
Test status
Simulation time 465138334 ps
CPU time 5.22 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 218280 kb
Host smart-8f56f73f-b49c-48c7-8c17-2482fa7fdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167859386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4167859386
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2499203082
Short name T656
Test name
Test status
Simulation time 146374838 ps
CPU time 2.67 seconds
Started Jun 01 03:04:38 PM PDT 24
Finished Jun 01 03:04:41 PM PDT 24
Peak memory 205768 kb
Host smart-23e4c1fa-79ce-4495-b45f-174f37bb6c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499203082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2499203082
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1592717998
Short name T753
Test name
Test status
Simulation time 346085200 ps
CPU time 5.76 seconds
Started Jun 01 03:04:46 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 219616 kb
Host smart-70703682-838c-4e95-ba35-3faeb32b4ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592717998 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1592717998
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2222206514
Short name T1023
Test name
Test status
Simulation time 195509794 ps
CPU time 2.66 seconds
Started Jun 01 03:04:49 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 207096 kb
Host smart-4985bb51-9ad8-4d8b-b9ed-6f063db3bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222206514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2222206514
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3197757664
Short name T787
Test name
Test status
Simulation time 110659338 ps
CPU time 2.43 seconds
Started Jun 01 03:04:54 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 209628 kb
Host smart-44d5688d-56ec-4f4d-8cbc-46eb1accd3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197757664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3197757664
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.570785070
Short name T939
Test name
Test status
Simulation time 14103777 ps
CPU time 0.92 seconds
Started Jun 01 03:04:51 PM PDT 24
Finished Jun 01 03:04:53 PM PDT 24
Peak memory 205616 kb
Host smart-fdb36211-5adc-4315-846e-1321231edac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570785070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.570785070
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3042536642
Short name T673
Test name
Test status
Simulation time 5074917010 ps
CPU time 15.65 seconds
Started Jun 01 03:04:49 PM PDT 24
Finished Jun 01 03:05:05 PM PDT 24
Peak memory 208596 kb
Host smart-bf66a7ad-d7d3-4891-937d-e9396b6a641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042536642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3042536642
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.8205657
Short name T73
Test name
Test status
Simulation time 1239693277 ps
CPU time 9.2 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 214020 kb
Host smart-8ea7736a-c7b5-49bb-bc17-6b6bdd5922c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8205657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.8205657
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1450767498
Short name T411
Test name
Test status
Simulation time 90543156 ps
CPU time 4.38 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 217824 kb
Host smart-632572c3-8cf1-4eec-a6bd-a44d95a72a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450767498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1450767498
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2767831283
Short name T403
Test name
Test status
Simulation time 604562457 ps
CPU time 5.73 seconds
Started Jun 01 03:04:51 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 210380 kb
Host smart-c8f0cb7a-5e09-4a15-aa7d-8c1bf695b8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767831283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2767831283
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3903874078
Short name T46
Test name
Test status
Simulation time 167844773 ps
CPU time 2.7 seconds
Started Jun 01 03:04:53 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 209448 kb
Host smart-c7337fa7-116d-4c70-bfed-a69872a7a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903874078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3903874078
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.877324455
Short name T770
Test name
Test status
Simulation time 371545145 ps
CPU time 4.62 seconds
Started Jun 01 03:04:46 PM PDT 24
Finished Jun 01 03:04:52 PM PDT 24
Peak memory 214112 kb
Host smart-94978113-9415-4a11-a568-f6d49de870fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877324455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.877324455
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2060600928
Short name T705
Test name
Test status
Simulation time 1581025994 ps
CPU time 5.48 seconds
Started Jun 01 03:04:52 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 208176 kb
Host smart-a800d604-2838-4679-b3e7-f3276331e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060600928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2060600928
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3267530538
Short name T760
Test name
Test status
Simulation time 115048458 ps
CPU time 3.18 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 207200 kb
Host smart-371ec1b2-a0c0-4ca3-888c-fcba48a73148
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267530538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3267530538
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2645089943
Short name T891
Test name
Test status
Simulation time 95734843 ps
CPU time 2.02 seconds
Started Jun 01 03:04:51 PM PDT 24
Finished Jun 01 03:04:53 PM PDT 24
Peak memory 206952 kb
Host smart-ee07fbd2-48e4-4203-b64e-316904ec7a4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645089943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2645089943
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2059339323
Short name T834
Test name
Test status
Simulation time 27408155 ps
CPU time 2.09 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:51 PM PDT 24
Peak memory 208264 kb
Host smart-807419ed-c7c5-46c2-9512-bd1e44c66779
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059339323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2059339323
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2999288536
Short name T43
Test name
Test status
Simulation time 232320817 ps
CPU time 6.27 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 222112 kb
Host smart-675b20b3-2f34-4760-9ef7-4725e9a20068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999288536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2999288536
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3389990496
Short name T586
Test name
Test status
Simulation time 100095129 ps
CPU time 2.58 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:53 PM PDT 24
Peak memory 207792 kb
Host smart-def8d0d8-0711-4c11-9ef3-3d2c02f437f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389990496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3389990496
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.867283954
Short name T799
Test name
Test status
Simulation time 318252912 ps
CPU time 2.49 seconds
Started Jun 01 03:04:46 PM PDT 24
Finished Jun 01 03:04:49 PM PDT 24
Peak memory 217848 kb
Host smart-2b37ab73-a03d-4599-8942-85640f1b353d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867283954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.867283954
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.194971289
Short name T888
Test name
Test status
Simulation time 152528955 ps
CPU time 6.27 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:04:55 PM PDT 24
Peak memory 219456 kb
Host smart-05557d42-5a78-41d7-b9b9-7f763361c472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194971289 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.194971289
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4220262278
Short name T368
Test name
Test status
Simulation time 217611155 ps
CPU time 6.57 seconds
Started Jun 01 03:04:46 PM PDT 24
Finished Jun 01 03:04:54 PM PDT 24
Peak memory 218016 kb
Host smart-6ba95065-a3f0-493d-b598-a514f2cb9c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220262278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4220262278
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2888911227
Short name T1026
Test name
Test status
Simulation time 26677641 ps
CPU time 1.76 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:50 PM PDT 24
Peak memory 209588 kb
Host smart-a7714fe6-839f-46d7-b86b-17d2e4997b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888911227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2888911227
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3499618416
Short name T837
Test name
Test status
Simulation time 87325532 ps
CPU time 1.05 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 205808 kb
Host smart-8e19891c-1e46-4414-a154-1b1cd0954642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499618416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3499618416
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.350618989
Short name T460
Test name
Test status
Simulation time 174516111 ps
CPU time 5.1 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:03 PM PDT 24
Peak memory 209756 kb
Host smart-db2ddac0-c3f2-41e4-917c-0fd67080d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350618989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.350618989
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.462613667
Short name T581
Test name
Test status
Simulation time 1068787433 ps
CPU time 4.02 seconds
Started Jun 01 03:04:51 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 208932 kb
Host smart-8bd61c53-44d0-4c9d-84e6-b628b34e67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462613667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.462613667
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1690501868
Short name T409
Test name
Test status
Simulation time 1490440586 ps
CPU time 26.94 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 208712 kb
Host smart-e1bd7d36-b7ab-47d7-ac08-2fabb54b177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690501868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1690501868
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3938250934
Short name T371
Test name
Test status
Simulation time 741135724 ps
CPU time 5.92 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 213940 kb
Host smart-72072420-eb27-40f6-9d2e-4e6a3e899c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938250934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3938250934
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.2424756299
Short name T44
Test name
Test status
Simulation time 1162869064 ps
CPU time 8.9 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 207672 kb
Host smart-825db612-7f9e-4e18-ae05-bdf11462192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424756299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2424756299
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2234159884
Short name T276
Test name
Test status
Simulation time 678743945 ps
CPU time 5.28 seconds
Started Jun 01 03:04:52 PM PDT 24
Finished Jun 01 03:04:57 PM PDT 24
Peak memory 208104 kb
Host smart-bd042551-1282-4b47-b4bf-1c2a5040f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234159884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2234159884
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3372428439
Short name T1014
Test name
Test status
Simulation time 301407109 ps
CPU time 7.96 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 208288 kb
Host smart-a3557a6c-4add-42e6-a446-112018e1ddb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372428439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3372428439
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3229743137
Short name T729
Test name
Test status
Simulation time 120985958 ps
CPU time 2.49 seconds
Started Jun 01 03:04:47 PM PDT 24
Finished Jun 01 03:04:50 PM PDT 24
Peak memory 206556 kb
Host smart-6c8e53df-2281-447b-ac02-0205a11a23ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229743137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3229743137
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2200794053
Short name T985
Test name
Test status
Simulation time 1729453748 ps
CPU time 51.62 seconds
Started Jun 01 03:04:50 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 208284 kb
Host smart-56d280a9-e401-4e31-923c-0f3ddff31926
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200794053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2200794053
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1401999495
Short name T854
Test name
Test status
Simulation time 33242569 ps
CPU time 1.81 seconds
Started Jun 01 03:04:55 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 215528 kb
Host smart-98cf2960-0f2d-4169-88c2-2c28a633c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401999495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1401999495
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3699492737
Short name T579
Test name
Test status
Simulation time 3471761389 ps
CPU time 10.74 seconds
Started Jun 01 03:04:48 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 208268 kb
Host smart-2fb5433e-cd23-473f-92c0-ad0bc8680984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699492737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3699492737
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2359630657
Short name T78
Test name
Test status
Simulation time 1347366911 ps
CPU time 50.98 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 222124 kb
Host smart-741aacaf-add8-466c-b68b-3f560b589e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359630657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2359630657
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1320846593
Short name T629
Test name
Test status
Simulation time 163754995 ps
CPU time 5.66 seconds
Started Jun 01 03:04:52 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 206932 kb
Host smart-75d4840b-5272-4c12-b825-952312278227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320846593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1320846593
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4103003133
Short name T462
Test name
Test status
Simulation time 19745288 ps
CPU time 1.03 seconds
Started Jun 01 03:04:55 PM PDT 24
Finished Jun 01 03:04:56 PM PDT 24
Peak memory 205696 kb
Host smart-df93da52-b710-48a8-8244-3f94068d9acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103003133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4103003133
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1119925245
Short name T113
Test name
Test status
Simulation time 197532472 ps
CPU time 3.7 seconds
Started Jun 01 03:05:01 PM PDT 24
Finished Jun 01 03:05:05 PM PDT 24
Peak memory 214020 kb
Host smart-94e7c839-89bf-45ce-8a74-1302dd6f40d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119925245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1119925245
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4076604966
Short name T923
Test name
Test status
Simulation time 225191367 ps
CPU time 2.77 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 214024 kb
Host smart-b5f5f0ad-20fc-4480-aa79-d55ec48c76b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076604966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4076604966
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_random.1149505757
Short name T736
Test name
Test status
Simulation time 94165482 ps
CPU time 4.51 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:02 PM PDT 24
Peak memory 209072 kb
Host smart-a6b0f811-6901-422d-af76-ced61b97c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149505757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1149505757
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2861690285
Short name T1039
Test name
Test status
Simulation time 2724027619 ps
CPU time 12.3 seconds
Started Jun 01 03:05:01 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 208440 kb
Host smart-0fc276bc-78ac-4efe-a1ff-7b3567e7e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861690285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2861690285
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.543339187
Short name T773
Test name
Test status
Simulation time 2590945317 ps
CPU time 27.48 seconds
Started Jun 01 03:05:01 PM PDT 24
Finished Jun 01 03:05:29 PM PDT 24
Peak memory 207960 kb
Host smart-0331e70e-8685-4532-9273-09b7c5164c69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543339187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.543339187
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1283485863
Short name T432
Test name
Test status
Simulation time 48565083 ps
CPU time 2.43 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 206596 kb
Host smart-809728e8-e5f7-4c17-b4c8-ac96c8c77313
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283485863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1283485863
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3201239379
Short name T889
Test name
Test status
Simulation time 602566755 ps
CPU time 4.82 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:03 PM PDT 24
Peak memory 206404 kb
Host smart-c77731df-0c0c-47fc-bfd5-ddb2c1541a13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201239379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3201239379
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.223904523
Short name T747
Test name
Test status
Simulation time 172841806 ps
CPU time 5.84 seconds
Started Jun 01 03:05:02 PM PDT 24
Finished Jun 01 03:05:08 PM PDT 24
Peak memory 208244 kb
Host smart-70bc83d7-dd6d-416c-af24-997e230be280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223904523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.223904523
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3017447806
Short name T841
Test name
Test status
Simulation time 456652067 ps
CPU time 5.26 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:03 PM PDT 24
Peak memory 207928 kb
Host smart-1b211c4f-40fa-4949-8785-380efb6330a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017447806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3017447806
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1522510350
Short name T396
Test name
Test status
Simulation time 3303778306 ps
CPU time 51.72 seconds
Started Jun 01 03:04:59 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 215968 kb
Host smart-e79d7043-482e-4d5b-ba51-a9716cbd9ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522510350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1522510350
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1000494544
Short name T318
Test name
Test status
Simulation time 3591245321 ps
CPU time 36.43 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 208824 kb
Host smart-51fdffad-394b-43cf-bcdd-42d8fb53e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000494544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1000494544
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.23073545
Short name T422
Test name
Test status
Simulation time 63041429 ps
CPU time 2.02 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 209960 kb
Host smart-7b432694-f98e-48ce-bfde-f3c8bd4dd556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23073545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.23073545
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.696524762
Short name T814
Test name
Test status
Simulation time 16293724 ps
CPU time 0.75 seconds
Started Jun 01 03:05:03 PM PDT 24
Finished Jun 01 03:05:04 PM PDT 24
Peak memory 205588 kb
Host smart-299735e9-55f4-4d0e-b6f4-f92c156e7707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696524762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.696524762
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.424391512
Short name T1064
Test name
Test status
Simulation time 198229590 ps
CPU time 3.37 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 215008 kb
Host smart-169d6a5c-06f9-4a78-b470-757beac54492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424391512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.424391512
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2727684035
Short name T35
Test name
Test status
Simulation time 283058001 ps
CPU time 4.01 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 221492 kb
Host smart-24c6c52c-9e9b-4195-a66b-f32176c3e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727684035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2727684035
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2779897856
Short name T647
Test name
Test status
Simulation time 21746700 ps
CPU time 1.59 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:04:58 PM PDT 24
Peak memory 207032 kb
Host smart-c5657fa7-d678-479c-a482-d5f657d63db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779897856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2779897856
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3095032666
Short name T332
Test name
Test status
Simulation time 250293377 ps
CPU time 7.07 seconds
Started Jun 01 03:05:10 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 214184 kb
Host smart-f28ce426-a0aa-4183-a40a-184752458ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095032666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3095032666
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1212847607
Short name T402
Test name
Test status
Simulation time 1108634731 ps
CPU time 9.05 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:16 PM PDT 24
Peak memory 213892 kb
Host smart-084f6439-8ade-429c-9c08-7ea37bb3f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212847607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1212847607
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3753700721
Short name T1035
Test name
Test status
Simulation time 136270283 ps
CPU time 2.33 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 209476 kb
Host smart-58100e96-289f-47d8-8164-6b95bbb908cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753700721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3753700721
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1896893510
Short name T723
Test name
Test status
Simulation time 58246206 ps
CPU time 3.02 seconds
Started Jun 01 03:04:57 PM PDT 24
Finished Jun 01 03:05:01 PM PDT 24
Peak memory 206536 kb
Host smart-0267de6f-a854-4e9c-8513-64f114ec96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896893510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1896893510
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2963272291
Short name T129
Test name
Test status
Simulation time 62055954 ps
CPU time 2.96 seconds
Started Jun 01 03:04:56 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 207608 kb
Host smart-41311c1a-c177-4fe2-8d21-0bbaa3bbc184
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963272291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2963272291
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4129196130
Short name T715
Test name
Test status
Simulation time 62857266 ps
CPU time 2.36 seconds
Started Jun 01 03:05:02 PM PDT 24
Finished Jun 01 03:05:05 PM PDT 24
Peak memory 206568 kb
Host smart-a49246d7-80bb-4236-a7ff-d4cae8224779
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129196130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4129196130
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.132618205
Short name T873
Test name
Test status
Simulation time 20823041 ps
CPU time 1.84 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:00 PM PDT 24
Peak memory 206576 kb
Host smart-aa5cd62d-642f-416a-9eae-63a3846b4296
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132618205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.132618205
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2288803340
Short name T1047
Test name
Test status
Simulation time 1171970696 ps
CPU time 6.53 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 207948 kb
Host smart-d1f091fb-d137-449a-b1f0-a13c5af4381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288803340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2288803340
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2515710453
Short name T900
Test name
Test status
Simulation time 277271718 ps
CPU time 3.08 seconds
Started Jun 01 03:04:58 PM PDT 24
Finished Jun 01 03:05:01 PM PDT 24
Peak memory 208212 kb
Host smart-78e068e2-e38d-4bb4-9a58-8bee2dd32033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515710453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2515710453
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1515513413
Short name T711
Test name
Test status
Simulation time 5613250768 ps
CPU time 38.36 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 222296 kb
Host smart-d9ae10bd-80f2-412b-80e6-58c00a791fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515513413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1515513413
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3218172228
Short name T905
Test name
Test status
Simulation time 402792448 ps
CPU time 15.1 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:21 PM PDT 24
Peak memory 222364 kb
Host smart-42dc3735-170e-4fa0-b9ef-f5113f13922d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218172228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3218172228
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3328701679
Short name T832
Test name
Test status
Simulation time 52515296 ps
CPU time 3.29 seconds
Started Jun 01 03:04:55 PM PDT 24
Finished Jun 01 03:04:59 PM PDT 24
Peak memory 207504 kb
Host smart-23d55b3e-485d-4081-9ca7-0dc000f40f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328701679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3328701679
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2773418718
Short name T69
Test name
Test status
Simulation time 1612037899 ps
CPU time 6.61 seconds
Started Jun 01 03:05:03 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 210676 kb
Host smart-4ea68e4e-7291-4926-a6af-6a1e05272ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773418718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2773418718
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.329688013
Short name T742
Test name
Test status
Simulation time 14027181 ps
CPU time 0.76 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:07 PM PDT 24
Peak memory 205528 kb
Host smart-57d7f28e-94ec-4325-b335-e2ad4f46ff60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329688013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.329688013
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1372486126
Short name T603
Test name
Test status
Simulation time 197695835 ps
CPU time 2.63 seconds
Started Jun 01 03:05:09 PM PDT 24
Finished Jun 01 03:05:12 PM PDT 24
Peak memory 218132 kb
Host smart-a94a61ae-fba9-47e2-b6d1-c80bd0763233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372486126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1372486126
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1458762341
Short name T606
Test name
Test status
Simulation time 118716336 ps
CPU time 4.36 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 219348 kb
Host smart-9d719028-e7b3-4be1-bcd4-cc5fc92aea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458762341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1458762341
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3063410362
Short name T64
Test name
Test status
Simulation time 2105152938 ps
CPU time 12.61 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 213868 kb
Host smart-20c89655-e77b-4f69-8ee4-55ad2b88118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063410362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3063410362
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.3869643136
Short name T392
Test name
Test status
Simulation time 714278422 ps
CPU time 7.83 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 214048 kb
Host smart-bbf7d9ae-db63-47c3-85b9-42492fd2c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869643136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3869643136
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2567655331
Short name T147
Test name
Test status
Simulation time 2006550208 ps
CPU time 37.36 seconds
Started Jun 01 03:05:04 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 208260 kb
Host smart-87298da5-c67e-48b9-8676-2c6748a9a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567655331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2567655331
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4181310052
Short name T860
Test name
Test status
Simulation time 68734524 ps
CPU time 3.35 seconds
Started Jun 01 03:05:04 PM PDT 24
Finished Jun 01 03:05:08 PM PDT 24
Peak memory 206520 kb
Host smart-3f695310-c73f-40be-a130-4d84bcdded12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181310052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4181310052
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.771898405
Short name T862
Test name
Test status
Simulation time 136878415 ps
CPU time 3.36 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:15 PM PDT 24
Peak memory 206564 kb
Host smart-adbf01b7-eb01-46c1-b8e7-7e222a3d807a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771898405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.771898405
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1415760955
Short name T980
Test name
Test status
Simulation time 166679665 ps
CPU time 5.97 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 208044 kb
Host smart-aa8aa415-9375-4a5d-bdb4-efec90f189ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415760955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1415760955
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1672131331
Short name T632
Test name
Test status
Simulation time 118469791 ps
CPU time 4.45 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:11 PM PDT 24
Peak memory 209688 kb
Host smart-30190a2f-6627-465c-a4a9-fa3a6e3c0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672131331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1672131331
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3836163893
Short name T587
Test name
Test status
Simulation time 143972612 ps
CPU time 3.07 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 207996 kb
Host smart-b333dd2e-d563-47e2-b374-0bbfe8e1810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836163893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3836163893
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3452937564
Short name T285
Test name
Test status
Simulation time 376787489 ps
CPU time 4.45 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 208944 kb
Host smart-ed4a0bce-ba2f-4deb-9b85-2eedb10e5578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452937564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3452937564
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3653528692
Short name T800
Test name
Test status
Simulation time 54944042 ps
CPU time 3.54 seconds
Started Jun 01 03:05:04 PM PDT 24
Finished Jun 01 03:05:08 PM PDT 24
Peak memory 214100 kb
Host smart-d09f07b5-4b8b-4b21-82ff-8a60163ae48e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653528692 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3653528692
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2627883715
Short name T261
Test name
Test status
Simulation time 252657459 ps
CPU time 4.07 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:12 PM PDT 24
Peak memory 210036 kb
Host smart-f5982faf-11e6-4b51-8197-3c31ed5c7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627883715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2627883715
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2203556084
Short name T636
Test name
Test status
Simulation time 124224887 ps
CPU time 2.08 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 209956 kb
Host smart-e75b5d5b-2790-4503-a59a-d7eb1943a531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203556084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2203556084
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.22453276
Short name T718
Test name
Test status
Simulation time 19969946 ps
CPU time 0.84 seconds
Started Jun 01 03:05:12 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 205584 kb
Host smart-f78f62d3-2e00-4b5d-933b-53b6b705df61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22453276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.22453276
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4229019438
Short name T254
Test name
Test status
Simulation time 182606293 ps
CPU time 3.86 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 214412 kb
Host smart-86a7e188-675e-42a2-8e53-7de4bf228213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229019438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4229019438
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.290744913
Short name T988
Test name
Test status
Simulation time 90359169 ps
CPU time 3.52 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:15 PM PDT 24
Peak memory 208872 kb
Host smart-d5b56917-95f4-434d-9d99-c80c688cb057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290744913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.290744913
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2280885141
Short name T410
Test name
Test status
Simulation time 497735616 ps
CPU time 7.53 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:15 PM PDT 24
Peak memory 220148 kb
Host smart-8a01624f-a2f5-48c7-8d5a-2bc557628d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280885141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2280885141
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.304324450
Short name T699
Test name
Test status
Simulation time 179172233 ps
CPU time 2.63 seconds
Started Jun 01 03:05:10 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 209460 kb
Host smart-e0adb49c-b082-4d57-ac31-d4df2694fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304324450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.304324450
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.986737947
Short name T359
Test name
Test status
Simulation time 654570687 ps
CPU time 8.21 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 208860 kb
Host smart-5c9a7630-843e-479d-80f6-858bda6f7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986737947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.986737947
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1470821536
Short name T680
Test name
Test status
Simulation time 134966423 ps
CPU time 5.54 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:12 PM PDT 24
Peak memory 208416 kb
Host smart-7defc913-4ff5-4c09-bce1-45bb0fc26331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470821536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1470821536
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.4276765777
Short name T341
Test name
Test status
Simulation time 239415394 ps
CPU time 7.03 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 208332 kb
Host smart-263d3a41-eadc-49d3-859a-7747c9e0a0ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276765777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4276765777
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1984841373
Short name T640
Test name
Test status
Simulation time 236599569 ps
CPU time 3.03 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 208580 kb
Host smart-f4f9d04b-c784-43e9-909a-e3322c271fa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984841373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1984841373
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3839066339
Short name T796
Test name
Test status
Simulation time 102431956 ps
CPU time 4.15 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:10 PM PDT 24
Peak memory 206524 kb
Host smart-363270dc-89a0-45a3-ac49-10c8b2ceda90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839066339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3839066339
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1587341317
Short name T961
Test name
Test status
Simulation time 14637245 ps
CPU time 1.27 seconds
Started Jun 01 03:05:05 PM PDT 24
Finished Jun 01 03:05:07 PM PDT 24
Peak memory 206884 kb
Host smart-50d118ff-9e29-4c25-88cf-2655d23120f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587341317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1587341317
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3896675285
Short name T801
Test name
Test status
Simulation time 39230937 ps
CPU time 2.25 seconds
Started Jun 01 03:05:06 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 206484 kb
Host smart-bc17fc01-aff1-4da2-bc2f-9533642058d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896675285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3896675285
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2012828100
Short name T256
Test name
Test status
Simulation time 824334121 ps
CPU time 19.86 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 215520 kb
Host smart-068e2174-29d9-4f7d-90d3-eb8ca71d1004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012828100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2012828100
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2670408216
Short name T247
Test name
Test status
Simulation time 459068073 ps
CPU time 14.18 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:26 PM PDT 24
Peak memory 222380 kb
Host smart-42b25491-128e-48fe-93a3-19975214935b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670408216 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2670408216
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1957491497
Short name T1050
Test name
Test status
Simulation time 81534541 ps
CPU time 4.07 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:12 PM PDT 24
Peak memory 208408 kb
Host smart-d6f5fc76-b41e-4470-b7c9-11d12fad77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957491497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1957491497
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.334494561
Short name T608
Test name
Test status
Simulation time 27935998 ps
CPU time 1.51 seconds
Started Jun 01 03:05:07 PM PDT 24
Finished Jun 01 03:05:09 PM PDT 24
Peak memory 209504 kb
Host smart-2bf7a4d5-94d1-42ea-b2d1-a631340102e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334494561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.334494561
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3178995360
Short name T102
Test name
Test status
Simulation time 71275000 ps
CPU time 0.99 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:13 PM PDT 24
Peak memory 205548 kb
Host smart-3c80939c-443f-4456-b0eb-1bb070e2e02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178995360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3178995360
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2136469411
Short name T31
Test name
Test status
Simulation time 805475494 ps
CPU time 4.8 seconds
Started Jun 01 03:05:10 PM PDT 24
Finished Jun 01 03:05:16 PM PDT 24
Peak memory 219692 kb
Host smart-f8aac622-c5f3-4c39-8517-de70a6cd9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136469411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2136469411
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3107936795
Short name T953
Test name
Test status
Simulation time 210543446 ps
CPU time 4.6 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:17 PM PDT 24
Peak memory 210160 kb
Host smart-12ac15e3-1bb5-45d6-8b18-c7a44c3301dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107936795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3107936795
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1339865797
Short name T789
Test name
Test status
Simulation time 114190004 ps
CPU time 5.13 seconds
Started Jun 01 03:05:13 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 214040 kb
Host smart-f523447d-19d7-4382-ac1d-ae67d06a8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339865797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1339865797
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2924315414
Short name T892
Test name
Test status
Simulation time 282805702 ps
CPU time 7.06 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 222112 kb
Host smart-1a21d835-ad11-4cb0-b096-62de8d722a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924315414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2924315414
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.512919123
Short name T337
Test name
Test status
Simulation time 231317016 ps
CPU time 7.15 seconds
Started Jun 01 03:05:13 PM PDT 24
Finished Jun 01 03:05:21 PM PDT 24
Peak memory 208592 kb
Host smart-b9fd0c5d-1d58-413d-b43d-49e03e71b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512919123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.512919123
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.767943585
Short name T599
Test name
Test status
Simulation time 3460363816 ps
CPU time 62.73 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 208712 kb
Host smart-d15a4c72-c776-4a86-b2bf-c83e8b3f348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767943585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.767943585
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2563573996
Short name T929
Test name
Test status
Simulation time 462285314 ps
CPU time 3.43 seconds
Started Jun 01 03:05:15 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 208484 kb
Host smart-47732388-5d6f-4fb5-9b34-4c54b8a5fd8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563573996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2563573996
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.953703605
Short name T984
Test name
Test status
Simulation time 400674272 ps
CPU time 2.31 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 206300 kb
Host smart-40130365-ddfe-488c-891b-bbb9ab2b0fae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953703605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.953703605
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3599614494
Short name T687
Test name
Test status
Simulation time 865254455 ps
CPU time 3.7 seconds
Started Jun 01 03:05:15 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 217852 kb
Host smart-18d5d1a7-385f-4598-8ecd-73642a8f26a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599614494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3599614494
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2395816877
Short name T616
Test name
Test status
Simulation time 49761310 ps
CPU time 2.22 seconds
Started Jun 01 03:05:12 PM PDT 24
Finished Jun 01 03:05:15 PM PDT 24
Peak memory 206564 kb
Host smart-83bb11aa-2035-4f79-80b1-f87609ea070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395816877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2395816877
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1562215917
Short name T957
Test name
Test status
Simulation time 474507221 ps
CPU time 13.78 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 221396 kb
Host smart-af583f9b-6a38-4556-848c-6e7bd28ab654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562215917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1562215917
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2269969495
Short name T427
Test name
Test status
Simulation time 204253171 ps
CPU time 4.48 seconds
Started Jun 01 03:05:13 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 222256 kb
Host smart-3106064c-6d74-425c-bb69-a936cf44f4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269969495 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2269969495
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1073216771
Short name T1002
Test name
Test status
Simulation time 425460175 ps
CPU time 10.89 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 214024 kb
Host smart-92ba32c2-dd7d-46d2-b4bb-21e16bc56e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073216771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1073216771
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1403265451
Short name T858
Test name
Test status
Simulation time 257233218 ps
CPU time 2.09 seconds
Started Jun 01 03:05:15 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 209900 kb
Host smart-6d209ad2-1d5d-4d88-82f4-9d64e77d4271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403265451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1403265451
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1032279201
Short name T962
Test name
Test status
Simulation time 106436135 ps
CPU time 1.06 seconds
Started Jun 01 03:05:21 PM PDT 24
Finished Jun 01 03:05:22 PM PDT 24
Peak memory 205920 kb
Host smart-a9e1a4aa-c8b1-4bc5-8763-abc6cade2f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032279201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1032279201
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3736289709
Short name T288
Test name
Test status
Simulation time 93980838 ps
CPU time 3.43 seconds
Started Jun 01 03:05:21 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 214960 kb
Host smart-692e3382-4e41-471f-a668-d00a3cab8b20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736289709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3736289709
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2109833537
Short name T34
Test name
Test status
Simulation time 551013933 ps
CPU time 4.89 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 210100 kb
Host smart-e1795a17-9375-46c0-8bbc-f06761720a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109833537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2109833537
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4055049637
Short name T1011
Test name
Test status
Simulation time 239550908 ps
CPU time 3.18 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 210168 kb
Host smart-1e5b40d1-72b8-459a-9cb6-0d30cd4795b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055049637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4055049637
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1058036764
Short name T313
Test name
Test status
Simulation time 83714128 ps
CPU time 4.47 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:24 PM PDT 24
Peak memory 208980 kb
Host smart-38d035b5-1d5e-44cb-b863-84076fae6326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058036764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1058036764
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3927924776
Short name T307
Test name
Test status
Simulation time 1491259871 ps
CPU time 17.09 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:36 PM PDT 24
Peak memory 222096 kb
Host smart-0a9438b6-6cfd-4e6f-97c0-f02323d2ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927924776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3927924776
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.180398151
Short name T676
Test name
Test status
Simulation time 217154172 ps
CPU time 2.46 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:22 PM PDT 24
Peak memory 213972 kb
Host smart-34ac8042-6b77-46cc-b4f0-ef6e6a06f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180398151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.180398151
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3400982718
Short name T315
Test name
Test status
Simulation time 206633735 ps
CPU time 4.94 seconds
Started Jun 01 03:05:13 PM PDT 24
Finished Jun 01 03:05:19 PM PDT 24
Peak memory 218140 kb
Host smart-934e0df8-a01e-4bd2-9655-235dfbb9a249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400982718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3400982718
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1040208045
Short name T898
Test name
Test status
Simulation time 45962248 ps
CPU time 2.11 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:22 PM PDT 24
Peak memory 208144 kb
Host smart-93aeb952-2ee3-46d7-9465-270b1994492a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040208045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1040208045
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2898769462
Short name T925
Test name
Test status
Simulation time 271755648 ps
CPU time 3.02 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 206560 kb
Host smart-d92d01bf-f6a4-405d-8169-5dba4748dce7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898769462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2898769462
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4217512538
Short name T223
Test name
Test status
Simulation time 170330186 ps
CPU time 5.47 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:05:18 PM PDT 24
Peak memory 207708 kb
Host smart-e807818b-8364-48eb-a4fd-970a19a240ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217512538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4217512538
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.569074077
Short name T882
Test name
Test status
Simulation time 11882157851 ps
CPU time 83.25 seconds
Started Jun 01 03:05:11 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 208204 kb
Host smart-cc50c9f5-e704-4d23-8f60-04b7d0b3f9ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569074077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.569074077
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1958103947
Short name T651
Test name
Test status
Simulation time 171699120 ps
CPU time 3.25 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 207248 kb
Host smart-2c5c7c9d-d287-4b73-ba9b-3ea694f4e412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958103947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1958103947
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4201622274
Short name T136
Test name
Test status
Simulation time 1761817620 ps
CPU time 7.69 seconds
Started Jun 01 03:05:13 PM PDT 24
Finished Jun 01 03:05:22 PM PDT 24
Peak memory 206452 kb
Host smart-8c5f729f-996f-44dc-824b-4959e9cf85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201622274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4201622274
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1604218842
Short name T806
Test name
Test status
Simulation time 74472777 ps
CPU time 4.19 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:24 PM PDT 24
Peak memory 214836 kb
Host smart-8c37c2bb-c3a7-49c9-b9b7-d3e10771fd77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604218842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1604218842
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.131063407
Short name T840
Test name
Test status
Simulation time 337047908 ps
CPU time 3.45 seconds
Started Jun 01 03:05:21 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 222424 kb
Host smart-6d52a7e5-e30a-4156-8346-6702c326ba2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131063407 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.131063407
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3405514754
Short name T291
Test name
Test status
Simulation time 129008225 ps
CPU time 5.75 seconds
Started Jun 01 03:05:18 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 209808 kb
Host smart-5dfdf233-905b-4e12-b9ab-67c2fb849a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405514754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3405514754
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4734195
Short name T914
Test name
Test status
Simulation time 464091589 ps
CPU time 2.77 seconds
Started Jun 01 03:05:20 PM PDT 24
Finished Jun 01 03:05:23 PM PDT 24
Peak memory 210500 kb
Host smart-b1a5a935-446d-4051-ae6e-7d7bd2db63d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4734195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4734195
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1531212130
Short name T971
Test name
Test status
Simulation time 22690538 ps
CPU time 0.91 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:28 PM PDT 24
Peak memory 205508 kb
Host smart-2e5caa72-f5fe-42c6-869b-038c88a0828c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531212130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1531212130
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2597045089
Short name T449
Test name
Test status
Simulation time 64944045 ps
CPU time 4.43 seconds
Started Jun 01 03:05:26 PM PDT 24
Finished Jun 01 03:05:31 PM PDT 24
Peak memory 215080 kb
Host smart-b56a147f-055e-41e8-87de-a509896bb158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597045089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2597045089
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3361355457
Short name T713
Test name
Test status
Simulation time 1025852446 ps
CPU time 5.83 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:33 PM PDT 24
Peak memory 209496 kb
Host smart-a609ce6f-2707-4446-8f58-283bfafbe05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361355457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3361355457
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1811764404
Short name T1019
Test name
Test status
Simulation time 1365634127 ps
CPU time 12.67 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:41 PM PDT 24
Peak memory 220004 kb
Host smart-67e42e90-3ef5-4270-837d-ddd2d0c7357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811764404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1811764404
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1791266799
Short name T993
Test name
Test status
Simulation time 138941568 ps
CPU time 5.8 seconds
Started Jun 01 03:05:28 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 219836 kb
Host smart-fcc92d1a-4786-4164-8e3a-d8316c085f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791266799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1791266799
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2995674305
Short name T397
Test name
Test status
Simulation time 325830431 ps
CPU time 10.04 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:38 PM PDT 24
Peak memory 207800 kb
Host smart-57bc91a4-ed0a-4f94-8c0d-9a1d7c43b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995674305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2995674305
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1929984840
Short name T418
Test name
Test status
Simulation time 177056650 ps
CPU time 2.54 seconds
Started Jun 01 03:05:22 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 208108 kb
Host smart-93f72268-ba14-442b-954a-2972d9a18417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929984840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1929984840
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3868049866
Short name T887
Test name
Test status
Simulation time 937799563 ps
CPU time 6.48 seconds
Started Jun 01 03:05:20 PM PDT 24
Finished Jun 01 03:05:27 PM PDT 24
Peak memory 207504 kb
Host smart-970f5b70-2384-43e2-9c72-85474a4e47e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868049866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3868049866
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.699286673
Short name T393
Test name
Test status
Simulation time 11177653536 ps
CPU time 26.79 seconds
Started Jun 01 03:05:19 PM PDT 24
Finished Jun 01 03:05:47 PM PDT 24
Peak memory 207864 kb
Host smart-642c8d46-895f-4f75-92f4-04a0612cefc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699286673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.699286673
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1021643065
Short name T735
Test name
Test status
Simulation time 394670115 ps
CPU time 5.46 seconds
Started Jun 01 03:05:28 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 207624 kb
Host smart-05346181-0f91-49fa-9bb5-0606cdac3336
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021643065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1021643065
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2532348029
Short name T339
Test name
Test status
Simulation time 55012125 ps
CPU time 2.97 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:30 PM PDT 24
Peak memory 215528 kb
Host smart-c9202424-4007-4f21-96c3-bc2d8ab674ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532348029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2532348029
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3102878889
Short name T975
Test name
Test status
Simulation time 1350313682 ps
CPU time 6.65 seconds
Started Jun 01 03:05:18 PM PDT 24
Finished Jun 01 03:05:25 PM PDT 24
Peak memory 207580 kb
Host smart-a8e4a6fe-665a-4d79-bf62-1d8540e1043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102878889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3102878889
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.274036394
Short name T280
Test name
Test status
Simulation time 6741541671 ps
CPU time 56.78 seconds
Started Jun 01 03:05:26 PM PDT 24
Finished Jun 01 03:06:23 PM PDT 24
Peak memory 215792 kb
Host smart-939abaf7-1b64-48a5-857b-968024606330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274036394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.274036394
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1479405952
Short name T589
Test name
Test status
Simulation time 279787927 ps
CPU time 4.87 seconds
Started Jun 01 03:05:29 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 222408 kb
Host smart-4903ef49-f00d-4a00-8065-8dfe37cb9b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479405952 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1479405952
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2999021784
Short name T268
Test name
Test status
Simulation time 872350872 ps
CPU time 6.03 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:34 PM PDT 24
Peak memory 214020 kb
Host smart-dacec37e-6da8-43c2-ad31-594682fbf8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999021784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2999021784
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.831896199
Short name T730
Test name
Test status
Simulation time 69427515 ps
CPU time 2.47 seconds
Started Jun 01 03:05:27 PM PDT 24
Finished Jun 01 03:05:30 PM PDT 24
Peak memory 209488 kb
Host smart-d0f01c08-f0a8-4908-9f7b-35c2096dfd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831896199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.831896199
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2173795998
Short name T628
Test name
Test status
Simulation time 12402023 ps
CPU time 0.78 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 205384 kb
Host smart-60b19f65-e20a-49df-b2f6-2fb23f39ba31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173795998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2173795998
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2607629413
Short name T36
Test name
Test status
Simulation time 124344198 ps
CPU time 3.65 seconds
Started Jun 01 03:03:14 PM PDT 24
Finished Jun 01 03:03:18 PM PDT 24
Peak memory 209660 kb
Host smart-64ccc236-7988-4261-ba55-939602e3354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607629413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2607629413
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.152688160
Short name T83
Test name
Test status
Simulation time 302859801 ps
CPU time 7.23 seconds
Started Jun 01 03:03:13 PM PDT 24
Finished Jun 01 03:03:20 PM PDT 24
Peak memory 208476 kb
Host smart-77cce36a-641b-47e4-84aa-f05961b8309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152688160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.152688160
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2102938738
Short name T354
Test name
Test status
Simulation time 254771459 ps
CPU time 3.64 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:19 PM PDT 24
Peak memory 213892 kb
Host smart-7b90d71a-2533-4796-ad22-0858fc18fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102938738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2102938738
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3661627061
Short name T937
Test name
Test status
Simulation time 1501998188 ps
CPU time 34.65 seconds
Started Jun 01 03:03:14 PM PDT 24
Finished Jun 01 03:03:49 PM PDT 24
Peak memory 207704 kb
Host smart-630920d5-d29f-4a91-b3cc-ee3cad970de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661627061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3661627061
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2707029012
Short name T106
Test name
Test status
Simulation time 2775445832 ps
CPU time 17.93 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:33 PM PDT 24
Peak memory 238020 kb
Host smart-2bca2908-914f-458c-811b-f721f0f4399b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707029012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2707029012
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4027386403
Short name T302
Test name
Test status
Simulation time 185620622 ps
CPU time 4.26 seconds
Started Jun 01 03:03:13 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 208180 kb
Host smart-651d5915-53e3-4532-95f9-b4acc96e8d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027386403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4027386403
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3037549008
Short name T982
Test name
Test status
Simulation time 168980480 ps
CPU time 3.29 seconds
Started Jun 01 03:03:18 PM PDT 24
Finished Jun 01 03:03:22 PM PDT 24
Peak memory 206316 kb
Host smart-e16ede02-4e70-45a1-b210-d949bc6d95d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037549008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3037549008
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2224292866
Short name T430
Test name
Test status
Simulation time 231627169 ps
CPU time 7.57 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:23 PM PDT 24
Peak memory 208212 kb
Host smart-2d7bf0e6-e478-4314-96bc-4b6612b9c9be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224292866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2224292866
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.741081105
Short name T1015
Test name
Test status
Simulation time 96434724 ps
CPU time 2.52 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:19 PM PDT 24
Peak memory 206392 kb
Host smart-3577f24c-add8-448e-8814-e190ef2d02a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741081105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.741081105
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1754538766
Short name T954
Test name
Test status
Simulation time 2226091149 ps
CPU time 11.08 seconds
Started Jun 01 03:03:13 PM PDT 24
Finished Jun 01 03:03:24 PM PDT 24
Peak memory 209708 kb
Host smart-b4047eee-1d86-4be0-8741-b817c68d74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754538766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1754538766
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.880555102
Short name T820
Test name
Test status
Simulation time 2886999086 ps
CPU time 16.6 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 208064 kb
Host smart-0d830ea4-182d-407e-a08f-f873311a6632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880555102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.880555102
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3668870715
Short name T334
Test name
Test status
Simulation time 358737377 ps
CPU time 5.1 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:20 PM PDT 24
Peak memory 215776 kb
Host smart-adfc0fab-dd26-49c2-aff4-eda7e1054b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668870715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3668870715
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.672835002
Short name T229
Test name
Test status
Simulation time 1405102756 ps
CPU time 3.79 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:19 PM PDT 24
Peak memory 219564 kb
Host smart-3402c3bc-1462-4436-b4bb-85d35fc25704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672835002 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.672835002
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3901912744
Short name T997
Test name
Test status
Simulation time 129066240 ps
CPU time 2.5 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:18 PM PDT 24
Peak memory 207096 kb
Host smart-09bd424c-eb04-4fe0-90ae-5595e9b84a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901912744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3901912744
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.642619233
Short name T836
Test name
Test status
Simulation time 31131997 ps
CPU time 2.13 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:17 PM PDT 24
Peak memory 209888 kb
Host smart-e4d7bebe-1e1b-41b8-91b4-26791f378e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642619233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.642619233
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.641711009
Short name T731
Test name
Test status
Simulation time 67211592 ps
CPU time 0.95 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:36 PM PDT 24
Peak memory 205456 kb
Host smart-43862616-76dc-4b64-8436-fcc1c30b6aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641711009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.641711009
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.172605795
Short name T442
Test name
Test status
Simulation time 324566953 ps
CPU time 3.65 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:38 PM PDT 24
Peak memory 214820 kb
Host smart-aef9df7b-acfb-4c9a-8538-ae8c3af38a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172605795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.172605795
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3517655311
Short name T62
Test name
Test status
Simulation time 2827300536 ps
CPU time 10.19 seconds
Started Jun 01 03:05:33 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 209348 kb
Host smart-685aca20-c030-4913-ac80-c87c1d8894cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517655311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3517655311
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1670038683
Short name T412
Test name
Test status
Simulation time 322894282 ps
CPU time 9.32 seconds
Started Jun 01 03:05:33 PM PDT 24
Finished Jun 01 03:05:43 PM PDT 24
Peak memory 208916 kb
Host smart-5eb18544-01f5-49a9-96c5-2117f8208295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670038683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1670038683
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3816608689
Short name T98
Test name
Test status
Simulation time 2216591611 ps
CPU time 30.24 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 214376 kb
Host smart-56e1d31f-16d4-46f8-9e02-0873e4dab212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816608689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3816608689
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2564532186
Short name T752
Test name
Test status
Simulation time 58272019 ps
CPU time 3.35 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 215080 kb
Host smart-8e285d60-1227-402d-99f8-1336afb41d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564532186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2564532186
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.273043040
Short name T362
Test name
Test status
Simulation time 44490253 ps
CPU time 2.97 seconds
Started Jun 01 03:05:35 PM PDT 24
Finished Jun 01 03:05:38 PM PDT 24
Peak memory 218132 kb
Host smart-99a71c53-49ae-47a8-a728-e83b5abda6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273043040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.273043040
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1581606371
Short name T624
Test name
Test status
Simulation time 225204400 ps
CPU time 2.94 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 206452 kb
Host smart-f76faa47-6935-406d-a83c-803ac162e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581606371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1581606371
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.421281083
Short name T1009
Test name
Test status
Simulation time 182012926 ps
CPU time 2.8 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 206540 kb
Host smart-464ba1f1-3409-4f9a-b8ac-ece721e1bcc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421281083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.421281083
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2173767428
Short name T290
Test name
Test status
Simulation time 1031472684 ps
CPU time 26.37 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:06:03 PM PDT 24
Peak memory 208304 kb
Host smart-246fc698-68e8-439f-a0a5-427f4e4a3d3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173767428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2173767428
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.718575441
Short name T347
Test name
Test status
Simulation time 97530923 ps
CPU time 3.78 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 208112 kb
Host smart-baaf7fb3-e9f8-4c12-8e71-6339fa4eda04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718575441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.718575441
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.618715716
Short name T1061
Test name
Test status
Simulation time 121680702 ps
CPU time 2.04 seconds
Started Jun 01 03:05:38 PM PDT 24
Finished Jun 01 03:05:41 PM PDT 24
Peak memory 215284 kb
Host smart-1ec15339-8dd3-4828-9801-3e6222edaa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618715716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.618715716
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1349022474
Short name T622
Test name
Test status
Simulation time 44835064 ps
CPU time 2.48 seconds
Started Jun 01 03:05:26 PM PDT 24
Finished Jun 01 03:05:29 PM PDT 24
Peak memory 206752 kb
Host smart-6cc30934-141e-4761-a7c5-7716c3e2e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349022474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1349022474
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2006372025
Short name T822
Test name
Test status
Simulation time 314476122 ps
CPU time 11.39 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 207664 kb
Host smart-a838002b-1666-4470-831c-931225bac51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006372025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2006372025
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1789267693
Short name T1045
Test name
Test status
Simulation time 243729872 ps
CPU time 2.27 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 214112 kb
Host smart-ff1cde07-04a1-42cf-afec-2f371765af08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789267693 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1789267693
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.168562270
Short name T369
Test name
Test status
Simulation time 84199223 ps
CPU time 3.18 seconds
Started Jun 01 03:05:33 PM PDT 24
Finished Jun 01 03:05:37 PM PDT 24
Peak memory 207472 kb
Host smart-f9ddc92b-3a26-40e5-a061-9f986a48f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168562270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.168562270
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4149857843
Short name T232
Test name
Test status
Simulation time 942808958 ps
CPU time 3.07 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 209952 kb
Host smart-17fefb03-fbbb-4203-8843-378114bc590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149857843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4149857843
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1589316831
Short name T970
Test name
Test status
Simulation time 44644183 ps
CPU time 0.76 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:37 PM PDT 24
Peak memory 205596 kb
Host smart-f52560cd-db25-4c81-bbb0-01bf89c4bdc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589316831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1589316831
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.457398083
Short name T205
Test name
Test status
Simulation time 463458159 ps
CPU time 3.51 seconds
Started Jun 01 03:05:35 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 218092 kb
Host smart-ce14e9b3-5e52-45fd-b8e6-c81338fad19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457398083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.457398083
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2873039541
Short name T959
Test name
Test status
Simulation time 61540896 ps
CPU time 3.37 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 218460 kb
Host smart-93abcf7e-be14-4804-a9fd-0e8068bdfc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873039541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2873039541
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.941999911
Short name T308
Test name
Test status
Simulation time 88204679 ps
CPU time 4.15 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:41 PM PDT 24
Peak memory 213976 kb
Host smart-2e32eaa5-b4fd-435e-ad9b-79a93929ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941999911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.941999911
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.121268655
Short name T246
Test name
Test status
Simulation time 1168845246 ps
CPU time 10.89 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:47 PM PDT 24
Peak memory 218020 kb
Host smart-6abc2ed4-1097-4b19-a99c-7e30ee43b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121268655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.121268655
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3076812385
Short name T903
Test name
Test status
Simulation time 220552604 ps
CPU time 8.7 seconds
Started Jun 01 03:05:35 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 213972 kb
Host smart-8dc67471-0840-49e3-a530-f6dc97ff69b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076812385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3076812385
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2349037254
Short name T653
Test name
Test status
Simulation time 32232023 ps
CPU time 2.22 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:36 PM PDT 24
Peak memory 206504 kb
Host smart-4c579c24-a1db-4485-bc72-0d6cada12493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349037254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2349037254
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3600294836
Short name T1025
Test name
Test status
Simulation time 315769161 ps
CPU time 5.19 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:39 PM PDT 24
Peak memory 208364 kb
Host smart-efce2c4d-e69c-43f4-b21e-5d37428d3a97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600294836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3600294836
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.971731380
Short name T798
Test name
Test status
Simulation time 540351643 ps
CPU time 4.31 seconds
Started Jun 01 03:05:37 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 206820 kb
Host smart-74e3734b-e829-475a-b524-7fa76c989b89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971731380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.971731380
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.318948451
Short name T601
Test name
Test status
Simulation time 174492177 ps
CPU time 5.24 seconds
Started Jun 01 03:05:37 PM PDT 24
Finished Jun 01 03:05:43 PM PDT 24
Peak memory 208084 kb
Host smart-d680ad5f-13ec-44e5-b520-7e6b672a8e7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318948451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.318948451
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2422990469
Short name T274
Test name
Test status
Simulation time 96785423 ps
CPU time 2.07 seconds
Started Jun 01 03:05:40 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 209660 kb
Host smart-bf7ca011-861d-4f54-b0a1-20494b539a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422990469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2422990469
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2161934514
Short name T763
Test name
Test status
Simulation time 120933192 ps
CPU time 3.48 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:38 PM PDT 24
Peak memory 207816 kb
Host smart-b4bc3065-41b1-4292-ad31-5f67705d459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161934514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2161934514
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2898594384
Short name T950
Test name
Test status
Simulation time 1759797514 ps
CPU time 28.07 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:06:07 PM PDT 24
Peak memory 207572 kb
Host smart-69233c55-b809-46be-8be8-d9fa9509dba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898594384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2898594384
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3705800857
Short name T235
Test name
Test status
Simulation time 806228642 ps
CPU time 7.79 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:45 PM PDT 24
Peak memory 222356 kb
Host smart-c05c1e3b-ca8b-4671-bdf3-6a57d563fe3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705800857 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3705800857
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3458465488
Short name T310
Test name
Test status
Simulation time 1793865936 ps
CPU time 7.07 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:43 PM PDT 24
Peak memory 217888 kb
Host smart-d5e44863-bd36-4172-9480-f9daf31167db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458465488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3458465488
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2228229642
Short name T818
Test name
Test status
Simulation time 58996904 ps
CPU time 1.41 seconds
Started Jun 01 03:05:34 PM PDT 24
Finished Jun 01 03:05:36 PM PDT 24
Peak memory 209504 kb
Host smart-c6746314-76aa-4012-a8d3-b1e533088a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228229642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2228229642
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3566606616
Short name T991
Test name
Test status
Simulation time 20335674 ps
CPU time 0.75 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 205668 kb
Host smart-6b258d3e-840e-405e-822a-7bb008711ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566606616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3566606616
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3642915856
Short name T977
Test name
Test status
Simulation time 617821274 ps
CPU time 3.97 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:47 PM PDT 24
Peak memory 209656 kb
Host smart-56d1f3b9-dcc7-4fe9-85fd-faae5ba72356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642915856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3642915856
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1142815366
Short name T935
Test name
Test status
Simulation time 62447188 ps
CPU time 2.94 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:05:42 PM PDT 24
Peak memory 208520 kb
Host smart-5594ea26-2d58-4732-bc0c-87f659854e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142815366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1142815366
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1646439909
Short name T97
Test name
Test status
Simulation time 303508841 ps
CPU time 4.22 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:47 PM PDT 24
Peak memory 211244 kb
Host smart-c38348fc-af53-4c53-ae3b-f57a056827ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646439909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1646439909
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2944888840
Short name T59
Test name
Test status
Simulation time 81020577 ps
CPU time 3.52 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:41 PM PDT 24
Peak memory 219860 kb
Host smart-510731cb-0bea-4ebe-96c4-2bcdf1f659e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944888840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2944888840
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1960037560
Short name T596
Test name
Test status
Simulation time 92182147 ps
CPU time 3.06 seconds
Started Jun 01 03:05:33 PM PDT 24
Finished Jun 01 03:05:36 PM PDT 24
Peak memory 207908 kb
Host smart-6effa61f-1ba0-4b01-92df-cf0ea4427b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960037560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1960037560
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2889040726
Short name T615
Test name
Test status
Simulation time 87085600 ps
CPU time 3.48 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 206532 kb
Host smart-4f4624d2-6d1a-4be0-9569-fa325429c1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889040726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2889040726
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.228076379
Short name T943
Test name
Test status
Simulation time 653841231 ps
CPU time 7.7 seconds
Started Jun 01 03:05:39 PM PDT 24
Finished Jun 01 03:05:47 PM PDT 24
Peak memory 208740 kb
Host smart-4b7a607c-386b-4664-a830-db1808e948aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228076379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.228076379
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1729421260
Short name T714
Test name
Test status
Simulation time 268885790 ps
CPU time 3.42 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:40 PM PDT 24
Peak memory 208164 kb
Host smart-64e6dcf7-19a7-433e-b807-405ccf6db536
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729421260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1729421260
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1836436942
Short name T933
Test name
Test status
Simulation time 201092224 ps
CPU time 2.75 seconds
Started Jun 01 03:05:35 PM PDT 24
Finished Jun 01 03:05:38 PM PDT 24
Peak memory 206664 kb
Host smart-6fd9b639-9393-4c16-9de2-96992eece04f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836436942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1836436942
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1028097497
Short name T289
Test name
Test status
Simulation time 100785746 ps
CPU time 3.65 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 213996 kb
Host smart-4d12120d-ec8e-456a-9075-3055d8df1081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028097497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1028097497
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2171184700
Short name T658
Test name
Test status
Simulation time 151646340 ps
CPU time 3.69 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:41 PM PDT 24
Peak memory 207512 kb
Host smart-84b29c54-3e66-4c64-8a7a-0712ebc24de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171184700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2171184700
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.237399864
Short name T643
Test name
Test status
Simulation time 252624468 ps
CPU time 4.4 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:05:49 PM PDT 24
Peak memory 222396 kb
Host smart-f72f2838-540e-4b4c-a635-a58c4ed15146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237399864 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.237399864
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2795379096
Short name T1058
Test name
Test status
Simulation time 413780701 ps
CPU time 11.97 seconds
Started Jun 01 03:05:36 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 208196 kb
Host smart-8e3bf815-eab3-49ef-956c-30f96b206a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795379096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2795379096
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3686202641
Short name T805
Test name
Test status
Simulation time 80951444 ps
CPU time 1.63 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:43 PM PDT 24
Peak memory 208300 kb
Host smart-3af51777-b01a-4290-93ac-b5fcaf696ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686202641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3686202641
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.371708566
Short name T607
Test name
Test status
Simulation time 40667352 ps
CPU time 0.76 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 205572 kb
Host smart-c66857a5-3407-4227-bf6a-24f628ed36ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371708566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.371708566
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1050609990
Short name T33
Test name
Test status
Simulation time 90891542 ps
CPU time 3.53 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 216672 kb
Host smart-15650227-fab4-4487-81ee-06f014efb0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050609990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1050609990
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2103539559
Short name T810
Test name
Test status
Simulation time 147284753 ps
CPU time 3.02 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 213952 kb
Host smart-5d70be97-356b-4ba2-b369-b5567890cd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103539559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2103539559
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2882257870
Short name T897
Test name
Test status
Simulation time 192523224 ps
CPU time 4.52 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 208796 kb
Host smart-30161c5f-2aa0-40e8-b889-dee2ef6c7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882257870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2882257870
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1167122678
Short name T597
Test name
Test status
Simulation time 316466762 ps
CPU time 2.32 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 219144 kb
Host smart-7f0f337c-0394-4d1b-b893-f789c27c167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167122678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1167122678
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1681378761
Short name T145
Test name
Test status
Simulation time 58756287 ps
CPU time 3.79 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 218112 kb
Host smart-3435f085-7630-440e-b46a-d42f74543a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681378761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1681378761
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3876773686
Short name T788
Test name
Test status
Simulation time 83667044 ps
CPU time 1.83 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:43 PM PDT 24
Peak memory 206224 kb
Host smart-fa7e6964-2b12-46fe-a475-02d7c071441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876773686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3876773686
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4217238486
Short name T864
Test name
Test status
Simulation time 516275601 ps
CPU time 7.9 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 207592 kb
Host smart-bc8eaf91-aa7a-4c56-8cb5-f0e656e04af3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217238486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4217238486
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4178952276
Short name T17
Test name
Test status
Simulation time 153760111 ps
CPU time 2.24 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:44 PM PDT 24
Peak memory 206512 kb
Host smart-87527790-94fc-4a0d-b652-26b3c9b773fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178952276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4178952276
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1173460776
Short name T1049
Test name
Test status
Simulation time 742389753 ps
CPU time 8.55 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:50 PM PDT 24
Peak memory 207800 kb
Host smart-1a1b0dac-b5a2-4848-934f-70ce95e719d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173460776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1173460776
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4123184990
Short name T737
Test name
Test status
Simulation time 46940291 ps
CPU time 2.27 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:45 PM PDT 24
Peak memory 208072 kb
Host smart-f03f0c9f-2e2f-49a5-ab11-3b3a0d06ed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123184990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4123184990
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.465938352
Short name T1059
Test name
Test status
Simulation time 122763317 ps
CPU time 2.23 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:45 PM PDT 24
Peak memory 206364 kb
Host smart-c0422c44-de34-4757-a4e3-b0063d7ee4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465938352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.465938352
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3517953113
Short name T358
Test name
Test status
Simulation time 4076881002 ps
CPU time 34.65 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:06:17 PM PDT 24
Peak memory 222272 kb
Host smart-8b90f8d3-d11d-4c0e-ad3b-0dc7ea4db611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517953113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3517953113
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.742954131
Short name T682
Test name
Test status
Simulation time 714439651 ps
CPU time 6.97 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:49 PM PDT 24
Peak memory 222336 kb
Host smart-fced7a12-a4d3-4730-bd8f-806512a5fce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742954131 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.742954131
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3203132573
Short name T710
Test name
Test status
Simulation time 232746615 ps
CPU time 8.67 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:52 PM PDT 24
Peak memory 208084 kb
Host smart-c2d3b0b5-55f6-4880-965b-b2964a15f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203132573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3203132573
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1715984412
Short name T686
Test name
Test status
Simulation time 1111982103 ps
CPU time 14.3 seconds
Started Jun 01 03:05:45 PM PDT 24
Finished Jun 01 03:05:59 PM PDT 24
Peak memory 210436 kb
Host smart-f65c73fd-cc4e-4949-a39e-8f3b132afdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715984412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1715984412
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.725794408
Short name T995
Test name
Test status
Simulation time 30766481 ps
CPU time 0.79 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 205556 kb
Host smart-d826be34-2a9e-4099-bd62-5ee2b35b91a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725794408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.725794408
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2605685408
Short name T438
Test name
Test status
Simulation time 93336408 ps
CPU time 2.95 seconds
Started Jun 01 03:05:43 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 215148 kb
Host smart-c2e71e71-eb6f-4e99-870b-0383bdcc43e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605685408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2605685408
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3751462486
Short name T872
Test name
Test status
Simulation time 538964625 ps
CPU time 10.79 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:06:03 PM PDT 24
Peak memory 222464 kb
Host smart-95cbf246-0c91-4232-96be-e336f98031d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751462486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3751462486
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2464473902
Short name T75
Test name
Test status
Simulation time 181639261 ps
CPU time 5.98 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 207228 kb
Host smart-b89275be-ddde-4562-b97d-9cd75beee951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464473902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2464473902
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2432486738
Short name T88
Test name
Test status
Simulation time 8549068868 ps
CPU time 58.77 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 214324 kb
Host smart-d4d71c6f-0218-4bc1-8042-22f5cb81b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432486738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2432486738
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.21803249
Short name T265
Test name
Test status
Simulation time 333566581 ps
CPU time 4.85 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:56 PM PDT 24
Peak memory 210708 kb
Host smart-c8cb8faa-e436-4ae6-ade2-3b3a21efb54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21803249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.21803249
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2309911837
Short name T734
Test name
Test status
Simulation time 108714502 ps
CPU time 3.33 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:56 PM PDT 24
Peak memory 215844 kb
Host smart-71f10c08-8c82-4cc4-9008-10cfdb3110f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309911837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2309911837
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.301623691
Short name T447
Test name
Test status
Simulation time 2768661348 ps
CPU time 8.66 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 214104 kb
Host smart-ed9bad94-8c17-423a-a864-c9822ab1f6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301623691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.301623691
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4009014623
Short name T225
Test name
Test status
Simulation time 35796843 ps
CPU time 2.52 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:45 PM PDT 24
Peak memory 208164 kb
Host smart-65402afd-0827-45c9-9ab0-cc3a0e03aedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009014623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4009014623
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1127576700
Short name T856
Test name
Test status
Simulation time 210854919 ps
CPU time 3.93 seconds
Started Jun 01 03:05:44 PM PDT 24
Finished Jun 01 03:05:48 PM PDT 24
Peak memory 208560 kb
Host smart-c6c4d5bc-f18b-4488-9cef-8d66f0260fc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127576700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1127576700
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3074943522
Short name T777
Test name
Test status
Simulation time 271230781 ps
CPU time 7.33 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:49 PM PDT 24
Peak memory 207604 kb
Host smart-cd37e72f-c3bf-4714-86df-ed74f4b37ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074943522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3074943522
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3175743680
Short name T141
Test name
Test status
Simulation time 69569584 ps
CPU time 3.4 seconds
Started Jun 01 03:05:42 PM PDT 24
Finished Jun 01 03:05:46 PM PDT 24
Peak memory 208248 kb
Host smart-c2206485-ddd3-43a3-b8c2-b7e9b5c4de60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175743680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3175743680
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3500850269
Short name T609
Test name
Test status
Simulation time 25944449 ps
CPU time 1.66 seconds
Started Jun 01 03:05:49 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 206868 kb
Host smart-550a3a23-65c8-44d2-98a4-12c6e25854ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500850269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3500850269
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1628145548
Short name T569
Test name
Test status
Simulation time 988680225 ps
CPU time 17.03 seconds
Started Jun 01 03:05:41 PM PDT 24
Finished Jun 01 03:05:59 PM PDT 24
Peak memory 207908 kb
Host smart-abdeb35a-821b-4209-9f59-6bd8d38eb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628145548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1628145548
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4186401698
Short name T80
Test name
Test status
Simulation time 270054783 ps
CPU time 11.86 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:06:03 PM PDT 24
Peak memory 222032 kb
Host smart-011926d8-9078-4893-b961-e3f8b791ca6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186401698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4186401698
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3215835002
Short name T828
Test name
Test status
Simulation time 2140393496 ps
CPU time 8.49 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 222272 kb
Host smart-49cedba8-2f33-4a21-8fc9-29f205da5a8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215835002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3215835002
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2228294472
Short name T417
Test name
Test status
Simulation time 114784698 ps
CPU time 5.64 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:56 PM PDT 24
Peak memory 214004 kb
Host smart-60218077-e52e-4230-a527-a3956b48925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228294472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2228294472
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2933611743
Short name T420
Test name
Test status
Simulation time 141500353 ps
CPU time 3.24 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:05:54 PM PDT 24
Peak memory 209564 kb
Host smart-dd78075f-4f4f-4f78-a6d2-a08826eb140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933611743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2933611743
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1123299263
Short name T813
Test name
Test status
Simulation time 13183410 ps
CPU time 0.74 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:51 PM PDT 24
Peak memory 205548 kb
Host smart-776c2c4c-dc8d-4b2c-855f-033e735d53fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123299263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1123299263
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2622097345
Short name T374
Test name
Test status
Simulation time 483244479 ps
CPU time 4.21 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 214020 kb
Host smart-abb29ea9-4b7c-47ac-9284-492fd9d700e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622097345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2622097345
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3852661481
Short name T766
Test name
Test status
Simulation time 1374967030 ps
CPU time 30.08 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:06:21 PM PDT 24
Peak memory 222176 kb
Host smart-d11cacb6-1661-4252-b58d-bf0745f3e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852661481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3852661481
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3980284806
Short name T19
Test name
Test status
Simulation time 347444871 ps
CPU time 5.63 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 214032 kb
Host smart-9d2c2b56-57a4-46b7-890b-9421ac13bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980284806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3980284806
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3273197855
Short name T385
Test name
Test status
Simulation time 304405451 ps
CPU time 5.08 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 214048 kb
Host smart-f75ceac5-2c5a-457b-81d4-856fa80ae682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273197855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3273197855
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2881392619
Short name T227
Test name
Test status
Simulation time 91505318 ps
CPU time 4.2 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 209664 kb
Host smart-9de787f4-0d59-45f7-8342-e128f8b356ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881392619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2881392619
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1441813941
Short name T405
Test name
Test status
Simulation time 935078309 ps
CPU time 10.22 seconds
Started Jun 01 03:05:54 PM PDT 24
Finished Jun 01 03:06:05 PM PDT 24
Peak memory 208624 kb
Host smart-bb5c23eb-24d9-449a-aa37-b85367ece641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441813941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1441813941
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2832083108
Short name T259
Test name
Test status
Simulation time 60058572 ps
CPU time 2.68 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 207728 kb
Host smart-21672049-1dac-4f1e-8f0a-9a9cd09ac059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832083108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2832083108
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.543589928
Short name T584
Test name
Test status
Simulation time 533001922 ps
CPU time 4.65 seconds
Started Jun 01 03:05:54 PM PDT 24
Finished Jun 01 03:05:59 PM PDT 24
Peak memory 206596 kb
Host smart-120ddadf-9419-42f2-ada1-e821a4587a64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543589928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.543589928
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2518532394
Short name T618
Test name
Test status
Simulation time 1010016920 ps
CPU time 7.17 seconds
Started Jun 01 03:05:50 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 207660 kb
Host smart-f0ec28e7-37b6-4909-8b89-493d51c5513b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518532394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2518532394
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4122550187
Short name T702
Test name
Test status
Simulation time 171991704 ps
CPU time 2 seconds
Started Jun 01 03:05:53 PM PDT 24
Finished Jun 01 03:05:56 PM PDT 24
Peak memory 206640 kb
Host smart-fe756bdb-c6f7-49f3-a5db-755f87037f27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122550187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4122550187
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.114315814
Short name T883
Test name
Test status
Simulation time 310216888 ps
CPU time 6.91 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:06:00 PM PDT 24
Peak memory 220224 kb
Host smart-43802b7c-703d-474d-8c65-e692360a2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114315814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.114315814
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1568445159
Short name T721
Test name
Test status
Simulation time 119379151 ps
CPU time 2.73 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:05:54 PM PDT 24
Peak memory 208236 kb
Host smart-3c98264b-4341-4617-9f62-9d41a6b992a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568445159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1568445159
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.614951548
Short name T434
Test name
Test status
Simulation time 134685867 ps
CPU time 7.27 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:05:59 PM PDT 24
Peak memory 216484 kb
Host smart-3e7f7159-3489-4c6b-babb-adf1fbb01c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614951548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.614951548
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1382890369
Short name T77
Test name
Test status
Simulation time 355744432 ps
CPU time 8.85 seconds
Started Jun 01 03:05:53 PM PDT 24
Finished Jun 01 03:06:03 PM PDT 24
Peak memory 220168 kb
Host smart-97cd95c0-b30b-498f-aaff-dbffeae4c743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382890369 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1382890369
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2091444516
Short name T335
Test name
Test status
Simulation time 423554772 ps
CPU time 6.1 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:59 PM PDT 24
Peak memory 213932 kb
Host smart-92502418-849d-4668-89ca-5185f10cbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091444516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2091444516
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2692394007
Short name T108
Test name
Test status
Simulation time 193471419 ps
CPU time 2.78 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:05:54 PM PDT 24
Peak memory 209872 kb
Host smart-2453517d-76f5-4312-9601-33d42d20c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692394007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2692394007
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1036159196
Short name T1042
Test name
Test status
Simulation time 27730631 ps
CPU time 0.79 seconds
Started Jun 01 03:05:59 PM PDT 24
Finished Jun 01 03:06:00 PM PDT 24
Peak memory 205552 kb
Host smart-20655482-542f-4b4f-82dd-3e85c775e1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036159196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1036159196
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.967012838
Short name T356
Test name
Test status
Simulation time 136704932 ps
CPU time 2.93 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 215008 kb
Host smart-c9855f29-ee2f-4fa5-9151-bdbcb794b743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967012838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.967012838
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2924331355
Short name T700
Test name
Test status
Simulation time 492542832 ps
CPU time 3.62 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:57 PM PDT 24
Peak memory 207568 kb
Host smart-0e50176e-4002-4cb0-8ad3-cd65e4b218d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924331355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2924331355
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1479763219
Short name T414
Test name
Test status
Simulation time 427124475 ps
CPU time 10.84 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 209232 kb
Host smart-8814162b-0086-4743-8402-8e67efb9506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479763219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1479763219
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3590682305
Short name T326
Test name
Test status
Simulation time 2256185451 ps
CPU time 12.79 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:10 PM PDT 24
Peak memory 215892 kb
Host smart-379a1386-9e5d-43e8-abfb-1a4a728efd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590682305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3590682305
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3847414652
Short name T448
Test name
Test status
Simulation time 261849863 ps
CPU time 2.99 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:56 PM PDT 24
Peak memory 208216 kb
Host smart-0f6718e1-7f70-4bdd-8dfb-0a36671b4521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847414652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3847414652
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2371455321
Short name T764
Test name
Test status
Simulation time 55975334 ps
CPU time 3.6 seconds
Started Jun 01 03:05:51 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 207044 kb
Host smart-efbbe56a-5e8d-4500-8928-5d6b08a1569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371455321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2371455321
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3004278678
Short name T794
Test name
Test status
Simulation time 893812139 ps
CPU time 4.99 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 208404 kb
Host smart-0c20d114-2121-4567-aba9-dd0b1ee93801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004278678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3004278678
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1871826305
Short name T669
Test name
Test status
Simulation time 240036352 ps
CPU time 8.01 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:06:01 PM PDT 24
Peak memory 208460 kb
Host smart-0343f97b-5518-4357-920a-df41873f73d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871826305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1871826305
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3840813610
Short name T871
Test name
Test status
Simulation time 165135406 ps
CPU time 3.78 seconds
Started Jun 01 03:05:49 PM PDT 24
Finished Jun 01 03:05:53 PM PDT 24
Peak memory 208400 kb
Host smart-66b09a40-f97b-4ea1-9e39-2776a853c474
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840813610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3840813610
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3340361219
Short name T617
Test name
Test status
Simulation time 100504753 ps
CPU time 2.8 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:05:55 PM PDT 24
Peak memory 206504 kb
Host smart-59e2c19e-09cf-40fb-8630-a2d95998bd13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340361219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3340361219
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.527347940
Short name T881
Test name
Test status
Simulation time 151222107 ps
CPU time 3.34 seconds
Started Jun 01 03:05:56 PM PDT 24
Finished Jun 01 03:06:00 PM PDT 24
Peak memory 209520 kb
Host smart-cdc76930-251a-4ded-8540-67e7b69037b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527347940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.527347940
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2486319289
Short name T910
Test name
Test status
Simulation time 54150805 ps
CPU time 2.74 seconds
Started Jun 01 03:05:49 PM PDT 24
Finished Jun 01 03:05:52 PM PDT 24
Peak memory 207588 kb
Host smart-2259f279-f9bb-4cfb-bf71-12db0fc56665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486319289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2486319289
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1367735603
Short name T429
Test name
Test status
Simulation time 370423460 ps
CPU time 3.28 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:04 PM PDT 24
Peak memory 221952 kb
Host smart-35e26e38-387d-446b-97e5-ad6c3cd081a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367735603 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1367735603
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1814169718
Short name T25
Test name
Test status
Simulation time 552308258 ps
CPU time 7.96 seconds
Started Jun 01 03:05:52 PM PDT 24
Finished Jun 01 03:06:01 PM PDT 24
Peak memory 208236 kb
Host smart-e2b89b1f-ff49-4060-b5e2-4fb3010cfad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814169718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1814169718
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2229073879
Short name T103
Test name
Test status
Simulation time 101996584 ps
CPU time 2.12 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 209728 kb
Host smart-ef4a7743-8bd7-4718-801e-999676539a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229073879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2229073879
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.732511783
Short name T771
Test name
Test status
Simulation time 54570189 ps
CPU time 0.88 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:05:58 PM PDT 24
Peak memory 205600 kb
Host smart-dff9e8ad-eecc-47e8-bfb4-0939a6cb849a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732511783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.732511783
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3230512994
Short name T159
Test name
Test status
Simulation time 207866252 ps
CPU time 10.16 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:08 PM PDT 24
Peak memory 214776 kb
Host smart-1213426f-309c-4be0-91bc-72132d2a6454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230512994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3230512994
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2242463874
Short name T667
Test name
Test status
Simulation time 71001422 ps
CPU time 3.79 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:01 PM PDT 24
Peak memory 209856 kb
Host smart-6e427fc2-a030-46d0-8b27-f19fce9b91ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242463874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2242463874
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1117068997
Short name T733
Test name
Test status
Simulation time 316393259 ps
CPU time 2.28 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:02 PM PDT 24
Peak memory 206608 kb
Host smart-be873c28-cad8-420b-ba08-7e34f9f72c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117068997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1117068997
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3482155717
Short name T413
Test name
Test status
Simulation time 57742590 ps
CPU time 3.96 seconds
Started Jun 01 03:05:59 PM PDT 24
Finished Jun 01 03:06:04 PM PDT 24
Peak memory 222084 kb
Host smart-a4e95d5f-0323-4835-9952-35d69d002458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482155717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3482155717
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.488104439
Short name T707
Test name
Test status
Simulation time 281268014 ps
CPU time 4.16 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:12 PM PDT 24
Peak memory 219808 kb
Host smart-20c2971c-759c-4345-980f-84f37ed00b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488104439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.488104439
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1795251149
Short name T850
Test name
Test status
Simulation time 464371953 ps
CPU time 8.09 seconds
Started Jun 01 03:05:58 PM PDT 24
Finished Jun 01 03:06:07 PM PDT 24
Peak memory 209108 kb
Host smart-95250035-fc72-44e8-9ff5-395a8ea10460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795251149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1795251149
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2792342313
Short name T792
Test name
Test status
Simulation time 133406296 ps
CPU time 2.5 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:03 PM PDT 24
Peak memory 206432 kb
Host smart-c51add2d-ef3e-4256-8df5-1859b8ac23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792342313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2792342313
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1734890261
Short name T948
Test name
Test status
Simulation time 916884432 ps
CPU time 22.89 seconds
Started Jun 01 03:05:57 PM PDT 24
Finished Jun 01 03:06:20 PM PDT 24
Peak memory 207728 kb
Host smart-d9bc74fa-0049-4412-ae30-37df2f838ed3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734890261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1734890261
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.142164542
Short name T109
Test name
Test status
Simulation time 246994848 ps
CPU time 3.15 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:10 PM PDT 24
Peak memory 206456 kb
Host smart-6251a9a7-8744-4026-8461-7ffa16248578
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142164542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.142164542
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2959083819
Short name T81
Test name
Test status
Simulation time 3443254419 ps
CPU time 65.47 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:07:06 PM PDT 24
Peak memory 207860 kb
Host smart-8f40f8aa-b532-4e65-8a49-ff98a16e8ecf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959083819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2959083819
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.492256953
Short name T668
Test name
Test status
Simulation time 684529040 ps
CPU time 4.68 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:12 PM PDT 24
Peak memory 209936 kb
Host smart-210a53db-0299-4240-91a6-fe9c96400490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492256953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.492256953
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.727346583
Short name T588
Test name
Test status
Simulation time 227819534 ps
CPU time 5.31 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:06 PM PDT 24
Peak memory 207392 kb
Host smart-8269eb7e-a955-480c-889d-8c7a52c547e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727346583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.727346583
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.160453996
Short name T719
Test name
Test status
Simulation time 250851040 ps
CPU time 4.62 seconds
Started Jun 01 03:05:59 PM PDT 24
Finished Jun 01 03:06:04 PM PDT 24
Peak memory 219976 kb
Host smart-ee0f2b79-8d4c-4f1d-a464-f095ca631e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160453996 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.160453996
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2348718815
Short name T930
Test name
Test status
Simulation time 611934598 ps
CPU time 4.68 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:05 PM PDT 24
Peak memory 217736 kb
Host smart-13be04fe-0464-4e0c-a1a8-726f591a5237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348718815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2348718815
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.789234592
Short name T659
Test name
Test status
Simulation time 104033182 ps
CPU time 2.63 seconds
Started Jun 01 03:05:59 PM PDT 24
Finished Jun 01 03:06:02 PM PDT 24
Peak memory 209688 kb
Host smart-fc12b0cf-5df9-4e15-9775-8ae827566c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789234592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.789234592
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1459015577
Short name T704
Test name
Test status
Simulation time 17091898 ps
CPU time 0.74 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:06 PM PDT 24
Peak memory 205484 kb
Host smart-74ea2050-2983-4bf0-9136-a14764846308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459015577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1459015577
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3594240847
Short name T436
Test name
Test status
Simulation time 395861190 ps
CPU time 13.77 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:19 PM PDT 24
Peak memory 214008 kb
Host smart-4deb4102-6798-4b0e-bf62-51c3f8a13a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594240847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3594240847
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2778976258
Short name T749
Test name
Test status
Simulation time 134073385 ps
CPU time 4.17 seconds
Started Jun 01 03:06:08 PM PDT 24
Finished Jun 01 03:06:13 PM PDT 24
Peak memory 215940 kb
Host smart-1c9d37f9-38d3-42a7-996d-930b26b6581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778976258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2778976258
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1361155991
Short name T72
Test name
Test status
Simulation time 2213069828 ps
CPU time 39.97 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:48 PM PDT 24
Peak memory 218332 kb
Host smart-7c955a57-3e03-463e-80ef-42fcf4285b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361155991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1361155991
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1688274814
Short name T869
Test name
Test status
Simulation time 221272496 ps
CPU time 4.87 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:12 PM PDT 24
Peak memory 209284 kb
Host smart-1198d54e-145b-4f59-a0d1-0e954789f929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688274814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1688274814
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3230785318
Short name T874
Test name
Test status
Simulation time 485414454 ps
CPU time 3.16 seconds
Started Jun 01 03:06:03 PM PDT 24
Finished Jun 01 03:06:06 PM PDT 24
Peak memory 208540 kb
Host smart-266e8772-dd3a-47f3-ad3c-24891d3e2768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230785318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3230785318
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3206501898
Short name T683
Test name
Test status
Simulation time 244613643 ps
CPU time 8.86 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 208824 kb
Host smart-06617423-0229-4508-9d79-3f9d667c8f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206501898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3206501898
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1782629526
Short name T855
Test name
Test status
Simulation time 203238157 ps
CPU time 2.92 seconds
Started Jun 01 03:05:59 PM PDT 24
Finished Jun 01 03:06:02 PM PDT 24
Peak memory 206564 kb
Host smart-6635139c-d6d4-429c-8574-17b719a45403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782629526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1782629526
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4064203342
Short name T915
Test name
Test status
Simulation time 229878297 ps
CPU time 4.31 seconds
Started Jun 01 03:06:04 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 208004 kb
Host smart-d9d305ba-1477-4bc5-b2c9-a4fd1800421b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064203342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4064203342
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.349266242
Short name T626
Test name
Test status
Simulation time 105156777 ps
CPU time 2.33 seconds
Started Jun 01 03:06:00 PM PDT 24
Finished Jun 01 03:06:02 PM PDT 24
Peak memory 208744 kb
Host smart-38ac8ff9-9d30-48ea-bc04-5c45f09fc30a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349266242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.349266242
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.708765414
Short name T431
Test name
Test status
Simulation time 496811986 ps
CPU time 6.52 seconds
Started Jun 01 03:06:04 PM PDT 24
Finished Jun 01 03:06:11 PM PDT 24
Peak memory 207584 kb
Host smart-69de7497-2b76-485c-9bbb-70aeed13b9c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708765414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.708765414
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2548880513
Short name T701
Test name
Test status
Simulation time 153275644 ps
CPU time 4.2 seconds
Started Jun 01 03:06:03 PM PDT 24
Finished Jun 01 03:06:08 PM PDT 24
Peak memory 217968 kb
Host smart-7d4e1565-c8db-43d3-8b90-9bd81e025f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548880513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2548880513
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4146152555
Short name T838
Test name
Test status
Simulation time 493563591 ps
CPU time 9.49 seconds
Started Jun 01 03:06:01 PM PDT 24
Finished Jun 01 03:06:10 PM PDT 24
Peak memory 208096 kb
Host smart-5350dcdc-000e-4785-8f6a-d43074ea1130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146152555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4146152555
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3119046552
Short name T238
Test name
Test status
Simulation time 3608511160 ps
CPU time 26.94 seconds
Started Jun 01 03:06:03 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 222236 kb
Host smart-d05549df-1f0e-4e12-a13a-8c2acc85ad21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119046552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3119046552
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1914690965
Short name T233
Test name
Test status
Simulation time 244781645 ps
CPU time 4.91 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:12 PM PDT 24
Peak memory 223180 kb
Host smart-8f316658-5f8d-41e6-ab80-9029ee167de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914690965 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1914690965
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1475781893
Short name T279
Test name
Test status
Simulation time 648089477 ps
CPU time 13.26 seconds
Started Jun 01 03:06:04 PM PDT 24
Finished Jun 01 03:06:18 PM PDT 24
Peak memory 207928 kb
Host smart-916e40ba-ac11-49ff-b21d-0af5d574dfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475781893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1475781893
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.451423927
Short name T717
Test name
Test status
Simulation time 53985402 ps
CPU time 0.75 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:22 PM PDT 24
Peak memory 205584 kb
Host smart-0b47dd98-528b-4d6b-afd1-7fa9cab91806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451423927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.451423927
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3988067524
Short name T728
Test name
Test status
Simulation time 262742766 ps
CPU time 2.31 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:08 PM PDT 24
Peak memory 214040 kb
Host smart-8e49c12c-348f-432b-bbe8-f4c761fb9acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988067524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3988067524
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1415652543
Short name T91
Test name
Test status
Simulation time 281294811 ps
CPU time 5.05 seconds
Started Jun 01 03:06:04 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 214004 kb
Host smart-230c9d9b-4e18-47b7-90e9-9eb376406adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415652543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1415652543
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2627643744
Short name T95
Test name
Test status
Simulation time 71722522 ps
CPU time 3.95 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:11 PM PDT 24
Peak memory 209184 kb
Host smart-8efe023e-7971-4832-83c1-519a9e502194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627643744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2627643744
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2381686089
Short name T945
Test name
Test status
Simulation time 297907899 ps
CPU time 5.48 seconds
Started Jun 01 03:06:08 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 219644 kb
Host smart-e10f131e-c0ee-4203-a76a-76433a77c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381686089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2381686089
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.816063364
Short name T963
Test name
Test status
Simulation time 839242119 ps
CPU time 5.36 seconds
Started Jun 01 03:06:08 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 218280 kb
Host smart-05cae695-722e-4cd0-87e8-3ee036c499cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816063364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.816063364
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4089989596
Short name T321
Test name
Test status
Simulation time 175644117 ps
CPU time 4.91 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:11 PM PDT 24
Peak memory 208032 kb
Host smart-e12971f2-cd13-424c-99fa-23d68146be2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089989596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4089989596
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3940298953
Short name T875
Test name
Test status
Simulation time 323485722 ps
CPU time 6.04 seconds
Started Jun 01 03:06:08 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 208080 kb
Host smart-c35d6b40-a9bb-4da5-8037-deb0667cbbfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940298953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3940298953
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1939712694
Short name T433
Test name
Test status
Simulation time 164293470 ps
CPU time 5.6 seconds
Started Jun 01 03:06:03 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 208020 kb
Host smart-0b166f1d-407a-4a2c-8d8a-fa946e54b666
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939712694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1939712694
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3956253689
Short name T901
Test name
Test status
Simulation time 76452472 ps
CPU time 2.57 seconds
Started Jun 01 03:06:04 PM PDT 24
Finished Jun 01 03:06:07 PM PDT 24
Peak memory 208288 kb
Host smart-f4b92ab5-8c7f-4114-9b37-9a2c59474ddd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956253689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3956253689
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2335433269
Short name T949
Test name
Test status
Simulation time 406775811 ps
CPU time 2.48 seconds
Started Jun 01 03:06:06 PM PDT 24
Finished Jun 01 03:06:09 PM PDT 24
Peak memory 208696 kb
Host smart-3ea45a25-b28f-43fa-84d5-580692abdbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335433269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2335433269
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3932533752
Short name T804
Test name
Test status
Simulation time 200612943 ps
CPU time 4.81 seconds
Started Jun 01 03:06:07 PM PDT 24
Finished Jun 01 03:06:12 PM PDT 24
Peak memory 207772 kb
Host smart-050ba4be-9910-42f0-913f-8d137bd62fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932533752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3932533752
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1928658008
Short name T655
Test name
Test status
Simulation time 169064788 ps
CPU time 2.76 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 221724 kb
Host smart-b925d1fe-706f-4561-898c-347a5d41f894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928658008 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1928658008
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3411012222
Short name T689
Test name
Test status
Simulation time 296325387 ps
CPU time 5.26 seconds
Started Jun 01 03:06:05 PM PDT 24
Finished Jun 01 03:06:10 PM PDT 24
Peak memory 207164 kb
Host smart-cae1f473-5836-421e-aab8-7817510b3bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411012222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3411012222
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.366371030
Short name T1052
Test name
Test status
Simulation time 54500267 ps
CPU time 2.59 seconds
Started Jun 01 03:06:13 PM PDT 24
Finished Jun 01 03:06:16 PM PDT 24
Peak memory 210476 kb
Host smart-2348c06c-a964-445e-a554-4739f4c35576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366371030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.366371030
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1196334557
Short name T100
Test name
Test status
Simulation time 15122772 ps
CPU time 0.93 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 205640 kb
Host smart-2b37a871-027a-4fca-a07e-9e39551cb758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196334557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1196334557
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1952069304
Short name T453
Test name
Test status
Simulation time 673158755 ps
CPU time 10.22 seconds
Started Jun 01 03:03:22 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 222112 kb
Host smart-77efad96-e7e3-4331-bae6-a8e738b662f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952069304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1952069304
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2215392918
Short name T867
Test name
Test status
Simulation time 969831976 ps
CPU time 4.75 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:29 PM PDT 24
Peak memory 217972 kb
Host smart-d7f23def-c5e9-461d-8be2-09827dd4286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215392918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2215392918
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1796890756
Short name T340
Test name
Test status
Simulation time 88533223 ps
CPU time 3.81 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 208148 kb
Host smart-d1378c83-a76c-484c-bc3e-0d4502508c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796890756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1796890756
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1915994019
Short name T884
Test name
Test status
Simulation time 234903788 ps
CPU time 4.12 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 213984 kb
Host smart-0d345dab-6f9e-49e1-aa73-73f36407796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915994019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1915994019
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.308208438
Short name T309
Test name
Test status
Simulation time 1675124807 ps
CPU time 6.77 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 213968 kb
Host smart-9d38733d-e1b0-4a6f-9404-a7e60c229de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308208438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.308208438
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1163461586
Short name T695
Test name
Test status
Simulation time 315185390 ps
CPU time 4.17 seconds
Started Jun 01 03:03:26 PM PDT 24
Finished Jun 01 03:03:31 PM PDT 24
Peak memory 219236 kb
Host smart-95b3a67a-3f95-4b9b-b991-f02f7aeb4850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163461586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1163461586
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3953013448
Short name T379
Test name
Test status
Simulation time 509779443 ps
CPU time 4.01 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:30 PM PDT 24
Peak memory 207700 kb
Host smart-558dbe75-3aed-45b6-9ef7-dca6bc1745f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953013448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3953013448
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3943053471
Short name T958
Test name
Test status
Simulation time 124512965 ps
CPU time 2.47 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:19 PM PDT 24
Peak memory 206800 kb
Host smart-5dcfec5a-6218-4c55-b1f7-aa397adc96c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943053471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3943053471
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.249852043
Short name T870
Test name
Test status
Simulation time 26231761 ps
CPU time 2.27 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:26 PM PDT 24
Peak memory 208608 kb
Host smart-91355a52-2631-457f-ac13-cbabf1c6eeb8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249852043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.249852043
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.666581722
Short name T650
Test name
Test status
Simulation time 102192575 ps
CPU time 3.63 seconds
Started Jun 01 03:03:16 PM PDT 24
Finished Jun 01 03:03:20 PM PDT 24
Peak memory 206556 kb
Host smart-b1e78419-0046-45e4-b07f-95166f63de36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666581722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.666581722
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3910945080
Short name T976
Test name
Test status
Simulation time 198676491 ps
CPU time 2.68 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:26 PM PDT 24
Peak memory 208332 kb
Host smart-28c92613-1194-494b-80cd-447ec557b5eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910945080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3910945080
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1482765918
Short name T625
Test name
Test status
Simulation time 248081093 ps
CPU time 3.37 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 207852 kb
Host smart-6719ff92-2ba0-46e6-a251-869a87361330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482765918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1482765918
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3945861852
Short name T660
Test name
Test status
Simulation time 1786324646 ps
CPU time 17.11 seconds
Started Jun 01 03:03:15 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 207692 kb
Host smart-0c11ab7e-8fab-4f1c-b4b5-16b2e8bba5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945861852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3945861852
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1499309131
Short name T323
Test name
Test status
Simulation time 256956628 ps
CPU time 12.09 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:36 PM PDT 24
Peak memory 222288 kb
Host smart-9363c0a9-ffe6-4901-a678-6ea565381336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499309131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1499309131
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3276642271
Short name T239
Test name
Test status
Simulation time 700668727 ps
CPU time 9.1 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:34 PM PDT 24
Peak memory 222420 kb
Host smart-0be3d9be-fc3b-44bd-9c59-5f14671c7177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276642271 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3276642271
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.939615286
Short name T979
Test name
Test status
Simulation time 2275165520 ps
CPU time 19.48 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:45 PM PDT 24
Peak memory 217804 kb
Host smart-53aac234-8bb3-465e-be12-a49c35cbccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939615286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.939615286
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.763426740
Short name T421
Test name
Test status
Simulation time 52763850 ps
CPU time 1.51 seconds
Started Jun 01 03:03:22 PM PDT 24
Finished Jun 01 03:03:24 PM PDT 24
Peak memory 209280 kb
Host smart-60bbb457-f7a1-4da5-90a5-ac6f8be672f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763426740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.763426740
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.410141978
Short name T598
Test name
Test status
Simulation time 20547003 ps
CPU time 0.89 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:22 PM PDT 24
Peak memory 205584 kb
Host smart-0dfe62b1-bcdb-4635-af5b-867d02e0f02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410141978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.410141978
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2113086909
Short name T459
Test name
Test status
Simulation time 100153537 ps
CPU time 3.91 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 214092 kb
Host smart-d73e3362-80bd-4516-8c2b-91fed40a5f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113086909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2113086909
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3118340874
Short name T815
Test name
Test status
Simulation time 1066442070 ps
CPU time 24.3 seconds
Started Jun 01 03:06:13 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 214000 kb
Host smart-c37e05b8-5d8f-4e6e-8daf-4a9b97444f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118340874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3118340874
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.44566745
Short name T978
Test name
Test status
Simulation time 50462480 ps
CPU time 2.32 seconds
Started Jun 01 03:06:15 PM PDT 24
Finished Jun 01 03:06:17 PM PDT 24
Peak memory 217864 kb
Host smart-25db9231-0f48-4d16-b96a-9236dafe35d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44566745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.44566745
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1976945439
Short name T92
Test name
Test status
Simulation time 131810344 ps
CPU time 4.3 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 218776 kb
Host smart-6287ad7d-1451-4eaf-a93b-c2899c0e6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976945439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1976945439
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3624716321
Short name T305
Test name
Test status
Simulation time 2238552718 ps
CPU time 8.45 seconds
Started Jun 01 03:06:11 PM PDT 24
Finished Jun 01 03:06:20 PM PDT 24
Peak memory 210896 kb
Host smart-a0b27846-1e11-4d3f-b2ab-8b3a9c1bd193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624716321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3624716321
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2778966500
Short name T455
Test name
Test status
Simulation time 107827246 ps
CPU time 5.47 seconds
Started Jun 01 03:06:12 PM PDT 24
Finished Jun 01 03:06:18 PM PDT 24
Peak memory 209324 kb
Host smart-de14186e-26ed-4543-ab77-62ea26d4d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778966500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2778966500
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2340196636
Short name T826
Test name
Test status
Simulation time 496760013 ps
CPU time 6 seconds
Started Jun 01 03:06:14 PM PDT 24
Finished Jun 01 03:06:20 PM PDT 24
Peak memory 206608 kb
Host smart-5a9f989d-ef0b-4a16-8300-9cfaa9b397c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340196636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2340196636
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3138425370
Short name T890
Test name
Test status
Simulation time 1004292182 ps
CPU time 21.79 seconds
Started Jun 01 03:06:13 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 208648 kb
Host smart-280b500e-f355-497f-b6c6-2fb7bbdfc3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138425370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3138425370
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3576681497
Short name T952
Test name
Test status
Simulation time 100952697 ps
CPU time 4.17 seconds
Started Jun 01 03:06:11 PM PDT 24
Finished Jun 01 03:06:16 PM PDT 24
Peak memory 208580 kb
Host smart-368329e8-38a6-4c79-8508-97fb8027cfc6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576681497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3576681497
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1243440394
Short name T1057
Test name
Test status
Simulation time 1150161606 ps
CPU time 33.35 seconds
Started Jun 01 03:06:14 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 206548 kb
Host smart-e54c4203-7b02-495e-8722-b4fc971536a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243440394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1243440394
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1242879345
Short name T931
Test name
Test status
Simulation time 129402819 ps
CPU time 4.33 seconds
Started Jun 01 03:06:14 PM PDT 24
Finished Jun 01 03:06:18 PM PDT 24
Peak memory 206620 kb
Host smart-0b6c29c7-decc-423d-8dc6-e61368bd8c08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242879345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1242879345
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3351561453
Short name T724
Test name
Test status
Simulation time 197290860 ps
CPU time 2.1 seconds
Started Jun 01 03:06:15 PM PDT 24
Finished Jun 01 03:06:17 PM PDT 24
Peak memory 208652 kb
Host smart-7db5e00e-f07a-4719-8efe-d5f79da39c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351561453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3351561453
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.229900127
Short name T219
Test name
Test status
Simulation time 104100112 ps
CPU time 2.29 seconds
Started Jun 01 03:06:13 PM PDT 24
Finished Jun 01 03:06:15 PM PDT 24
Peak memory 208552 kb
Host smart-c9de56a2-0abe-4d93-a6e2-a369feba16a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229900127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.229900127
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.903482355
Short name T928
Test name
Test status
Simulation time 158737602 ps
CPU time 4.49 seconds
Started Jun 01 03:06:12 PM PDT 24
Finished Jun 01 03:06:16 PM PDT 24
Peak memory 219200 kb
Host smart-e0d5073e-fdb8-4c5a-baba-9a3f5a6de1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903482355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.903482355
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1866551313
Short name T257
Test name
Test status
Simulation time 130912878 ps
CPU time 5.58 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:27 PM PDT 24
Peak memory 207296 kb
Host smart-6650cb5e-6713-4744-8ed6-98a8d401d92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866551313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1866551313
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4054165098
Short name T619
Test name
Test status
Simulation time 41969853 ps
CPU time 1.5 seconds
Started Jun 01 03:06:12 PM PDT 24
Finished Jun 01 03:06:14 PM PDT 24
Peak memory 209888 kb
Host smart-7c28b3d4-df16-40a4-bd18-9824c9c9ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054165098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4054165098
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2764746074
Short name T1033
Test name
Test status
Simulation time 42898961 ps
CPU time 0.77 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:21 PM PDT 24
Peak memory 205548 kb
Host smart-2a2af819-1a6c-45c4-ab78-141ecd4e529c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764746074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2764746074
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1647908525
Short name T450
Test name
Test status
Simulation time 43842970 ps
CPU time 3.39 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:27 PM PDT 24
Peak memory 214016 kb
Host smart-b98ea3ec-d0e9-4e5b-93e4-f1a123e8e99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647908525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1647908525
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1810149355
Short name T671
Test name
Test status
Simulation time 2413666603 ps
CPU time 36.12 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:59 PM PDT 24
Peak memory 222656 kb
Host smart-a61d8c2c-605d-4d87-85d8-ff5b2153fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810149355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1810149355
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3578869468
Short name T852
Test name
Test status
Simulation time 50207830 ps
CPU time 3.1 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 209432 kb
Host smart-797930af-3228-484e-8f21-7ac9eb631d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578869468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3578869468
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3132672305
Short name T389
Test name
Test status
Simulation time 122929021 ps
CPU time 4.68 seconds
Started Jun 01 03:06:19 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 213964 kb
Host smart-17df0511-c087-459e-8ad7-c0efb8a87c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132672305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3132672305
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3813384269
Short name T784
Test name
Test status
Simulation time 412497229 ps
CPU time 3.75 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 219796 kb
Host smart-8601ffc8-9814-4499-8ddb-8e69cd96084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813384269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3813384269
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.26827352
Short name T146
Test name
Test status
Simulation time 319009468 ps
CPU time 3.42 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 209512 kb
Host smart-19a57f1e-272a-44bd-aa7b-3a744952b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26827352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.26827352
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1892817612
Short name T296
Test name
Test status
Simulation time 32619765 ps
CPU time 2.54 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:25 PM PDT 24
Peak memory 208160 kb
Host smart-022c2d13-2411-47b9-84a4-b50e257774de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892817612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1892817612
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.745264893
Short name T367
Test name
Test status
Simulation time 1858951379 ps
CPU time 38.04 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:07:00 PM PDT 24
Peak memory 207512 kb
Host smart-2e5587b3-a4e0-4e21-aad2-c7d2c2f9fd30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745264893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.745264893
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3427940724
Short name T758
Test name
Test status
Simulation time 5650931568 ps
CPU time 40.87 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:07:04 PM PDT 24
Peak memory 208924 kb
Host smart-3a44ff6b-32a7-4f86-a51c-13a23e7dbe69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427940724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3427940724
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.32593328
Short name T938
Test name
Test status
Simulation time 272492427 ps
CPU time 7.61 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 208256 kb
Host smart-044d6bc9-ce44-4cdc-b820-807e38c2452e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.32593328
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2146056389
Short name T918
Test name
Test status
Simulation time 1460653028 ps
CPU time 9.97 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 209480 kb
Host smart-69d341bf-68bd-41f4-b67a-658e3135b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146056389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2146056389
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1849911309
Short name T767
Test name
Test status
Simulation time 139733336 ps
CPU time 3.41 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 206288 kb
Host smart-2a3ec60b-4939-4bbd-a3c2-7bf8530ab192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849911309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1849911309
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2857698388
Short name T1024
Test name
Test status
Simulation time 30329618593 ps
CPU time 294.46 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:11:16 PM PDT 24
Peak memory 222184 kb
Host smart-44220a00-3592-45c0-9cea-91c884183595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857698388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2857698388
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3907053410
Short name T645
Test name
Test status
Simulation time 51522653 ps
CPU time 3.09 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:25 PM PDT 24
Peak memory 222348 kb
Host smart-daedaa14-7368-402c-b057-5d59842acb17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907053410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3907053410
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1596614269
Short name T778
Test name
Test status
Simulation time 136676382 ps
CPU time 5.47 seconds
Started Jun 01 03:06:24 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 208092 kb
Host smart-474abeb2-12a0-41b5-a705-468d1c6829ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596614269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1596614269
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3254793956
Short name T739
Test name
Test status
Simulation time 148800159 ps
CPU time 1.83 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:23 PM PDT 24
Peak memory 209508 kb
Host smart-4ee7fc48-ff26-4071-8b81-f4ff6162ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254793956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3254793956
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1126603786
Short name T791
Test name
Test status
Simulation time 34903013 ps
CPU time 0.79 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:22 PM PDT 24
Peak memory 205576 kb
Host smart-05b83e33-4642-4fe7-a1d3-4752a087f539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126603786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1126603786
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3069833331
Short name T376
Test name
Test status
Simulation time 124395520 ps
CPU time 2.68 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 214144 kb
Host smart-a5103988-6139-40c7-9e79-8eaaf6790599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069833331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3069833331
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.423704666
Short name T50
Test name
Test status
Simulation time 123893933 ps
CPU time 3.47 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:26 PM PDT 24
Peak memory 214060 kb
Host smart-3219e637-b6a3-47eb-8d33-79d75ec67e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423704666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.423704666
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.76115123
Short name T722
Test name
Test status
Simulation time 63137867 ps
CPU time 3.65 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:27 PM PDT 24
Peak memory 219132 kb
Host smart-0267643e-480f-4ace-bbfa-8370c910a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76115123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.76115123
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2952954693
Short name T990
Test name
Test status
Simulation time 116604530 ps
CPU time 6.02 seconds
Started Jun 01 03:06:25 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 222336 kb
Host smart-f2d45d88-5f50-43d0-b0d1-7daccff09075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952954693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2952954693
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2082342265
Short name T218
Test name
Test status
Simulation time 4683723710 ps
CPU time 9.3 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 214092 kb
Host smart-6fa988e0-4799-4ced-ac4d-9af1a0267ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082342265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2082342265
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3711761295
Short name T1032
Test name
Test status
Simulation time 63832543 ps
CPU time 2.29 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:25 PM PDT 24
Peak memory 206864 kb
Host smart-061b53f0-2274-4f00-a33e-28d82dfaabcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711761295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3711761295
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1277195227
Short name T365
Test name
Test status
Simulation time 212895213 ps
CPU time 8.09 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 208572 kb
Host smart-70605d75-d35d-4f62-bc41-7b194044130f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277195227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1277195227
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3845703107
Short name T779
Test name
Test status
Simulation time 296708209 ps
CPU time 7.48 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 208404 kb
Host smart-29c5c093-df9f-45ec-ab88-1fa4198a9888
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845703107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3845703107
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3957985303
Short name T613
Test name
Test status
Simulation time 335538410 ps
CPU time 3.42 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:27 PM PDT 24
Peak memory 206848 kb
Host smart-99f410ae-4f68-4e6b-b69a-a9a72b82c25b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957985303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3957985303
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1823222347
Short name T691
Test name
Test status
Simulation time 464878193 ps
CPU time 6.11 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:27 PM PDT 24
Peak memory 222052 kb
Host smart-46266070-9d35-4151-bbcc-19bad8f36985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823222347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1823222347
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3046381262
Short name T960
Test name
Test status
Simulation time 527441182 ps
CPU time 6.87 seconds
Started Jun 01 03:06:25 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 208140 kb
Host smart-0cdf9251-2704-4bab-8ee0-534489bb3f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046381262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3046381262
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2698326854
Short name T344
Test name
Test status
Simulation time 2433416478 ps
CPU time 60.14 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:07:22 PM PDT 24
Peak memory 216436 kb
Host smart-87f9b9a7-ba55-4fb9-863c-08ff4fe08518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698326854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2698326854
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2196835548
Short name T755
Test name
Test status
Simulation time 3421016619 ps
CPU time 9.75 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 206820 kb
Host smart-3abd62ec-3d10-4ce0-b5aa-5233828a082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196835548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2196835548
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2547235870
Short name T780
Test name
Test status
Simulation time 37821820 ps
CPU time 1.56 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:22 PM PDT 24
Peak memory 209304 kb
Host smart-c7ac1a32-1b66-4db0-a271-5b1fa2334d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547235870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2547235870
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1331387223
Short name T741
Test name
Test status
Simulation time 13380588 ps
CPU time 0.73 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:28 PM PDT 24
Peak memory 205456 kb
Host smart-fd807e6d-a1dc-4386-8705-9724a3143c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331387223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1331387223
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1679513009
Short name T338
Test name
Test status
Simulation time 133754219 ps
CPU time 7.2 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 214412 kb
Host smart-73554a3e-69a0-40f0-95c5-6a6ad3a78a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679513009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1679513009
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.305545103
Short name T40
Test name
Test status
Simulation time 284006421 ps
CPU time 3.27 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 210044 kb
Host smart-36313e09-d410-4187-af38-bde38e5c6631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305545103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.305545103
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3403938563
Short name T694
Test name
Test status
Simulation time 101863845 ps
CPU time 2.14 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 206996 kb
Host smart-c44415c2-5998-49bf-8878-67f0370e61d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403938563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3403938563
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1134012036
Short name T286
Test name
Test status
Simulation time 1579203337 ps
CPU time 8.95 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 218696 kb
Host smart-fcfa9df7-404c-41a0-94f6-7aeaba07d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134012036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1134012036
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3607057814
Short name T306
Test name
Test status
Simulation time 471135631 ps
CPU time 9.98 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:39 PM PDT 24
Peak memory 221796 kb
Host smart-1f15b32c-e95f-4e4f-bc91-da83341259f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607057814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3607057814
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4169102251
Short name T446
Test name
Test status
Simulation time 29961070 ps
CPU time 1.73 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 207108 kb
Host smart-12487bd2-723a-435a-aaf8-723c1a18598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169102251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4169102251
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1346034545
Short name T299
Test name
Test status
Simulation time 98193031 ps
CPU time 4.79 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:28 PM PDT 24
Peak memory 208448 kb
Host smart-50e58417-8de5-498e-b799-5623dd4b4402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346034545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1346034545
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3532123878
Short name T1017
Test name
Test status
Simulation time 74523622 ps
CPU time 2.25 seconds
Started Jun 01 03:06:21 PM PDT 24
Finished Jun 01 03:06:24 PM PDT 24
Peak memory 206440 kb
Host smart-e5776473-fbb8-41b2-9441-960df96352b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532123878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3532123878
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3958544472
Short name T112
Test name
Test status
Simulation time 91965193 ps
CPU time 1.93 seconds
Started Jun 01 03:06:22 PM PDT 24
Finished Jun 01 03:06:25 PM PDT 24
Peak memory 206612 kb
Host smart-91e8cca3-020e-4243-a05d-28ec82cb8e53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958544472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3958544472
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3448465078
Short name T745
Test name
Test status
Simulation time 154620128 ps
CPU time 5.9 seconds
Started Jun 01 03:06:23 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 207792 kb
Host smart-d506bd96-b388-4c25-b64c-a1627d5ffe73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448465078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3448465078
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.237447307
Short name T394
Test name
Test status
Simulation time 719317478 ps
CPU time 17.69 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:38 PM PDT 24
Peak memory 208528 kb
Host smart-65ba9dcc-7e67-45fd-9b55-0aa63c0f84a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237447307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.237447307
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.175436851
Short name T917
Test name
Test status
Simulation time 51771031 ps
CPU time 2.74 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 207640 kb
Host smart-090d0ad9-f614-4d30-8a05-33eddd36266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175436851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.175436851
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3682774209
Short name T1043
Test name
Test status
Simulation time 335615077 ps
CPU time 4.9 seconds
Started Jun 01 03:06:20 PM PDT 24
Finished Jun 01 03:06:25 PM PDT 24
Peak memory 206468 kb
Host smart-e034f90c-b154-4cd0-89af-d2e4f4615b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682774209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3682774209
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3808265560
Short name T360
Test name
Test status
Simulation time 1801321893 ps
CPU time 29.51 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:59 PM PDT 24
Peak memory 216732 kb
Host smart-688d1c7a-b7e2-40fc-84b5-3dacc23b0d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808265560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3808265560
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.590042684
Short name T638
Test name
Test status
Simulation time 198102819 ps
CPU time 5.82 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 223200 kb
Host smart-6a2d9ee7-0f8c-4aa9-87f9-6976d5c20bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590042684 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.590042684
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2636321109
Short name T757
Test name
Test status
Simulation time 102414800 ps
CPU time 2.4 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 207196 kb
Host smart-8fd3c20b-1440-4ab8-884f-8016eff3cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636321109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2636321109
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.388674224
Short name T786
Test name
Test status
Simulation time 874800578 ps
CPU time 9.44 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:39 PM PDT 24
Peak memory 210912 kb
Host smart-9e14a4d0-2e0c-43fc-bf4e-bf4e3b89ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388674224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.388674224
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3556423745
Short name T825
Test name
Test status
Simulation time 9808085 ps
CPU time 0.76 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:29 PM PDT 24
Peak memory 205588 kb
Host smart-a6e65d77-2867-4d98-bc08-30f49c525771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556423745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3556423745
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2562589096
Short name T973
Test name
Test status
Simulation time 411697183 ps
CPU time 5.82 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:34 PM PDT 24
Peak memory 217004 kb
Host smart-37324ead-e8a5-4754-ad4c-e9191752f2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562589096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2562589096
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.260535770
Short name T325
Test name
Test status
Simulation time 748921076 ps
CPU time 4.04 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 207684 kb
Host smart-df1fc9d8-9019-4642-a094-23e24c6960d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260535770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.260535770
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2377002717
Short name T22
Test name
Test status
Simulation time 1416621639 ps
CPU time 10.49 seconds
Started Jun 01 03:06:30 PM PDT 24
Finished Jun 01 03:06:41 PM PDT 24
Peak memory 208804 kb
Host smart-09d127b9-42b5-43dc-b611-4fa1b1f85687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377002717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2377002717
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_random.1146224542
Short name T703
Test name
Test status
Simulation time 52577983 ps
CPU time 2.75 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 207200 kb
Host smart-7f354240-058a-44f7-b859-72aa12899c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146224542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1146224542
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2115125540
Short name T1041
Test name
Test status
Simulation time 64656306 ps
CPU time 2.3 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 206508 kb
Host smart-e76c29e7-3003-4597-a5fc-5e1a1c9ac41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115125540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2115125540
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1587154885
Short name T4
Test name
Test status
Simulation time 74650143 ps
CPU time 2.93 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 208404 kb
Host smart-76928d93-95dc-42b7-b97b-e1aee524cdee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587154885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1587154885
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.79411829
Short name T1053
Test name
Test status
Simulation time 34189069 ps
CPU time 2.37 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 206632 kb
Host smart-91ffda55-c596-40be-9a3d-6095b1ee5467
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79411829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.79411829
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1148337787
Short name T911
Test name
Test status
Simulation time 124065034 ps
CPU time 3.75 seconds
Started Jun 01 03:06:33 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 208416 kb
Host smart-0d429d92-2318-44a7-a029-a7011315da89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148337787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1148337787
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3342635134
Short name T1021
Test name
Test status
Simulation time 410531199 ps
CPU time 3.2 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:32 PM PDT 24
Peak memory 213988 kb
Host smart-1aa456eb-d404-41d0-9277-9fc3f532823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342635134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3342635134
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3639702710
Short name T610
Test name
Test status
Simulation time 51613493 ps
CPU time 2.5 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:31 PM PDT 24
Peak memory 208020 kb
Host smart-a5e9f5f0-ee60-4f0b-ada1-4779993230da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639702710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3639702710
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1126513482
Short name T395
Test name
Test status
Simulation time 10762840880 ps
CPU time 106.05 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:08:16 PM PDT 24
Peak memory 222344 kb
Host smart-842711eb-1d4d-4260-a015-d1c1ae29e960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126513482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1126513482
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.476404726
Short name T1048
Test name
Test status
Simulation time 135077430 ps
CPU time 4.29 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:34 PM PDT 24
Peak memory 207140 kb
Host smart-3dd94067-0407-4ed7-96e6-cf5da4e6f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476404726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.476404726
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2136338516
Short name T184
Test name
Test status
Simulation time 52536026 ps
CPU time 2.3 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:30 PM PDT 24
Peak memory 209800 kb
Host smart-a1dbe2c2-dda0-4338-9da8-65db52e607f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136338516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2136338516
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2749211917
Short name T947
Test name
Test status
Simulation time 25198131 ps
CPU time 0.76 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:06:39 PM PDT 24
Peak memory 205604 kb
Host smart-0a7bf4d1-5b4f-448b-aa6e-067cec769c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749211917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2749211917
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2965760401
Short name T981
Test name
Test status
Simulation time 90366587 ps
CPU time 2.6 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:33 PM PDT 24
Peak memory 217880 kb
Host smart-21cda78f-67e9-4b37-8359-1462714a36c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965760401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2965760401
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1868973239
Short name T865
Test name
Test status
Simulation time 110880823 ps
CPU time 5.31 seconds
Started Jun 01 03:06:27 PM PDT 24
Finished Jun 01 03:06:33 PM PDT 24
Peak memory 208812 kb
Host smart-54732942-b7e2-4e96-a53e-326c0a7848c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868973239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1868973239
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2725755922
Short name T96
Test name
Test status
Simulation time 425147810 ps
CPU time 8.62 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:06:48 PM PDT 24
Peak memory 214036 kb
Host smart-00323c41-1ecc-45b0-8de7-53f59a71ff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725755922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2725755922
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.1581459082
Short name T966
Test name
Test status
Simulation time 208950951 ps
CPU time 5.27 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 207000 kb
Host smart-8580e923-29aa-42b0-a598-0eb90f3c4a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581459082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1581459082
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1895702539
Short name T275
Test name
Test status
Simulation time 65200157 ps
CPU time 2.91 seconds
Started Jun 01 03:06:30 PM PDT 24
Finished Jun 01 03:06:33 PM PDT 24
Peak memory 206548 kb
Host smart-7d5ea858-e472-4bb0-92c1-a93a696dd583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895702539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1895702539
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.381828207
Short name T348
Test name
Test status
Simulation time 394366942 ps
CPU time 6.36 seconds
Started Jun 01 03:06:30 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 208384 kb
Host smart-541fe447-60c4-4a15-9007-7460f8647ada
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381828207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.381828207
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1470359422
Short name T835
Test name
Test status
Simulation time 468940364 ps
CPU time 5.43 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:35 PM PDT 24
Peak memory 206692 kb
Host smart-d4d50c5f-c8de-4d4e-bbf3-81c199fd2932
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470359422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1470359422
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1468766038
Short name T602
Test name
Test status
Simulation time 1887799952 ps
CPU time 5.84 seconds
Started Jun 01 03:06:28 PM PDT 24
Finished Jun 01 03:06:34 PM PDT 24
Peak memory 207648 kb
Host smart-2fb5d9d2-e4b8-42ac-bdfe-3e48cae1e408
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468766038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1468766038
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2272347991
Short name T851
Test name
Test status
Simulation time 6395953984 ps
CPU time 48.12 seconds
Started Jun 01 03:06:35 PM PDT 24
Finished Jun 01 03:07:24 PM PDT 24
Peak memory 218116 kb
Host smart-ab910eab-27c4-4f3c-9b02-7047d5d3124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272347991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2272347991
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1152741065
Short name T697
Test name
Test status
Simulation time 210966274 ps
CPU time 2.57 seconds
Started Jun 01 03:06:30 PM PDT 24
Finished Jun 01 03:06:33 PM PDT 24
Peak memory 206604 kb
Host smart-30cdcb6c-69a5-4f16-b74c-998622b7aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152741065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1152741065
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1932633052
Short name T243
Test name
Test status
Simulation time 351847815 ps
CPU time 12.59 seconds
Started Jun 01 03:06:34 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 214468 kb
Host smart-2458df9d-32a6-4dde-85dc-d71131074512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932633052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1932633052
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2912933925
Short name T1022
Test name
Test status
Simulation time 1228484140 ps
CPU time 5.84 seconds
Started Jun 01 03:06:40 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 222276 kb
Host smart-65d9cf61-5912-4b9e-a4b2-ba3e03e60b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912933925 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2912933925
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3116220973
Short name T107
Test name
Test status
Simulation time 1133112717 ps
CPU time 8.02 seconds
Started Jun 01 03:06:29 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 213992 kb
Host smart-c17c28f4-94f1-4146-beac-21700ec897a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116220973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3116220973
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2479941606
Short name T605
Test name
Test status
Simulation time 60326449 ps
CPU time 2.61 seconds
Started Jun 01 03:06:35 PM PDT 24
Finished Jun 01 03:06:38 PM PDT 24
Peak memory 209960 kb
Host smart-334690b8-d8f2-4b6d-afc5-90cfb23712da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479941606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2479941606
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.578573921
Short name T1054
Test name
Test status
Simulation time 12819846 ps
CPU time 0.75 seconds
Started Jun 01 03:06:36 PM PDT 24
Finished Jun 01 03:06:37 PM PDT 24
Peak memory 205508 kb
Host smart-a86876a1-b6d7-45e3-9234-f9d09d0a1fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578573921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.578573921
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1221528094
Short name T372
Test name
Test status
Simulation time 491030225 ps
CPU time 4.63 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:06:44 PM PDT 24
Peak memory 216152 kb
Host smart-a4d407d9-4d39-4d02-bbcc-dca2022323ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221528094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1221528094
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3523862457
Short name T57
Test name
Test status
Simulation time 73429759 ps
CPU time 3.34 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:06:41 PM PDT 24
Peak memory 209708 kb
Host smart-572d01f1-fcfc-4d55-b684-090fab17a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523862457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3523862457
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3265325591
Short name T831
Test name
Test status
Simulation time 161108806 ps
CPU time 4.58 seconds
Started Jun 01 03:06:41 PM PDT 24
Finished Jun 01 03:06:45 PM PDT 24
Peak memory 209356 kb
Host smart-3be13c21-332e-4c07-9262-4c0f03dad30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265325591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3265325591
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.697750852
Short name T906
Test name
Test status
Simulation time 335804947 ps
CPU time 4.37 seconds
Started Jun 01 03:06:35 PM PDT 24
Finished Jun 01 03:06:40 PM PDT 24
Peak memory 209380 kb
Host smart-c9862c57-f1f7-410d-bca6-1166bd1715ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697750852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.697750852
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3096904027
Short name T693
Test name
Test status
Simulation time 136213920 ps
CPU time 2.25 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:06:40 PM PDT 24
Peak memory 210460 kb
Host smart-9ecb5b3b-cdd2-4c0b-b2a7-b7ef75538e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096904027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3096904027
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4138868885
Short name T143
Test name
Test status
Simulation time 154809310 ps
CPU time 4.31 seconds
Started Jun 01 03:06:38 PM PDT 24
Finished Jun 01 03:06:43 PM PDT 24
Peak memory 206848 kb
Host smart-fc884285-a669-41c8-93d9-7b43fd7da3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138868885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4138868885
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.452292937
Short name T1004
Test name
Test status
Simulation time 3251690295 ps
CPU time 32.27 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:07:11 PM PDT 24
Peak memory 208720 kb
Host smart-5917df73-a6aa-4ca4-8038-f6b580d3d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452292937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.452292937
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4124539200
Short name T924
Test name
Test status
Simulation time 1000883075 ps
CPU time 10.64 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:06:50 PM PDT 24
Peak memory 208468 kb
Host smart-9131f691-aea3-42c3-8a67-f7ef026e5cc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124539200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4124539200
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1679574021
Short name T1013
Test name
Test status
Simulation time 226994310 ps
CPU time 1.84 seconds
Started Jun 01 03:06:38 PM PDT 24
Finished Jun 01 03:06:40 PM PDT 24
Peak memory 206500 kb
Host smart-53e1169d-bcfb-4b54-ad44-514e26318684
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679574021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1679574021
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1900611351
Short name T1037
Test name
Test status
Simulation time 1142847857 ps
CPU time 4.49 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:06:44 PM PDT 24
Peak memory 208476 kb
Host smart-327a557b-a0ff-43b0-861a-ebf69275ca4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900611351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1900611351
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1503904640
Short name T919
Test name
Test status
Simulation time 51857525 ps
CPU time 2.56 seconds
Started Jun 01 03:06:36 PM PDT 24
Finished Jun 01 03:06:39 PM PDT 24
Peak memory 209396 kb
Host smart-7a80c19d-47f3-44f3-b12d-f146396f7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503904640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1503904640
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.4207212795
Short name T637
Test name
Test status
Simulation time 43803277 ps
CPU time 2.49 seconds
Started Jun 01 03:06:38 PM PDT 24
Finished Jun 01 03:06:41 PM PDT 24
Peak memory 208348 kb
Host smart-2fedebc3-7646-47bf-98b4-8deeaa4ab0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207212795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4207212795
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3699028352
Short name T52
Test name
Test status
Simulation time 973203050 ps
CPU time 33.4 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:07:11 PM PDT 24
Peak memory 222080 kb
Host smart-dbe78b51-dd6d-44e6-a103-abb074c7d9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699028352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3699028352
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1583545746
Short name T387
Test name
Test status
Simulation time 754232616 ps
CPU time 5.54 seconds
Started Jun 01 03:06:39 PM PDT 24
Finished Jun 01 03:06:45 PM PDT 24
Peak memory 222200 kb
Host smart-685e162a-0137-4477-88f8-1b6aa3020278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583545746 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1583545746
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3576943300
Short name T893
Test name
Test status
Simulation time 119876588 ps
CPU time 5.79 seconds
Started Jun 01 03:06:35 PM PDT 24
Finished Jun 01 03:06:41 PM PDT 24
Peak memory 209624 kb
Host smart-77606333-b3d4-46c2-8e8d-a2f15a5c2f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576943300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3576943300
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2889514128
Short name T593
Test name
Test status
Simulation time 54153030 ps
CPU time 2.11 seconds
Started Jun 01 03:06:40 PM PDT 24
Finished Jun 01 03:06:42 PM PDT 24
Peak memory 209640 kb
Host smart-d9af80bc-50e0-498a-91b9-7101844da100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889514128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2889514128
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3619739709
Short name T670
Test name
Test status
Simulation time 27154715 ps
CPU time 1.18 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:50 PM PDT 24
Peak memory 205708 kb
Host smart-a6c3baa2-f112-4312-9157-33084db7e49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619739709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3619739709
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2310097437
Short name T441
Test name
Test status
Simulation time 88795322 ps
CPU time 3.03 seconds
Started Jun 01 03:06:41 PM PDT 24
Finished Jun 01 03:06:44 PM PDT 24
Peak memory 214588 kb
Host smart-aed0e740-aa3c-488b-9ec3-0ccf4a6aeecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310097437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2310097437
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3498910760
Short name T250
Test name
Test status
Simulation time 233478862 ps
CPU time 3.16 seconds
Started Jun 01 03:06:47 PM PDT 24
Finished Jun 01 03:06:50 PM PDT 24
Peak memory 207940 kb
Host smart-eda39b59-ec45-49bb-bb9c-091104db5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498910760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3498910760
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1217461159
Short name T853
Test name
Test status
Simulation time 297514414 ps
CPU time 5.62 seconds
Started Jun 01 03:06:41 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 213988 kb
Host smart-43a3624e-6ec4-4c34-8255-dbfda123d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217461159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1217461159
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3870449279
Short name T1006
Test name
Test status
Simulation time 382311848 ps
CPU time 10.45 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:57 PM PDT 24
Peak memory 214028 kb
Host smart-776d0f69-b099-4747-9044-d58b8cd0b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870449279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3870449279
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.938410129
Short name T284
Test name
Test status
Simulation time 545661428 ps
CPU time 6.17 seconds
Started Jun 01 03:06:50 PM PDT 24
Finished Jun 01 03:06:56 PM PDT 24
Peak memory 222236 kb
Host smart-ae314264-bbc3-4dfa-814c-888ca0196a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938410129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.938410129
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4124513605
Short name T258
Test name
Test status
Simulation time 105600804 ps
CPU time 3.36 seconds
Started Jun 01 03:06:42 PM PDT 24
Finished Jun 01 03:06:46 PM PDT 24
Peak memory 213992 kb
Host smart-46c22c1f-2c0d-4a12-a883-4f014ab26c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124513605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4124513605
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3128244271
Short name T868
Test name
Test status
Simulation time 240143758 ps
CPU time 4.42 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:06:42 PM PDT 24
Peak memory 209320 kb
Host smart-6192fdb5-3301-45d9-9764-438d415cbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128244271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3128244271
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3030062224
Short name T214
Test name
Test status
Simulation time 3834192398 ps
CPU time 27.88 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:07:06 PM PDT 24
Peak memory 208180 kb
Host smart-389ec696-a2c3-43b7-aa04-7cc79ab51701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030062224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3030062224
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.294409480
Short name T802
Test name
Test status
Simulation time 157082117 ps
CPU time 4.14 seconds
Started Jun 01 03:06:41 PM PDT 24
Finished Jun 01 03:06:46 PM PDT 24
Peak memory 208240 kb
Host smart-60d1b194-f8c7-4206-93d8-84f384293280
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294409480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.294409480
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.899377272
Short name T435
Test name
Test status
Simulation time 596753262 ps
CPU time 4.86 seconds
Started Jun 01 03:06:36 PM PDT 24
Finished Jun 01 03:06:42 PM PDT 24
Peak memory 207716 kb
Host smart-b387f8f6-c722-4ca7-bf05-fd858456b320
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899377272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.899377272
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4004256773
Short name T765
Test name
Test status
Simulation time 151188003 ps
CPU time 2.46 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 215172 kb
Host smart-c9f19c38-7f79-4e20-b66d-2dc2d0be201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004256773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4004256773
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3991057490
Short name T85
Test name
Test status
Simulation time 4249639188 ps
CPU time 36.12 seconds
Started Jun 01 03:06:37 PM PDT 24
Finished Jun 01 03:07:14 PM PDT 24
Peak memory 208200 kb
Host smart-b6042e6c-cadd-4ddb-893b-6eea728d6d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991057490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3991057490
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2994150215
Short name T759
Test name
Test status
Simulation time 10134642382 ps
CPU time 70.35 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:07:56 PM PDT 24
Peak memory 209020 kb
Host smart-0e97444d-3ebe-4fb9-a85e-c6fdfe1981a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994150215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2994150215
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.907210269
Short name T646
Test name
Test status
Simulation time 2019791721 ps
CPU time 5.55 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 222096 kb
Host smart-5a2ea92d-3bfc-472c-bd18-26dd297b0f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907210269 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.907210269
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2875238570
Short name T987
Test name
Test status
Simulation time 112436978 ps
CPU time 5.19 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:53 PM PDT 24
Peak memory 208972 kb
Host smart-854257c6-1d6d-4283-96f4-b7ccdead8e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875238570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2875238570
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3664315134
Short name T110
Test name
Test status
Simulation time 109401665 ps
CPU time 2.11 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:49 PM PDT 24
Peak memory 210428 kb
Host smart-4c26b34c-8c76-4761-9dec-3fa9004fd710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664315134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3664315134
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3593970448
Short name T101
Test name
Test status
Simulation time 27822152 ps
CPU time 0.78 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:47 PM PDT 24
Peak memory 205588 kb
Host smart-378be433-381a-40d2-9851-b6fe38592f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593970448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3593970448
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3999605073
Short name T451
Test name
Test status
Simulation time 264104277 ps
CPU time 8.5 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:58 PM PDT 24
Peak memory 214744 kb
Host smart-93af54d8-9686-4050-965b-03c0aced4f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999605073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3999605073
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2817728649
Short name T876
Test name
Test status
Simulation time 1753080418 ps
CPU time 8.46 seconds
Started Jun 01 03:06:50 PM PDT 24
Finished Jun 01 03:06:59 PM PDT 24
Peak memory 216568 kb
Host smart-30e7decc-e7c1-4e21-bb7f-489b053bc60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817728649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2817728649
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.834936248
Short name T941
Test name
Test status
Simulation time 474951917 ps
CPU time 5.35 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:54 PM PDT 24
Peak memory 207448 kb
Host smart-6389d780-a55a-469b-a49b-0d9bba9b695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834936248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.834936248
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1709529335
Short name T37
Test name
Test status
Simulation time 126648417 ps
CPU time 5.87 seconds
Started Jun 01 03:06:50 PM PDT 24
Finished Jun 01 03:06:56 PM PDT 24
Peak memory 209840 kb
Host smart-ca3e6b4d-f188-4778-8e1d-1241f5a79c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709529335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1709529335
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3650087598
Short name T999
Test name
Test status
Simulation time 89654264 ps
CPU time 2.83 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 209520 kb
Host smart-f023f4a8-074b-4cb0-a557-0ee1ee474614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650087598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3650087598
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3838147256
Short name T215
Test name
Test status
Simulation time 135202052 ps
CPU time 4.66 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:53 PM PDT 24
Peak memory 207364 kb
Host smart-a865904e-fb4a-498c-83e1-ae0b25fbe9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838147256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3838147256
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2961230225
Short name T357
Test name
Test status
Simulation time 47812639 ps
CPU time 2.09 seconds
Started Jun 01 03:06:47 PM PDT 24
Finished Jun 01 03:06:50 PM PDT 24
Peak memory 208256 kb
Host smart-dc95d7ac-dca6-4655-b266-03e8f83babcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961230225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2961230225
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3702652334
Short name T1040
Test name
Test status
Simulation time 95460531 ps
CPU time 3.22 seconds
Started Jun 01 03:06:45 PM PDT 24
Finished Jun 01 03:06:49 PM PDT 24
Peak memory 206592 kb
Host smart-131d2cbb-aeda-4595-ab3d-03b5b6579bc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702652334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3702652334
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.726910852
Short name T566
Test name
Test status
Simulation time 70145891 ps
CPU time 3.15 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 206496 kb
Host smart-bf3ac412-8d69-446c-95ef-ee5b40908e0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726910852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.726910852
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2202274263
Short name T361
Test name
Test status
Simulation time 343917343 ps
CPU time 3.36 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:50 PM PDT 24
Peak memory 208152 kb
Host smart-f2614122-2122-49a2-b763-7649212830f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202274263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2202274263
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2821470871
Short name T292
Test name
Test status
Simulation time 149982613 ps
CPU time 4.55 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:53 PM PDT 24
Peak memory 209560 kb
Host smart-3e252704-7c91-4f1e-903a-be1157b083a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821470871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2821470871
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3146787204
Short name T956
Test name
Test status
Simulation time 140308993 ps
CPU time 2.84 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 208088 kb
Host smart-284ee27a-dfc5-48f8-ab61-457dc398670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146787204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3146787204
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.486876185
Short name T848
Test name
Test status
Simulation time 7264291213 ps
CPU time 25.96 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:07:13 PM PDT 24
Peak memory 215732 kb
Host smart-5ca1060b-8895-4ff6-afba-5a2ffd7be6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486876185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.486876185
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2216538507
Short name T907
Test name
Test status
Simulation time 71587827 ps
CPU time 2.19 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:48 PM PDT 24
Peak memory 222332 kb
Host smart-8c9b6d23-496a-4ac9-a91e-ca7838f8abbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216538507 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2216538507
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.778686837
Short name T811
Test name
Test status
Simulation time 3075990706 ps
CPU time 6.94 seconds
Started Jun 01 03:06:53 PM PDT 24
Finished Jun 01 03:07:01 PM PDT 24
Peak memory 210244 kb
Host smart-ba2cbd90-b280-4950-baf2-a9fe8a473888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778686837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.778686837
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1037090034
Short name T631
Test name
Test status
Simulation time 121170125 ps
CPU time 4.59 seconds
Started Jun 01 03:06:53 PM PDT 24
Finished Jun 01 03:06:58 PM PDT 24
Peak memory 210220 kb
Host smart-3afaa2ad-bcb4-4152-8505-d1b0192322c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037090034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1037090034
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2549285339
Short name T726
Test name
Test status
Simulation time 45510476 ps
CPU time 0.73 seconds
Started Jun 01 03:06:57 PM PDT 24
Finished Jun 01 03:06:58 PM PDT 24
Peak memory 205508 kb
Host smart-1a338177-d777-4035-a02a-d31791ff9c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549285339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2549285339
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1650043944
Short name T122
Test name
Test status
Simulation time 37240648 ps
CPU time 3.14 seconds
Started Jun 01 03:06:56 PM PDT 24
Finished Jun 01 03:06:59 PM PDT 24
Peak memory 213884 kb
Host smart-696c88fc-4723-4f24-84bd-69d2e3f34f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650043944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1650043944
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1912902609
Short name T1007
Test name
Test status
Simulation time 290918390 ps
CPU time 3.81 seconds
Started Jun 01 03:06:58 PM PDT 24
Finished Jun 01 03:07:02 PM PDT 24
Peak memory 209820 kb
Host smart-106d5ce3-377a-4878-a4c7-ee9270b76d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912902609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1912902609
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.429270431
Short name T746
Test name
Test status
Simulation time 555932997 ps
CPU time 4.59 seconds
Started Jun 01 03:06:53 PM PDT 24
Finished Jun 01 03:06:58 PM PDT 24
Peak memory 213956 kb
Host smart-06754c64-2513-49af-a518-cd2c433655c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429270431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.429270431
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.384599085
Short name T327
Test name
Test status
Simulation time 180764952 ps
CPU time 4.45 seconds
Started Jun 01 03:06:56 PM PDT 24
Finished Jun 01 03:07:01 PM PDT 24
Peak memory 211360 kb
Host smart-ebf1eb2f-4a15-4656-88ef-08f016100789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384599085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.384599085
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2912569300
Short name T55
Test name
Test status
Simulation time 87657669 ps
CPU time 3.72 seconds
Started Jun 01 03:06:58 PM PDT 24
Finished Jun 01 03:07:02 PM PDT 24
Peak memory 209328 kb
Host smart-34576d6a-2d50-401e-a5b6-19e22e08a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912569300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2912569300
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1239964388
Short name T634
Test name
Test status
Simulation time 952775203 ps
CPU time 9.73 seconds
Started Jun 01 03:06:56 PM PDT 24
Finished Jun 01 03:07:06 PM PDT 24
Peak memory 208564 kb
Host smart-b80ec222-0b77-400a-853d-033df4f8477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239964388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1239964388
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.627172038
Short name T15
Test name
Test status
Simulation time 931270417 ps
CPU time 10.36 seconds
Started Jun 01 03:06:46 PM PDT 24
Finished Jun 01 03:06:57 PM PDT 24
Peak memory 206388 kb
Host smart-b5c7aedb-8069-4c5b-9540-e9e87c38e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627172038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.627172038
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1332046079
Short name T709
Test name
Test status
Simulation time 167482134 ps
CPU time 2.44 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:51 PM PDT 24
Peak memory 206656 kb
Host smart-8bd75c37-dbcf-4a17-b2f3-76d16ebea0df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332046079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1332046079
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1341186032
Short name T649
Test name
Test status
Simulation time 200775432 ps
CPU time 5.46 seconds
Started Jun 01 03:06:47 PM PDT 24
Finished Jun 01 03:06:53 PM PDT 24
Peak memory 208248 kb
Host smart-67dd313f-6c2e-4596-a4a7-f7aa269f485a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341186032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1341186032
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4001095487
Short name T1020
Test name
Test status
Simulation time 106781950 ps
CPU time 2.97 seconds
Started Jun 01 03:06:48 PM PDT 24
Finished Jun 01 03:06:52 PM PDT 24
Peak memory 208224 kb
Host smart-786d182f-d0ab-4578-84da-3e995ca26db3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001095487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4001095487
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1452778287
Short name T114
Test name
Test status
Simulation time 297179791 ps
CPU time 5.69 seconds
Started Jun 01 03:06:54 PM PDT 24
Finished Jun 01 03:07:00 PM PDT 24
Peak memory 222180 kb
Host smart-b481f578-5be7-481c-962c-c6b8c4ab2f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452778287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1452778287
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1329539472
Short name T142
Test name
Test status
Simulation time 89898914 ps
CPU time 1.92 seconds
Started Jun 01 03:06:49 PM PDT 24
Finished Jun 01 03:06:51 PM PDT 24
Peak memory 207056 kb
Host smart-6fb939c0-81d1-4b21-bcd2-a90b25f89e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329539472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1329539472
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2738063328
Short name T65
Test name
Test status
Simulation time 538447621 ps
CPU time 15.45 seconds
Started Jun 01 03:06:57 PM PDT 24
Finished Jun 01 03:07:14 PM PDT 24
Peak memory 216000 kb
Host smart-373f5e11-3ee8-4a18-9863-594d040dae69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738063328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2738063328
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.55085485
Short name T240
Test name
Test status
Simulation time 1032408810 ps
CPU time 16.93 seconds
Started Jun 01 03:06:55 PM PDT 24
Finished Jun 01 03:07:12 PM PDT 24
Peak memory 222344 kb
Host smart-c8626a5f-39aa-4d00-9891-dc32fd411d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55085485 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.55085485
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3228262810
Short name T378
Test name
Test status
Simulation time 21006412557 ps
CPU time 65.37 seconds
Started Jun 01 03:06:55 PM PDT 24
Finished Jun 01 03:08:01 PM PDT 24
Peak memory 209192 kb
Host smart-2bc1b8c5-bbd6-4b7f-b8d1-99a255776da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228262810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3228262810
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3191298134
Short name T675
Test name
Test status
Simulation time 586273230 ps
CPU time 12.01 seconds
Started Jun 01 03:06:58 PM PDT 24
Finished Jun 01 03:07:11 PM PDT 24
Peak memory 210684 kb
Host smart-6e4b3880-0b66-439a-8869-5ebbd2bfe4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191298134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3191298134
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.177398122
Short name T926
Test name
Test status
Simulation time 9195961 ps
CPU time 0.81 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:25 PM PDT 24
Peak memory 205572 kb
Host smart-005afcb7-316b-4bce-b0ed-8c3d637d76e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177398122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.177398122
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3075372649
Short name T319
Test name
Test status
Simulation time 69019116 ps
CPU time 4.51 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:30 PM PDT 24
Peak memory 214904 kb
Host smart-7a27838f-efab-4972-a113-75a71ad80881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075372649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3075372649
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2354655283
Short name T26
Test name
Test status
Simulation time 183010113 ps
CPU time 2.84 seconds
Started Jun 01 03:03:26 PM PDT 24
Finished Jun 01 03:03:29 PM PDT 24
Peak memory 217160 kb
Host smart-8af7ef49-f3b6-4929-90c5-791ca1b7218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354655283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2354655283
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.249853361
Short name T264
Test name
Test status
Simulation time 131549518 ps
CPU time 1.94 seconds
Started Jun 01 03:03:26 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 206832 kb
Host smart-00f5ca74-0337-4a3d-8794-26726985e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249853361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.249853361
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1082160787
Short name T23
Test name
Test status
Simulation time 181621596 ps
CPU time 5.51 seconds
Started Jun 01 03:03:26 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 208892 kb
Host smart-a7da56bc-5f9d-4655-b1a9-e8f2a1cae00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082160787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1082160787
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.462630058
Short name T384
Test name
Test status
Simulation time 310500745 ps
CPU time 4.18 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 222088 kb
Host smart-dbaa4760-11a4-47dc-8e5b-a6955af96756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462630058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.462630058
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3212129007
Short name T60
Test name
Test status
Simulation time 93704223 ps
CPU time 2.61 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 209912 kb
Host smart-f755cca1-bf5b-43c5-9ac6-8d07f271e629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212129007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3212129007
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1322429215
Short name T986
Test name
Test status
Simulation time 1006706102 ps
CPU time 22.93 seconds
Started Jun 01 03:03:23 PM PDT 24
Finished Jun 01 03:03:47 PM PDT 24
Peak memory 208336 kb
Host smart-a27ebc94-1bad-4660-aa2d-254f98d7f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322429215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1322429215
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2160794686
Short name T16
Test name
Test status
Simulation time 141648812 ps
CPU time 3.12 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 206308 kb
Host smart-7b7f1fc5-f83c-47f4-9e94-7f6313894e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160794686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2160794686
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.835853889
Short name T399
Test name
Test status
Simulation time 233676144 ps
CPU time 3.99 seconds
Started Jun 01 03:03:27 PM PDT 24
Finished Jun 01 03:03:32 PM PDT 24
Peak memory 208320 kb
Host smart-35c0a1a1-0271-42c3-b0de-c184d022fe05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835853889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.835853889
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1303308752
Short name T1005
Test name
Test status
Simulation time 393794081 ps
CPU time 9.81 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:34 PM PDT 24
Peak memory 208260 kb
Host smart-dbbafde2-7fec-44f8-ab8f-debd5ddc5c28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303308752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1303308752
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2752838473
Short name T144
Test name
Test status
Simulation time 128375290 ps
CPU time 3.59 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 207864 kb
Host smart-6b382e33-98b3-4532-a2d9-101baef59cd9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752838473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2752838473
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2227072603
Short name T946
Test name
Test status
Simulation time 7112913163 ps
CPU time 34.48 seconds
Started Jun 01 03:03:21 PM PDT 24
Finished Jun 01 03:03:56 PM PDT 24
Peak memory 208080 kb
Host smart-35ac5b82-045d-40f6-933e-ec1b16a947b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227072603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2227072603
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2787503196
Short name T878
Test name
Test status
Simulation time 3070519793 ps
CPU time 15.21 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:40 PM PDT 24
Peak memory 222228 kb
Host smart-182a76b8-997c-42cb-ba20-ccb4fc9772ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787503196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2787503196
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1844226498
Short name T295
Test name
Test status
Simulation time 397514470 ps
CPU time 6.48 seconds
Started Jun 01 03:03:22 PM PDT 24
Finished Jun 01 03:03:28 PM PDT 24
Peak memory 207296 kb
Host smart-19606609-6b41-4c6d-b1c4-f82c81f58c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844226498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1844226498
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4104417904
Short name T234
Test name
Test status
Simulation time 146339311 ps
CPU time 3.96 seconds
Started Jun 01 03:03:26 PM PDT 24
Finished Jun 01 03:03:31 PM PDT 24
Peak memory 210128 kb
Host smart-24bdbdbd-26c5-4aba-8f5c-9cce84d3403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104417904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4104417904
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4083981171
Short name T627
Test name
Test status
Simulation time 49644753 ps
CPU time 0.8 seconds
Started Jun 01 03:03:34 PM PDT 24
Finished Jun 01 03:03:36 PM PDT 24
Peak memory 205504 kb
Host smart-8001492d-eafe-463c-8a63-3672477442ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083981171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4083981171
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1117497024
Short name T458
Test name
Test status
Simulation time 334212671 ps
CPU time 5.82 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:45 PM PDT 24
Peak memory 222188 kb
Host smart-c3ae4a3d-0ad9-46e0-bc8b-d9384295c186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117497024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1117497024
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2228018052
Short name T71
Test name
Test status
Simulation time 19001315 ps
CPU time 1.31 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:37 PM PDT 24
Peak memory 208260 kb
Host smart-9edc314b-fba8-47dd-ac62-0bfda5b9ffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228018052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2228018052
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1202570599
Short name T816
Test name
Test status
Simulation time 76998144 ps
CPU time 3.46 seconds
Started Jun 01 03:03:33 PM PDT 24
Finished Jun 01 03:03:37 PM PDT 24
Peak memory 208132 kb
Host smart-2fd84bc2-0312-4431-a632-06d9b2b588ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202570599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1202570599
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.687819592
Short name T674
Test name
Test status
Simulation time 434961811 ps
CPU time 3.58 seconds
Started Jun 01 03:03:31 PM PDT 24
Finished Jun 01 03:03:35 PM PDT 24
Peak memory 209556 kb
Host smart-928d938b-04a7-41a0-9438-8a3351758599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687819592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.687819592
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1075798357
Short name T657
Test name
Test status
Simulation time 79878763 ps
CPU time 4.33 seconds
Started Jun 01 03:03:31 PM PDT 24
Finished Jun 01 03:03:36 PM PDT 24
Peak memory 209004 kb
Host smart-ccf4ec7f-5ae8-46a3-bad2-32cf5ddcccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075798357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1075798357
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2306231317
Short name T1056
Test name
Test status
Simulation time 803776969 ps
CPU time 6.98 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:31 PM PDT 24
Peak memory 208284 kb
Host smart-0d818e79-0df1-4a54-819b-74667ab3ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306231317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2306231317
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.850990307
Short name T567
Test name
Test status
Simulation time 335575407 ps
CPU time 2.7 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 206284 kb
Host smart-b5c27157-c136-45cf-a8dd-2915f85f0f13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850990307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.850990307
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2013404203
Short name T879
Test name
Test status
Simulation time 2812148983 ps
CPU time 20.87 seconds
Started Jun 01 03:03:25 PM PDT 24
Finished Jun 01 03:03:47 PM PDT 24
Peak memory 208384 kb
Host smart-0a5e7acc-4353-43f0-8738-65f252399f31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013404203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2013404203
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2410098016
Short name T727
Test name
Test status
Simulation time 43590755 ps
CPU time 2.59 seconds
Started Jun 01 03:03:28 PM PDT 24
Finished Jun 01 03:03:31 PM PDT 24
Peak memory 206500 kb
Host smart-c64353ea-df13-42f8-a1a6-dd30147d8843
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410098016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2410098016
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3524657467
Short name T827
Test name
Test status
Simulation time 69571483 ps
CPU time 2.77 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 218068 kb
Host smart-389bff6e-fdd7-48ed-8265-18e3af1c3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524657467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3524657467
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2852606623
Short name T797
Test name
Test status
Simulation time 70818683 ps
CPU time 3.06 seconds
Started Jun 01 03:03:24 PM PDT 24
Finished Jun 01 03:03:27 PM PDT 24
Peak memory 208028 kb
Host smart-f26b7538-dec2-4782-8654-68c46a602ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852606623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2852606623
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2405021397
Short name T692
Test name
Test status
Simulation time 1184901652 ps
CPU time 12.21 seconds
Started Jun 01 03:03:30 PM PDT 24
Finished Jun 01 03:03:43 PM PDT 24
Peak memory 219684 kb
Host smart-58a07966-76fb-4dfb-bf67-70fe98c9dd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405021397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2405021397
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3624147455
Short name T842
Test name
Test status
Simulation time 336534316 ps
CPU time 5.51 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 222424 kb
Host smart-62466a14-4d83-4724-885f-2219b65cfbd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624147455 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3624147455
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1617746129
Short name T967
Test name
Test status
Simulation time 220568207 ps
CPU time 3.35 seconds
Started Jun 01 03:03:29 PM PDT 24
Finished Jun 01 03:03:33 PM PDT 24
Peak memory 206936 kb
Host smart-6703fab7-bc1c-4f61-8c28-76be3cfcfcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617746129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1617746129
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3206277406
Short name T1018
Test name
Test status
Simulation time 405549682 ps
CPU time 2.52 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 210032 kb
Host smart-28b5f198-503e-4f4a-9b45-e386fbb5e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206277406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3206277406
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4074180399
Short name T582
Test name
Test status
Simulation time 13321592 ps
CPU time 0.81 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:36 PM PDT 24
Peak memory 205488 kb
Host smart-dcf7ce24-598d-4af1-aa03-85fa3305dfb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074180399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4074180399
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1721958495
Short name T270
Test name
Test status
Simulation time 39205194 ps
CPU time 2.8 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:39 PM PDT 24
Peak memory 213976 kb
Host smart-053ea58d-4b61-4e02-9600-19474f7dd0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721958495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1721958495
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1756488214
Short name T885
Test name
Test status
Simulation time 336568730 ps
CPU time 4.48 seconds
Started Jun 01 03:03:30 PM PDT 24
Finished Jun 01 03:03:35 PM PDT 24
Peak memory 222536 kb
Host smart-05804b3c-ce01-4b3e-a1c3-90446e2065a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756488214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1756488214
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1181442780
Short name T955
Test name
Test status
Simulation time 2940710556 ps
CPU time 31.39 seconds
Started Jun 01 03:03:34 PM PDT 24
Finished Jun 01 03:04:06 PM PDT 24
Peak memory 208800 kb
Host smart-dc7c7a29-37a7-40bd-8dd4-e17f3d19ac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181442780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1181442780
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2039254396
Short name T983
Test name
Test status
Simulation time 2158362101 ps
CPU time 46.54 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:04:25 PM PDT 24
Peak memory 214100 kb
Host smart-3cb985c8-1468-4187-ac2e-39199f20356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039254396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2039254396
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3702402511
Short name T282
Test name
Test status
Simulation time 80890042 ps
CPU time 3.15 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:39 PM PDT 24
Peak memory 219880 kb
Host smart-78a55f53-2717-4de3-a330-32ed854c4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702402511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3702402511
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1952017358
Short name T989
Test name
Test status
Simulation time 94423435 ps
CPU time 2.83 seconds
Started Jun 01 03:03:31 PM PDT 24
Finished Jun 01 03:03:34 PM PDT 24
Peak memory 213964 kb
Host smart-b48d53e6-7076-4318-bdad-37386db2566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952017358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1952017358
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2789829654
Short name T909
Test name
Test status
Simulation time 134011647 ps
CPU time 4.22 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:43 PM PDT 24
Peak memory 206776 kb
Host smart-ea4e495c-e2a9-4c9d-841a-e4517247327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789829654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2789829654
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1678161267
Short name T648
Test name
Test status
Simulation time 260572454 ps
CPU time 2.89 seconds
Started Jun 01 03:03:30 PM PDT 24
Finished Jun 01 03:03:33 PM PDT 24
Peak memory 206540 kb
Host smart-bcf960f8-0530-432e-a12a-f614422566e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678161267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1678161267
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2196360080
Short name T1051
Test name
Test status
Simulation time 277585398 ps
CPU time 3.17 seconds
Started Jun 01 03:03:29 PM PDT 24
Finished Jun 01 03:03:33 PM PDT 24
Peak memory 208412 kb
Host smart-9a1ec1f6-d7f2-43a4-bcc1-1c31e7bc4d64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196360080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2196360080
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3030133750
Short name T666
Test name
Test status
Simulation time 678382731 ps
CPU time 4.62 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 208536 kb
Host smart-0cb4086b-1195-44b3-9c3c-4cd53e1d06bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030133750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3030133750
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3008059445
Short name T740
Test name
Test status
Simulation time 237622723 ps
CPU time 7.55 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:46 PM PDT 24
Peak memory 206580 kb
Host smart-476c6632-2a8f-4c50-8130-0c7a195e66cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008059445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3008059445
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1418013354
Short name T969
Test name
Test status
Simulation time 229901707 ps
CPU time 4.68 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:43 PM PDT 24
Peak memory 217668 kb
Host smart-dd8c44fa-fd41-4a4d-b469-8e6c18518a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418013354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1418013354
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3674045352
Short name T428
Test name
Test status
Simulation time 45254092 ps
CPU time 2.37 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:38 PM PDT 24
Peak memory 206496 kb
Host smart-c4081a94-a671-441a-a57e-0d07b8f899dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674045352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3674045352
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3419563906
Short name T844
Test name
Test status
Simulation time 235882621 ps
CPU time 9.76 seconds
Started Jun 01 03:03:33 PM PDT 24
Finished Jun 01 03:03:44 PM PDT 24
Peak memory 222316 kb
Host smart-d1e69ddd-687d-4d6c-bade-86b00b5ae425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419563906 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3419563906
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.69537108
Short name T380
Test name
Test status
Simulation time 1616361455 ps
CPU time 54.51 seconds
Started Jun 01 03:03:34 PM PDT 24
Finished Jun 01 03:04:30 PM PDT 24
Peak memory 219440 kb
Host smart-35b7530d-84f0-4e48-a57c-0cfbc6be0bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69537108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.69537108
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3451098377
Short name T181
Test name
Test status
Simulation time 32211936 ps
CPU time 1.67 seconds
Started Jun 01 03:03:35 PM PDT 24
Finished Jun 01 03:03:38 PM PDT 24
Peak memory 209764 kb
Host smart-9757e9a4-f057-4e45-a745-e823dfc5cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451098377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3451098377
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2739988179
Short name T708
Test name
Test status
Simulation time 22459966 ps
CPU time 1 seconds
Started Jun 01 03:03:39 PM PDT 24
Finished Jun 01 03:03:40 PM PDT 24
Peak memory 205720 kb
Host smart-980a8a66-8b52-4f41-af78-f4bcaf84c560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739988179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2739988179
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4145841961
Short name T457
Test name
Test status
Simulation time 40762452 ps
CPU time 3.16 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:42 PM PDT 24
Peak memory 214812 kb
Host smart-c1218995-bceb-419c-9284-62487ab8e69f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145841961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4145841961
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1268224160
Short name T863
Test name
Test status
Simulation time 346067706 ps
CPU time 5.93 seconds
Started Jun 01 03:03:43 PM PDT 24
Finished Jun 01 03:03:50 PM PDT 24
Peak memory 221216 kb
Host smart-a77b2404-21dd-41a4-8b15-30ec13669c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268224160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1268224160
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.438648141
Short name T678
Test name
Test status
Simulation time 84472928 ps
CPU time 2.92 seconds
Started Jun 01 03:03:36 PM PDT 24
Finished Jun 01 03:03:40 PM PDT 24
Peak memory 208200 kb
Host smart-1d8ad893-e6e3-4ed8-8339-092bf3de261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438648141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.438648141
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2528753319
Short name T105
Test name
Test status
Simulation time 116927437 ps
CPU time 4.73 seconds
Started Jun 01 03:03:42 PM PDT 24
Finished Jun 01 03:03:47 PM PDT 24
Peak memory 214112 kb
Host smart-c1c0fcd6-f341-47cc-9c58-5a55244e92c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528753319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2528753319
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3684603833
Short name T383
Test name
Test status
Simulation time 163245445 ps
CPU time 4.51 seconds
Started Jun 01 03:03:39 PM PDT 24
Finished Jun 01 03:03:44 PM PDT 24
Peak memory 222040 kb
Host smart-a80c1301-b586-473b-a2a2-15ea69fcc37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684603833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3684603833
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2532111021
Short name T595
Test name
Test status
Simulation time 411371440 ps
CPU time 4.5 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:43 PM PDT 24
Peak memory 213948 kb
Host smart-9f344326-7f80-452b-9228-57e4486a54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532111021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2532111021
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.309362460
Short name T790
Test name
Test status
Simulation time 183402935 ps
CPU time 6.62 seconds
Started Jun 01 03:03:41 PM PDT 24
Finished Jun 01 03:03:48 PM PDT 24
Peak memory 207184 kb
Host smart-cce7e05c-a0e0-49d9-878f-7bc87b8fa509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309362460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.309362460
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1449749960
Short name T262
Test name
Test status
Simulation time 1046581678 ps
CPU time 8.25 seconds
Started Jun 01 03:03:31 PM PDT 24
Finished Jun 01 03:03:40 PM PDT 24
Peak memory 208060 kb
Host smart-5f94bcc7-39b7-4942-abfc-8b7c0eb06b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449749960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1449749960
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2654169741
Short name T614
Test name
Test status
Simulation time 3987716248 ps
CPU time 25.35 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:04:05 PM PDT 24
Peak memory 207864 kb
Host smart-4e1393d4-2c21-493b-84e1-53a1bd234392
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654169741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2654169741
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.888461197
Short name T819
Test name
Test status
Simulation time 420426788 ps
CPU time 2.9 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 206600 kb
Host smart-1ac81c7f-8e1b-4cdb-a4c8-73a5c612e4db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888461197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.888461197
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2981907590
Short name T803
Test name
Test status
Simulation time 4310623960 ps
CPU time 53.35 seconds
Started Jun 01 03:03:37 PM PDT 24
Finished Jun 01 03:04:30 PM PDT 24
Peak memory 206712 kb
Host smart-eeed8f14-bb5e-4438-9a23-04301cfa7f99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981907590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2981907590
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3482350937
Short name T1016
Test name
Test status
Simulation time 133453389 ps
CPU time 3.74 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:42 PM PDT 24
Peak memory 213908 kb
Host smart-a1beac69-79c5-4e8e-8349-84e6b784e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482350937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3482350937
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4085218973
Short name T1001
Test name
Test status
Simulation time 1125060863 ps
CPU time 5.59 seconds
Started Jun 01 03:03:30 PM PDT 24
Finished Jun 01 03:03:36 PM PDT 24
Peak memory 208300 kb
Host smart-1d814487-ab29-46c2-9e78-d618bf2758c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085218973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4085218973
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3258402738
Short name T635
Test name
Test status
Simulation time 252710740 ps
CPU time 8.48 seconds
Started Jun 01 03:03:43 PM PDT 24
Finished Jun 01 03:03:52 PM PDT 24
Peak memory 222276 kb
Host smart-cb7e7d1f-7535-40a6-b39d-72782981926f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258402738 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3258402738
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.110383885
Short name T221
Test name
Test status
Simulation time 73598141 ps
CPU time 3.6 seconds
Started Jun 01 03:03:41 PM PDT 24
Finished Jun 01 03:03:45 PM PDT 24
Peak memory 208816 kb
Host smart-de0ff176-44d1-4f4f-a962-f457547cfa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110383885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.110383885
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.624301527
Short name T1003
Test name
Test status
Simulation time 46588175 ps
CPU time 2.22 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 209804 kb
Host smart-7714bb5e-ce59-43d2-b743-2e69781b1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624301527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.624301527
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.708414985
Short name T633
Test name
Test status
Simulation time 41562553 ps
CPU time 0.83 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:48 PM PDT 24
Peak memory 205584 kb
Host smart-75aa7777-f39b-4ba5-9029-bfde0b7b7ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708414985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.708414985
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1825925450
Short name T391
Test name
Test status
Simulation time 1501072738 ps
CPU time 87.23 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:05:14 PM PDT 24
Peak memory 222288 kb
Host smart-4ba1e6be-56d6-4384-bdf6-30ad89a89cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825925450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1825925450
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1579565892
Short name T11
Test name
Test status
Simulation time 372056182 ps
CPU time 15.93 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:04:03 PM PDT 24
Peak memory 222500 kb
Host smart-59fee52c-3651-45a5-a427-de1afc2568ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579565892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1579565892
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1793479305
Short name T880
Test name
Test status
Simulation time 103074431 ps
CPU time 2.83 seconds
Started Jun 01 03:03:45 PM PDT 24
Finished Jun 01 03:03:49 PM PDT 24
Peak memory 206392 kb
Host smart-71e70650-b829-42e1-bbe6-b40d770b26f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793479305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1793479305
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3042971122
Short name T90
Test name
Test status
Simulation time 774938232 ps
CPU time 6.28 seconds
Started Jun 01 03:03:45 PM PDT 24
Finished Jun 01 03:03:52 PM PDT 24
Peak memory 218812 kb
Host smart-af796f4f-129d-4438-8fe1-abdc7639f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042971122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3042971122
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1173881869
Short name T304
Test name
Test status
Simulation time 216993878 ps
CPU time 5.2 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:52 PM PDT 24
Peak memory 210760 kb
Host smart-e7adc36c-4dd0-4367-9181-78bc69a2f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173881869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1173881869
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1266779454
Short name T641
Test name
Test status
Simulation time 183735065 ps
CPU time 4.16 seconds
Started Jun 01 03:03:48 PM PDT 24
Finished Jun 01 03:03:53 PM PDT 24
Peak memory 208704 kb
Host smart-0c9e71a8-fa13-47fb-b965-fdb5472f87a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266779454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1266779454
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1209136793
Short name T685
Test name
Test status
Simulation time 788734778 ps
CPU time 22.79 seconds
Started Jun 01 03:03:48 PM PDT 24
Finished Jun 01 03:04:11 PM PDT 24
Peak memory 207588 kb
Host smart-17f630fa-d1be-4486-a636-577b1caa23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209136793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1209136793
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3601265867
Short name T300
Test name
Test status
Simulation time 104799911 ps
CPU time 2.22 seconds
Started Jun 01 03:03:38 PM PDT 24
Finished Jun 01 03:03:41 PM PDT 24
Peak memory 208180 kb
Host smart-8f1955cf-82ad-4f12-a865-6013f6aae4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601265867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3601265867
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1466164550
Short name T972
Test name
Test status
Simulation time 234680099 ps
CPU time 3.28 seconds
Started Jun 01 03:03:45 PM PDT 24
Finished Jun 01 03:03:49 PM PDT 24
Peak memory 206524 kb
Host smart-19a8754c-6975-4988-aa48-664d2c147f77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466164550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1466164550
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2144833131
Short name T716
Test name
Test status
Simulation time 1855080234 ps
CPU time 28.62 seconds
Started Jun 01 03:03:43 PM PDT 24
Finished Jun 01 03:04:12 PM PDT 24
Peak memory 207836 kb
Host smart-9339cb22-6041-4cff-b4cf-45cc7c3c365c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144833131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2144833131
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1467816420
Short name T366
Test name
Test status
Simulation time 578798749 ps
CPU time 3.68 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:50 PM PDT 24
Peak memory 206564 kb
Host smart-5b2154ea-3411-4f52-aa5e-ad7f9c0693be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467816420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1467816420
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2897143313
Short name T600
Test name
Test status
Simulation time 93659688 ps
CPU time 2.05 seconds
Started Jun 01 03:03:46 PM PDT 24
Finished Jun 01 03:03:49 PM PDT 24
Peak memory 207536 kb
Host smart-d27944a6-5a89-45bb-b06e-a729eee77b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897143313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2897143313
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1480831318
Short name T829
Test name
Test status
Simulation time 58284818 ps
CPU time 2.94 seconds
Started Jun 01 03:03:43 PM PDT 24
Finished Jun 01 03:03:46 PM PDT 24
Peak memory 206528 kb
Host smart-5008a72b-cc9a-40ce-af0f-2cb97e66ff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480831318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1480831318
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2248058678
Short name T63
Test name
Test status
Simulation time 1163767867 ps
CPU time 13.71 seconds
Started Jun 01 03:03:50 PM PDT 24
Finished Jun 01 03:04:04 PM PDT 24
Peak memory 222272 kb
Host smart-35a3491f-ef4f-4307-8ed4-55e5ee875f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248058678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2248058678
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2002562945
Short name T927
Test name
Test status
Simulation time 1012534885 ps
CPU time 7.35 seconds
Started Jun 01 03:03:47 PM PDT 24
Finished Jun 01 03:03:54 PM PDT 24
Peak memory 222332 kb
Host smart-c3bf1b1a-4122-4c13-9126-050bf9d6aa27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002562945 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2002562945
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2636196552
Short name T936
Test name
Test status
Simulation time 415828159 ps
CPU time 11.06 seconds
Started Jun 01 03:03:48 PM PDT 24
Finished Jun 01 03:03:59 PM PDT 24
Peak memory 214112 kb
Host smart-9a3d7238-cbf0-4d74-82aa-deffc39b6446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636196552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2636196552
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2867289830
Short name T839
Test name
Test status
Simulation time 49625523 ps
CPU time 2.67 seconds
Started Jun 01 03:03:47 PM PDT 24
Finished Jun 01 03:03:50 PM PDT 24
Peak memory 209864 kb
Host smart-f06600cd-5938-4843-a294-064d50d8bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867289830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2867289830
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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