Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
76.19 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 0 14 100.00
Crosses 49 15 34 69.39


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 0 5 100.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 14 21 60.00 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 74 1 T34 1 T44 1 T106 3
auto[OpGenId] 16 1 T56 1 T197 1 T211 1
auto[OpGenSwOut] 29 1 T109 2 T197 2 T212 1
auto[OpGenHwOut] 15 1 T28 1 T47 1 T48 1
auto[OpDisable] 1 1 T213 1 - - - -


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1593 1 T106 3 T27 1 T107 5
auto[StInit] 153 1 T13 1 T34 1 T44 1
auto[StCreatorRootKey] 46 1 T25 1 T106 1 T29 1
auto[StOwnerIntKey] 35 1 T33 1 T61 1 T39 1
auto[StOwnerKey] 31 1 T106 1 T45 1 T18 1
auto[StDisabled] 333 1 T69 1 T70 1 T107 2
auto[StInvalid] 43 1 T21 1 T35 1 T93 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3162 1 T1 1 T2 1 T3 1
auto[1] 135 1 T34 1 T44 1 T106 3


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1574 1 T106 1 T107 5 T109 6
auto[StReset] auto[1] 19 1 T106 2 T27 1 T54 2
auto[StInit] auto[0] 78 1 T13 1 T107 1 T109 2
auto[StInit] auto[1] 75 1 T34 1 T44 1 T28 1
auto[StCreatorRootKey] auto[0] 34 1 T25 1 T106 1 T29 1
auto[StCreatorRootKey] auto[1] 12 1 T56 1 T38 1 T47 1
auto[StOwnerIntKey] auto[0] 24 1 T33 1 T61 1 T209 1
auto[StOwnerIntKey] auto[1] 11 1 T39 1 T197 2 T48 1
auto[StOwnerKey] auto[0] 23 1 T18 1 T64 1 T67 1
auto[StOwnerKey] auto[1] 8 1 T106 1 T45 1 T46 1
auto[StDisabled] auto[0] 323 1 T69 1 T70 1 T107 2
auto[StDisabled] auto[1] 10 1 T58 1 T214 1 T75 1
auto[StInvalid] auto[0] 43 1 T21 1 T35 1 T93 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 14 21 60.00 14


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId]] 0 1 1
[auto[StReset]] [auto[OpGenHwOut] , auto[OpDisable]] -- -- 2
[auto[StCreatorRootKey] , auto[StOwnerIntKey]] [auto[OpDisable]] -- -- 2
[auto[StOwnerKey]] [auto[OpGenSwOut]] 0 1 1
[auto[StOwnerKey]] [auto[OpDisable]] 0 1 1
[auto[StDisabled]] [auto[OpGenHwOut] , auto[OpDisable]] -- -- 2


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 18 1 T106 2 T27 1 T54 2
auto[StReset] auto[OpGenSwOut] 1 1 T215 1 - - - -
auto[StInit] auto[OpAdvance] 37 1 T34 1 T44 1 T107 1
auto[StInit] auto[OpGenId] 6 1 T211 1 T216 1 T217 1
auto[StInit] auto[OpGenSwOut] 21 1 T109 2 T197 1 T212 1
auto[StInit] auto[OpGenHwOut] 10 1 T28 1 T49 1 T218 1
auto[StInit] auto[OpDisable] 1 1 T213 1 - - - -
auto[StCreatorRootKey] auto[OpAdvance] 4 1 T38 1 T58 1 T219 1
auto[StCreatorRootKey] auto[OpGenId] 4 1 T56 1 T220 1 T221 1
auto[StCreatorRootKey] auto[OpGenSwOut] 2 1 T213 1 T222 1 - -
auto[StCreatorRootKey] auto[OpGenHwOut] 2 1 T47 1 T223 1 - -
auto[StOwnerIntKey] auto[OpAdvance] 3 1 T39 1 T224 1 T225 1
auto[StOwnerIntKey] auto[OpGenId] 3 1 T197 1 T63 1 T226 1
auto[StOwnerIntKey] auto[OpGenSwOut] 3 1 T197 1 T227 1 T228 1
auto[StOwnerIntKey] auto[OpGenHwOut] 2 1 T48 1 T229 1 - -
auto[StOwnerKey] auto[OpAdvance] 6 1 T106 1 T45 1 T46 1
auto[StOwnerKey] auto[OpGenId] 1 1 T77 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T230 1 - - - -
auto[StDisabled] auto[OpAdvance] 6 1 T58 1 T75 1 T231 1
auto[StDisabled] auto[OpGenId] 2 1 T214 1 T232 1 - -
auto[StDisabled] auto[OpGenSwOut] 2 1 T233 1 T226 1 - -