Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10549

1

T1

11

T2

11

T3

13

auto[Attestation]

7385

1

T1

4

T2

7

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2599	1			T1	2		T2	6		T3	1
auto[Aes]	3261	1			T1	1		T2	2		T3	2
auto[Kmac]	3268	1			T1	4		T2	3		T3	2
auto[Otbn]	3181	1			T1	3		T2	1		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7252	1			T1	5		T2	5		T3	8
auto[OpGenId]	5625	1			T1	5		T2	6		T3	12
auto[OpGenSwOut]	5545	1			T1	7		T2	7		T3	6
auto[OpGenHwOut]	6764	1			T1	3		T2	5		T4	5
auto[OpDisable]	122	1			T1	1		T2	1		T16	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9352

1

T1

13

T2

16

T3

8

auto[OpDoneFail]

15956

1

T1

8

T2

8

T3

18

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5988	1			T1	6		T2	4		T3	11
auto[StInit]	4150	1			T1	2		T2	4		T3	2
auto[StCreatorRootKey]	2727	1			T1	3		T2	5		T3	2
auto[StOwnerIntKey]	2408	1			T1	5		T2	5		T3	2
auto[StOwnerKey]	2171	1			T1	3		T2	4		T3	2
auto[StDisabled]	6864	1			T1	2		T2	2		T3	7
auto[StInvalid]	1000	1			T21	22		T35	20		T93	17

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	291	1			T3	1		T13	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	112	1			T21	1		T70	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	75	1			T142	1		T29	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	51	1			T57	1		T84	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T70	1		T57	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	216	1			T40	1		T91	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T21	2		T35	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T13	1		T91	2		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T91	1		T187	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	70	1			T2	1		T107	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T3	1		T188	1		T189	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	173	1			T40	1		T124	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T190	1		T100	2		T191	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	281	1			T1	1		T3	1		T40	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	133	1			T41	1		T21	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	61	1			T2	1		T137	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T2	1		T124	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	68	1			T40	1		T91	1		T187	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	195	1			T1	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T21	1		T93	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	286	1			T1	1		T13	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T194	1		T25	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T195	1		T193	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T1	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	53	1			T12	1		T15	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	179	1			T3	1		T4	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	24	1			T21	2		T35	1		T191	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T109	1		T57	1		T197	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	132	1			T2	1		T194	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	61	1			T1	1		T2	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T69	1		T57	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	57	1			T2	1		T70	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	176	1			T4	1		T193	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T21	1		T35	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T106	1		T109	3		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T70	1		T142	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	63	1			T57	1		T116	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	48	1			T188	1		T84	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	50	1			T143	1		T192	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	162	1			T3	1		T15	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	35	1			T21	1		T93	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	89	1			T106	1		T109	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T22	1		T57	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T40	1		T41	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	54	1			T12	1		T202	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	48	1			T40	1		T143	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	160	1			T3	1		T12	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T21	1		T93	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	89	1			T106	1		T109	2		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T16	1		T40	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	69	1			T69	1		T36	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	71	1			T124	1		T199	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	42	1			T4	1		T26	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	174	1			T40	1		T187	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T190	1		T100	1		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	263	1			T2	2		T13	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T195	1		T69	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	51	1			T26	1		T197	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T108	1		T143	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	46	1			T124	1		T26	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	138	1			T12	1		T40	2		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	24	1			T21	2		T35	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	490	1			T17	2		T40	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T21	1		T107	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T14	1		T204	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T14	1		T202	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	71	1			T205	1		T26	1		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	248	1			T12	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T21	1		T35	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	398	1			T1	1		T13	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	159	1			T16	2		T202	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T4	1		T108	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T40	1		T203	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T1	1		T40	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	271	1			T40	1		T124	2		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T93	1		T24	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	418	1			T40	1		T195	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	151	1			T107	1		T56	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T17	1		T207	1		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T40	1		T203	1		T142	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T207	1		T188	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	258	1			T16	1		T124	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T21	1		T35	1		T100	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	52	1			T109	2		T57	2		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T2	1		T12	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	60	1			T137	1		T36	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	42	1			T12	1		T57	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T1	1		T70	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	144	1			T4	1		T12	1		T195	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T21	1		T100	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T109	1		T57	3		T197	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T14	1		T69	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T203	1		T205	1		T142	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T202	1		T204	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	98	1			T14	1		T204	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	270	1			T4	1		T14	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	36	1			T21	1		T93	2		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T109	2		T197	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T92	1		T195	1		T28	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T4	1		T29	1		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T2	1		T92	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T4	1		T124	2		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	259	1			T12	1		T92	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	29	1			T100	1		T88	2		T200	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	61	1			T57	2		T197	4		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	129	1			T41	1		T195	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T41	1		T194	1		T142	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T12	1		T69	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	71	1			T2	1		T57	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	235	1			T17	1		T40	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T35	1		T24	1		T191	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T70	1		T142	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	654	1			T3	1		T13	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	194	1			T1	1		T2	2		T3	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	611	1			T13	1		T40	1		T91	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	182	1			T2	2		T40	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	643	1			T1	2		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	179	1			T1	2		T4	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	619	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	168	1			T1	1		T2	2		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	427	1			T2	1		T4	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	148	1			T188	1		T57	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	393	1			T3	1		T15	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T12	1		T40	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	400	1			T3	1		T12	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	167	1			T4	1		T124	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	418	1			T16	1		T40	2		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	137	1			T124	1		T108	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	555	1			T2	2		T12	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	242	1			T14	2		T202	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	895	1			T12	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T1	1		T4	1		T40	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	868	1			T1	1		T13	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	246	1			T17	1		T40	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	866	1			T16	1		T40	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	140	1			T1	1		T70	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	351	1			T2	1		T4	1		T12	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	270	1			T14	1		T202	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	508	1			T4	1		T14	4		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T2	1		T4	2		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T12	1		T92	2		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	219	1			T2	1		T12	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	467	1			T17	1		T40	1		T41	1