Unified Coverage Report :: Group Instance : attest_sw_binding

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	29100	1		T1	24	T2	28	T3	29
auto[134217728:268435455]	8	1		T124	1	T369	1	T418	1
auto[268435456:402653183]	8	1		T124	1	T244	1	T273	1
auto[402653184:536870911]	6	1		T137	1	T235	1	T382	1
auto[536870912:671088639]	9	1		T320	1	T239	1	T380	1
auto[671088640:805306367]	8	1		T124	1	T351	1	T234	1
auto[805306368:939524095]	6	1		T334	1	T239	1	T394	1
auto[939524096:1073741823]	11	1		T137	1	T86	1	T238	1
auto[1073741824:1207959551]	6	1		T124	1	T234	1	T419	1
auto[1207959552:1342177279]	10	1		T243	1	T369	1	T394	1
auto[1342177280:1476395007]	8	1		T334	1	T418	1	T419	1
auto[1476395008:1610612735]	9	1		T351	1	T418	1	T234	1
auto[1610612736:1744830463]	10	1		T238	1	T239	1	T369	1
auto[1744830464:1879048191]	10	1		T86	1	T239	2	T420	1
auto[1879048192:2013265919]	10	1		T124	3	T394	1	T234	1
auto[2013265920:2147483647]	8	1		T238	1	T420	1	T421	1
auto[2147483648:2281701375]	7	1		T320	1	T243	1	T394	1
auto[2281701376:2415919103]	5	1		T422	1	T423	1	T424	2
auto[2415919104:2550136831]	9	1		T243	1	T369	2	T418	1
auto[2550136832:2684354559]	6	1		T334	1	T369	1	T422	1
auto[2684354560:2818572287]	1	1		T243	1	-	-	-	-
auto[2818572288:2952790015]	8	1		T243	2	T369	1	T394	1
auto[2952790016:3087007743]	7	1		T86	1	T238	1	T422	2
auto[3087007744:3221225471]	9	1		T334	1	T369	1	T283	1
auto[3221225472:3355443199]	6	1		T143	1	T304	1	T423	1
auto[3355443200:3489660927]	8	1		T137	1	T334	1	T234	2
auto[3489660928:3623878655]	12	1		T137	1	T86	1	T369	1
auto[3623878656:3758096383]	4	1		T86	1	T380	1	T283	1
auto[3758096384:3892314111]	12	1		T124	1	T273	1	T304	2
auto[3892314112:4026531839]	9	1		T124	1	T137	1	T304	1
auto[4026531840:4160749567]	11	1		T243	2	T239	1	T369	1
auto[4160749568:4294967295]	9	1		T320	1	T243	1	T425	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	29093	1		T1	24	T2	28	T3	29
auto[0:134217727]	auto[1]	7	1		T259	1	T418	1	T234	1
auto[134217728:268435455]	auto[1]	8	1		T124	1	T369	1	T418	1
auto[268435456:402653183]	auto[1]	8	1		T124	1	T244	1	T273	1
auto[402653184:536870911]	auto[1]	6	1		T137	1	T235	1	T382	1
auto[536870912:671088639]	auto[1]	9	1		T320	1	T239	1	T380	1
auto[671088640:805306367]	auto[1]	8	1		T124	1	T351	1	T234	1
auto[805306368:939524095]	auto[1]	6	1		T334	1	T239	1	T394	1
auto[939524096:1073741823]	auto[1]	11	1		T137	1	T86	1	T238	1
auto[1073741824:1207959551]	auto[1]	6	1		T124	1	T234	1	T419	1
auto[1207959552:1342177279]	auto[1]	10	1		T243	1	T369	1	T394	1
auto[1342177280:1476395007]	auto[1]	8	1		T334	1	T418	1	T419	1
auto[1476395008:1610612735]	auto[1]	9	1		T351	1	T418	1	T234	1
auto[1610612736:1744830463]	auto[1]	10	1		T238	1	T239	1	T369	1
auto[1744830464:1879048191]	auto[1]	10	1		T86	1	T239	2	T420	1
auto[1879048192:2013265919]	auto[1]	10	1		T124	3	T394	1	T234	1
auto[2013265920:2147483647]	auto[1]	8	1		T238	1	T420	1	T421	1
auto[2147483648:2281701375]	auto[1]	7	1		T320	1	T243	1	T394	1
auto[2281701376:2415919103]	auto[1]	5	1		T422	1	T423	1	T424	2
auto[2415919104:2550136831]	auto[1]	9	1		T243	1	T369	2	T418	1
auto[2550136832:2684354559]	auto[1]	6	1		T334	1	T369	1	T422	1
auto[2684354560:2818572287]	auto[1]	1	1		T243	1	-	-	-	-
auto[2818572288:2952790015]	auto[1]	8	1		T243	2	T369	1	T394	1
auto[2952790016:3087007743]	auto[1]	7	1		T86	1	T238	1	T422	2
auto[3087007744:3221225471]	auto[1]	9	1		T334	1	T369	1	T283	1
auto[3221225472:3355443199]	auto[1]	6	1		T143	1	T304	1	T423	1
auto[3355443200:3489660927]	auto[1]	8	1		T137	1	T334	1	T234	2
auto[3489660928:3623878655]	auto[1]	12	1		T137	1	T86	1	T369	1
auto[3623878656:3758096383]	auto[1]	4	1		T86	1	T380	1	T283	1
auto[3758096384:3892314111]	auto[1]	12	1		T124	1	T273	1	T304	2
auto[3892314112:4026531839]	auto[1]	9	1		T124	1	T137	1	T304	1
auto[4026531840:4160749567]	auto[1]	11	1		T243	2	T239	1	T369	1
auto[4160749568:4294967295]	auto[1]	9	1		T320	1	T243	1	T425	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1385

T13

T16

auto[1]

1552

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	84	1		T202	1	T26	1	T57	1
auto[134217728:268435455]	101	1		T16	1	T34	1	T25	1
auto[268435456:402653183]	84	1		T4	1	T44	1	T22	1
auto[402653184:536870911]	82	1		T21	2	T194	1	T26	1
auto[536870912:671088639]	87	1		T13	1	T69	1	T27	1
auto[671088640:805306367]	85	1		T124	2	T195	1	T25	2
auto[805306368:939524095]	86	1		T4	1	T195	1	T69	1
auto[939524096:1073741823]	99	1		T2	1	T21	1	T34	1
auto[1073741824:1207959551]	90	1		T4	1	T12	1	T195	1
auto[1207959552:1342177279]	97	1		T40	1	T29	2	T107	1
auto[1342177280:1476395007]	82	1		T2	1	T203	1	T26	1
auto[1476395008:1610612735]	93	1		T1	1	T2	1	T124	1
auto[1610612736:1744830463]	94	1		T124	1	T29	1	T86	1
auto[1744830464:1879048191]	92	1		T12	1	T142	1	T109	2
auto[1879048192:2013265919]	84	1		T69	1	T107	2	T109	1
auto[2013265920:2147483647]	102	1		T2	1	T13	1	T44	1
auto[2147483648:2281701375]	94	1		T203	1	T69	1	T194	2
auto[2281701376:2415919103]	95	1		T40	1	T27	1	T57	1
auto[2415919104:2550136831]	98	1		T2	1	T44	1	T70	1
auto[2550136832:2684354559]	118	1		T194	1	T70	1	T56	1
auto[2684354560:2818572287]	89	1		T1	1	T69	1	T194	1
auto[2818572288:2952790015]	110	1		T13	1	T70	1	T201	1
auto[2952790016:3087007743]	75	1		T40	1	T124	2	T29	1
auto[3087007744:3221225471]	87	1		T4	1	T195	1	T23	1
auto[3221225472:3355443199]	95	1		T21	1	T195	1	T107	2
auto[3355443200:3489660927]	93	1		T13	1	T41	1	T57	1
auto[3489660928:3623878655]	88	1		T70	2	T137	1	T23	1
auto[3623878656:3758096383]	89	1		T21	1	T56	1	T143	1
auto[3758096384:3892314111]	81	1		T44	1	T25	1	T188	1
auto[3892314112:4026531839]	111	1		T2	1	T12	1	T13	1
auto[4026531840:4160749567]	82	1		T70	1	T29	1	T107	1
auto[4160749568:4294967295]	90	1		T16	1	T107	1	T22	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	36	1		T198	1	T333	1	T334	1
auto[0:134217727]	auto[1]	48	1		T202	1	T26	1	T57	1
auto[134217728:268435455]	auto[0]	48	1		T16	1	T25	1	T47	1
auto[134217728:268435455]	auto[1]	53	1		T34	1	T56	1	T189	1
auto[268435456:402653183]	auto[0]	37	1		T22	1	T57	1	T93	1
auto[268435456:402653183]	auto[1]	47	1		T4	1	T44	1	T199	1
auto[402653184:536870911]	auto[0]	43	1		T26	1	T188	1	T45	1
auto[402653184:536870911]	auto[1]	39	1		T21	2	T194	1	T56	1
auto[536870912:671088639]	auto[0]	48	1		T13	1	T22	2	T143	1
auto[536870912:671088639]	auto[1]	39	1		T69	1	T27	1	T109	1
auto[671088640:805306367]	auto[0]	36	1		T124	1	T25	2	T142	1
auto[671088640:805306367]	auto[1]	49	1		T124	1	T195	1	T188	1
auto[805306368:939524095]	auto[0]	38	1		T68	1	T334	1	T60	1
auto[805306368:939524095]	auto[1]	48	1		T4	1	T195	1	T69	1
auto[939524096:1073741823]	auto[0]	44	1		T34	1	T25	1	T113	1
auto[939524096:1073741823]	auto[1]	55	1		T2	1	T21	1	T288	1
auto[1073741824:1207959551]	auto[0]	32	1		T69	1	T194	1	T109	1
auto[1073741824:1207959551]	auto[1]	58	1		T4	1	T12	1	T195	1
auto[1207959552:1342177279]	auto[0]	50	1		T29	2	T197	2	T333	1
auto[1207959552:1342177279]	auto[1]	47	1		T40	1	T107	1	T72	1
auto[1342177280:1476395007]	auto[0]	44	1		T2	1	T203	1	T238	1
auto[1342177280:1476395007]	auto[1]	38	1		T26	1	T57	1	T23	1
auto[1476395008:1610612735]	auto[0]	45	1		T2	1	T22	1	T210	1
auto[1476395008:1610612735]	auto[1]	48	1		T1	1	T124	1	T72	1
auto[1610612736:1744830463]	auto[0]	49	1		T29	1	T86	1	T55	1
auto[1610612736:1744830463]	auto[1]	45	1		T124	1	T87	1	T30	1
auto[1744830464:1879048191]	auto[0]	42	1		T142	1	T109	1	T24	1
auto[1744830464:1879048191]	auto[1]	50	1		T12	1	T109	1	T57	1
auto[1879048192:2013265919]	auto[0]	33	1		T69	1	T107	1	T109	1
auto[1879048192:2013265919]	auto[1]	51	1		T107	1	T426	1	T86	1
auto[2013265920:2147483647]	auto[0]	49	1		T2	1	T13	1	T44	1
auto[2013265920:2147483647]	auto[1]	53	1		T23	1	T288	1	T55	1
auto[2147483648:2281701375]	auto[0]	52	1		T203	1	T194	1	T186	1
auto[2147483648:2281701375]	auto[1]	42	1		T69	1	T194	1	T57	2
auto[2281701376:2415919103]	auto[0]	48	1		T40	1	T27	1	T57	1
auto[2281701376:2415919103]	auto[1]	47	1		T72	1	T333	1	T24	1
auto[2415919104:2550136831]	auto[0]	44	1		T2	1	T186	1	T39	1
auto[2415919104:2550136831]	auto[1]	54	1		T44	1	T70	1	T137	2
auto[2550136832:2684354559]	auto[0]	51	1		T87	1	T239	1	T380	1
auto[2550136832:2684354559]	auto[1]	67	1		T194	1	T70	1	T56	1
auto[2684354560:2818572287]	auto[0]	36	1		T194	1	T26	1	T192	1
auto[2684354560:2818572287]	auto[1]	53	1		T1	1	T69	1	T137	1
auto[2818572288:2952790015]	auto[0]	57	1		T13	1	T70	1	T84	1
auto[2818572288:2952790015]	auto[1]	53	1		T201	1	T208	1	T305	1
auto[2952790016:3087007743]	auto[0]	35	1		T29	1	T107	1	T57	1
auto[2952790016:3087007743]	auto[1]	40	1		T40	1	T124	2	T57	1
auto[3087007744:3221225471]	auto[0]	35	1		T312	1	T58	1	T75	2
auto[3087007744:3221225471]	auto[1]	52	1		T4	1	T195	1	T23	1
auto[3221225472:3355443199]	auto[0]	40	1		T195	1	T199	1	T112	1
auto[3221225472:3355443199]	auto[1]	55	1		T21	1	T107	2	T199	1
auto[3355443200:3489660927]	auto[0]	45	1		T13	1	T199	2	T55	1
auto[3355443200:3489660927]	auto[1]	48	1		T41	1	T57	1	T54	1
auto[3489660928:3623878655]	auto[0]	46	1		T137	1	T23	1	T201	1
auto[3489660928:3623878655]	auto[1]	42	1		T70	2	T288	1	T71	1
auto[3623878656:3758096383]	auto[0]	41	1		T95	1	T331	1	T58	1
auto[3623878656:3758096383]	auto[1]	48	1		T21	1	T56	1	T143	1
auto[3758096384:3892314111]	auto[0]	44	1		T44	1	T25	1	T188	1
auto[3758096384:3892314111]	auto[1]	37	1		T57	1	T198	1	T112	1
auto[3892314112:4026531839]	auto[0]	56	1		T2	1	T13	1	T28	1
auto[3892314112:4026531839]	auto[1]	55	1		T12	1	T143	2	T118	1
auto[4026531840:4160749567]	auto[0]	36	1		T95	2	T54	1	T35	1
auto[4026531840:4160749567]	auto[1]	46	1		T70	1	T29	1	T107	1
auto[4160749568:4294967295]	auto[0]	45	1		T16	1	T107	1	T143	1
auto[4160749568:4294967295]	auto[1]	45	1		T22	1	T312	1	T427	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1350

T12

T13

auto[1]

1584

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	84	1		T2	1	T69	1	T22	1
auto[134217728:268435455]	91	1		T13	1	T201	1	T86	1
auto[268435456:402653183]	86	1		T2	1	T13	1	T21	1
auto[402653184:536870911]	76	1		T124	1	T195	1	T70	2
auto[536870912:671088639]	102	1		T188	1	T137	1	T57	3
auto[671088640:805306367]	104	1		T12	1	T21	1	T44	1
auto[805306368:939524095]	96	1		T195	1	T70	1	T57	1
auto[939524096:1073741823]	89	1		T4	1	T195	1	T28	1
auto[1073741824:1207959551]	92	1		T4	1	T44	1	T194	1
auto[1207959552:1342177279]	108	1		T124	1	T203	1	T194	1
auto[1342177280:1476395007]	115	1		T29	1	T109	1	T57	1
auto[1476395008:1610612735]	87	1		T1	1	T4	1	T25	1
auto[1610612736:1744830463]	79	1		T13	1	T124	1	T107	1
auto[1744830464:1879048191]	112	1		T2	1	T41	1	T21	1
auto[1879048192:2013265919]	96	1		T13	1	T34	1	T44	1
auto[2013265920:2147483647]	88	1		T4	1	T202	1	T29	1
auto[2147483648:2281701375]	91	1		T2	1	T21	1	T44	1
auto[2281701376:2415919103]	87	1		T69	2	T25	1	T28	1
auto[2415919104:2550136831]	78	1		T2	1	T109	1	T210	1
auto[2550136832:2684354559]	92	1		T194	1	T22	1	T109	1
auto[2684354560:2818572287]	93	1		T1	1	T13	1	T188	1
auto[2818572288:2952790015]	86	1		T16	1	T25	1	T142	1
auto[2952790016:3087007743]	93	1		T69	1	T27	1	T29	1
auto[3087007744:3221225471]	70	1		T12	2	T57	1	T55	1
auto[3221225472:3355443199]	91	1		T16	1	T26	2	T109	2
auto[3355443200:3489660927]	92	1		T70	1	T25	1	T107	1
auto[3489660928:3623878655]	76	1		T69	1	T74	1	T87	1
auto[3623878656:3758096383]	94	1		T40	1	T27	1	T56	1
auto[3758096384:3892314111]	99	1		T195	1	T107	2	T22	1
auto[3892314112:4026531839]	94	1		T2	1	T124	1	T195	1
auto[4026531840:4160749567]	90	1		T21	1	T34	1	T29	1
auto[4160749568:4294967295]	103	1		T40	2	T124	1	T203	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	35	1		T2	1	T22	1	T87	1
auto[0:134217727]	auto[1]	49	1		T69	1	T84	1	T86	1
auto[134217728:268435455]	auto[0]	41	1		T13	1	T118	1	T312	1
auto[134217728:268435455]	auto[1]	50	1		T201	1	T86	1	T312	1
auto[268435456:402653183]	auto[0]	42	1		T2	1	T13	1	T25	1
auto[268435456:402653183]	auto[1]	44	1		T21	1	T198	1	T87	1
auto[402653184:536870911]	auto[0]	35	1		T70	1	T107	1	T199	1
auto[402653184:536870911]	auto[1]	41	1		T124	1	T195	1	T70	1
auto[536870912:671088639]	auto[0]	45	1		T188	1	T57	2	T210	1
auto[536870912:671088639]	auto[1]	57	1		T137	1	T57	1	T192	1
auto[671088640:805306367]	auto[0]	45	1		T44	1	T28	1	T86	1
auto[671088640:805306367]	auto[1]	59	1		T12	1	T21	1	T56	2
auto[805306368:939524095]	auto[0]	37	1		T93	1	T67	1	T245	2
auto[805306368:939524095]	auto[1]	59	1		T195	1	T70	1	T57	1
auto[939524096:1073741823]	auto[0]	39	1		T195	1	T188	1	T22	1
auto[939524096:1073741823]	auto[1]	50	1		T4	1	T28	1	T107	1
auto[1073741824:1207959551]	auto[0]	28	1		T194	1	T70	1	T199	1
auto[1073741824:1207959551]	auto[1]	64	1		T4	1	T44	1	T56	1
auto[1207959552:1342177279]	auto[0]	55	1		T124	1	T203	1	T194	1
auto[1207959552:1342177279]	auto[1]	53	1		T23	1	T87	1	T24	1
auto[1342177280:1476395007]	auto[0]	56	1		T29	1	T57	1	T186	1
auto[1342177280:1476395007]	auto[1]	59	1		T109	1	T39	1	T197	1
auto[1476395008:1610612735]	auto[0]	37	1		T25	1	T72	1	T209	1
auto[1476395008:1610612735]	auto[1]	50	1		T1	1	T4	1	T86	1
auto[1610612736:1744830463]	auto[0]	43	1		T13	1	T124	1	T107	1
auto[1610612736:1744830463]	auto[1]	36	1		T197	1	T30	1	T55	1
auto[1744830464:1879048191]	auto[0]	58	1		T2	1	T210	1	T84	1
auto[1744830464:1879048191]	auto[1]	54	1		T41	1	T21	1	T124	1
auto[1879048192:2013265919]	auto[0]	46	1		T13	1	T34	1	T26	1
auto[1879048192:2013265919]	auto[1]	50	1		T44	1	T69	1	T194	1
auto[2013265920:2147483647]	auto[0]	34	1		T29	1	T48	2	T264	1
auto[2013265920:2147483647]	auto[1]	54	1		T4	1	T202	1	T26	1
auto[2147483648:2281701375]	auto[0]	44	1		T186	1	T113	1	T95	1
auto[2147483648:2281701375]	auto[1]	47	1		T2	1	T21	1	T44	1
auto[2281701376:2415919103]	auto[0]	46	1		T69	1	T25	1	T28	1
auto[2281701376:2415919103]	auto[1]	41	1		T69	1	T244	1	T68	1
auto[2415919104:2550136831]	auto[0]	34	1		T118	1	T273	1	T239	1
auto[2415919104:2550136831]	auto[1]	44	1		T2	1	T109	1	T210	1
auto[2550136832:2684354559]	auto[0]	40	1		T22	1	T54	1	T334	1
auto[2550136832:2684354559]	auto[1]	52	1		T194	1	T109	1	T23	1
auto[2684354560:2818572287]	auto[0]	49	1		T13	1	T143	1	T46	1
auto[2684354560:2818572287]	auto[1]	44	1		T1	1	T188	1	T137	1
auto[2818572288:2952790015]	auto[0]	39	1		T16	1	T25	1	T142	1
auto[2818572288:2952790015]	auto[1]	47	1		T143	1	T72	1	T112	1
auto[2952790016:3087007743]	auto[0]	52	1		T69	1	T29	1	T109	1
auto[2952790016:3087007743]	auto[1]	41	1		T27	1	T333	1	T244	1
auto[3087007744:3221225471]	auto[0]	29	1		T12	1	T57	1	T58	1
auto[3087007744:3221225471]	auto[1]	41	1		T12	1	T55	1	T102	1
auto[3221225472:3355443199]	auto[0]	41	1		T16	1	T109	2	T192	1
auto[3221225472:3355443199]	auto[1]	50	1		T26	2	T86	1	T67	1
auto[3355443200:3489660927]	auto[0]	45	1		T25	1	T107	1	T23	1
auto[3355443200:3489660927]	auto[1]	47	1		T70	1	T57	1	T86	1
auto[3489660928:3623878655]	auto[0]	38	1		T74	1	T87	1	T35	1
auto[3489660928:3623878655]	auto[1]	38	1		T69	1	T209	1	T305	2
auto[3623878656:3758096383]	auto[0]	38	1		T27	1	T23	1	T55	1
auto[3623878656:3758096383]	auto[1]	56	1		T40	1	T56	1	T199	2
auto[3758096384:3892314111]	auto[0]	45	1		T22	1	T201	1	T112	1
auto[3758096384:3892314111]	auto[1]	54	1		T195	1	T107	2	T143	1
auto[3892314112:4026531839]	auto[0]	47	1		T195	1	T57	1	T143	1
auto[3892314112:4026531839]	auto[1]	47	1		T2	1	T124	1	T194	1
auto[4026531840:4160749567]	auto[0]	45	1		T34	1	T29	1	T23	1
auto[4026531840:4160749567]	auto[1]	45	1		T21	1	T57	1	T288	1
auto[4160749568:4294967295]	auto[0]	42	1		T40	1	T203	1	T47	1
auto[4160749568:4294967295]	auto[1]	61	1		T40	1	T124	1	T194	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1372

T12

T13

auto[1]

1565

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	91	1		T13	1	T124	1	T70	1
auto[134217728:268435455]	100	1		T2	1	T124	1	T70	1
auto[268435456:402653183]	99	1		T137	1	T57	1	T199	1
auto[402653184:536870911]	105	1		T25	1	T109	1	T198	1
auto[536870912:671088639]	83	1		T2	1	T12	1	T16	1
auto[671088640:805306367]	110	1		T4	1	T13	1	T16	1
auto[805306368:939524095]	91	1		T41	1	T44	1	T57	1
auto[939524096:1073741823]	96	1		T72	1	T87	1	T39	1
auto[1073741824:1207959551]	87	1		T2	1	T34	1	T124	1
auto[1207959552:1342177279]	95	1		T2	1	T70	1	T137	1
auto[1342177280:1476395007]	88	1		T142	1	T27	1	T56	1
auto[1476395008:1610612735]	97	1		T195	1	T188	1	T56	1
auto[1610612736:1744830463]	94	1		T1	1	T2	1	T194	1
auto[1744830464:1879048191]	81	1		T13	1	T194	1	T26	1
auto[1879048192:2013265919]	79	1		T56	1	T109	1	T57	1
auto[2013265920:2147483647]	92	1		T202	1	T195	2	T194	1
auto[2147483648:2281701375]	103	1		T4	1	T34	1	T142	1
auto[2281701376:2415919103]	87	1		T21	1	T44	2	T25	1
auto[2415919104:2550136831]	99	1		T13	1	T40	2	T69	1
auto[2550136832:2684354559]	88	1		T4	1	T40	1	T124	2
auto[2684354560:2818572287]	87	1		T2	1	T195	1	T44	1
auto[2818572288:2952790015]	84	1		T1	1	T12	1	T28	1
auto[2952790016:3087007743]	83	1		T69	1	T194	1	T70	1
auto[3087007744:3221225471]	92	1		T27	1	T107	1	T109	1
auto[3221225472:3355443199]	104	1		T13	1	T21	1	T124	1
auto[3355443200:3489660927]	95	1		T4	1	T21	1	T195	1
auto[3489660928:3623878655]	83	1		T194	1	T137	1	T312	1
auto[3623878656:3758096383]	88	1		T25	1	T57	1	T143	1
auto[3758096384:3892314111]	80	1		T28	1	T22	1	T86	1
auto[3892314112:4026531839]	100	1		T203	1	T69	1	T29	1
auto[4026531840:4160749567]	84	1		T69	1	T29	1	T26	1
auto[4160749568:4294967295]	92	1		T12	1	T21	1	T203	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	44	1		T13	1	T186	1	T72	1
auto[0:134217727]	auto[1]	47	1		T124	1	T70	1	T107	1
auto[134217728:268435455]	auto[0]	54	1		T2	1	T35	1	T238	1
auto[134217728:268435455]	auto[1]	46	1		T124	1	T70	1	T28	1
auto[268435456:402653183]	auto[0]	45	1		T199	1	T333	1	T190	1
auto[268435456:402653183]	auto[1]	54	1		T137	1	T57	1	T72	2
auto[402653184:536870911]	auto[0]	47	1		T25	1	T84	1	T93	1
auto[402653184:536870911]	auto[1]	58	1		T109	1	T198	1	T86	1
auto[536870912:671088639]	auto[0]	41	1		T16	1	T192	1	T186	1
auto[536870912:671088639]	auto[1]	42	1		T2	1	T12	1	T57	2
auto[671088640:805306367]	auto[0]	54	1		T13	1	T16	1	T29	1
auto[671088640:805306367]	auto[1]	56	1		T4	1	T21	1	T201	1
auto[805306368:939524095]	auto[0]	41	1		T143	1	T84	1	T87	1
auto[805306368:939524095]	auto[1]	50	1		T41	1	T44	1	T57	1
auto[939524096:1073741823]	auto[0]	45	1		T312	1	T95	1	T305	1
auto[939524096:1073741823]	auto[1]	51	1		T72	1	T87	1	T39	1
auto[1073741824:1207959551]	auto[0]	42	1		T2	1	T23	1	T95	1
auto[1073741824:1207959551]	auto[1]	45	1		T34	1	T124	1	T199	1
auto[1207959552:1342177279]	auto[0]	38	1		T2	1	T70	1	T112	1
auto[1207959552:1342177279]	auto[1]	57	1		T137	1	T57	1	T427	1
auto[1342177280:1476395007]	auto[0]	48	1		T142	1	T27	1	T143	1
auto[1342177280:1476395007]	auto[1]	40	1		T56	1	T143	1	T201	1
auto[1476395008:1610612735]	auto[0]	40	1		T188	1	T186	1	T197	1
auto[1476395008:1610612735]	auto[1]	57	1		T195	1	T56	1	T57	1
auto[1610612736:1744830463]	auto[0]	45	1		T2	1	T107	1	T22	1
auto[1610612736:1744830463]	auto[1]	49	1		T1	1	T194	1	T84	1
auto[1744830464:1879048191]	auto[0]	38	1		T13	1	T194	1	T199	1
auto[1744830464:1879048191]	auto[1]	43	1		T26	1	T192	1	T39	1
auto[1879048192:2013265919]	auto[0]	36	1		T54	1	T35	1	T93	1
auto[1879048192:2013265919]	auto[1]	43	1		T56	1	T109	1	T57	1
auto[2013265920:2147483647]	auto[0]	36	1		T195	1	T194	1	T25	1
auto[2013265920:2147483647]	auto[1]	56	1		T202	1	T195	1	T57	1
auto[2147483648:2281701375]	auto[0]	40	1		T34	1	T142	1	T29	1
auto[2147483648:2281701375]	auto[1]	63	1		T4	1	T137	1	T210	1
auto[2281701376:2415919103]	auto[0]	37	1		T44	2	T25	1	T22	1
auto[2281701376:2415919103]	auto[1]	50	1		T21	1	T107	1	T57	1
auto[2415919104:2550136831]	auto[0]	41	1		T13	1	T40	1	T47	1
auto[2415919104:2550136831]	auto[1]	58	1		T40	1	T69	1	T57	1
auto[2550136832:2684354559]	auto[0]	37	1		T40	1	T124	1	T22	1
auto[2550136832:2684354559]	auto[1]	51	1		T4	1	T124	1	T86	1
auto[2684354560:2818572287]	auto[0]	36	1		T194	1	T23	1	T198	1
auto[2684354560:2818572287]	auto[1]	51	1		T2	1	T195	1	T44	1
auto[2818572288:2952790015]	auto[0]	44	1		T12	1	T28	1	T143	1
auto[2818572288:2952790015]	auto[1]	40	1		T1	1	T137	1	T57	1
auto[2952790016:3087007743]	auto[0]	41	1		T70	1	T29	1	T238	1
auto[2952790016:3087007743]	auto[1]	42	1		T69	1	T194	1	T57	1
auto[3087007744:3221225471]	auto[0]	48	1		T107	1	T109	1	T210	1
auto[3087007744:3221225471]	auto[1]	44	1		T27	1	T189	1	T209	1
auto[3221225472:3355443199]	auto[0]	49	1		T13	1	T124	1	T107	1
auto[3221225472:3355443199]	auto[1]	55	1		T21	1	T70	1	T26	1
auto[3355443200:3489660927]	auto[0]	44	1		T25	1	T23	1	T86	1
auto[3355443200:3489660927]	auto[1]	51	1		T4	1	T21	1	T195	1
auto[3489660928:3623878655]	auto[0]	40	1		T194	1	T312	1	T95	1
auto[3489660928:3623878655]	auto[1]	43	1		T137	1	T197	1	T93	1
auto[3623878656:3758096383]	auto[0]	41	1		T25	1	T397	1	T55	1
auto[3623878656:3758096383]	auto[1]	47	1		T57	1	T143	1	T210	1
auto[3758096384:3892314111]	auto[0]	43	1		T28	1	T22	1	T39	1
auto[3758096384:3892314111]	auto[1]	37	1		T86	1	T197	1	T305	1
auto[3892314112:4026531839]	auto[0]	57	1		T28	1	T199	1	T291	1
auto[3892314112:4026531839]	auto[1]	43	1		T203	1	T69	1	T29	1
auto[4026531840:4160749567]	auto[0]	34	1		T69	1	T29	1	T26	1
auto[4026531840:4160749567]	auto[1]	50	1		T199	2	T112	1	T54	1
auto[4160749568:4294967295]	auto[0]	46	1		T203	1	T107	1	T22	1
auto[4160749568:4294967295]	auto[1]	46	1		T12	1	T21	1	T69	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1350

T13

T16

auto[1]

1587

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	99	1		T13	1	T21	1	T69	2
auto[134217728:268435455]	87	1		T40	1	T203	1	T25	1
auto[268435456:402653183]	104	1		T70	1	T107	1	T22	2
auto[402653184:536870911]	91	1		T2	1	T21	1	T44	1
auto[536870912:671088639]	83	1		T27	1	T22	1	T57	1
auto[671088640:805306367]	85	1		T1	1	T195	1	T70	1
auto[805306368:939524095]	110	1		T12	1	T34	1	T124	1
auto[939524096:1073741823]	85	1		T2	1	T57	2	T186	1
auto[1073741824:1207959551]	81	1		T4	1	T13	1	T195	1
auto[1207959552:1342177279]	87	1		T29	2	T107	1	T199	1
auto[1342177280:1476395007]	111	1		T12	1	T195	2	T57	1
auto[1476395008:1610612735]	91	1		T2	1	T84	1	T189	3
auto[1610612736:1744830463]	99	1		T69	1	T26	1	T57	2
auto[1744830464:1879048191]	93	1		T13	1	T16	1	T195	1
auto[1879048192:2013265919]	82	1		T13	1	T29	1	T28	1
auto[2013265920:2147483647]	104	1		T4	1	T109	1	T57	1
auto[2147483648:2281701375]	80	1		T12	1	T124	1	T194	1
auto[2281701376:2415919103]	98	1		T2	1	T21	1	T194	1
auto[2415919104:2550136831]	94	1		T16	1	T124	1	T70	1
auto[2550136832:2684354559]	95	1		T41	1	T124	1	T69	1
auto[2684354560:2818572287]	91	1		T2	1	T4	1	T13	1
auto[2818572288:2952790015]	77	1		T40	1	T25	1	T109	1
auto[2952790016:3087007743]	85	1		T202	1	T34	1	T27	1
auto[3087007744:3221225471]	97	1		T186	1	T23	1	T198	1
auto[3221225472:3355443199]	102	1		T2	1	T124	1	T142	1
auto[3355443200:3489660927]	85	1		T40	1	T29	1	T56	1
auto[3489660928:3623878655]	80	1		T21	1	T70	1	T84	1
auto[3623878656:3758096383]	107	1		T203	1	T70	1	T107	1
auto[3758096384:3892314111]	85	1		T124	1	T107	1	T23	1
auto[3892314112:4026531839]	93	1		T4	1	T194	1	T188	1
auto[4026531840:4160749567]	82	1		T44	1	T186	1	T112	1
auto[4160749568:4294967295]	94	1		T1	1	T44	1	T57	2