Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3912

1

T2

8

T4

6

T12

4

auto[1]

1962

1

T1

4

T2

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	190	1			T13	4		T69	2		T29	2
auto[134217728:268435455]	158	1			T12	2		T21	2		T44	2
auto[268435456:402653183]	174	1			T197	2		T305	2		T24	2
auto[402653184:536870911]	184	1			T69	2		T194	2		T25	2
auto[536870912:671088639]	160	1			T13	2		T40	4		T124	2
auto[671088640:805306367]	204	1			T2	6		T16	2		T124	2
auto[805306368:939524095]	170	1			T1	2		T69	2		T28	2
auto[939524096:1073741823]	198	1			T2	4		T22	2		T109	2
auto[1073741824:1207959551]	182	1			T21	2		T44	2		T107	2
auto[1207959552:1342177279]	208	1			T21	2		T44	2		T109	2
auto[1342177280:1476395007]	172	1			T4	2		T21	2		T195	2
auto[1476395008:1610612735]	170	1			T40	2		T124	2		T29	2
auto[1610612736:1744830463]	196	1			T13	2		T203	2		T69	2
auto[1744830464:1879048191]	184	1			T16	2		T44	2		T29	2
auto[1879048192:2013265919]	196	1			T4	2		T57	2		T84	2
auto[2013265920:2147483647]	204	1			T194	2		T109	2		T23	2
auto[2147483648:2281701375]	224	1			T13	2		T124	2		T25	2
auto[2281701376:2415919103]	152	1			T194	2		T188	2		T143	2
auto[2415919104:2550136831]	166	1			T4	2		T124	2		T195	4
auto[2550136832:2684354559]	208	1			T203	2		T69	2		T194	2
auto[2684354560:2818572287]	198	1			T194	2		T25	2		T56	2
auto[2818572288:2952790015]	166	1			T202	2		T124	2		T25	2
auto[2952790016:3087007743]	166	1			T41	2		T70	2		T57	4
auto[3087007744:3221225471]	194	1			T107	2		T57	2		T192	2
auto[3221225472:3355443199]	188	1			T107	2		T56	2		T57	2
auto[3355443200:3489660927]	174	1			T143	2		T426	2		T86	2
auto[3489660928:3623878655]	174	1			T28	2		T26	2		T188	2
auto[3623878656:3758096383]	172	1			T1	2		T2	2		T4	2
auto[3758096384:3892314111]	208	1			T34	2		T28	2		T22	2
auto[3892314112:4026531839]	162	1			T12	2		T69	2		T70	2
auto[4026531840:4160749567]	194	1			T12	2		T21	2		T34	2
auto[4160749568:4294967295]	178	1			T70	2		T137	2		T22	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	126	1			T13	4		T69	2		T57	2
auto[0:134217727]	auto[1]	64	1			T29	2		T109	2		T55	4
auto[134217728:268435455]	auto[0]	104	1			T12	2		T21	2		T44	2
auto[134217728:268435455]	auto[1]	54	1			T57	2		T192	2		T100	2
auto[268435456:402653183]	auto[0]	122	1			T305	2		T55	2		T67	2
auto[268435456:402653183]	auto[1]	52	1			T197	2		T24	2		T304	2
auto[402653184:536870911]	auto[0]	122	1			T69	2		T25	2		T143	2
auto[402653184:536870911]	auto[1]	62	1			T194	2		T39	2		T189	2
auto[536870912:671088639]	auto[0]	102	1			T13	2		T40	4		T124	2
auto[536870912:671088639]	auto[1]	58	1			T189	2		T55	2		T429	2
auto[671088640:805306367]	auto[0]	142	1			T2	2		T124	2		T195	2
auto[671088640:805306367]	auto[1]	62	1			T2	4		T16	2		T93	2
auto[805306368:939524095]	auto[0]	110	1			T69	2		T84	2		T86	2
auto[805306368:939524095]	auto[1]	60	1			T1	2		T28	2		T288	2
auto[939524096:1073741823]	auto[0]	132	1			T2	4		T22	2		T84	2
auto[939524096:1073741823]	auto[1]	66	1			T109	2		T72	2		T35	2
auto[1073741824:1207959551]	auto[0]	110	1			T21	2		T44	2		T109	2
auto[1073741824:1207959551]	auto[1]	72	1			T107	2		T86	2		T197	2
auto[1207959552:1342177279]	auto[0]	134	1			T21	2		T44	2		T109	2
auto[1207959552:1342177279]	auto[1]	74	1			T57	2		T427	2		T24	2
auto[1342177280:1476395007]	auto[0]	114	1			T4	2		T21	2		T195	2
auto[1342177280:1476395007]	auto[1]	58	1			T137	2		T22	2		T57	2
auto[1476395008:1610612735]	auto[0]	130	1			T124	2		T29	2		T137	2
auto[1476395008:1610612735]	auto[1]	40	1			T40	2		T87	2		T209	2
auto[1610612736:1744830463]	auto[0]	138	1			T13	2		T69	2		T70	4
auto[1610612736:1744830463]	auto[1]	58	1			T203	2		T142	2		T29	2
auto[1744830464:1879048191]	auto[0]	130	1			T16	2		T44	2		T29	2
auto[1744830464:1879048191]	auto[1]	54	1			T107	2		T45	2		T312	2
auto[1879048192:2013265919]	auto[0]	136	1			T4	2		T84	2		T112	2
auto[1879048192:2013265919]	auto[1]	60	1			T57	2		T95	2		T431	2
auto[2013265920:2147483647]	auto[0]	138	1			T23	2		T72	2		T112	2
auto[2013265920:2147483647]	auto[1]	66	1			T194	2		T109	2		T39	2
auto[2147483648:2281701375]	auto[0]	152	1			T25	2		T188	2		T22	2
auto[2147483648:2281701375]	auto[1]	72	1			T13	2		T124	2		T27	2
auto[2281701376:2415919103]	auto[0]	100	1			T194	2		T188	2		T143	2
auto[2281701376:2415919103]	auto[1]	52	1			T273	2		T334	2		T320	2
auto[2415919104:2550136831]	auto[0]	96	1			T124	2		T195	4		T197	2
auto[2415919104:2550136831]	auto[1]	70	1			T4	2		T27	2		T210	2
auto[2550136832:2684354559]	auto[0]	140	1			T69	2		T186	2		T86	4
auto[2550136832:2684354559]	auto[1]	68	1			T203	2		T194	2		T189	2
auto[2684354560:2818572287]	auto[0]	118	1			T194	2		T56	2		T198	2
auto[2684354560:2818572287]	auto[1]	80	1			T25	2		T57	2		T67	2
auto[2818572288:2952790015]	auto[0]	108	1			T202	2		T124	2		T25	2
auto[2818572288:2952790015]	auto[1]	58	1			T26	2		T397	2		T24	2
auto[2952790016:3087007743]	auto[0]	130	1			T70	2		T57	2		T143	2
auto[2952790016:3087007743]	auto[1]	36	1			T41	2		T57	2		T197	2
auto[3087007744:3221225471]	auto[0]	132	1			T57	2		T186	2		T95	2
auto[3087007744:3221225471]	auto[1]	62	1			T107	2		T192	2		T212	2
auto[3221225472:3355443199]	auto[0]	112	1			T57	2		T198	2		T59	4
auto[3221225472:3355443199]	auto[1]	76	1			T107	2		T56	2		T118	2
auto[3355443200:3489660927]	auto[0]	128	1			T143	2		T86	2		T112	2
auto[3355443200:3489660927]	auto[1]	46	1			T426	2		T48	2		T214	2
auto[3489660928:3623878655]	auto[0]	108	1			T28	2		T67	2		T273	2
auto[3489660928:3623878655]	auto[1]	66	1			T26	2		T188	2		T67	2
auto[3623878656:3758096383]	auto[0]	116	1			T2	2		T4	2		T199	2
auto[3623878656:3758096383]	auto[1]	56	1			T1	2		T260	2		T62	4
auto[3758096384:3892314111]	auto[0]	144	1			T34	2		T28	2		T22	2
auto[3758096384:3892314111]	auto[1]	64	1			T112	2		T189	2		T334	2
auto[3892314112:4026531839]	auto[0]	104	1			T12	2		T69	2		T70	2
auto[3892314112:4026531839]	auto[1]	58	1			T192	2		T54	2		T46	2
auto[4026531840:4160749567]	auto[0]	116	1			T21	2		T34	2		T195	2
auto[4026531840:4160749567]	auto[1]	78	1			T12	2		T26	2		T57	2
auto[4160749568:4294967295]	auto[0]	118	1			T137	2		T22	2		T57	2
auto[4160749568:4294967295]	auto[1]	60	1			T70	2		T87	2		T39	2