Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2635

1

T1

2

T2

6

T4

4

auto[1]

273

1

T124

4

T137

4

T143

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T41	1		T34	1		T124	1
auto[134217728:268435455]	97	1			T195	1		T70	1		T107	2
auto[268435456:402653183]	95	1			T4	1		T70	1		T25	1
auto[402653184:536870911]	83	1			T195	1		T194	1		T28	1
auto[536870912:671088639]	89	1			T12	1		T124	1		T137	1
auto[671088640:805306367]	101	1			T21	1		T124	1		T27	1
auto[805306368:939524095]	91	1			T202	1		T124	1		T70	1
auto[939524096:1073741823]	105	1			T16	1		T124	1		T25	1
auto[1073741824:1207959551]	65	1			T16	1		T69	1		T143	1
auto[1207959552:1342177279]	104	1			T69	1		T194	1		T107	1
auto[1342177280:1476395007]	90	1			T21	2		T107	1		T57	1
auto[1476395008:1610612735]	84	1			T13	1		T21	2		T195	1
auto[1610612736:1744830463]	92	1			T2	1		T12	1		T124	1
auto[1744830464:1879048191]	83	1			T4	1		T194	1		T57	1
auto[1879048192:2013265919]	110	1			T34	1		T137	1		T57	1
auto[2013265920:2147483647]	109	1			T1	1		T2	1		T4	1
auto[2147483648:2281701375]	93	1			T107	1		T210	1		T198	1
auto[2281701376:2415919103]	83	1			T124	2		T109	1		T57	1
auto[2415919104:2550136831]	73	1			T69	1		T107	1		T199	1
auto[2550136832:2684354559]	88	1			T1	1		T25	1		T142	1
auto[2684354560:2818572287]	97	1			T2	1		T12	1		T40	1
auto[2818572288:2952790015]	83	1			T2	1		T13	1		T40	1
auto[2952790016:3087007743]	89	1			T124	1		T194	1		T109	1
auto[3087007744:3221225471]	77	1			T4	1		T29	1		T23	1
auto[3221225472:3355443199]	84	1			T13	1		T143	1		T199	1
auto[3355443200:3489660927]	114	1			T40	1		T69	1		T137	1
auto[3489660928:3623878655]	87	1			T70	1		T188	1		T198	1
auto[3623878656:3758096383]	89	1			T2	1		T13	1		T26	1
auto[3758096384:3892314111]	93	1			T194	1		T107	1		T56	1
auto[3892314112:4026531839]	85	1			T203	1		T29	1		T22	1
auto[4026531840:4160749567]	85	1			T2	1		T70	1		T25	1
auto[4160749568:4294967295]	97	1			T124	1		T28	2		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	78	1			T41	1		T34	1		T124	1
auto[0:134217727]	auto[1]	15	1			T238	1		T369	1		T283	1
auto[134217728:268435455]	auto[0]	88	1			T195	1		T70	1		T107	2
auto[134217728:268435455]	auto[1]	9	1			T137	1		T86	1		T436	1
auto[268435456:402653183]	auto[0]	88	1			T4	1		T70	1		T25	1
auto[268435456:402653183]	auto[1]	7	1			T86	1		T380	1		T283	1
auto[402653184:536870911]	auto[0]	78	1			T195	1		T194	1		T28	1
auto[402653184:536870911]	auto[1]	5	1			T334	1		T234	1		T419	1
auto[536870912:671088639]	auto[0]	79	1			T12	1		T124	1		T137	1
auto[536870912:671088639]	auto[1]	10	1			T273	1		T243	1		T283	1
auto[671088640:805306367]	auto[0]	90	1			T21	1		T27	1		T26	1
auto[671088640:805306367]	auto[1]	11	1			T124	1		T380	1		T394	1
auto[805306368:939524095]	auto[0]	81	1			T202	1		T70	1		T29	1
auto[805306368:939524095]	auto[1]	10	1			T124	1		T244	1		T304	1
auto[939524096:1073741823]	auto[0]	96	1			T16	1		T124	1		T25	1
auto[939524096:1073741823]	auto[1]	9	1			T243	1		T304	1		T394	2
auto[1073741824:1207959551]	auto[0]	60	1			T16	1		T69	1		T143	1
auto[1073741824:1207959551]	auto[1]	5	1			T418	1		T234	1		T361	1
auto[1207959552:1342177279]	auto[0]	93	1			T69	1		T194	1		T107	1
auto[1207959552:1342177279]	auto[1]	11	1			T239	1		T380	1		T394	1
auto[1342177280:1476395007]	auto[0]	80	1			T21	2		T107	1		T57	1
auto[1342177280:1476395007]	auto[1]	10	1			T238	1		T422	2		T436	1
auto[1476395008:1610612735]	auto[0]	76	1			T13	1		T21	2		T195	1
auto[1476395008:1610612735]	auto[1]	8	1			T86	1		T238	1		T334	1
auto[1610612736:1744830463]	auto[0]	85	1			T2	1		T12	1		T124	1
auto[1610612736:1744830463]	auto[1]	7	1			T137	1		T283	1		T361	2
auto[1744830464:1879048191]	auto[0]	73	1			T4	1		T194	1		T57	1
auto[1744830464:1879048191]	auto[1]	10	1			T143	1		T86	1		T380	1
auto[1879048192:2013265919]	auto[0]	95	1			T34	1		T57	1		T199	1
auto[1879048192:2013265919]	auto[1]	15	1			T137	1		T143	1		T86	1
auto[2013265920:2147483647]	auto[0]	102	1			T1	1		T2	1		T4	1
auto[2013265920:2147483647]	auto[1]	7	1			T369	1		T425	1		T433	1
auto[2147483648:2281701375]	auto[0]	86	1			T107	1		T210	1		T198	1
auto[2147483648:2281701375]	auto[1]	7	1			T334	1		T418	1		T420	1
auto[2281701376:2415919103]	auto[0]	77	1			T109	1		T57	1		T143	1
auto[2281701376:2415919103]	auto[1]	6	1			T124	2		T239	1		T394	1
auto[2415919104:2550136831]	auto[0]	68	1			T69	1		T107	1		T199	1
auto[2415919104:2550136831]	auto[1]	5	1			T380	1		T283	1		T422	1
auto[2550136832:2684354559]	auto[0]	82	1			T1	1		T25	1		T142	1
auto[2550136832:2684354559]	auto[1]	6	1			T304	1		T239	1		T425	1
auto[2684354560:2818572287]	auto[0]	89	1			T2	1		T12	1		T40	1
auto[2684354560:2818572287]	auto[1]	8	1			T86	1		T239	1		T422	4
auto[2818572288:2952790015]	auto[0]	77	1			T2	1		T13	1		T40	1
auto[2818572288:2952790015]	auto[1]	6	1			T137	1		T243	1		T422	1
auto[2952790016:3087007743]	auto[0]	76	1			T124	1		T194	1		T109	1
auto[2952790016:3087007743]	auto[1]	13	1			T143	1		T238	1		T244	1
auto[3087007744:3221225471]	auto[0]	73	1			T4	1		T29	1		T23	1
auto[3087007744:3221225471]	auto[1]	4	1			T369	1		T261	1		T437	1
auto[3221225472:3355443199]	auto[0]	78	1			T13	1		T143	1		T199	1
auto[3221225472:3355443199]	auto[1]	6	1			T243	1		T283	1		T234	1
auto[3355443200:3489660927]	auto[0]	106	1			T40	1		T69	1		T137	1
auto[3355443200:3489660927]	auto[1]	8	1			T86	1		T273	1		T304	1
auto[3489660928:3623878655]	auto[0]	80	1			T70	1		T188	1		T198	1
auto[3489660928:3623878655]	auto[1]	7	1			T86	1		T244	1		T304	1
auto[3623878656:3758096383]	auto[0]	83	1			T2	1		T13	1		T26	1
auto[3623878656:3758096383]	auto[1]	6	1			T143	1		T243	1		T394	1
auto[3758096384:3892314111]	auto[0]	81	1			T194	1		T107	1		T56	1
auto[3758096384:3892314111]	auto[1]	12	1			T243	2		T239	1		T283	1
auto[3892314112:4026531839]	auto[0]	72	1			T203	1		T29	1		T22	1
auto[3892314112:4026531839]	auto[1]	13	1			T234	1		T289	2		T420	1
auto[4026531840:4160749567]	auto[0]	74	1			T2	1		T70	1		T25	1
auto[4026531840:4160749567]	auto[1]	11	1			T244	1		T334	1		T243	2
auto[4160749568:4294967295]	auto[0]	91	1			T124	1		T28	2		T56	1
auto[4160749568:4294967295]	auto[1]	6	1			T242	2		T433	2		T423	1