Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1366

1

T2

3

T13

5

T16

1

auto[1]

1568

1

T1

2

T2

3

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T13	1		T34	1		T124	1
auto[134217728:268435455]	95	1			T4	1		T13	1		T202	1
auto[268435456:402653183]	75	1			T199	1		T72	1		T95	1
auto[402653184:536870911]	97	1			T4	1		T13	1		T124	1
auto[536870912:671088639]	92	1			T2	1		T21	2		T203	1
auto[671088640:805306367]	95	1			T195	1		T142	1		T27	1
auto[805306368:939524095]	78	1			T12	1		T56	1		T192	1
auto[939524096:1073741823]	90	1			T4	1		T203	1		T194	1
auto[1073741824:1207959551]	94	1			T124	1		T194	1		T29	1
auto[1207959552:1342177279]	92	1			T40	1		T21	1		T44	1
auto[1342177280:1476395007]	87	1			T34	1		T56	1		T86	1
auto[1476395008:1610612735]	100	1			T25	2		T27	1		T56	1
auto[1610612736:1744830463]	104	1			T25	1		T107	2		T137	1
auto[1744830464:1879048191]	80	1			T1	1		T16	1		T143	2
auto[1879048192:2013265919]	116	1			T2	1		T13	1		T69	1
auto[2013265920:2147483647]	95	1			T40	1		T44	1		T35	1
auto[2147483648:2281701375]	93	1			T44	1		T69	1		T70	1
auto[2281701376:2415919103]	85	1			T12	1		T124	1		T28	1
auto[2415919104:2550136831]	93	1			T25	1		T29	1		T22	2
auto[2550136832:2684354559]	74	1			T12	1		T195	1		T70	1
auto[2684354560:2818572287]	94	1			T41	1		T69	1		T29	1
auto[2818572288:2952790015]	94	1			T2	1		T21	1		T195	1
auto[2952790016:3087007743]	117	1			T195	1		T28	1		T107	1
auto[3087007744:3221225471]	82	1			T26	1		T84	1		T197	1
auto[3221225472:3355443199]	76	1			T2	1		T13	1		T69	1
auto[3355443200:3489660927]	100	1			T2	2		T40	1		T57	1
auto[3489660928:3623878655]	89	1			T25	1		T22	1		T109	1
auto[3623878656:3758096383]	97	1			T1	1		T4	1		T124	1
auto[3758096384:3892314111]	91	1			T70	2		T137	1		T186	1
auto[3892314112:4026531839]	81	1			T21	1		T70	1		T26	1
auto[4026531840:4160749567]	101	1			T124	1		T194	1		T188	1
auto[4160749568:4294967295]	83	1			T16	1		T29	1		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T13	1		T34	1		T124	1
auto[0:134217727]	auto[1]	41	1			T69	1		T194	1		T26	1
auto[134217728:268435455]	auto[0]	38	1			T13	1		T107	1		T57	1
auto[134217728:268435455]	auto[1]	57	1			T4	1		T202	1		T195	1
auto[268435456:402653183]	auto[0]	36	1			T72	1		T95	1		T334	1
auto[268435456:402653183]	auto[1]	39	1			T199	1		T67	1		T68	1
auto[402653184:536870911]	auto[0]	45	1			T13	1		T29	1		T23	1
auto[402653184:536870911]	auto[1]	52	1			T4	1		T124	1		T201	1
auto[536870912:671088639]	auto[0]	42	1			T203	1		T23	1		T305	1
auto[536870912:671088639]	auto[1]	50	1			T2	1		T21	2		T57	1
auto[671088640:805306367]	auto[0]	42	1			T190	1		T331	1		T47	1
auto[671088640:805306367]	auto[1]	53	1			T195	1		T142	1		T27	1
auto[805306368:939524095]	auto[0]	33	1			T192	1		T35	1		T93	1
auto[805306368:939524095]	auto[1]	45	1			T12	1		T56	1		T24	1
auto[939524096:1073741823]	auto[0]	48	1			T143	1		T197	1		T93	1
auto[939524096:1073741823]	auto[1]	42	1			T4	1		T203	1		T194	1
auto[1073741824:1207959551]	auto[0]	41	1			T124	1		T29	1		T23	1
auto[1073741824:1207959551]	auto[1]	53	1			T194	1		T57	1		T143	1
auto[1207959552:1342177279]	auto[0]	44	1			T44	1		T70	1		T186	1
auto[1207959552:1342177279]	auto[1]	48	1			T40	1		T21	1		T57	1
auto[1342177280:1476395007]	auto[0]	39	1			T86	1		T113	1		T95	1
auto[1342177280:1476395007]	auto[1]	48	1			T34	1		T56	1		T93	1
auto[1476395008:1610612735]	auto[0]	39	1			T25	2		T109	1		T143	1
auto[1476395008:1610612735]	auto[1]	61	1			T27	1		T56	1		T84	1
auto[1610612736:1744830463]	auto[0]	45	1			T25	1		T137	1		T22	1
auto[1610612736:1744830463]	auto[1]	59	1			T107	2		T109	1		T199	1
auto[1744830464:1879048191]	auto[0]	38	1			T143	1		T245	1		T75	2
auto[1744830464:1879048191]	auto[1]	42	1			T1	1		T16	1		T143	1
auto[1879048192:2013265919]	auto[0]	58	1			T2	1		T13	1		T69	1
auto[1879048192:2013265919]	auto[1]	58	1			T107	1		T137	1		T427	1
auto[2013265920:2147483647]	auto[0]	49	1			T35	1		T238	1		T212	1
auto[2013265920:2147483647]	auto[1]	46	1			T40	1		T44	1		T47	1
auto[2147483648:2281701375]	auto[0]	47	1			T44	1		T69	1		T188	1
auto[2147483648:2281701375]	auto[1]	46	1			T70	1		T188	1		T107	1
auto[2281701376:2415919103]	auto[0]	37	1			T28	1		T22	1		T186	1
auto[2281701376:2415919103]	auto[1]	48	1			T12	1		T124	1		T312	1
auto[2415919104:2550136831]	auto[0]	48	1			T25	1		T22	2		T198	1
auto[2415919104:2550136831]	auto[1]	45	1			T29	1		T109	1		T199	1
auto[2550136832:2684354559]	auto[0]	29	1			T195	1		T45	1		T118	1
auto[2550136832:2684354559]	auto[1]	45	1			T12	1		T70	1		T137	1
auto[2684354560:2818572287]	auto[0]	43	1			T29	1		T112	1		T95	1
auto[2684354560:2818572287]	auto[1]	51	1			T41	1		T69	1		T57	1
auto[2818572288:2952790015]	auto[0]	43	1			T194	1		T68	2		T400	1
auto[2818572288:2952790015]	auto[1]	51	1			T2	1		T21	1		T195	1
auto[2952790016:3087007743]	auto[0]	55	1			T28	1		T107	1		T54	1
auto[2952790016:3087007743]	auto[1]	62	1			T195	1		T57	1		T23	1
auto[3087007744:3221225471]	auto[0]	34	1			T84	1		T93	1		T333	1
auto[3087007744:3221225471]	auto[1]	48	1			T26	1		T197	1		T189	1
auto[3221225472:3355443199]	auto[0]	34	1			T2	1		T13	1		T67	1
auto[3221225472:3355443199]	auto[1]	42	1			T69	1		T45	1		T112	1
auto[3355443200:3489660927]	auto[0]	42	1			T2	1		T40	1		T210	1
auto[3355443200:3489660927]	auto[1]	58	1			T2	1		T57	1		T72	1
auto[3489660928:3623878655]	auto[0]	38	1			T25	1		T22	1		T57	1
auto[3489660928:3623878655]	auto[1]	51	1			T109	1		T39	1		T67	1
auto[3623878656:3758096383]	auto[0]	45	1			T124	1		T28	1		T211	1
auto[3623878656:3758096383]	auto[1]	52	1			T1	1		T4	1		T44	1
auto[3758096384:3892314111]	auto[0]	43	1			T186	1		T84	1		T190	1
auto[3758096384:3892314111]	auto[1]	48	1			T70	2		T137	1		T312	1
auto[3892314112:4026531839]	auto[0]	43	1			T70	1		T26	1		T55	1
auto[3892314112:4026531839]	auto[1]	38	1			T21	1		T210	1		T429	1
auto[4026531840:4160749567]	auto[0]	47	1			T194	1		T188	1		T107	1
auto[4026531840:4160749567]	auto[1]	54	1			T124	1		T57	2		T199	1
auto[4160749568:4294967295]	auto[0]	48	1			T16	1		T29	1		T28	1
auto[4160749568:4294967295]	auto[1]	35	1			T429	1		T60	1		T62	1