Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.10 98.03 98.25 100.00 99.12 98.41 91.71


Total test records in report: 1063
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T355 /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3303331529 Jun 08 02:52:45 PM PDT 24 Jun 08 02:52:48 PM PDT 24 85716050 ps
T1008 /workspace/coverage/default/19.keymgr_smoke.4205578651 Jun 08 02:52:39 PM PDT 24 Jun 08 02:52:44 PM PDT 24 811097529 ps
T1009 /workspace/coverage/default/6.keymgr_smoke.3642434985 Jun 08 02:51:17 PM PDT 24 Jun 08 02:51:23 PM PDT 24 222063221 ps
T42 /workspace/coverage/default/3.keymgr_sec_cm.2632916649 Jun 08 02:51:11 PM PDT 24 Jun 08 02:51:40 PM PDT 24 3792405217 ps
T1010 /workspace/coverage/default/7.keymgr_stress_all.1286895553 Jun 08 02:51:32 PM PDT 24 Jun 08 02:52:15 PM PDT 24 1143499986 ps
T1011 /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3945365220 Jun 08 02:52:14 PM PDT 24 Jun 08 02:52:18 PM PDT 24 88016847 ps
T1012 /workspace/coverage/default/1.keymgr_sideload_protect.1882100639 Jun 08 02:50:48 PM PDT 24 Jun 08 02:50:51 PM PDT 24 373560741 ps
T1013 /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2852198366 Jun 08 02:51:32 PM PDT 24 Jun 08 02:51:35 PM PDT 24 376445423 ps
T1014 /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2911934609 Jun 08 02:51:44 PM PDT 24 Jun 08 02:51:49 PM PDT 24 1114203852 ps
T1015 /workspace/coverage/default/11.keymgr_sideload.357314085 Jun 08 02:51:51 PM PDT 24 Jun 08 02:52:01 PM PDT 24 836328532 ps
T1016 /workspace/coverage/default/28.keymgr_sideload.3117718345 Jun 08 02:53:26 PM PDT 24 Jun 08 02:53:30 PM PDT 24 85132528 ps
T1017 /workspace/coverage/default/12.keymgr_sideload_aes.3095921446 Jun 08 02:51:57 PM PDT 24 Jun 08 02:52:06 PM PDT 24 241987464 ps
T1018 /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1896337247 Jun 08 02:54:21 PM PDT 24 Jun 08 02:54:24 PM PDT 24 101729266 ps
T1019 /workspace/coverage/default/13.keymgr_sideload_kmac.2553748595 Jun 08 02:52:10 PM PDT 24 Jun 08 02:52:46 PM PDT 24 15185486555 ps
T1020 /workspace/coverage/default/38.keymgr_alert_test.4272764524 Jun 08 02:54:23 PM PDT 24 Jun 08 02:54:24 PM PDT 24 22948421 ps
T1021 /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2836869144 Jun 08 02:54:43 PM PDT 24 Jun 08 02:54:46 PM PDT 24 30187179 ps
T1022 /workspace/coverage/default/22.keymgr_sw_invalid_input.3245368634 Jun 08 02:52:54 PM PDT 24 Jun 08 02:52:58 PM PDT 24 153520872 ps
T1023 /workspace/coverage/default/23.keymgr_sideload_aes.2817017789 Jun 08 02:53:02 PM PDT 24 Jun 08 02:53:17 PM PDT 24 505678088 ps
T308 /workspace/coverage/default/26.keymgr_random.3824415584 Jun 08 02:53:17 PM PDT 24 Jun 08 02:55:15 PM PDT 24 49641026309 ps
T1024 /workspace/coverage/default/15.keymgr_custom_cm.2983516882 Jun 08 02:52:17 PM PDT 24 Jun 08 02:52:33 PM PDT 24 1347505853 ps
T1025 /workspace/coverage/default/17.keymgr_alert_test.351890389 Jun 08 02:52:34 PM PDT 24 Jun 08 02:52:35 PM PDT 24 22749885 ps
T1026 /workspace/coverage/default/12.keymgr_sideload.3670275099 Jun 08 02:52:00 PM PDT 24 Jun 08 02:52:02 PM PDT 24 289510795 ps
T1027 /workspace/coverage/default/8.keymgr_sideload.2996437215 Jun 08 02:51:33 PM PDT 24 Jun 08 02:51:36 PM PDT 24 238531553 ps
T1028 /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1241004646 Jun 08 02:54:34 PM PDT 24 Jun 08 02:54:37 PM PDT 24 88658514 ps
T1029 /workspace/coverage/default/8.keymgr_random.4054652377 Jun 08 02:51:33 PM PDT 24 Jun 08 02:51:41 PM PDT 24 622834625 ps
T1030 /workspace/coverage/default/15.keymgr_sideload_otbn.3117318650 Jun 08 02:52:17 PM PDT 24 Jun 08 02:52:21 PM PDT 24 241198065 ps
T1031 /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1754067555 Jun 08 02:53:57 PM PDT 24 Jun 08 02:54:01 PM PDT 24 992046026 ps
T1032 /workspace/coverage/default/7.keymgr_sideload_aes.2509693303 Jun 08 02:51:28 PM PDT 24 Jun 08 02:52:05 PM PDT 24 6175430238 ps
T1033 /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2030226083 Jun 08 02:52:20 PM PDT 24 Jun 08 02:52:31 PM PDT 24 573738625 ps
T362 /workspace/coverage/default/42.keymgr_sw_invalid_input.279166918 Jun 08 02:54:44 PM PDT 24 Jun 08 02:54:50 PM PDT 24 191891263 ps
T1034 /workspace/coverage/default/29.keymgr_sideload_protect.2168608734 Jun 08 02:53:38 PM PDT 24 Jun 08 02:53:44 PM PDT 24 939861827 ps
T1035 /workspace/coverage/default/42.keymgr_alert_test.765538894 Jun 08 02:54:43 PM PDT 24 Jun 08 02:54:44 PM PDT 24 26363574 ps
T1036 /workspace/coverage/default/44.keymgr_sideload_protect.1154306947 Jun 08 02:54:51 PM PDT 24 Jun 08 02:54:53 PM PDT 24 49072940 ps
T1037 /workspace/coverage/default/35.keymgr_sideload_otbn.3364076352 Jun 08 02:54:02 PM PDT 24 Jun 08 02:54:44 PM PDT 24 3105056383 ps
T1038 /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.303665297 Jun 08 02:51:53 PM PDT 24 Jun 08 02:52:04 PM PDT 24 1029214975 ps
T1039 /workspace/coverage/default/17.keymgr_sw_invalid_input.2532612681 Jun 08 02:52:29 PM PDT 24 Jun 08 02:52:35 PM PDT 24 663733238 ps
T1040 /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3433080481 Jun 08 02:51:52 PM PDT 24 Jun 08 02:51:59 PM PDT 24 292932365 ps
T1041 /workspace/coverage/default/39.keymgr_sideload_otbn.3141645173 Jun 08 02:54:25 PM PDT 24 Jun 08 02:54:29 PM PDT 24 365471395 ps
T1042 /workspace/coverage/default/28.keymgr_cfg_regwen.4043078518 Jun 08 02:53:34 PM PDT 24 Jun 08 02:54:32 PM PDT 24 1837907030 ps
T1043 /workspace/coverage/default/32.keymgr_lc_disable.1580014807 Jun 08 02:53:52 PM PDT 24 Jun 08 02:53:54 PM PDT 24 82529514 ps
T1044 /workspace/coverage/default/4.keymgr_cfg_regwen.2039473279 Jun 08 02:51:09 PM PDT 24 Jun 08 02:51:16 PM PDT 24 913537428 ps
T267 /workspace/coverage/default/37.keymgr_cfg_regwen.2290581821 Jun 08 02:54:17 PM PDT 24 Jun 08 02:55:33 PM PDT 24 2900382773 ps
T1045 /workspace/coverage/default/46.keymgr_direct_to_disabled.546510546 Jun 08 02:55:04 PM PDT 24 Jun 08 02:55:07 PM PDT 24 81770535 ps
T1046 /workspace/coverage/default/40.keymgr_sideload.3009957521 Jun 08 02:54:32 PM PDT 24 Jun 08 02:54:35 PM PDT 24 61054989 ps
T1047 /workspace/coverage/default/31.keymgr_sideload_aes.1727386602 Jun 08 02:53:44 PM PDT 24 Jun 08 02:54:49 PM PDT 24 3424867156 ps
T1048 /workspace/coverage/default/33.keymgr_smoke.432769459 Jun 08 02:53:57 PM PDT 24 Jun 08 02:54:01 PM PDT 24 251742903 ps
T1049 /workspace/coverage/default/28.keymgr_alert_test.2105912776 Jun 08 02:53:30 PM PDT 24 Jun 08 02:53:31 PM PDT 24 49320725 ps
T1050 /workspace/coverage/default/47.keymgr_direct_to_disabled.2519815652 Jun 08 02:55:04 PM PDT 24 Jun 08 02:55:06 PM PDT 24 421412875 ps
T1051 /workspace/coverage/default/48.keymgr_sideload_aes.3007258878 Jun 08 02:55:06 PM PDT 24 Jun 08 02:55:08 PM PDT 24 93338145 ps
T1052 /workspace/coverage/default/32.keymgr_sideload_otbn.3742949475 Jun 08 02:53:52 PM PDT 24 Jun 08 02:53:56 PM PDT 24 624501151 ps
T1053 /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1621331532 Jun 08 02:53:41 PM PDT 24 Jun 08 02:53:44 PM PDT 24 149257551 ps
T1054 /workspace/coverage/default/18.keymgr_random.3119453198 Jun 08 02:52:36 PM PDT 24 Jun 08 02:52:39 PM PDT 24 156731364 ps
T1055 /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1002653896 Jun 08 02:51:32 PM PDT 24 Jun 08 02:51:39 PM PDT 24 255369057 ps
T1056 /workspace/coverage/default/35.keymgr_random.700543040 Jun 08 02:54:01 PM PDT 24 Jun 08 02:54:40 PM PDT 24 4221892657 ps
T1057 /workspace/coverage/default/0.keymgr_kmac_rsp_err.2917558768 Jun 08 02:50:44 PM PDT 24 Jun 08 02:51:54 PM PDT 24 17012411495 ps
T1058 /workspace/coverage/default/4.keymgr_sw_invalid_input.642960907 Jun 08 02:51:09 PM PDT 24 Jun 08 02:51:14 PM PDT 24 2575048790 ps
T1059 /workspace/coverage/default/9.keymgr_custom_cm.1744858940 Jun 08 02:51:41 PM PDT 24 Jun 08 02:51:52 PM PDT 24 296904257 ps
T1060 /workspace/coverage/default/25.keymgr_sideload.1273370896 Jun 08 02:53:13 PM PDT 24 Jun 08 02:53:17 PM PDT 24 98573793 ps
T1061 /workspace/coverage/default/7.keymgr_kmac_rsp_err.1047964865 Jun 08 02:51:33 PM PDT 24 Jun 08 02:51:37 PM PDT 24 766370455 ps
T1062 /workspace/coverage/default/27.keymgr_sideload_otbn.1963239141 Jun 08 02:53:21 PM PDT 24 Jun 08 02:53:25 PM PDT 24 82162726 ps
T384 /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2512876660 Jun 08 02:51:31 PM PDT 24 Jun 08 02:51:35 PM PDT 24 384760898 ps
T343 /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1543561991 Jun 08 02:53:21 PM PDT 24 Jun 08 02:53:24 PM PDT 24 37997704 ps
T1063 /workspace/coverage/default/49.keymgr_lc_disable.2287842862 Jun 08 02:55:11 PM PDT 24 Jun 08 02:55:15 PM PDT 24 407398590 ps

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1352065656
Short name T12
Test name
Test status
Simulation time 163827455 ps
CPU time 4.42 seconds
Started Jun 08 02:50:53 PM PDT 24
Finished Jun 08 02:50:58 PM PDT 24
Peak memory 207048 kb
Host smart-ca409887-2e00-4fb9-92b3-640886b4469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352065656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1352065656
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2794334321
Short name T57
Test name
Test status
Simulation time 62797821869 ps
CPU time 358.86 seconds
Started Jun 08 02:51:07 PM PDT 24
Finished Jun 08 02:57:06 PM PDT 24
Peak memory 222240 kb
Host smart-aa201b75-6b72-4e4e-b3f7-08eb8a760d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794334321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2794334321
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2510690509
Short name T70
Test name
Test status
Simulation time 59832500 ps
CPU time 3.52 seconds
Started Jun 08 02:54:30 PM PDT 24
Finished Jun 08 02:54:34 PM PDT 24
Peak memory 209384 kb
Host smart-e8bb54f2-5e92-4b4a-9a21-81709fe8d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510690509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2510690509
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3459140809
Short name T5
Test name
Test status
Simulation time 2090125313 ps
CPU time 32.52 seconds
Started Jun 08 02:51:01 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 234888 kb
Host smart-4782edc5-1d30-4200-b8a9-9f693ca7bad0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459140809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3459140809
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2336089477
Short name T58
Test name
Test status
Simulation time 3964567738 ps
CPU time 45.36 seconds
Started Jun 08 02:52:58 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 222356 kb
Host smart-65d5d116-4956-4c99-af37-f35c11b7468d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336089477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2336089477
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2675676245
Short name T107
Test name
Test status
Simulation time 1096711639 ps
CPU time 18.79 seconds
Started Jun 08 02:52:37 PM PDT 24
Finished Jun 08 02:52:56 PM PDT 24
Peak memory 222336 kb
Host smart-086f4d4f-ded3-471e-80bc-d39da5dfbfee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675676245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2675676245
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2544687751
Short name T123
Test name
Test status
Simulation time 942614529 ps
CPU time 5.09 seconds
Started Jun 08 02:23:29 PM PDT 24
Finished Jun 08 02:23:34 PM PDT 24
Peak memory 214008 kb
Host smart-54dfdaa3-4f9d-4c6a-84b1-a0bed3af2a87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544687751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2544687751
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.172772770
Short name T21
Test name
Test status
Simulation time 716850918 ps
CPU time 21.58 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:50 PM PDT 24
Peak memory 213928 kb
Host smart-6dd42531-59df-48df-8989-d8647a72003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172772770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.172772770
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1672542689
Short name T124
Test name
Test status
Simulation time 1974744855 ps
CPU time 10.57 seconds
Started Jun 08 02:53:16 PM PDT 24
Finished Jun 08 02:53:27 PM PDT 24
Peak memory 222188 kb
Host smart-b3211f69-9a89-452a-b0a3-c50809063700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672542689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1672542689
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1152562314
Short name T48
Test name
Test status
Simulation time 5734493149 ps
CPU time 59.66 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:55:45 PM PDT 24
Peak memory 215052 kb
Host smart-0b65137a-dd65-465d-aae0-dd5a661d5640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152562314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1152562314
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2740118564
Short name T8
Test name
Test status
Simulation time 35637459 ps
CPU time 2.14 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:13 PM PDT 24
Peak memory 207212 kb
Host smart-91315ed8-6f84-4d9c-b388-d4bdc02c3a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740118564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2740118564
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2040815241
Short name T60
Test name
Test status
Simulation time 25042816766 ps
CPU time 52.97 seconds
Started Jun 08 02:50:52 PM PDT 24
Finished Jun 08 02:51:45 PM PDT 24
Peak memory 222260 kb
Host smart-84c30efb-ff42-4d23-b047-8990602e9d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040815241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2040815241
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.171510006
Short name T86
Test name
Test status
Simulation time 717779258 ps
CPU time 10.61 seconds
Started Jun 08 02:52:18 PM PDT 24
Finished Jun 08 02:52:29 PM PDT 24
Peak memory 215336 kb
Host smart-424c8f8e-d32f-4983-b73b-ff4e08f6468a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171510006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.171510006
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2457879813
Short name T23
Test name
Test status
Simulation time 1035508274 ps
CPU time 10.28 seconds
Started Jun 08 02:53:55 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 214056 kb
Host smart-985b8b19-706b-4789-b406-e5c9acf68755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457879813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2457879813
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.46972277
Short name T50
Test name
Test status
Simulation time 320268873 ps
CPU time 2.47 seconds
Started Jun 08 02:54:50 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 214056 kb
Host smart-bd51a9b5-e839-401c-a8cb-a3a3460db4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46972277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.46972277
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1248725102
Short name T139
Test name
Test status
Simulation time 1440131824 ps
CPU time 12.92 seconds
Started Jun 08 02:23:05 PM PDT 24
Finished Jun 08 02:23:18 PM PDT 24
Peak memory 213768 kb
Host smart-f7cb948e-2cb3-4b60-b209-ef4cbc1f2b11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248725102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1248725102
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1460518082
Short name T137
Test name
Test status
Simulation time 389870612 ps
CPU time 3.35 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:31 PM PDT 24
Peak memory 213976 kb
Host smart-ba3b640b-c110-42a6-b74b-58f17d113a01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460518082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1460518082
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4115573735
Short name T13
Test name
Test status
Simulation time 408813928 ps
CPU time 3.77 seconds
Started Jun 08 02:51:52 PM PDT 24
Finished Jun 08 02:51:56 PM PDT 24
Peak memory 209868 kb
Host smart-193f7dce-eb10-4d64-a67d-901301d41e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115573735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4115573735
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4284070475
Short name T243
Test name
Test status
Simulation time 265862191 ps
CPU time 13.29 seconds
Started Jun 08 02:52:51 PM PDT 24
Finished Jun 08 02:53:04 PM PDT 24
Peak memory 213960 kb
Host smart-fb98cdb4-5421-4841-a05f-3d9265f180ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284070475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4284070475
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3360363279
Short name T261
Test name
Test status
Simulation time 7526938075 ps
CPU time 130.71 seconds
Started Jun 08 02:54:26 PM PDT 24
Finished Jun 08 02:56:37 PM PDT 24
Peak memory 219540 kb
Host smart-c45739ff-9511-4fa9-b318-b2b774aa60c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360363279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3360363279
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2679113457
Short name T55
Test name
Test status
Simulation time 5784810190 ps
CPU time 18.47 seconds
Started Jun 08 02:53:55 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 216044 kb
Host smart-3f12e91e-6c9f-4f30-bd96-7580ec000318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679113457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2679113457
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.965370447
Short name T25
Test name
Test status
Simulation time 64057008 ps
CPU time 3.68 seconds
Started Jun 08 02:51:30 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 222592 kb
Host smart-a34cc962-e6a2-4d67-9f8d-7906ad8738ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965370447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.965370447
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1140026159
Short name T35
Test name
Test status
Simulation time 9329533048 ps
CPU time 82.99 seconds
Started Jun 08 02:55:01 PM PDT 24
Finished Jun 08 02:56:24 PM PDT 24
Peak memory 228180 kb
Host smart-24e9c0f7-3e30-48a8-b22c-05e07c362d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140026159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1140026159
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1807392950
Short name T437
Test name
Test status
Simulation time 375874485 ps
CPU time 19.34 seconds
Started Jun 08 02:55:13 PM PDT 24
Finished Jun 08 02:55:33 PM PDT 24
Peak memory 215412 kb
Host smart-41cabbe7-2138-4606-a69e-0d033a29c79f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807392950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1807392950
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2562253401
Short name T189
Test name
Test status
Simulation time 502327541 ps
CPU time 20.74 seconds
Started Jun 08 02:52:04 PM PDT 24
Finished Jun 08 02:52:25 PM PDT 24
Peak memory 222304 kb
Host smart-3bb4c777-1857-46ec-b4f9-ebbb3f8deb6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562253401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2562253401
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3507016869
Short name T75
Test name
Test status
Simulation time 214962375 ps
CPU time 10.16 seconds
Started Jun 08 02:52:20 PM PDT 24
Finished Jun 08 02:52:31 PM PDT 24
Peak memory 219872 kb
Host smart-92819929-fac0-4466-af5b-e2a4ee91876e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507016869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3507016869
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_random.1448661195
Short name T40
Test name
Test status
Simulation time 5088642448 ps
CPU time 9.11 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 209456 kb
Host smart-d4d0b2bf-c0f1-4022-b4ee-9602e3911bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448661195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1448661195
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.402215167
Short name T239
Test name
Test status
Simulation time 488168106 ps
CPU time 6.55 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:56 PM PDT 24
Peak memory 214432 kb
Host smart-cfa5aeed-c5e9-4704-bf02-95278e333ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402215167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.402215167
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.756170889
Short name T62
Test name
Test status
Simulation time 1157313621 ps
CPU time 42.92 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:55 PM PDT 24
Peak memory 222216 kb
Host smart-2c07b24a-2193-4820-945a-a712b7d94390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756170889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.756170889
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3183158503
Short name T224
Test name
Test status
Simulation time 141999305 ps
CPU time 5.75 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:34 PM PDT 24
Peak memory 210136 kb
Host smart-ebcfdf18-5769-4042-b05e-44b6dfa69b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183158503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3183158503
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3955164432
Short name T143
Test name
Test status
Simulation time 199285019 ps
CPU time 3.77 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:05 PM PDT 24
Peak memory 213980 kb
Host smart-308cef25-7c05-43c3-bfc5-a94247778b73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955164432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3955164432
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.562065713
Short name T197
Test name
Test status
Simulation time 245811510 ps
CPU time 12.37 seconds
Started Jun 08 02:54:42 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 222624 kb
Host smart-6812ee40-887b-4828-abb6-2400ada53ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562065713 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.562065713
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1468431843
Short name T157
Test name
Test status
Simulation time 463482033 ps
CPU time 6.13 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 217520 kb
Host smart-36b037ea-c2d3-432d-9578-9b9cb94fc664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468431843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1468431843
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.766777690
Short name T121
Test name
Test status
Simulation time 222599614 ps
CPU time 6.01 seconds
Started Jun 08 02:22:06 PM PDT 24
Finished Jun 08 02:22:12 PM PDT 24
Peak memory 214016 kb
Host smart-a54b1187-9310-4934-b366-143bb8640604
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766777690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.766777690
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1568566931
Short name T204
Test name
Test status
Simulation time 62674103 ps
CPU time 3.07 seconds
Started Jun 08 02:50:44 PM PDT 24
Finished Jun 08 02:50:47 PM PDT 24
Peak memory 208144 kb
Host smart-066a9b9a-6cca-4c13-bbee-a3f600cd2439
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568566931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1568566931
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1565023448
Short name T20
Test name
Test status
Simulation time 3030209217 ps
CPU time 9.64 seconds
Started Jun 08 02:54:09 PM PDT 24
Finished Jun 08 02:54:19 PM PDT 24
Peak memory 214084 kb
Host smart-ee595491-78cd-47c6-97ae-e0bb9fe95e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565023448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1565023448
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.4043078518
Short name T1042
Test name
Test status
Simulation time 1837907030 ps
CPU time 58.39 seconds
Started Jun 08 02:53:34 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 214032 kb
Host smart-bb18f45c-7729-4262-a83f-f8bc50161aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043078518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4043078518
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2672919674
Short name T49
Test name
Test status
Simulation time 646108354 ps
CPU time 30.68 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:37 PM PDT 24
Peak memory 216104 kb
Host smart-db12670d-2393-48eb-a6a3-75d6a8dfe314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672919674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2672919674
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.815309651
Short name T93
Test name
Test status
Simulation time 64637937 ps
CPU time 3.27 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 213868 kb
Host smart-cb99b7b0-6e52-4766-83ee-619af6a48a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815309651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.815309651
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1459043846
Short name T252
Test name
Test status
Simulation time 150948890 ps
CPU time 6.08 seconds
Started Jun 08 02:52:55 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 222132 kb
Host smart-025ae299-f57f-4adb-ab7c-91ce6236663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459043846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1459043846
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1416883559
Short name T235
Test name
Test status
Simulation time 45926449 ps
CPU time 3.42 seconds
Started Jun 08 02:53:51 PM PDT 24
Finished Jun 08 02:53:55 PM PDT 24
Peak memory 213968 kb
Host smart-0830ac20-c667-4a0d-825f-cdf4262e66b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416883559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1416883559
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2816771203
Short name T352
Test name
Test status
Simulation time 1356998813 ps
CPU time 46.03 seconds
Started Jun 08 02:53:22 PM PDT 24
Finished Jun 08 02:54:08 PM PDT 24
Peak memory 222256 kb
Host smart-866bbe9b-ad29-4a94-b454-4b44f97559ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816771203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2816771203
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2850139840
Short name T334
Test name
Test status
Simulation time 3037793578 ps
CPU time 42.13 seconds
Started Jun 08 02:54:52 PM PDT 24
Finished Jun 08 02:55:34 PM PDT 24
Peak memory 214536 kb
Host smart-2297d1b2-0376-44b6-8222-c2fc09cdd996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850139840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2850139840
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3614399447
Short name T164
Test name
Test status
Simulation time 3432560071 ps
CPU time 24.72 seconds
Started Jun 08 02:23:51 PM PDT 24
Finished Jun 08 02:24:16 PM PDT 24
Peak memory 208708 kb
Host smart-9eb9b496-1309-46b3-9933-b42e0f4efc29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614399447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3614399447
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2554059635
Short name T135
Test name
Test status
Simulation time 9523012 ps
CPU time 0.74 seconds
Started Jun 08 02:50:51 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 205524 kb
Host smart-e789d258-b764-4b5b-a0bc-71041156974b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554059635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2554059635
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1964942296
Short name T232
Test name
Test status
Simulation time 803098241 ps
CPU time 29.84 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 222228 kb
Host smart-4876d410-8bf9-4d59-a9f4-b22872e3452b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964942296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1964942296
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1491375367
Short name T95
Test name
Test status
Simulation time 508205123 ps
CPU time 5.33 seconds
Started Jun 08 02:54:57 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 218296 kb
Host smart-a570e4eb-5bda-43da-9e46-dfe42312610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491375367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1491375367
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2916924834
Short name T273
Test name
Test status
Simulation time 336370961 ps
CPU time 4.18 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:55 PM PDT 24
Peak memory 214992 kb
Host smart-52093691-4dcb-4fb7-b7f4-41ae6b82b506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916924834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2916924834
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4173217992
Short name T338
Test name
Test status
Simulation time 75602192 ps
CPU time 2.41 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 210860 kb
Host smart-08e2d7a6-0eae-45ab-9fef-8e3efcb6c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173217992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4173217992
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.181068179
Short name T266
Test name
Test status
Simulation time 170459194 ps
CPU time 6.68 seconds
Started Jun 08 02:54:31 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 222148 kb
Host smart-e88871f9-ea0e-473d-a856-3b69eb07d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181068179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.181068179
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.1161679877
Short name T194
Test name
Test status
Simulation time 668102371 ps
CPU time 9.09 seconds
Started Jun 08 02:51:12 PM PDT 24
Finished Jun 08 02:51:21 PM PDT 24
Peak memory 208692 kb
Host smart-09b1f116-7d23-4252-bd0b-7296dea2fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161679877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1161679877
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4106709120
Short name T165
Test name
Test status
Simulation time 229155228 ps
CPU time 5.92 seconds
Started Jun 08 02:23:13 PM PDT 24
Finished Jun 08 02:23:19 PM PDT 24
Peak memory 213668 kb
Host smart-cb6c4e4c-3f58-43df-8d49-cdab06fafc42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106709120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4106709120
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3640748894
Short name T745
Test name
Test status
Simulation time 613570518 ps
CPU time 4.24 seconds
Started Jun 08 02:52:44 PM PDT 24
Finished Jun 08 02:52:49 PM PDT 24
Peak memory 222428 kb
Host smart-a57b5601-8f5d-4578-827e-6ffd05e9e483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640748894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3640748894
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3724605894
Short name T161
Test name
Test status
Simulation time 434645701 ps
CPU time 8.43 seconds
Started Jun 08 02:23:47 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 213820 kb
Host smart-dec69ea8-e083-4e86-be43-636e0f3f4b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724605894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3724605894
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.461382596
Short name T159
Test name
Test status
Simulation time 317956685 ps
CPU time 7.61 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 222236 kb
Host smart-6eb7ff7f-0453-47d1-b031-5db8b44825fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461382596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.461382596
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1593341647
Short name T307
Test name
Test status
Simulation time 739165368 ps
CPU time 29.49 seconds
Started Jun 08 02:50:48 PM PDT 24
Finished Jun 08 02:51:18 PM PDT 24
Peak memory 221336 kb
Host smart-43bb9791-d0ae-4170-a6ee-fb5e4c36d3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593341647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1593341647
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1296581126
Short name T419
Test name
Test status
Simulation time 1108501837 ps
CPU time 29.09 seconds
Started Jun 08 02:52:12 PM PDT 24
Finished Jun 08 02:52:41 PM PDT 24
Peak memory 214080 kb
Host smart-d217aa45-d773-4686-8ba4-8f5542920995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296581126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1296581126
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2189641346
Short name T227
Test name
Test status
Simulation time 3861988848 ps
CPU time 119.49 seconds
Started Jun 08 02:53:15 PM PDT 24
Finished Jun 08 02:55:15 PM PDT 24
Peak memory 215384 kb
Host smart-35ec10ab-765e-43c1-afbc-23b204f39481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189641346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2189641346
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.981982787
Short name T67
Test name
Test status
Simulation time 297183920 ps
CPU time 4.13 seconds
Started Jun 08 02:53:14 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 220280 kb
Host smart-6fde8bb5-525d-4073-a640-bda35e3211c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981982787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.981982787
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.651296464
Short name T109
Test name
Test status
Simulation time 456509191 ps
CPU time 8.44 seconds
Started Jun 08 02:52:02 PM PDT 24
Finished Jun 08 02:52:10 PM PDT 24
Peak memory 224236 kb
Host smart-10c7d12d-bf73-4d92-bbc4-1ef2459cf783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651296464 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.651296464
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3310209544
Short name T163
Test name
Test status
Simulation time 327417412 ps
CPU time 10.46 seconds
Started Jun 08 02:22:08 PM PDT 24
Finished Jun 08 02:22:19 PM PDT 24
Peak memory 213792 kb
Host smart-454e116b-1eb0-4da4-8fbb-aeeafde67585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310209544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3310209544
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3338310281
Short name T167
Test name
Test status
Simulation time 279755836 ps
CPU time 9.87 seconds
Started Jun 08 02:23:18 PM PDT 24
Finished Jun 08 02:23:28 PM PDT 24
Peak memory 213740 kb
Host smart-c5945f17-3b1f-4e11-8b77-7e5475bf4375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338310281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3338310281
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.851820198
Short name T174
Test name
Test status
Simulation time 1032598385 ps
CPU time 9.29 seconds
Started Jun 08 02:22:57 PM PDT 24
Finished Jun 08 02:23:06 PM PDT 24
Peak memory 217672 kb
Host smart-37dc449f-2a38-45c4-ba99-7f7ed619d2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851820198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
851820198
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1409283831
Short name T213
Test name
Test status
Simulation time 146516570 ps
CPU time 9.72 seconds
Started Jun 08 02:52:19 PM PDT 24
Finished Jun 08 02:52:28 PM PDT 24
Peak memory 223300 kb
Host smart-6ff9cfdf-e301-49ce-89a5-bd13c1b440ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409283831 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1409283831
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.328237281
Short name T350
Test name
Test status
Simulation time 1533347640 ps
CPU time 7.34 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:54:03 PM PDT 24
Peak memory 214276 kb
Host smart-174ec4ec-d98d-4775-9974-a03d63fd1a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328237281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.328237281
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3820756351
Short name T259
Test name
Test status
Simulation time 42400832 ps
CPU time 3.44 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 214996 kb
Host smart-321fc646-88e9-4096-a185-811ad3327ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820756351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3820756351
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1682736478
Short name T354
Test name
Test status
Simulation time 1580169819 ps
CPU time 45.63 seconds
Started Jun 08 02:51:07 PM PDT 24
Finished Jun 08 02:51:53 PM PDT 24
Peak memory 222268 kb
Host smart-a790996e-2c8b-47ec-afc0-e9a3cf85ad7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682736478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1682736478
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2700603349
Short name T220
Test name
Test status
Simulation time 2380311208 ps
CPU time 10.1 seconds
Started Jun 08 02:51:17 PM PDT 24
Finished Jun 08 02:51:28 PM PDT 24
Peak memory 222408 kb
Host smart-77a1ba73-ee54-4722-953e-e4ba9e4d3521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700603349 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2700603349
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2534191517
Short name T158
Test name
Test status
Simulation time 43547237 ps
CPU time 1.89 seconds
Started Jun 08 02:50:50 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 214436 kb
Host smart-5ee1da75-7ec5-487e-98ac-efa130f1dc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534191517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2534191517
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3422243595
Short name T236
Test name
Test status
Simulation time 401351472 ps
CPU time 10.68 seconds
Started Jun 08 02:50:42 PM PDT 24
Finished Jun 08 02:50:53 PM PDT 24
Peak memory 214044 kb
Host smart-49cb9599-cc03-401e-bbf9-679b4107d09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422243595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3422243595
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3024311614
Short name T275
Test name
Test status
Simulation time 573589140 ps
CPU time 9.23 seconds
Started Jun 08 02:52:01 PM PDT 24
Finished Jun 08 02:52:10 PM PDT 24
Peak memory 209444 kb
Host smart-9daad4ed-c31f-4211-9a3b-29cd1ac04202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024311614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3024311614
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3395116147
Short name T114
Test name
Test status
Simulation time 4940743597 ps
CPU time 25.52 seconds
Started Jun 08 02:52:11 PM PDT 24
Finished Jun 08 02:52:37 PM PDT 24
Peak memory 208684 kb
Host smart-253dd3a4-9685-431c-80ef-53dc6d6e4dd3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395116147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3395116147
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.590456014
Short name T395
Test name
Test status
Simulation time 208154609 ps
CPU time 2.27 seconds
Started Jun 08 02:52:49 PM PDT 24
Finished Jun 08 02:52:51 PM PDT 24
Peak memory 209760 kb
Host smart-ba05a3c2-03e8-4dab-b6ad-fc373efdb29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590456014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.590456014
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1078786156
Short name T98
Test name
Test status
Simulation time 87203061 ps
CPU time 4.62 seconds
Started Jun 08 02:52:54 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 213960 kb
Host smart-c9cfbd93-8c5a-4973-a147-52d5ae6b9128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078786156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1078786156
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2271644791
Short name T340
Test name
Test status
Simulation time 158232463 ps
CPU time 4.64 seconds
Started Jun 08 02:53:04 PM PDT 24
Finished Jun 08 02:53:09 PM PDT 24
Peak memory 211044 kb
Host smart-c8379373-b9e4-43a2-b58a-b30c70b7a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271644791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2271644791
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2596742668
Short name T388
Test name
Test status
Simulation time 47482443 ps
CPU time 2.44 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:14 PM PDT 24
Peak memory 207160 kb
Host smart-78caa0dd-3ecb-467f-9f55-903cd890c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596742668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2596742668
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3893365100
Short name T337
Test name
Test status
Simulation time 467700779 ps
CPU time 6.03 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:57 PM PDT 24
Peak memory 222140 kb
Host smart-57bf0657-9c23-40c5-9886-53b086ade547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893365100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3893365100
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.940969275
Short name T162
Test name
Test status
Simulation time 175633677 ps
CPU time 6.83 seconds
Started Jun 08 02:23:20 PM PDT 24
Finished Jun 08 02:23:27 PM PDT 24
Peak memory 209016 kb
Host smart-fa1b7945-41e5-41e8-90b2-260f3f41bfdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940969275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.940969275
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2861378569
Short name T173
Test name
Test status
Simulation time 576080763 ps
CPU time 7.12 seconds
Started Jun 08 02:23:35 PM PDT 24
Finished Jun 08 02:23:42 PM PDT 24
Peak memory 213684 kb
Host smart-86e77c46-e7f8-4e28-9cf8-f8ffa4f325f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861378569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2861378569
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.137130928
Short name T11
Test name
Test status
Simulation time 1542845802 ps
CPU time 47.28 seconds
Started Jun 08 02:50:48 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 242880 kb
Host smart-43d47232-a242-41f7-b4cb-03614e6d1c74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137130928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.137130928
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2462373228
Short name T1002
Test name
Test status
Simulation time 616775434 ps
CPU time 7.65 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:57 PM PDT 24
Peak memory 217968 kb
Host smart-76f937a3-bdc0-4d27-bd03-034a5bd3ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462373228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2462373228
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2539607767
Short name T215
Test name
Test status
Simulation time 208130210 ps
CPU time 3.25 seconds
Started Jun 08 02:51:51 PM PDT 24
Finished Jun 08 02:51:55 PM PDT 24
Peak memory 222540 kb
Host smart-87c05943-d669-4f9a-be08-8d80c7c09b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539607767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2539607767
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1040810264
Short name T576
Test name
Test status
Simulation time 91038001 ps
CPU time 2.46 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:52:00 PM PDT 24
Peak memory 210180 kb
Host smart-44821384-4e1d-47b8-93b2-d20345ae284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040810264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1040810264
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2139887459
Short name T198
Test name
Test status
Simulation time 214286616 ps
CPU time 7.39 seconds
Started Jun 08 02:52:01 PM PDT 24
Finished Jun 08 02:52:09 PM PDT 24
Peak memory 209296 kb
Host smart-c26dba96-6500-4af5-90eb-569479713a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139887459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2139887459
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3314869235
Short name T391
Test name
Test status
Simulation time 1148369282 ps
CPU time 13.34 seconds
Started Jun 08 02:52:08 PM PDT 24
Finished Jun 08 02:52:22 PM PDT 24
Peak memory 213900 kb
Host smart-f8dea44e-f3f1-4486-991b-0ffe0d0b2181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314869235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3314869235
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.388531600
Short name T375
Test name
Test status
Simulation time 93710666 ps
CPU time 4.59 seconds
Started Jun 08 02:52:09 PM PDT 24
Finished Jun 08 02:52:13 PM PDT 24
Peak memory 209936 kb
Host smart-a5e027e9-ecb7-42d5-b28e-6cf3095b818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388531600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.388531600
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3294924712
Short name T282
Test name
Test status
Simulation time 217675984 ps
CPU time 4.03 seconds
Started Jun 08 02:52:21 PM PDT 24
Finished Jun 08 02:52:25 PM PDT 24
Peak memory 214064 kb
Host smart-402f2817-89c8-406c-83bb-13cec6530e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294924712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3294924712
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1129751180
Short name T77
Test name
Test status
Simulation time 3224249361 ps
CPU time 23.31 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:57 PM PDT 24
Peak memory 222292 kb
Host smart-ac938b2a-2dac-41a7-8e9e-4418a5ce9942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129751180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1129751180
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1147739669
Short name T315
Test name
Test status
Simulation time 141947579 ps
CPU time 5.71 seconds
Started Jun 08 02:52:41 PM PDT 24
Finished Jun 08 02:52:46 PM PDT 24
Peak memory 214060 kb
Host smart-a257c5e2-ab48-42ac-9dc5-c01cc8c22336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147739669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1147739669
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3691124594
Short name T257
Test name
Test status
Simulation time 39428517 ps
CPU time 2.93 seconds
Started Jun 08 02:50:53 PM PDT 24
Finished Jun 08 02:50:56 PM PDT 24
Peak memory 215212 kb
Host smart-bc7498fc-b40e-44c8-ba41-804028e796c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691124594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3691124594
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2763645351
Short name T316
Test name
Test status
Simulation time 168886261 ps
CPU time 6.83 seconds
Started Jun 08 02:51:00 PM PDT 24
Finished Jun 08 02:51:07 PM PDT 24
Peak memory 222128 kb
Host smart-8a0bb5a8-2af7-4e2d-b2dd-c4e196d9f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763645351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2763645351
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1870759150
Short name T190
Test name
Test status
Simulation time 14532052987 ps
CPU time 63.36 seconds
Started Jun 08 02:52:59 PM PDT 24
Finished Jun 08 02:54:03 PM PDT 24
Peak memory 230356 kb
Host smart-9f44c163-e6a3-46ab-87c2-21651d783c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870759150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1870759150
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.2444793083
Short name T610
Test name
Test status
Simulation time 2069206018 ps
CPU time 9.13 seconds
Started Jun 08 02:53:10 PM PDT 24
Finished Jun 08 02:53:20 PM PDT 24
Peak memory 208504 kb
Host smart-ce63ca25-2127-46e5-8c34-ac86608509ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444793083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2444793083
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.229675026
Short name T233
Test name
Test status
Simulation time 299186777 ps
CPU time 5.89 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:19 PM PDT 24
Peak memory 219308 kb
Host smart-a2a5e6ce-91f1-4360-9d0f-a8bd3f5fc7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229675026 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.229675026
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1543561991
Short name T343
Test name
Test status
Simulation time 37997704 ps
CPU time 2.81 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 218788 kb
Host smart-16f1a961-167c-4e30-b293-7e4203c458f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543561991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1543561991
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3091329690
Short name T47
Test name
Test status
Simulation time 1212760133 ps
CPU time 3.89 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:50 PM PDT 24
Peak memory 222188 kb
Host smart-28ea2195-fd49-4894-b134-83e543b593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091329690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3091329690
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.611705545
Short name T81
Test name
Test status
Simulation time 2368832072 ps
CPU time 53.55 seconds
Started Jun 08 02:53:54 PM PDT 24
Finished Jun 08 02:54:48 PM PDT 24
Peak memory 215916 kb
Host smart-39df4006-b2ac-4723-ac06-e388bd2e1d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611705545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.611705545
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.828271289
Short name T230
Test name
Test status
Simulation time 2038656971 ps
CPU time 49.02 seconds
Started Jun 08 02:54:10 PM PDT 24
Finished Jun 08 02:54:59 PM PDT 24
Peak memory 221476 kb
Host smart-5e7a951f-be18-47e7-bcc0-cc0f55d6b1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828271289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.828271289
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2290581821
Short name T267
Test name
Test status
Simulation time 2900382773 ps
CPU time 75.85 seconds
Started Jun 08 02:54:17 PM PDT 24
Finished Jun 08 02:55:33 PM PDT 24
Peak memory 214632 kb
Host smart-ebba25e1-24ca-45eb-8b2f-f428f9a6810f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290581821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2290581821
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1957786736
Short name T462
Test name
Test status
Simulation time 768873780 ps
CPU time 8.07 seconds
Started Jun 08 02:22:10 PM PDT 24
Finished Jun 08 02:22:18 PM PDT 24
Peak memory 205632 kb
Host smart-81f810bf-39e6-4fb2-a874-960f3c5ac4fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957786736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
957786736
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2845896619
Short name T530
Test name
Test status
Simulation time 450365672 ps
CPU time 1.58 seconds
Started Jun 08 02:22:06 PM PDT 24
Finished Jun 08 02:22:08 PM PDT 24
Peak memory 205536 kb
Host smart-d738e3c7-590a-4f35-9523-7b612e367139
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845896619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
845896619
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3772320811
Short name T527
Test name
Test status
Simulation time 16291137 ps
CPU time 1.17 seconds
Started Jun 08 02:22:13 PM PDT 24
Finished Jun 08 02:22:14 PM PDT 24
Peak memory 205616 kb
Host smart-18efdb80-b736-4999-97ab-112dc236e662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772320811 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3772320811
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1002612547
Short name T480
Test name
Test status
Simulation time 141310298 ps
CPU time 0.99 seconds
Started Jun 08 02:22:10 PM PDT 24
Finished Jun 08 02:22:12 PM PDT 24
Peak memory 205336 kb
Host smart-e1b8b433-3282-486a-9b5c-f20569ed32f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002612547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1002612547
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3086355114
Short name T396
Test name
Test status
Simulation time 13088798 ps
CPU time 0.74 seconds
Started Jun 08 02:22:11 PM PDT 24
Finished Jun 08 02:22:12 PM PDT 24
Peak memory 205344 kb
Host smart-f47f4935-2e8d-41c2-bf72-126b27eaafeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086355114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3086355114
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1379756341
Short name T526
Test name
Test status
Simulation time 640837840 ps
CPU time 4.21 seconds
Started Jun 08 02:22:02 PM PDT 24
Finished Jun 08 02:22:07 PM PDT 24
Peak memory 213932 kb
Host smart-f3bc2258-166c-46a5-8a02-38522c73d878
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379756341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1379756341
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1678709387
Short name T453
Test name
Test status
Simulation time 99254688 ps
CPU time 2.25 seconds
Started Jun 08 02:22:08 PM PDT 24
Finished Jun 08 02:22:10 PM PDT 24
Peak memory 205640 kb
Host smart-bdd359e9-0d84-461a-b104-e2859a47d4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678709387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1678709387
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3782844674
Short name T539
Test name
Test status
Simulation time 432931090 ps
CPU time 5.79 seconds
Started Jun 08 02:22:22 PM PDT 24
Finished Jun 08 02:22:28 PM PDT 24
Peak memory 205524 kb
Host smart-2fad9381-042d-4f44-bac8-5be7b4f9be7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782844674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
782844674
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3504013666
Short name T160
Test name
Test status
Simulation time 868770745 ps
CPU time 17.7 seconds
Started Jun 08 02:22:19 PM PDT 24
Finished Jun 08 02:22:37 PM PDT 24
Peak memory 205548 kb
Host smart-8821bff8-f2e0-4841-b9ee-26549faff813
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504013666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
504013666
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3387706258
Short name T519
Test name
Test status
Simulation time 43065495 ps
CPU time 1.26 seconds
Started Jun 08 02:22:19 PM PDT 24
Finished Jun 08 02:22:21 PM PDT 24
Peak memory 205640 kb
Host smart-10bc4611-f887-458d-879d-8013ef8f95cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387706258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
387706258
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1764665746
Short name T464
Test name
Test status
Simulation time 58491077 ps
CPU time 1.35 seconds
Started Jun 08 02:22:27 PM PDT 24
Finished Jun 08 02:22:28 PM PDT 24
Peak memory 213800 kb
Host smart-89c4efcf-2185-4e54-8dfe-bcb56b6e5727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764665746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1764665746
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2090344680
Short name T152
Test name
Test status
Simulation time 11912358 ps
CPU time 1.07 seconds
Started Jun 08 02:22:19 PM PDT 24
Finished Jun 08 02:22:20 PM PDT 24
Peak memory 205556 kb
Host smart-459e1fdb-64c9-45d4-99e8-bc35354ab81f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090344680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2090344680
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.627728724
Short name T535
Test name
Test status
Simulation time 41973831 ps
CPU time 0.71 seconds
Started Jun 08 02:22:15 PM PDT 24
Finished Jun 08 02:22:16 PM PDT 24
Peak memory 205224 kb
Host smart-964889ac-7c45-4743-858b-382007e6624a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627728724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.627728724
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2593916480
Short name T521
Test name
Test status
Simulation time 23848075 ps
CPU time 1.41 seconds
Started Jun 08 02:22:20 PM PDT 24
Finished Jun 08 02:22:22 PM PDT 24
Peak memory 205476 kb
Host smart-5270292c-03a2-45c0-a6d0-c553594f3531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593916480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2593916480
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3356090074
Short name T465
Test name
Test status
Simulation time 65470620 ps
CPU time 2.62 seconds
Started Jun 08 02:22:14 PM PDT 24
Finished Jun 08 02:22:16 PM PDT 24
Peak memory 214028 kb
Host smart-0a03deb8-520d-47fc-82ec-7ef1cc98fcf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356090074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3356090074
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4212580310
Short name T132
Test name
Test status
Simulation time 90871312 ps
CPU time 2.85 seconds
Started Jun 08 02:22:17 PM PDT 24
Finished Jun 08 02:22:20 PM PDT 24
Peak memory 213764 kb
Host smart-92645001-e868-4a55-8944-8c1920d059c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212580310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4212580310
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.946442013
Short name T507
Test name
Test status
Simulation time 25996554 ps
CPU time 1.28 seconds
Started Jun 08 02:23:16 PM PDT 24
Finished Jun 08 02:23:17 PM PDT 24
Peak memory 213772 kb
Host smart-5bffe299-e45d-429e-8aef-db101cb97949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946442013 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.946442013
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2701171896
Short name T537
Test name
Test status
Simulation time 41893572 ps
CPU time 0.73 seconds
Started Jun 08 02:23:15 PM PDT 24
Finished Jun 08 02:23:16 PM PDT 24
Peak memory 205356 kb
Host smart-b1982d70-25a3-49ea-afc0-0c71f6ae66c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701171896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2701171896
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3597198068
Short name T563
Test name
Test status
Simulation time 56501523 ps
CPU time 1.88 seconds
Started Jun 08 02:23:16 PM PDT 24
Finished Jun 08 02:23:18 PM PDT 24
Peak memory 205548 kb
Host smart-5893ce2f-7475-4b4a-bb82-d880a9ae0817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597198068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3597198068
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4226830006
Short name T176
Test name
Test status
Simulation time 722713154 ps
CPU time 5.91 seconds
Started Jun 08 02:23:13 PM PDT 24
Finished Jun 08 02:23:19 PM PDT 24
Peak memory 214036 kb
Host smart-8303828d-c1e5-471d-a7cc-c96ae4b630c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226830006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4226830006
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.335441465
Short name T479
Test name
Test status
Simulation time 187228952 ps
CPU time 5.15 seconds
Started Jun 08 02:23:17 PM PDT 24
Finished Jun 08 02:23:23 PM PDT 24
Peak memory 214004 kb
Host smart-660abfcb-3561-430d-8d06-7a3b1f3d5337
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335441465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.335441465
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3822771516
Short name T475
Test name
Test status
Simulation time 69504593 ps
CPU time 2.01 seconds
Started Jun 08 02:23:16 PM PDT 24
Finished Jun 08 02:23:18 PM PDT 24
Peak memory 214012 kb
Host smart-614652d8-cea5-4aae-9f10-ae99dad7dfa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822771516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3822771516
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3808470171
Short name T177
Test name
Test status
Simulation time 116528739 ps
CPU time 1.76 seconds
Started Jun 08 02:23:23 PM PDT 24
Finished Jun 08 02:23:25 PM PDT 24
Peak memory 213776 kb
Host smart-e86bbe0b-b7ed-48ad-8cc7-1ca6a6af4439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808470171 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3808470171
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3872816965
Short name T449
Test name
Test status
Simulation time 25495318 ps
CPU time 1.16 seconds
Started Jun 08 02:23:21 PM PDT 24
Finished Jun 08 02:23:22 PM PDT 24
Peak memory 205588 kb
Host smart-8ca69fa9-b489-42aa-9d28-40f2bb1b2b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872816965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3872816965
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2732460331
Short name T524
Test name
Test status
Simulation time 39067546 ps
CPU time 0.88 seconds
Started Jun 08 02:23:21 PM PDT 24
Finished Jun 08 02:23:22 PM PDT 24
Peak memory 205280 kb
Host smart-95690949-96c0-461b-bec7-28d70ded9b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732460331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2732460331
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2959380142
Short name T544
Test name
Test status
Simulation time 48266134 ps
CPU time 1.85 seconds
Started Jun 08 02:23:21 PM PDT 24
Finished Jun 08 02:23:23 PM PDT 24
Peak memory 205620 kb
Host smart-712599ce-442e-4a42-8996-8aa2c108998c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959380142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2959380142
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.802866802
Short name T525
Test name
Test status
Simulation time 354973501 ps
CPU time 3.63 seconds
Started Jun 08 02:23:18 PM PDT 24
Finished Jun 08 02:23:22 PM PDT 24
Peak memory 214004 kb
Host smart-0625d7e3-f29f-4071-a6a5-f889e00c851e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802866802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.802866802
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.850270085
Short name T571
Test name
Test status
Simulation time 83426366 ps
CPU time 3.01 seconds
Started Jun 08 02:23:24 PM PDT 24
Finished Jun 08 02:23:27 PM PDT 24
Peak memory 216896 kb
Host smart-6a151972-dbd6-43a9-89cd-ecede2955237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850270085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.850270085
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4097222673
Short name T172
Test name
Test status
Simulation time 411592987 ps
CPU time 5.86 seconds
Started Jun 08 02:23:20 PM PDT 24
Finished Jun 08 02:23:26 PM PDT 24
Peak memory 209028 kb
Host smart-aa1c17b0-38a4-431c-a10e-0a6af81c5221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097222673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4097222673
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1511471144
Short name T494
Test name
Test status
Simulation time 22564578 ps
CPU time 1.11 seconds
Started Jun 08 02:23:26 PM PDT 24
Finished Jun 08 02:23:28 PM PDT 24
Peak memory 205700 kb
Host smart-b0f96d3d-8e0a-4808-b8c4-f61415a89248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511471144 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1511471144
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2582577201
Short name T554
Test name
Test status
Simulation time 40583726 ps
CPU time 0.84 seconds
Started Jun 08 02:23:20 PM PDT 24
Finished Jun 08 02:23:21 PM PDT 24
Peak memory 205364 kb
Host smart-8413561a-d9ff-49ff-997a-807457a8a3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582577201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2582577201
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3798648269
Short name T488
Test name
Test status
Simulation time 595781242 ps
CPU time 3.91 seconds
Started Jun 08 02:23:26 PM PDT 24
Finished Jun 08 02:23:30 PM PDT 24
Peak memory 205580 kb
Host smart-06a69b36-4e87-4692-96d7-c753ce001141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798648269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3798648269
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2048486885
Short name T452
Test name
Test status
Simulation time 261047570 ps
CPU time 6.42 seconds
Started Jun 08 02:23:21 PM PDT 24
Finished Jun 08 02:23:28 PM PDT 24
Peak memory 213936 kb
Host smart-a97336b2-78ee-4215-b033-045619c834c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048486885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2048486885
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2454480463
Short name T486
Test name
Test status
Simulation time 516442532 ps
CPU time 3.74 seconds
Started Jun 08 02:23:21 PM PDT 24
Finished Jun 08 02:23:25 PM PDT 24
Peak memory 213832 kb
Host smart-fcface8b-5b59-4645-b341-8f38cee6bbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454480463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2454480463
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1640343249
Short name T459
Test name
Test status
Simulation time 184101045 ps
CPU time 1.44 seconds
Started Jun 08 02:23:32 PM PDT 24
Finished Jun 08 02:23:33 PM PDT 24
Peak memory 213752 kb
Host smart-3895596d-6496-4df8-bcfe-28e244e13cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640343249 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1640343249
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3228394739
Short name T568
Test name
Test status
Simulation time 51067697 ps
CPU time 1.06 seconds
Started Jun 08 02:23:32 PM PDT 24
Finished Jun 08 02:23:33 PM PDT 24
Peak memory 205420 kb
Host smart-a1e10bf9-d31d-44ed-a77d-630a07129164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228394739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3228394739
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1627187154
Short name T509
Test name
Test status
Simulation time 20977241 ps
CPU time 0.73 seconds
Started Jun 08 02:23:27 PM PDT 24
Finished Jun 08 02:23:28 PM PDT 24
Peak memory 205340 kb
Host smart-4f3d1fa7-a835-4c39-9ad1-be5dcbc2f227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627187154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1627187154
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4077039915
Short name T148
Test name
Test status
Simulation time 125147482 ps
CPU time 2.73 seconds
Started Jun 08 02:23:29 PM PDT 24
Finished Jun 08 02:23:32 PM PDT 24
Peak memory 205564 kb
Host smart-5c9517b8-b95c-47f2-8107-37159e371029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077039915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4077039915
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3659750489
Short name T119
Test name
Test status
Simulation time 713112822 ps
CPU time 5.97 seconds
Started Jun 08 02:23:27 PM PDT 24
Finished Jun 08 02:23:33 PM PDT 24
Peak memory 213992 kb
Host smart-4d1a7a90-2753-492c-a20a-20f1fb16ece3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659750489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3659750489
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1213829430
Short name T565
Test name
Test status
Simulation time 316513087 ps
CPU time 6.21 seconds
Started Jun 08 02:23:27 PM PDT 24
Finished Jun 08 02:23:34 PM PDT 24
Peak memory 214116 kb
Host smart-1ba4bcbf-e9c7-47e6-8f3a-1216575ef80a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213829430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1213829430
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3866584422
Short name T133
Test name
Test status
Simulation time 355285721 ps
CPU time 3.52 seconds
Started Jun 08 02:23:26 PM PDT 24
Finished Jun 08 02:23:30 PM PDT 24
Peak memory 213920 kb
Host smart-a49c1db3-30da-4735-81e2-16ae3538a7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866584422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3866584422
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.903392954
Short name T170
Test name
Test status
Simulation time 211585914 ps
CPU time 5.48 seconds
Started Jun 08 02:23:25 PM PDT 24
Finished Jun 08 02:23:31 PM PDT 24
Peak memory 213760 kb
Host smart-e7eb06a7-275d-4e96-be58-ebd86babc536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903392954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.903392954
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3469745160
Short name T516
Test name
Test status
Simulation time 27609115 ps
CPU time 1.31 seconds
Started Jun 08 02:23:34 PM PDT 24
Finished Jun 08 02:23:35 PM PDT 24
Peak memory 213744 kb
Host smart-c650b466-61c2-4a09-92d7-611bada5ed2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469745160 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3469745160
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1323822937
Short name T562
Test name
Test status
Simulation time 194037190 ps
CPU time 0.99 seconds
Started Jun 08 02:23:31 PM PDT 24
Finished Jun 08 02:23:32 PM PDT 24
Peak memory 205360 kb
Host smart-7c9fb059-7a5e-4259-810b-f317151deb42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323822937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1323822937
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4139715807
Short name T567
Test name
Test status
Simulation time 9922550 ps
CPU time 0.84 seconds
Started Jun 08 02:23:30 PM PDT 24
Finished Jun 08 02:23:31 PM PDT 24
Peak memory 205336 kb
Host smart-01f2649e-8431-4a48-9ab1-bd0961f2a3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139715807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4139715807
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3324849396
Short name T483
Test name
Test status
Simulation time 882718556 ps
CPU time 15.96 seconds
Started Jun 08 02:23:32 PM PDT 24
Finished Jun 08 02:23:48 PM PDT 24
Peak memory 214000 kb
Host smart-0761961f-66a3-48ba-b887-8b197d24a690
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324849396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3324849396
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3308241314
Short name T531
Test name
Test status
Simulation time 17845503 ps
CPU time 1.45 seconds
Started Jun 08 02:23:32 PM PDT 24
Finished Jun 08 02:23:34 PM PDT 24
Peak memory 213908 kb
Host smart-c545684b-7244-4322-95d3-ba51445b5d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308241314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3308241314
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3339505637
Short name T140
Test name
Test status
Simulation time 447240034 ps
CPU time 4.63 seconds
Started Jun 08 02:23:32 PM PDT 24
Finished Jun 08 02:23:37 PM PDT 24
Peak memory 208876 kb
Host smart-4a4c99ff-10c8-4833-8359-af8c87cd112f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339505637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3339505637
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.225575730
Short name T508
Test name
Test status
Simulation time 18376619 ps
CPU time 1.08 seconds
Started Jun 08 02:23:38 PM PDT 24
Finished Jun 08 02:23:39 PM PDT 24
Peak memory 205544 kb
Host smart-f83f6aaa-d149-4893-9041-549ebf9278da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225575730 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.225575730
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3221065632
Short name T145
Test name
Test status
Simulation time 15247797 ps
CPU time 0.98 seconds
Started Jun 08 02:23:38 PM PDT 24
Finished Jun 08 02:23:39 PM PDT 24
Peak memory 205564 kb
Host smart-e49e7391-7fb1-479a-8e0a-003acd676605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221065632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3221065632
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1704216713
Short name T473
Test name
Test status
Simulation time 45308801 ps
CPU time 0.73 seconds
Started Jun 08 02:23:39 PM PDT 24
Finished Jun 08 02:23:40 PM PDT 24
Peak memory 205356 kb
Host smart-58428fe5-bdf6-40ea-ba2b-4dfbb512cdae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704216713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1704216713
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1703515885
Short name T532
Test name
Test status
Simulation time 42744502 ps
CPU time 1.73 seconds
Started Jun 08 02:23:38 PM PDT 24
Finished Jun 08 02:23:40 PM PDT 24
Peak memory 205652 kb
Host smart-74bd2cc7-d28a-4578-8212-8c7592e2d388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703515885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1703515885
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1028718728
Short name T556
Test name
Test status
Simulation time 1457055151 ps
CPU time 5.86 seconds
Started Jun 08 02:23:33 PM PDT 24
Finished Jun 08 02:23:39 PM PDT 24
Peak memory 213944 kb
Host smart-8651ec55-8e40-47c9-8e3b-b8d72ce65ac6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028718728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1028718728
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.171015069
Short name T491
Test name
Test status
Simulation time 493855056 ps
CPU time 2.07 seconds
Started Jun 08 02:23:31 PM PDT 24
Finished Jun 08 02:23:33 PM PDT 24
Peak memory 213764 kb
Host smart-dd39936c-2a51-4377-a900-7359151b53da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171015069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.171015069
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.150628237
Short name T455
Test name
Test status
Simulation time 15643455 ps
CPU time 1.16 seconds
Started Jun 08 02:23:41 PM PDT 24
Finished Jun 08 02:23:43 PM PDT 24
Peak memory 205620 kb
Host smart-56c3579f-4ef7-4ec1-9fa6-954a9902935b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150628237 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.150628237
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1597024709
Short name T541
Test name
Test status
Simulation time 215951226 ps
CPU time 1.27 seconds
Started Jun 08 02:23:39 PM PDT 24
Finished Jun 08 02:23:41 PM PDT 24
Peak memory 205572 kb
Host smart-204c79c7-2021-41e6-b2e0-f3caff6eaf5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597024709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1597024709
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2312971384
Short name T528
Test name
Test status
Simulation time 36032558 ps
CPU time 0.76 seconds
Started Jun 08 02:23:37 PM PDT 24
Finished Jun 08 02:23:38 PM PDT 24
Peak memory 205264 kb
Host smart-f614cac0-2a6e-4a0f-a6ec-c984d768537d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312971384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2312971384
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4269240834
Short name T548
Test name
Test status
Simulation time 73662462 ps
CPU time 2.49 seconds
Started Jun 08 02:23:38 PM PDT 24
Finished Jun 08 02:23:41 PM PDT 24
Peak memory 205620 kb
Host smart-9aa605f1-e80c-4a5d-811d-79be6356410d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269240834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4269240834
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.471228226
Short name T122
Test name
Test status
Simulation time 713151522 ps
CPU time 4.47 seconds
Started Jun 08 02:23:36 PM PDT 24
Finished Jun 08 02:23:41 PM PDT 24
Peak memory 214008 kb
Host smart-f3c28a75-10e7-4142-91f3-9e6d4dd2dc35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471228226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.471228226
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.733398996
Short name T511
Test name
Test status
Simulation time 1307808290 ps
CPU time 10.47 seconds
Started Jun 08 02:23:37 PM PDT 24
Finished Jun 08 02:23:48 PM PDT 24
Peak memory 214008 kb
Host smart-36f4f12c-9608-4fbc-abe6-e930aabda0da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733398996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.733398996
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.711946913
Short name T559
Test name
Test status
Simulation time 127324362 ps
CPU time 3.49 seconds
Started Jun 08 02:23:37 PM PDT 24
Finished Jun 08 02:23:41 PM PDT 24
Peak memory 213828 kb
Host smart-9af30cf3-01e7-4bd1-b1d8-c4014cb4ec8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711946913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.711946913
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4232910500
Short name T534
Test name
Test status
Simulation time 22835592 ps
CPU time 1.47 seconds
Started Jun 08 02:23:42 PM PDT 24
Finished Jun 08 02:23:44 PM PDT 24
Peak memory 213764 kb
Host smart-84a4e729-c8c3-4646-b6c9-70e01fa83965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232910500 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4232910500
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3392628607
Short name T144
Test name
Test status
Simulation time 26545225 ps
CPU time 1.17 seconds
Started Jun 08 02:23:42 PM PDT 24
Finished Jun 08 02:23:44 PM PDT 24
Peak memory 205616 kb
Host smart-325e8f35-baf5-49a9-a685-c2173a5f7580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392628607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3392628607
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1830782649
Short name T456
Test name
Test status
Simulation time 12955426 ps
CPU time 0.75 seconds
Started Jun 08 02:23:47 PM PDT 24
Finished Jun 08 02:23:48 PM PDT 24
Peak memory 205336 kb
Host smart-df90a0ca-cd0f-4598-9c35-5a9e5acc02b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830782649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1830782649
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2632984443
Short name T487
Test name
Test status
Simulation time 1132336998 ps
CPU time 3.02 seconds
Started Jun 08 02:23:41 PM PDT 24
Finished Jun 08 02:23:45 PM PDT 24
Peak memory 205556 kb
Host smart-a800c03c-1e94-42c6-8694-90df08acb8f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632984443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2632984443
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3187179661
Short name T460
Test name
Test status
Simulation time 631212869 ps
CPU time 4.98 seconds
Started Jun 08 02:23:47 PM PDT 24
Finished Jun 08 02:23:53 PM PDT 24
Peak memory 218488 kb
Host smart-abd3c8a7-9d31-44a6-a197-999daabea5e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187179661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3187179661
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3810337783
Short name T489
Test name
Test status
Simulation time 719565628 ps
CPU time 7.96 seconds
Started Jun 08 02:23:42 PM PDT 24
Finished Jun 08 02:23:50 PM PDT 24
Peak memory 220148 kb
Host smart-9c1c0a6d-f0fe-49e1-838f-00fa1e52a187
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810337783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3810337783
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4054783212
Short name T545
Test name
Test status
Simulation time 142429601 ps
CPU time 4.99 seconds
Started Jun 08 02:23:45 PM PDT 24
Finished Jun 08 02:23:50 PM PDT 24
Peak memory 222012 kb
Host smart-03c49a81-6a97-4417-9ed0-1f60cd0e27a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054783212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4054783212
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2382497097
Short name T549
Test name
Test status
Simulation time 34061644 ps
CPU time 1.87 seconds
Started Jun 08 02:23:48 PM PDT 24
Finished Jun 08 02:23:50 PM PDT 24
Peak memory 213808 kb
Host smart-a05d2d1d-10a0-483e-b47b-3a5bf78fac74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382497097 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2382497097
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3898789640
Short name T147
Test name
Test status
Simulation time 33434460 ps
CPU time 1.2 seconds
Started Jun 08 02:23:48 PM PDT 24
Finished Jun 08 02:23:50 PM PDT 24
Peak memory 205572 kb
Host smart-fe70207e-5b77-4662-a8e8-b7508707f9d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898789640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3898789640
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3648561917
Short name T471
Test name
Test status
Simulation time 9519638 ps
CPU time 0.8 seconds
Started Jun 08 02:23:48 PM PDT 24
Finished Jun 08 02:23:49 PM PDT 24
Peak memory 205356 kb
Host smart-4f79d6ee-2ecf-4862-8989-245f2bda2fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648561917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3648561917
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.108563256
Short name T564
Test name
Test status
Simulation time 130669292 ps
CPU time 2.04 seconds
Started Jun 08 02:23:47 PM PDT 24
Finished Jun 08 02:23:50 PM PDT 24
Peak memory 205496 kb
Host smart-0b3ec8ff-0431-44ee-88ed-a186bf58a273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108563256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.108563256
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2598209958
Short name T529
Test name
Test status
Simulation time 159447151 ps
CPU time 1.72 seconds
Started Jun 08 02:23:49 PM PDT 24
Finished Jun 08 02:23:51 PM PDT 24
Peak memory 214088 kb
Host smart-6163050c-2d63-400a-a4a5-e7331437b9cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598209958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2598209958
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.4053053093
Short name T134
Test name
Test status
Simulation time 466325390 ps
CPU time 2.93 seconds
Started Jun 08 02:23:51 PM PDT 24
Finished Jun 08 02:23:54 PM PDT 24
Peak memory 213884 kb
Host smart-6545df62-d13c-469a-9929-36dcceb946a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053053093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.4053053093
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.497725025
Short name T128
Test name
Test status
Simulation time 509049995 ps
CPU time 2.2 seconds
Started Jun 08 02:23:50 PM PDT 24
Finished Jun 08 02:23:53 PM PDT 24
Peak memory 213856 kb
Host smart-6dc07db5-acdb-478c-b137-d514ae1be595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497725025 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.497725025
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1961476110
Short name T543
Test name
Test status
Simulation time 19752761 ps
CPU time 0.84 seconds
Started Jun 08 02:23:50 PM PDT 24
Finished Jun 08 02:23:51 PM PDT 24
Peak memory 205356 kb
Host smart-a3e1fcf3-4b23-4376-93a4-8a3cbe0cbb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961476110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1961476110
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1553270595
Short name T120
Test name
Test status
Simulation time 311742770 ps
CPU time 2.7 seconds
Started Jun 08 02:23:50 PM PDT 24
Finished Jun 08 02:23:53 PM PDT 24
Peak memory 214008 kb
Host smart-8c6d21c7-8977-4b93-a1ca-1da445d39552
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553270595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1553270595
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1766701983
Short name T496
Test name
Test status
Simulation time 44069093 ps
CPU time 2.07 seconds
Started Jun 08 02:23:53 PM PDT 24
Finished Jun 08 02:23:55 PM PDT 24
Peak memory 213804 kb
Host smart-375bd4db-a871-48aa-a788-177abe27c127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766701983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1766701983
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1605979685
Short name T500
Test name
Test status
Simulation time 130143907 ps
CPU time 7.59 seconds
Started Jun 08 02:22:44 PM PDT 24
Finished Jun 08 02:22:52 PM PDT 24
Peak memory 205588 kb
Host smart-0592d0ad-da3d-49dd-86b9-ac10d31251e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605979685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
605979685
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.146384438
Short name T457
Test name
Test status
Simulation time 1005874561 ps
CPU time 14.45 seconds
Started Jun 08 02:22:35 PM PDT 24
Finished Jun 08 02:22:49 PM PDT 24
Peak memory 205528 kb
Host smart-76143d94-fbfd-41ec-bf54-b3cb16f74698
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146384438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.146384438
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1879702010
Short name T180
Test name
Test status
Simulation time 60536743 ps
CPU time 1.45 seconds
Started Jun 08 02:22:30 PM PDT 24
Finished Jun 08 02:22:32 PM PDT 24
Peak memory 205408 kb
Host smart-9ac7e152-e46b-42da-99de-fbc3b17786b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879702010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
879702010
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1076750754
Short name T512
Test name
Test status
Simulation time 106546435 ps
CPU time 1.41 seconds
Started Jun 08 02:22:36 PM PDT 24
Finished Jun 08 02:22:37 PM PDT 24
Peak memory 205556 kb
Host smart-f0f114d1-e750-4454-9e28-a2c4e744f82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076750754 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1076750754
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1468115725
Short name T448
Test name
Test status
Simulation time 52088856 ps
CPU time 0.92 seconds
Started Jun 08 02:22:33 PM PDT 24
Finished Jun 08 02:22:34 PM PDT 24
Peak memory 205408 kb
Host smart-b802b76c-70a7-44f9-9856-80ed950ace05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468115725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1468115725
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1143783278
Short name T551
Test name
Test status
Simulation time 10650523 ps
CPU time 0.73 seconds
Started Jun 08 02:22:34 PM PDT 24
Finished Jun 08 02:22:35 PM PDT 24
Peak memory 205264 kb
Host smart-329c00a6-7456-4fcf-ac91-7a8897621677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143783278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1143783278
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2884742865
Short name T561
Test name
Test status
Simulation time 204908469 ps
CPU time 2.45 seconds
Started Jun 08 02:22:34 PM PDT 24
Finished Jun 08 02:22:37 PM PDT 24
Peak memory 205544 kb
Host smart-bc653690-ada8-4194-939d-039120b96d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884742865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2884742865
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.714909063
Short name T553
Test name
Test status
Simulation time 101771719 ps
CPU time 3.06 seconds
Started Jun 08 02:22:27 PM PDT 24
Finished Jun 08 02:22:31 PM PDT 24
Peak memory 213872 kb
Host smart-8c4ca6ce-6994-4994-9ee2-74c0e8e76622
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714909063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.714909063
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1836292985
Short name T467
Test name
Test status
Simulation time 2144559275 ps
CPU time 16.04 seconds
Started Jun 08 02:22:29 PM PDT 24
Finished Jun 08 02:22:45 PM PDT 24
Peak memory 214012 kb
Host smart-2c6860ba-7edd-4d06-b485-17f7ffc3a1a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836292985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1836292985
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.46880943
Short name T131
Test name
Test status
Simulation time 22747493 ps
CPU time 1.8 seconds
Started Jun 08 02:22:29 PM PDT 24
Finished Jun 08 02:22:31 PM PDT 24
Peak memory 213920 kb
Host smart-c6088ef1-913e-443a-997b-54d4176dc1a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46880943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.46880943
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.507219597
Short name T169
Test name
Test status
Simulation time 374601918 ps
CPU time 3.51 seconds
Started Jun 08 02:22:26 PM PDT 24
Finished Jun 08 02:22:30 PM PDT 24
Peak memory 209260 kb
Host smart-974ecd52-6cdd-45e2-8a93-05f57482b0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507219597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
507219597
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4197640933
Short name T513
Test name
Test status
Simulation time 11520214 ps
CPU time 0.82 seconds
Started Jun 08 02:23:50 PM PDT 24
Finished Jun 08 02:23:51 PM PDT 24
Peak memory 205264 kb
Host smart-81fc862b-2c1c-4c60-aa15-2e7b5004eda7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197640933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4197640933
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3987907993
Short name T523
Test name
Test status
Simulation time 11063736 ps
CPU time 0.87 seconds
Started Jun 08 02:23:52 PM PDT 24
Finished Jun 08 02:23:53 PM PDT 24
Peak memory 205364 kb
Host smart-88c30e49-ec0d-491e-a0de-8d33f71c0c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987907993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3987907993
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2470729426
Short name T183
Test name
Test status
Simulation time 11547247 ps
CPU time 0.77 seconds
Started Jun 08 02:23:51 PM PDT 24
Finished Jun 08 02:23:52 PM PDT 24
Peak memory 205340 kb
Host smart-1e65cb15-bf6b-4519-a0a4-1758c6b93022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470729426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2470729426
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2867621469
Short name T517
Test name
Test status
Simulation time 29385055 ps
CPU time 0.79 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205256 kb
Host smart-fbe83970-9c80-49a3-8fd1-07b4fed93c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867621469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2867621469
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3117872252
Short name T444
Test name
Test status
Simulation time 56700956 ps
CPU time 0.81 seconds
Started Jun 08 02:23:53 PM PDT 24
Finished Jun 08 02:23:54 PM PDT 24
Peak memory 205340 kb
Host smart-7ce3e80e-1cf5-4a7d-82eb-546e68ba54c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117872252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3117872252
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3703160318
Short name T443
Test name
Test status
Simulation time 71495836 ps
CPU time 0.78 seconds
Started Jun 08 02:23:50 PM PDT 24
Finished Jun 08 02:23:51 PM PDT 24
Peak memory 205340 kb
Host smart-4cd14b43-0dd0-4638-ae6c-915964a3155f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703160318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3703160318
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.259810724
Short name T476
Test name
Test status
Simulation time 10155286 ps
CPU time 0.69 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205224 kb
Host smart-c936c40b-c324-426f-b292-e77ecff1bd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259810724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.259810724
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2380064380
Short name T557
Test name
Test status
Simulation time 46184247 ps
CPU time 0.78 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205244 kb
Host smart-b10c8be8-5f88-409f-878d-6cf5e3d4e06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380064380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2380064380
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1347890282
Short name T485
Test name
Test status
Simulation time 21306879 ps
CPU time 1 seconds
Started Jun 08 02:23:58 PM PDT 24
Finished Jun 08 02:23:59 PM PDT 24
Peak memory 205492 kb
Host smart-f229ba05-97f1-456a-9d05-1e6cd1f3775c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347890282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1347890282
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2775407701
Short name T446
Test name
Test status
Simulation time 37538734 ps
CPU time 0.82 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205280 kb
Host smart-9028b6c8-75fc-42ba-89de-1cd4b1eb08d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775407701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2775407701
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.917986315
Short name T478
Test name
Test status
Simulation time 525013108 ps
CPU time 7.84 seconds
Started Jun 08 02:22:44 PM PDT 24
Finished Jun 08 02:22:52 PM PDT 24
Peak memory 205524 kb
Host smart-42700c7a-4eff-4a0c-8152-5eca4e95e516
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917986315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.917986315
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2010213908
Short name T445
Test name
Test status
Simulation time 1006904378 ps
CPU time 12.54 seconds
Started Jun 08 02:22:43 PM PDT 24
Finished Jun 08 02:22:56 PM PDT 24
Peak memory 205572 kb
Host smart-c12e94e7-9727-47f7-93f0-c1589e3e1a33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010213908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
010213908
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3325881267
Short name T538
Test name
Test status
Simulation time 52420063 ps
CPU time 1.05 seconds
Started Jun 08 02:22:43 PM PDT 24
Finished Jun 08 02:22:44 PM PDT 24
Peak memory 205412 kb
Host smart-3f7382cc-617f-4794-bf6a-931144b1ca3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325881267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
325881267
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3190356812
Short name T490
Test name
Test status
Simulation time 111857563 ps
CPU time 1.95 seconds
Started Jun 08 02:22:41 PM PDT 24
Finished Jun 08 02:22:43 PM PDT 24
Peak memory 213916 kb
Host smart-e4b9b864-d826-4c5f-9ad2-0e837b6fdb60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190356812 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3190356812
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2698259145
Short name T555
Test name
Test status
Simulation time 88748368 ps
CPU time 1.17 seconds
Started Jun 08 02:22:41 PM PDT 24
Finished Jun 08 02:22:42 PM PDT 24
Peak memory 205624 kb
Host smart-925eb180-4ed5-445d-9593-865fde4aeca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698259145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2698259145
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1742692078
Short name T451
Test name
Test status
Simulation time 47360382 ps
CPU time 0.76 seconds
Started Jun 08 02:22:43 PM PDT 24
Finished Jun 08 02:22:44 PM PDT 24
Peak memory 205272 kb
Host smart-d9553c80-33b9-4109-8e94-ea304c4781cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742692078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1742692078
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3595849615
Short name T153
Test name
Test status
Simulation time 75069497 ps
CPU time 1.41 seconds
Started Jun 08 02:22:42 PM PDT 24
Finished Jun 08 02:22:43 PM PDT 24
Peak memory 205580 kb
Host smart-5cc80071-71ec-4d38-9c83-ebb8e8685aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595849615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3595849615
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3430258898
Short name T185
Test name
Test status
Simulation time 766894698 ps
CPU time 14.01 seconds
Started Jun 08 02:22:35 PM PDT 24
Finished Jun 08 02:22:49 PM PDT 24
Peak memory 214028 kb
Host smart-177fb6d6-2e10-4683-b0fe-9b012e4c0586
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430258898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3430258898
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3972531843
Short name T155
Test name
Test status
Simulation time 678406871 ps
CPU time 7.43 seconds
Started Jun 08 02:22:37 PM PDT 24
Finished Jun 08 02:22:44 PM PDT 24
Peak memory 214100 kb
Host smart-746ac20f-9887-432a-8799-8eb962a03e6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972531843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3972531843
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4278586956
Short name T533
Test name
Test status
Simulation time 52506256 ps
CPU time 1.61 seconds
Started Jun 08 02:22:36 PM PDT 24
Finished Jun 08 02:22:38 PM PDT 24
Peak memory 213896 kb
Host smart-6abff659-f0ee-4515-bc28-0cd4e919ef30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278586956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4278586956
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.616045154
Short name T546
Test name
Test status
Simulation time 14590218 ps
CPU time 0.89 seconds
Started Jun 08 02:23:57 PM PDT 24
Finished Jun 08 02:23:58 PM PDT 24
Peak memory 205420 kb
Host smart-9b782a28-ef8d-48b1-bffe-30473a8caf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616045154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.616045154
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2272282814
Short name T498
Test name
Test status
Simulation time 12243544 ps
CPU time 0.72 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205264 kb
Host smart-ec64352c-c829-4ce5-9071-f3ae0515f727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272282814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2272282814
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.949148991
Short name T454
Test name
Test status
Simulation time 115847837 ps
CPU time 0.7 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205272 kb
Host smart-821872a0-21bf-45c5-9f54-040f67003b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949148991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.949148991
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3236630343
Short name T179
Test name
Test status
Simulation time 9291105 ps
CPU time 0.7 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205288 kb
Host smart-09d93f18-b267-4769-b7e5-fefff85a1c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236630343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3236630343
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3004211094
Short name T150
Test name
Test status
Simulation time 51374636 ps
CPU time 0.82 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205260 kb
Host smart-a1bb047f-d64b-4194-8da6-da861829c7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004211094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3004211094
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2595365694
Short name T497
Test name
Test status
Simulation time 8565064 ps
CPU time 0.71 seconds
Started Jun 08 02:24:02 PM PDT 24
Finished Jun 08 02:24:03 PM PDT 24
Peak memory 205260 kb
Host smart-ccbc57e3-9092-42e9-80ec-611f9cb165c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595365694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2595365694
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.550582525
Short name T570
Test name
Test status
Simulation time 23768504 ps
CPU time 0.89 seconds
Started Jun 08 02:24:02 PM PDT 24
Finished Jun 08 02:24:04 PM PDT 24
Peak memory 205252 kb
Host smart-4b86004f-65f5-4a9c-89a8-41ea2f65c736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550582525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.550582525
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2472620381
Short name T481
Test name
Test status
Simulation time 19785764 ps
CPU time 0.71 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205276 kb
Host smart-bf6a732b-a21f-46a9-b9dd-fa789a424cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472620381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2472620381
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.622444308
Short name T468
Test name
Test status
Simulation time 75929626 ps
CPU time 0.91 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205292 kb
Host smart-f93fde7d-abba-4341-9caa-f0b52da53cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622444308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.622444308
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.4151849017
Short name T522
Test name
Test status
Simulation time 12204699 ps
CPU time 0.82 seconds
Started Jun 08 02:23:56 PM PDT 24
Finished Jun 08 02:23:57 PM PDT 24
Peak memory 205516 kb
Host smart-d5feeb03-2518-4777-abe2-08e4901e2785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151849017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.4151849017
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2694219852
Short name T520
Test name
Test status
Simulation time 684978230 ps
CPU time 9 seconds
Started Jun 08 02:22:51 PM PDT 24
Finished Jun 08 02:23:00 PM PDT 24
Peak memory 205472 kb
Host smart-0fa44eba-7748-4b9c-a5e9-a974e07f84ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694219852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
694219852
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2124166744
Short name T515
Test name
Test status
Simulation time 1003216340 ps
CPU time 7.07 seconds
Started Jun 08 02:22:53 PM PDT 24
Finished Jun 08 02:23:00 PM PDT 24
Peak memory 205572 kb
Host smart-6df4644c-8f15-4268-b0d2-75ac7a4b5aa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124166744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
124166744
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3349557958
Short name T181
Test name
Test status
Simulation time 31985733 ps
CPU time 1.49 seconds
Started Jun 08 02:22:45 PM PDT 24
Finished Jun 08 02:22:46 PM PDT 24
Peak memory 205536 kb
Host smart-7e2527f0-df6c-4a50-9de5-95949bd8bdfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349557958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
349557958
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2571236839
Short name T503
Test name
Test status
Simulation time 37140271 ps
CPU time 1.51 seconds
Started Jun 08 02:22:52 PM PDT 24
Finished Jun 08 02:22:54 PM PDT 24
Peak memory 213820 kb
Host smart-dc43929d-66bd-4090-97d3-570e8fe54c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571236839 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2571236839
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3169274799
Short name T146
Test name
Test status
Simulation time 13560112 ps
CPU time 1.23 seconds
Started Jun 08 02:22:46 PM PDT 24
Finished Jun 08 02:22:47 PM PDT 24
Peak memory 205640 kb
Host smart-766ca1c0-94bd-495b-a6ed-a918e6ef17e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169274799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3169274799
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.548660349
Short name T547
Test name
Test status
Simulation time 35525024 ps
CPU time 0.75 seconds
Started Jun 08 02:22:45 PM PDT 24
Finished Jun 08 02:22:46 PM PDT 24
Peak memory 205348 kb
Host smart-f6f8a65b-5f69-41cc-9e38-b1e10a25ff48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548660349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.548660349
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4023829916
Short name T506
Test name
Test status
Simulation time 33132770 ps
CPU time 2.22 seconds
Started Jun 08 02:22:53 PM PDT 24
Finished Jun 08 02:22:55 PM PDT 24
Peak memory 213736 kb
Host smart-7b158b10-2a32-485d-bd17-598f2e6d6195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023829916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4023829916
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1015485971
Short name T127
Test name
Test status
Simulation time 952849544 ps
CPU time 8.4 seconds
Started Jun 08 02:22:46 PM PDT 24
Finished Jun 08 02:22:55 PM PDT 24
Peak memory 214016 kb
Host smart-71d9952a-b560-423d-abb4-ed08968c4529
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015485971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1015485971
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1519530033
Short name T518
Test name
Test status
Simulation time 71681744 ps
CPU time 2.64 seconds
Started Jun 08 02:22:46 PM PDT 24
Finished Jun 08 02:22:49 PM PDT 24
Peak memory 213844 kb
Host smart-af9f5608-8519-46cf-8d6a-2660b08e2098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519530033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1519530033
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3878844088
Short name T558
Test name
Test status
Simulation time 12599301 ps
CPU time 0.88 seconds
Started Jun 08 02:23:55 PM PDT 24
Finished Jun 08 02:23:56 PM PDT 24
Peak memory 205252 kb
Host smart-e5e0199f-0cc1-4a3d-ac35-01f46dcefa22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878844088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3878844088
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.318891856
Short name T184
Test name
Test status
Simulation time 16126059 ps
CPU time 1.03 seconds
Started Jun 08 02:24:02 PM PDT 24
Finished Jun 08 02:24:04 PM PDT 24
Peak memory 205396 kb
Host smart-b8460768-d546-4593-8da0-5b3d921c8a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318891856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.318891856
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3258544254
Short name T450
Test name
Test status
Simulation time 13998803 ps
CPU time 0.73 seconds
Started Jun 08 02:24:01 PM PDT 24
Finished Jun 08 02:24:02 PM PDT 24
Peak memory 205280 kb
Host smart-49cd6b45-f170-46c1-818e-131ae9f7d26b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258544254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3258544254
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1339832867
Short name T499
Test name
Test status
Simulation time 37421753 ps
CPU time 0.71 seconds
Started Jun 08 02:24:00 PM PDT 24
Finished Jun 08 02:24:01 PM PDT 24
Peak memory 205340 kb
Host smart-cf7f13e5-c0b3-4559-93d0-201b5e1d3c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339832867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1339832867
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.807887989
Short name T536
Test name
Test status
Simulation time 31625771 ps
CPU time 0.79 seconds
Started Jun 08 02:24:00 PM PDT 24
Finished Jun 08 02:24:01 PM PDT 24
Peak memory 205272 kb
Host smart-84b89d71-766d-4991-a3ed-0faf4cb2f6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807887989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.807887989
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3612927680
Short name T493
Test name
Test status
Simulation time 14604968 ps
CPU time 0.78 seconds
Started Jun 08 02:24:00 PM PDT 24
Finished Jun 08 02:24:01 PM PDT 24
Peak memory 205276 kb
Host smart-836fb91c-5274-4b45-bc48-7b4c268b863c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612927680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3612927680
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3844168798
Short name T463
Test name
Test status
Simulation time 18850936 ps
CPU time 0.72 seconds
Started Jun 08 02:24:02 PM PDT 24
Finished Jun 08 02:24:03 PM PDT 24
Peak memory 205288 kb
Host smart-b7f8c437-3870-4e9b-bf6d-a1ccb8183b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844168798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3844168798
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1287608201
Short name T151
Test name
Test status
Simulation time 10309664 ps
CPU time 0.72 seconds
Started Jun 08 02:24:02 PM PDT 24
Finished Jun 08 02:24:03 PM PDT 24
Peak memory 205336 kb
Host smart-c6e3c48c-aa52-4b48-a0c6-50875726428c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287608201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1287608201
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2380720779
Short name T472
Test name
Test status
Simulation time 66868875 ps
CPU time 0.72 seconds
Started Jun 08 02:24:00 PM PDT 24
Finished Jun 08 02:24:01 PM PDT 24
Peak memory 205300 kb
Host smart-58b10c91-371e-4ba3-abea-c8c4b35529cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380720779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2380720779
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1425607710
Short name T458
Test name
Test status
Simulation time 53762628 ps
CPU time 0.79 seconds
Started Jun 08 02:24:04 PM PDT 24
Finished Jun 08 02:24:05 PM PDT 24
Peak memory 205264 kb
Host smart-c65e0ad2-89dc-4c08-8209-2a1c74314a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425607710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1425607710
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.743819198
Short name T495
Test name
Test status
Simulation time 25361813 ps
CPU time 1.97 seconds
Started Jun 08 02:22:57 PM PDT 24
Finished Jun 08 02:22:59 PM PDT 24
Peak memory 213764 kb
Host smart-2dcb871f-12c9-40c9-a416-eb949759d6db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743819198 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.743819198
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3350282130
Short name T469
Test name
Test status
Simulation time 74461319 ps
CPU time 1.09 seconds
Started Jun 08 02:22:56 PM PDT 24
Finished Jun 08 02:22:57 PM PDT 24
Peak memory 205440 kb
Host smart-5d7ce7df-21d2-4349-b055-fc3852075660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350282130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3350282130
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1187690601
Short name T182
Test name
Test status
Simulation time 45435256 ps
CPU time 0.73 seconds
Started Jun 08 02:22:56 PM PDT 24
Finished Jun 08 02:22:57 PM PDT 24
Peak memory 205348 kb
Host smart-1c274e01-8986-43a1-af87-cc5a10e8fcc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187690601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1187690601
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3442620162
Short name T466
Test name
Test status
Simulation time 79501793 ps
CPU time 1.46 seconds
Started Jun 08 02:22:57 PM PDT 24
Finished Jun 08 02:22:58 PM PDT 24
Peak memory 205564 kb
Host smart-6cef39bf-94fd-43da-8e17-9d1038bb5d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442620162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3442620162
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2481365442
Short name T125
Test name
Test status
Simulation time 245916919 ps
CPU time 2.53 seconds
Started Jun 08 02:22:52 PM PDT 24
Finished Jun 08 02:22:55 PM PDT 24
Peak memory 214032 kb
Host smart-a1f5e4f6-2b1b-425b-a1f5-097a49e96b97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481365442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2481365442
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3348859581
Short name T505
Test name
Test status
Simulation time 358118450 ps
CPU time 8.46 seconds
Started Jun 08 02:22:51 PM PDT 24
Finished Jun 08 02:23:00 PM PDT 24
Peak memory 213968 kb
Host smart-14b81b1d-1931-4215-b626-f527f7dc7c6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348859581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3348859581
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2945210835
Short name T474
Test name
Test status
Simulation time 43520614 ps
CPU time 1.52 seconds
Started Jun 08 02:22:52 PM PDT 24
Finished Jun 08 02:22:54 PM PDT 24
Peak memory 213820 kb
Host smart-a36c54e4-b2f6-4ad3-8b58-ef4c6f9f2d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945210835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2945210835
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2992915809
Short name T566
Test name
Test status
Simulation time 58829247 ps
CPU time 1.54 seconds
Started Jun 08 02:22:55 PM PDT 24
Finished Jun 08 02:22:57 PM PDT 24
Peak memory 213816 kb
Host smart-33e2b9e3-72f4-4ea1-a843-bb4479909a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992915809 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2992915809
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3263352389
Short name T470
Test name
Test status
Simulation time 333274972 ps
CPU time 1.7 seconds
Started Jun 08 02:22:57 PM PDT 24
Finished Jun 08 02:22:59 PM PDT 24
Peak memory 205568 kb
Host smart-50416491-a3a0-45a7-8ee8-50c5ef33288d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263352389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3263352389
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3229415797
Short name T504
Test name
Test status
Simulation time 27357247 ps
CPU time 0.79 seconds
Started Jun 08 02:22:57 PM PDT 24
Finished Jun 08 02:22:58 PM PDT 24
Peak memory 205392 kb
Host smart-d15341d2-e509-4f8d-8073-552a7f57f1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229415797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3229415797
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.726201222
Short name T542
Test name
Test status
Simulation time 159690877 ps
CPU time 2.05 seconds
Started Jun 08 02:22:58 PM PDT 24
Finished Jun 08 02:23:00 PM PDT 24
Peak memory 205632 kb
Host smart-aac99aeb-6d72-43d1-b709-965ac61ecf94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726201222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.726201222
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3983223528
Short name T501
Test name
Test status
Simulation time 144190402 ps
CPU time 4.22 seconds
Started Jun 08 02:22:58 PM PDT 24
Finished Jun 08 02:23:02 PM PDT 24
Peak memory 214104 kb
Host smart-19b76305-2e2f-4d54-b0b3-069b6bfd54eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983223528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3983223528
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.50483408
Short name T569
Test name
Test status
Simulation time 2631775122 ps
CPU time 7.95 seconds
Started Jun 08 02:22:58 PM PDT 24
Finished Jun 08 02:23:06 PM PDT 24
Peak memory 214080 kb
Host smart-6c4aa00e-adb8-4a20-b256-cdff1b86c207
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50483408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_shadow_reg_errors_with_csr_rw.50483408
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1490749503
Short name T129
Test name
Test status
Simulation time 476253170 ps
CPU time 3.32 seconds
Started Jun 08 02:22:55 PM PDT 24
Finished Jun 08 02:22:59 PM PDT 24
Peak memory 215196 kb
Host smart-d0a140a3-cd7b-48f7-9ecb-1aa4e2cefa57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490749503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1490749503
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2774172024
Short name T552
Test name
Test status
Simulation time 27938912 ps
CPU time 1.43 seconds
Started Jun 08 02:23:07 PM PDT 24
Finished Jun 08 02:23:09 PM PDT 24
Peak memory 221940 kb
Host smart-ccca6078-908a-416d-a032-742df39c1baa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774172024 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2774172024
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2104628661
Short name T447
Test name
Test status
Simulation time 9054023 ps
CPU time 0.73 seconds
Started Jun 08 02:23:01 PM PDT 24
Finished Jun 08 02:23:02 PM PDT 24
Peak memory 205248 kb
Host smart-9f4604e2-2adf-48e3-937d-24be34ecea40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104628661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2104628661
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3528439406
Short name T484
Test name
Test status
Simulation time 85392731 ps
CPU time 3.55 seconds
Started Jun 08 02:23:06 PM PDT 24
Finished Jun 08 02:23:09 PM PDT 24
Peak memory 205560 kb
Host smart-3367435b-e8d5-4c4a-9d13-7ffb25c66d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528439406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3528439406
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1742440592
Short name T514
Test name
Test status
Simulation time 241467830 ps
CPU time 7.8 seconds
Started Jun 08 02:23:03 PM PDT 24
Finished Jun 08 02:23:11 PM PDT 24
Peak memory 213964 kb
Host smart-41313ecf-f1b2-45e7-a62d-29f7507b606e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742440592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1742440592
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1642477118
Short name T492
Test name
Test status
Simulation time 399486737 ps
CPU time 2.52 seconds
Started Jun 08 02:23:03 PM PDT 24
Finished Jun 08 02:23:06 PM PDT 24
Peak memory 213820 kb
Host smart-205d72bb-e6e1-4de0-ac56-de0a963ef86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642477118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1642477118
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2507188133
Short name T166
Test name
Test status
Simulation time 632805938 ps
CPU time 14.82 seconds
Started Jun 08 02:23:04 PM PDT 24
Finished Jun 08 02:23:19 PM PDT 24
Peak memory 213756 kb
Host smart-4d391d47-5c98-4e61-b979-fada8787471d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507188133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2507188133
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3394432085
Short name T540
Test name
Test status
Simulation time 32465091 ps
CPU time 0.96 seconds
Started Jun 08 02:23:13 PM PDT 24
Finished Jun 08 02:23:14 PM PDT 24
Peak memory 205436 kb
Host smart-19ef4e4c-84b9-441f-8333-4cb45c812126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394432085 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3394432085
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3708136393
Short name T154
Test name
Test status
Simulation time 14856240 ps
CPU time 0.88 seconds
Started Jun 08 02:23:07 PM PDT 24
Finished Jun 08 02:23:08 PM PDT 24
Peak memory 205408 kb
Host smart-70c21f4e-3049-4423-bf6e-32980e739926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708136393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3708136393
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.73152512
Short name T510
Test name
Test status
Simulation time 30399166 ps
CPU time 0.71 seconds
Started Jun 08 02:23:08 PM PDT 24
Finished Jun 08 02:23:09 PM PDT 24
Peak memory 205352 kb
Host smart-339692dd-00aa-41f0-b040-83dba1ae281f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73152512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.73152512
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3059250092
Short name T477
Test name
Test status
Simulation time 167407534 ps
CPU time 1.99 seconds
Started Jun 08 02:23:07 PM PDT 24
Finished Jun 08 02:23:09 PM PDT 24
Peak memory 205540 kb
Host smart-ec22663a-a5c6-44ce-8419-761aa7f69395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059250092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3059250092
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4079746916
Short name T126
Test name
Test status
Simulation time 276911000 ps
CPU time 3.42 seconds
Started Jun 08 02:23:06 PM PDT 24
Finished Jun 08 02:23:10 PM PDT 24
Peak memory 214036 kb
Host smart-d1e36655-6c3c-4b62-857b-612f60434773
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079746916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4079746916
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3070034249
Short name T482
Test name
Test status
Simulation time 272838616 ps
CPU time 3.29 seconds
Started Jun 08 02:23:08 PM PDT 24
Finished Jun 08 02:23:11 PM PDT 24
Peak memory 213788 kb
Host smart-af8b27ad-1947-4e28-aaf9-9d67f8bdc991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070034249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3070034249
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3462159983
Short name T130
Test name
Test status
Simulation time 17543025 ps
CPU time 1.43 seconds
Started Jun 08 02:23:12 PM PDT 24
Finished Jun 08 02:23:13 PM PDT 24
Peak memory 217256 kb
Host smart-d8fc4cef-26d3-4082-8be2-cbd1c8703816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462159983 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3462159983
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2174463012
Short name T178
Test name
Test status
Simulation time 37334323 ps
CPU time 0.91 seconds
Started Jun 08 02:23:13 PM PDT 24
Finished Jun 08 02:23:14 PM PDT 24
Peak memory 205344 kb
Host smart-922e6de6-95e3-4291-9c48-a6f85e37fc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174463012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2174463012
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3417981846
Short name T149
Test name
Test status
Simulation time 38281296 ps
CPU time 0.72 seconds
Started Jun 08 02:23:14 PM PDT 24
Finished Jun 08 02:23:14 PM PDT 24
Peak memory 205324 kb
Host smart-091ae2f4-e7b3-4f77-8cb1-57de33a3b217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417981846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3417981846
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1346273280
Short name T560
Test name
Test status
Simulation time 71286169 ps
CPU time 1.68 seconds
Started Jun 08 02:23:11 PM PDT 24
Finished Jun 08 02:23:13 PM PDT 24
Peak memory 205488 kb
Host smart-4117b5f5-f8c3-48b2-a3eb-96edd167c959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346273280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1346273280
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4007680325
Short name T550
Test name
Test status
Simulation time 200739386 ps
CPU time 3.23 seconds
Started Jun 08 02:23:13 PM PDT 24
Finished Jun 08 02:23:17 PM PDT 24
Peak memory 214024 kb
Host smart-5e1c0347-1d79-42fc-9dd5-a59ab7642ca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007680325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4007680325
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3483423146
Short name T502
Test name
Test status
Simulation time 1794894785 ps
CPU time 8.95 seconds
Started Jun 08 02:23:14 PM PDT 24
Finished Jun 08 02:23:23 PM PDT 24
Peak memory 214004 kb
Host smart-c7737617-bd73-43f4-8bbd-b295e798604d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483423146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3483423146
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.382308327
Short name T461
Test name
Test status
Simulation time 141561491 ps
CPU time 4.65 seconds
Started Jun 08 02:23:11 PM PDT 24
Finished Jun 08 02:23:15 PM PDT 24
Peak memory 216916 kb
Host smart-6527cd79-b300-474d-bfe2-6cb17d7b90f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382308327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.382308327
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2227032904
Short name T924
Test name
Test status
Simulation time 15656498 ps
CPU time 0.72 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:49 PM PDT 24
Peak memory 205524 kb
Host smart-eb227fdd-186a-4f6d-83e3-59eeae6f27ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227032904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2227032904
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1420904685
Short name T839
Test name
Test status
Simulation time 338827058 ps
CPU time 3.53 seconds
Started Jun 08 02:50:46 PM PDT 24
Finished Jun 08 02:50:49 PM PDT 24
Peak memory 214380 kb
Host smart-aca99137-6c95-4264-99cc-d45b32b4e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420904685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1420904685
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2212362786
Short name T662
Test name
Test status
Simulation time 5091258097 ps
CPU time 32.31 seconds
Started Jun 08 02:50:45 PM PDT 24
Finished Jun 08 02:51:18 PM PDT 24
Peak memory 209568 kb
Host smart-d865a94e-17b9-4734-8dd8-31573eee4469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212362786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2212362786
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2083221450
Short name T97
Test name
Test status
Simulation time 207525661 ps
CPU time 3.4 seconds
Started Jun 08 02:50:45 PM PDT 24
Finished Jun 08 02:50:49 PM PDT 24
Peak memory 208752 kb
Host smart-adb33e3b-23ab-4199-a44a-be4f71f207e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083221450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2083221450
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2917558768
Short name T1057
Test name
Test status
Simulation time 17012411495 ps
CPU time 69.55 seconds
Started Jun 08 02:50:44 PM PDT 24
Finished Jun 08 02:51:54 PM PDT 24
Peak memory 222856 kb
Host smart-5aebc40f-c34f-4b58-9acb-4e8714dccb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917558768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2917558768
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3298458113
Short name T646
Test name
Test status
Simulation time 461224894 ps
CPU time 5.43 seconds
Started Jun 08 02:50:46 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 209240 kb
Host smart-196d45b4-84b7-4b0d-a715-0b39a5245cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298458113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3298458113
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.754657154
Short name T694
Test name
Test status
Simulation time 81224044 ps
CPU time 3.94 seconds
Started Jun 08 02:50:42 PM PDT 24
Finished Jun 08 02:50:46 PM PDT 24
Peak memory 209428 kb
Host smart-22b4ed77-629a-4acf-846e-9a5763620d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754657154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.754657154
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3842542426
Short name T962
Test name
Test status
Simulation time 8512723997 ps
CPU time 92.13 seconds
Started Jun 08 02:50:44 PM PDT 24
Finished Jun 08 02:52:16 PM PDT 24
Peak memory 208104 kb
Host smart-9ca5b204-c608-4974-b913-2ec98113c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842542426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3842542426
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1151769866
Short name T279
Test name
Test status
Simulation time 323266053 ps
CPU time 9.11 seconds
Started Jun 08 02:50:45 PM PDT 24
Finished Jun 08 02:50:55 PM PDT 24
Peak memory 208364 kb
Host smart-0bf81c6a-b114-4b73-a75f-9637d0ae6bbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151769866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1151769866
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1311284059
Short name T896
Test name
Test status
Simulation time 1129445621 ps
CPU time 8.4 seconds
Started Jun 08 02:50:44 PM PDT 24
Finished Jun 08 02:50:53 PM PDT 24
Peak memory 207720 kb
Host smart-0d5686c3-62c9-4dd9-9773-44b319716cc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311284059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1311284059
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3452084175
Short name T187
Test name
Test status
Simulation time 508669871 ps
CPU time 3.17 seconds
Started Jun 08 02:50:37 PM PDT 24
Finished Jun 08 02:50:40 PM PDT 24
Peak memory 206328 kb
Host smart-f663e245-af3f-4f68-a15d-a83fa92f858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452084175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3452084175
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3169271427
Short name T587
Test name
Test status
Simulation time 101029648 ps
CPU time 2.74 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 214188 kb
Host smart-a1f25f19-bcef-4abe-808a-ad6cf0f55acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169271427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3169271427
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.103824221
Short name T923
Test name
Test status
Simulation time 101760618 ps
CPU time 3.76 seconds
Started Jun 08 02:50:44 PM PDT 24
Finished Jun 08 02:50:48 PM PDT 24
Peak memory 206792 kb
Host smart-f5b6b03b-f923-49a5-867a-eeb9d70fef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103824221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.103824221
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2784036613
Short name T782
Test name
Test status
Simulation time 129215151 ps
CPU time 4.77 seconds
Started Jun 08 02:50:48 PM PDT 24
Finished Jun 08 02:50:53 PM PDT 24
Peak memory 209608 kb
Host smart-756a8237-b3fe-4988-bee8-77e807c2b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784036613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2784036613
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1521482439
Short name T16
Test name
Test status
Simulation time 383086256 ps
CPU time 4.36 seconds
Started Jun 08 02:50:50 PM PDT 24
Finished Jun 08 02:50:54 PM PDT 24
Peak memory 209000 kb
Host smart-8e507d3c-391b-4c48-b408-dcb8d192fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521482439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1521482439
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1621990210
Short name T990
Test name
Test status
Simulation time 58234282 ps
CPU time 2.67 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 208308 kb
Host smart-8d9a865d-f93a-49a1-803f-d5377a5d350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621990210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1621990210
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1225290174
Short name T281
Test name
Test status
Simulation time 335183249 ps
CPU time 8.26 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:58 PM PDT 24
Peak memory 213988 kb
Host smart-e8429341-bac4-4eca-a0e5-16a19df0cd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225290174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1225290174
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2516300012
Short name T757
Test name
Test status
Simulation time 468069778 ps
CPU time 3.73 seconds
Started Jun 08 02:50:50 PM PDT 24
Finished Jun 08 02:50:54 PM PDT 24
Peak memory 214116 kb
Host smart-38069802-908b-4db2-baa6-638e6066ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516300012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2516300012
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3361863683
Short name T763
Test name
Test status
Simulation time 105171476 ps
CPU time 4.86 seconds
Started Jun 08 02:50:50 PM PDT 24
Finished Jun 08 02:50:55 PM PDT 24
Peak memory 208404 kb
Host smart-f37d64bd-c5db-44e5-aa2a-1f65f618f43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361863683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3361863683
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1572836842
Short name T600
Test name
Test status
Simulation time 250146185 ps
CPU time 2.85 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:52 PM PDT 24
Peak memory 207936 kb
Host smart-5d4b74be-00d0-44df-952f-50ff1db94724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572836842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1572836842
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.65587004
Short name T14
Test name
Test status
Simulation time 83332594 ps
CPU time 3.81 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:53 PM PDT 24
Peak memory 206616 kb
Host smart-39631d61-0020-4b0e-88db-31c5907e9374
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65587004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.65587004
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1865568212
Short name T999
Test name
Test status
Simulation time 243810530 ps
CPU time 8.45 seconds
Started Jun 08 02:50:50 PM PDT 24
Finished Jun 08 02:50:59 PM PDT 24
Peak memory 208244 kb
Host smart-b9bed01f-8800-4183-856e-9b9accc1f547
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865568212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1865568212
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.848473458
Short name T590
Test name
Test status
Simulation time 592065501 ps
CPU time 11.95 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:51:01 PM PDT 24
Peak memory 208288 kb
Host smart-929a2fd3-d844-456a-90e9-af71b0568298
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848473458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.848473458
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1882100639
Short name T1012
Test name
Test status
Simulation time 373560741 ps
CPU time 2.91 seconds
Started Jun 08 02:50:48 PM PDT 24
Finished Jun 08 02:50:51 PM PDT 24
Peak memory 209084 kb
Host smart-119e0a84-7b65-4010-b704-07b168fca4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882100639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1882100639
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4261134028
Short name T761
Test name
Test status
Simulation time 18788944 ps
CPU time 1.71 seconds
Started Jun 08 02:50:49 PM PDT 24
Finished Jun 08 02:50:51 PM PDT 24
Peak memory 206368 kb
Host smart-ca192480-f8a0-4428-82e4-ef7193879045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261134028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4261134028
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2061697431
Short name T325
Test name
Test status
Simulation time 111283054 ps
CPU time 4.91 seconds
Started Jun 08 02:50:52 PM PDT 24
Finished Jun 08 02:50:57 PM PDT 24
Peak memory 219376 kb
Host smart-d39e8192-52d1-4ccd-87aa-a01ff3d47808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061697431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2061697431
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2322161065
Short name T712
Test name
Test status
Simulation time 120098344 ps
CPU time 2.87 seconds
Started Jun 08 02:50:54 PM PDT 24
Finished Jun 08 02:50:57 PM PDT 24
Peak memory 210072 kb
Host smart-e7ac81fe-8545-413e-93ef-1bc2fb595c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322161065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2322161065
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1030651151
Short name T589
Test name
Test status
Simulation time 13020245 ps
CPU time 0.8 seconds
Started Jun 08 02:52:01 PM PDT 24
Finished Jun 08 02:52:02 PM PDT 24
Peak memory 205532 kb
Host smart-e95bc0b5-953f-4511-bb1b-8f6790ad1f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030651151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1030651151
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2203359682
Short name T238
Test name
Test status
Simulation time 37876614 ps
CPU time 3.24 seconds
Started Jun 08 02:51:48 PM PDT 24
Finished Jun 08 02:51:52 PM PDT 24
Peak memory 214188 kb
Host smart-d018e2e2-67fe-43dc-a471-2aa96c48f87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203359682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2203359682
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2328582807
Short name T41
Test name
Test status
Simulation time 38901930 ps
CPU time 1.77 seconds
Started Jun 08 02:51:47 PM PDT 24
Finished Jun 08 02:51:48 PM PDT 24
Peak memory 206812 kb
Host smart-fdd6072e-4fe6-44cb-af00-e62661b834bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328582807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2328582807
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.921434523
Short name T322
Test name
Test status
Simulation time 35907207 ps
CPU time 2.6 seconds
Started Jun 08 02:51:54 PM PDT 24
Finished Jun 08 02:51:57 PM PDT 24
Peak memory 208480 kb
Host smart-4529529c-016b-4f78-83d1-da0c7ef0aa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921434523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.921434523
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2728303090
Short name T249
Test name
Test status
Simulation time 156763721 ps
CPU time 6.74 seconds
Started Jun 08 02:51:52 PM PDT 24
Finished Jun 08 02:51:59 PM PDT 24
Peak memory 214000 kb
Host smart-a48abce2-8a29-4bdf-b4b7-8d2cdf8cc983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728303090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2728303090
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.219124521
Short name T45
Test name
Test status
Simulation time 46676292 ps
CPU time 2.8 seconds
Started Jun 08 02:51:49 PM PDT 24
Finished Jun 08 02:51:52 PM PDT 24
Peak memory 207508 kb
Host smart-345e2c1f-3697-4c6e-bd0d-4c05f7fa8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219124521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.219124521
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3756820723
Short name T739
Test name
Test status
Simulation time 112520076 ps
CPU time 3.64 seconds
Started Jun 08 02:51:48 PM PDT 24
Finished Jun 08 02:51:52 PM PDT 24
Peak memory 208964 kb
Host smart-154447c8-1a23-411a-a1e2-2259b7203b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756820723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3756820723
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3743834951
Short name T108
Test name
Test status
Simulation time 424533040 ps
CPU time 14.35 seconds
Started Jun 08 02:51:54 PM PDT 24
Finished Jun 08 02:52:09 PM PDT 24
Peak memory 206508 kb
Host smart-76cfd6db-3ab1-4caa-a1b7-c80d82be9d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743834951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3743834951
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.772963943
Short name T849
Test name
Test status
Simulation time 705978396 ps
CPU time 6.16 seconds
Started Jun 08 02:51:48 PM PDT 24
Finished Jun 08 02:51:54 PM PDT 24
Peak memory 208428 kb
Host smart-240ab970-6429-4d06-a2f8-1be797fded36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772963943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.772963943
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4000914449
Short name T723
Test name
Test status
Simulation time 141689236 ps
CPU time 2.69 seconds
Started Jun 08 02:51:48 PM PDT 24
Finished Jun 08 02:51:51 PM PDT 24
Peak memory 206616 kb
Host smart-fc176591-a6e2-4075-92d5-e4931d26ee28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000914449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4000914449
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1818401104
Short name T344
Test name
Test status
Simulation time 561053786 ps
CPU time 10.76 seconds
Started Jun 08 02:51:54 PM PDT 24
Finished Jun 08 02:52:05 PM PDT 24
Peak memory 208164 kb
Host smart-72af1e62-bba5-4e87-b1ca-c961bdf0b418
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818401104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1818401104
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.537922092
Short name T900
Test name
Test status
Simulation time 4784139163 ps
CPU time 41.01 seconds
Started Jun 08 02:51:54 PM PDT 24
Finished Jun 08 02:52:36 PM PDT 24
Peak memory 208676 kb
Host smart-c111b77a-15e2-4ca2-92b2-391ef85213c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537922092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.537922092
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1127412926
Short name T692
Test name
Test status
Simulation time 231794292 ps
CPU time 3.85 seconds
Started Jun 08 02:51:49 PM PDT 24
Finished Jun 08 02:51:53 PM PDT 24
Peak memory 206568 kb
Host smart-ff6d8969-19ba-4e02-82fe-7652c4a00fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127412926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1127412926
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.303665297
Short name T1038
Test name
Test status
Simulation time 1029214975 ps
CPU time 10.75 seconds
Started Jun 08 02:51:53 PM PDT 24
Finished Jun 08 02:52:04 PM PDT 24
Peak memory 222356 kb
Host smart-41681da5-bc40-4e8c-a540-9f0020725802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303665297 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.303665297
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2651010549
Short name T208
Test name
Test status
Simulation time 386875678 ps
CPU time 6.84 seconds
Started Jun 08 02:51:48 PM PDT 24
Finished Jun 08 02:51:55 PM PDT 24
Peak memory 207084 kb
Host smart-06af90ac-37d5-4a55-a587-bd946914b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651010549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2651010549
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3541622488
Short name T865
Test name
Test status
Simulation time 407026972 ps
CPU time 6.24 seconds
Started Jun 08 02:51:54 PM PDT 24
Finished Jun 08 02:52:00 PM PDT 24
Peak memory 209904 kb
Host smart-ad1f9f94-9c2f-4478-b279-51f2cb14abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541622488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3541622488
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1531116533
Short name T814
Test name
Test status
Simulation time 12990970 ps
CPU time 0.84 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:51:58 PM PDT 24
Peak memory 205520 kb
Host smart-7c799665-2633-4c45-8ff2-09280c527a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531116533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1531116533
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1198098029
Short name T424
Test name
Test status
Simulation time 95742319 ps
CPU time 3.95 seconds
Started Jun 08 02:51:53 PM PDT 24
Finished Jun 08 02:51:57 PM PDT 24
Peak memory 214968 kb
Host smart-c5af4485-4408-4d93-a5e9-0a9e4ceec556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198098029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1198098029
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3950732625
Short name T858
Test name
Test status
Simulation time 439624558 ps
CPU time 3.55 seconds
Started Jun 08 02:52:01 PM PDT 24
Finished Jun 08 02:52:05 PM PDT 24
Peak memory 209124 kb
Host smart-76b86930-6b41-4b4a-940d-b976be95e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950732625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3950732625
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3433080481
Short name T1040
Test name
Test status
Simulation time 292932365 ps
CPU time 7.41 seconds
Started Jun 08 02:51:52 PM PDT 24
Finished Jun 08 02:51:59 PM PDT 24
Peak memory 220168 kb
Host smart-344ea3fd-8397-4e7f-bd99-e59217f693e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433080481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3433080481
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1116460417
Short name T63
Test name
Test status
Simulation time 1877127473 ps
CPU time 5.44 seconds
Started Jun 08 02:51:51 PM PDT 24
Finished Jun 08 02:51:57 PM PDT 24
Peak memory 214112 kb
Host smart-551b3818-ca33-4efb-8d9b-5f175a1aad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116460417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1116460417
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.788764454
Short name T898
Test name
Test status
Simulation time 145997716 ps
CPU time 2.85 seconds
Started Jun 08 02:51:51 PM PDT 24
Finished Jun 08 02:51:55 PM PDT 24
Peak memory 207700 kb
Host smart-d19f5f86-dc7a-474a-98e4-460fb6c4e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788764454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.788764454
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.357314085
Short name T1015
Test name
Test status
Simulation time 836328532 ps
CPU time 9.5 seconds
Started Jun 08 02:51:51 PM PDT 24
Finished Jun 08 02:52:01 PM PDT 24
Peak memory 206592 kb
Host smart-34866cdd-b097-44d4-87fa-5405bcef08bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357314085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.357314085
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1935225158
Short name T637
Test name
Test status
Simulation time 676454153 ps
CPU time 6.16 seconds
Started Jun 08 02:51:59 PM PDT 24
Finished Jun 08 02:52:06 PM PDT 24
Peak memory 206384 kb
Host smart-24e15956-37a9-4794-85cb-c98fcfeeb095
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935225158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1935225158
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1256745669
Short name T997
Test name
Test status
Simulation time 132997469 ps
CPU time 3.27 seconds
Started Jun 08 02:51:53 PM PDT 24
Finished Jun 08 02:51:56 PM PDT 24
Peak memory 206716 kb
Host smart-1df3e7ec-7163-4d7e-8453-fba2c06f8317
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256745669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1256745669
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3711991072
Short name T798
Test name
Test status
Simulation time 50803478 ps
CPU time 2.62 seconds
Started Jun 08 02:51:52 PM PDT 24
Finished Jun 08 02:51:55 PM PDT 24
Peak memory 206664 kb
Host smart-11e716ba-d2ab-4274-9305-83503a7cd3c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711991072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3711991072
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3974180169
Short name T408
Test name
Test status
Simulation time 237469415 ps
CPU time 1.69 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:51:59 PM PDT 24
Peak memory 214024 kb
Host smart-3995c722-b09c-466e-9a9e-3ab5aed25877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974180169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3974180169
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.129641351
Short name T659
Test name
Test status
Simulation time 306685658 ps
CPU time 2.7 seconds
Started Jun 08 02:51:59 PM PDT 24
Finished Jun 08 02:52:02 PM PDT 24
Peak memory 208180 kb
Host smart-68c24859-c945-49c2-a258-7b85851bc421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129641351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.129641351
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2181898450
Short name T212
Test name
Test status
Simulation time 162059870 ps
CPU time 5.03 seconds
Started Jun 08 02:52:00 PM PDT 24
Finished Jun 08 02:52:05 PM PDT 24
Peak memory 222284 kb
Host smart-a1a9034b-3d0e-4bf4-a5a3-cadea1f6711d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181898450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2181898450
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3241534303
Short name T899
Test name
Test status
Simulation time 298314384 ps
CPU time 5.99 seconds
Started Jun 08 02:51:53 PM PDT 24
Finished Jun 08 02:52:00 PM PDT 24
Peak memory 214232 kb
Host smart-ecdf3396-c3c5-4059-a46c-36ef6f1434bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241534303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3241534303
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.829877336
Short name T703
Test name
Test status
Simulation time 13290851 ps
CPU time 0.74 seconds
Started Jun 08 02:52:06 PM PDT 24
Finished Jun 08 02:52:07 PM PDT 24
Peak memory 205468 kb
Host smart-b90e8c41-4b6b-4a82-972b-d36e0ea54d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829877336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.829877336
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2021696573
Short name T421
Test name
Test status
Simulation time 268870823 ps
CPU time 9.81 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:52:07 PM PDT 24
Peak memory 214500 kb
Host smart-2c92dd0d-482f-4869-8f53-0f24a6a525a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021696573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2021696573
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2794244386
Short name T774
Test name
Test status
Simulation time 211523128 ps
CPU time 3.65 seconds
Started Jun 08 02:52:04 PM PDT 24
Finished Jun 08 02:52:08 PM PDT 24
Peak memory 219700 kb
Host smart-d308e8fa-1ce1-4aaf-8d96-a20fd982a1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794244386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2794244386
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.192770548
Short name T812
Test name
Test status
Simulation time 372065232 ps
CPU time 4.05 seconds
Started Jun 08 02:52:03 PM PDT 24
Finished Jun 08 02:52:07 PM PDT 24
Peak memory 209664 kb
Host smart-88fc9c31-9d26-4cb4-b32b-d7e1694699ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192770548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.192770548
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.448174240
Short name T278
Test name
Test status
Simulation time 347535120 ps
CPU time 4 seconds
Started Jun 08 02:52:01 PM PDT 24
Finished Jun 08 02:52:05 PM PDT 24
Peak memory 214136 kb
Host smart-66ecf6fe-ae42-4526-9f8d-0f0c5ef0d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448174240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.448174240
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.740259066
Short name T766
Test name
Test status
Simulation time 328321929 ps
CPU time 4.31 seconds
Started Jun 08 02:52:03 PM PDT 24
Finished Jun 08 02:52:08 PM PDT 24
Peak memory 209824 kb
Host smart-ea881f32-e9ca-4590-a69f-850bad7fe2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740259066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.740259066
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3143036984
Short name T69
Test name
Test status
Simulation time 205296499 ps
CPU time 4.92 seconds
Started Jun 08 02:52:02 PM PDT 24
Finished Jun 08 02:52:07 PM PDT 24
Peak memory 209180 kb
Host smart-8bb21179-8885-467d-8a84-9643f0cb1a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143036984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3143036984
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3357366390
Short name T291
Test name
Test status
Simulation time 570949738 ps
CPU time 4.7 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:52:02 PM PDT 24
Peak memory 207144 kb
Host smart-010c5ef3-0b36-4f33-8a5c-a0c75b2e5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357366390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3357366390
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3670275099
Short name T1026
Test name
Test status
Simulation time 289510795 ps
CPU time 1.95 seconds
Started Jun 08 02:52:00 PM PDT 24
Finished Jun 08 02:52:02 PM PDT 24
Peak memory 206480 kb
Host smart-b4680627-df76-4e9b-b5d4-de1e6e579099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670275099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3670275099
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3095921446
Short name T1017
Test name
Test status
Simulation time 241987464 ps
CPU time 8.47 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:52:06 PM PDT 24
Peak memory 208464 kb
Host smart-44b51b1e-1e6e-4770-9cfd-0d064a214500
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095921446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3095921446
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2296632457
Short name T959
Test name
Test status
Simulation time 152369611 ps
CPU time 2.4 seconds
Started Jun 08 02:51:59 PM PDT 24
Finished Jun 08 02:52:01 PM PDT 24
Peak memory 206624 kb
Host smart-ece2f02a-450b-4874-b1d6-17caae1dc10c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296632457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2296632457
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2592897856
Short name T818
Test name
Test status
Simulation time 35053400 ps
CPU time 2.5 seconds
Started Jun 08 02:51:57 PM PDT 24
Finished Jun 08 02:51:59 PM PDT 24
Peak memory 206784 kb
Host smart-585a657c-3c21-4a9c-ac30-01764bbc1a38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592897856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2592897856
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.309048152
Short name T305
Test name
Test status
Simulation time 458739971 ps
CPU time 9.07 seconds
Started Jun 08 02:52:03 PM PDT 24
Finished Jun 08 02:52:12 PM PDT 24
Peak memory 209152 kb
Host smart-303e64a1-2158-4a03-9b94-a4767c766462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309048152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.309048152
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1545739708
Short name T993
Test name
Test status
Simulation time 1188229157 ps
CPU time 15.23 seconds
Started Jun 08 02:52:02 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 206500 kb
Host smart-5718cc18-9dc0-4eff-871f-3c6b15d2417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545739708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1545739708
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3624239492
Short name T736
Test name
Test status
Simulation time 79174276 ps
CPU time 3.11 seconds
Started Jun 08 02:52:03 PM PDT 24
Finished Jun 08 02:52:06 PM PDT 24
Peak memory 209896 kb
Host smart-2cfe0502-cad1-4082-a920-b1da126523f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624239492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3624239492
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3091210156
Short name T581
Test name
Test status
Simulation time 11096716 ps
CPU time 0.84 seconds
Started Jun 08 02:52:11 PM PDT 24
Finished Jun 08 02:52:12 PM PDT 24
Peak memory 205592 kb
Host smart-71fe4079-a864-4f90-b96c-93c6c2d6ee56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091210156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3091210156
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2946322783
Short name T425
Test name
Test status
Simulation time 42181099 ps
CPU time 2.87 seconds
Started Jun 08 02:52:07 PM PDT 24
Finished Jun 08 02:52:10 PM PDT 24
Peak memory 214036 kb
Host smart-d9175383-9a04-4e94-8210-74ac81f98e11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946322783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2946322783
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.620117678
Short name T38
Test name
Test status
Simulation time 70663224 ps
CPU time 3.57 seconds
Started Jun 08 02:52:09 PM PDT 24
Finished Jun 08 02:52:13 PM PDT 24
Peak memory 213980 kb
Host smart-41889462-17c7-422d-b4cd-317001b407b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620117678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.620117678
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1261410671
Short name T74
Test name
Test status
Simulation time 2201966621 ps
CPU time 38.58 seconds
Started Jun 08 02:52:10 PM PDT 24
Finished Jun 08 02:52:49 PM PDT 24
Peak memory 214028 kb
Host smart-5981e73e-a2de-4934-9f77-97748930e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261410671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1261410671
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1177234535
Short name T345
Test name
Test status
Simulation time 649430575 ps
CPU time 7.63 seconds
Started Jun 08 02:52:10 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 219956 kb
Host smart-298397cc-f925-4386-9a32-8bacd45a778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177234535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1177234535
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3573321143
Short name T977
Test name
Test status
Simulation time 91859962 ps
CPU time 2.64 seconds
Started Jun 08 02:52:08 PM PDT 24
Finished Jun 08 02:52:11 PM PDT 24
Peak memory 215012 kb
Host smart-79ad9974-7ca8-4473-88c5-249251701f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573321143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3573321143
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2269246312
Short name T651
Test name
Test status
Simulation time 10972459375 ps
CPU time 70.93 seconds
Started Jun 08 02:52:09 PM PDT 24
Finished Jun 08 02:53:20 PM PDT 24
Peak memory 220080 kb
Host smart-f6627092-e5db-448b-81ad-c4cfbafcd9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269246312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2269246312
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.853369517
Short name T940
Test name
Test status
Simulation time 1713456891 ps
CPU time 7.14 seconds
Started Jun 08 02:52:08 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 208164 kb
Host smart-8d5536b4-980e-42b6-b289-a94c000b0bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853369517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.853369517
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1649060987
Short name T265
Test name
Test status
Simulation time 262597618 ps
CPU time 6.68 seconds
Started Jun 08 02:52:08 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 207812 kb
Host smart-09a6f901-fa53-44bc-bdcd-fc210dd0d0ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649060987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1649060987
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2553748595
Short name T1019
Test name
Test status
Simulation time 15185486555 ps
CPU time 35.52 seconds
Started Jun 08 02:52:10 PM PDT 24
Finished Jun 08 02:52:46 PM PDT 24
Peak memory 207744 kb
Host smart-63f69b90-61fd-4fda-9b6d-49a28d9869b4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553748595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2553748595
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3915174602
Short name T608
Test name
Test status
Simulation time 324858403 ps
CPU time 6.78 seconds
Started Jun 08 02:52:09 PM PDT 24
Finished Jun 08 02:52:16 PM PDT 24
Peak memory 208428 kb
Host smart-b1ecc837-904b-473d-b49f-4c7f6ccf1ae9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915174602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3915174602
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2959014617
Short name T653
Test name
Test status
Simulation time 981335576 ps
CPU time 7.43 seconds
Started Jun 08 02:52:07 PM PDT 24
Finished Jun 08 02:52:14 PM PDT 24
Peak memory 207940 kb
Host smart-62307545-0659-4697-941b-c69b29df24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959014617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2959014617
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1271970893
Short name T828
Test name
Test status
Simulation time 2310249900 ps
CPU time 10.97 seconds
Started Jun 08 02:52:10 PM PDT 24
Finished Jun 08 02:52:21 PM PDT 24
Peak memory 208016 kb
Host smart-4f3c46c6-d696-48a5-b15b-515ed5b95050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271970893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1271970893
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3765586632
Short name T312
Test name
Test status
Simulation time 246887878 ps
CPU time 4.09 seconds
Started Jun 08 02:52:09 PM PDT 24
Finished Jun 08 02:52:14 PM PDT 24
Peak memory 219700 kb
Host smart-ef481992-27aa-415e-b3b8-e7f84b742ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765586632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3765586632
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2482685562
Short name T969
Test name
Test status
Simulation time 482979408 ps
CPU time 10.15 seconds
Started Jun 08 02:52:08 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 222372 kb
Host smart-ea4f00b3-ce5e-49cf-ba48-4be747a93a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482685562 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2482685562
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2435591206
Short name T66
Test name
Test status
Simulation time 621713589 ps
CPU time 16.69 seconds
Started Jun 08 02:52:10 PM PDT 24
Finished Jun 08 02:52:27 PM PDT 24
Peak memory 210660 kb
Host smart-0113d39b-7164-4b24-8b0d-5bc3214e9701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435591206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2435591206
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.591872874
Short name T912
Test name
Test status
Simulation time 14445534 ps
CPU time 0.67 seconds
Started Jun 08 02:52:11 PM PDT 24
Finished Jun 08 02:52:12 PM PDT 24
Peak memory 205608 kb
Host smart-7caec861-bee1-43f8-9b4a-34f4f0a81291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591872874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.591872874
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4223886537
Short name T807
Test name
Test status
Simulation time 1708457478 ps
CPU time 28.1 seconds
Started Jun 08 02:52:15 PM PDT 24
Finished Jun 08 02:52:44 PM PDT 24
Peak memory 220948 kb
Host smart-95b8d31e-eb0a-497a-ae00-4d07b3b84c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223886537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4223886537
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2446345791
Short name T633
Test name
Test status
Simulation time 329655331 ps
CPU time 2.79 seconds
Started Jun 08 02:52:12 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 209612 kb
Host smart-0ceb30d0-788a-4dd1-a696-567f3f497c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446345791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2446345791
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.535656683
Short name T300
Test name
Test status
Simulation time 51034438 ps
CPU time 2.62 seconds
Started Jun 08 02:52:13 PM PDT 24
Finished Jun 08 02:52:16 PM PDT 24
Peak memory 208048 kb
Host smart-1c3a60be-4355-43e2-8ce9-3220cf62f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535656683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.535656683
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1485041464
Short name T339
Test name
Test status
Simulation time 515064453 ps
CPU time 15.62 seconds
Started Jun 08 02:52:14 PM PDT 24
Finished Jun 08 02:52:30 PM PDT 24
Peak memory 216100 kb
Host smart-5ca8b8c0-96f2-4f8b-83f7-0b089dca5e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485041464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1485041464
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1965684359
Short name T762
Test name
Test status
Simulation time 44903776 ps
CPU time 2.67 seconds
Started Jun 08 02:52:12 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 218516 kb
Host smart-ce47a2e9-a96e-417f-8559-9d28117e8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965684359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1965684359
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.219725905
Short name T366
Test name
Test status
Simulation time 45231097 ps
CPU time 2.98 seconds
Started Jun 08 02:52:17 PM PDT 24
Finished Jun 08 02:52:20 PM PDT 24
Peak memory 218044 kb
Host smart-03d59fb1-93e3-4e68-89ef-dc5d3745659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219725905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.219725905
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.588069649
Short name T785
Test name
Test status
Simulation time 554677058 ps
CPU time 10.23 seconds
Started Jun 08 02:52:16 PM PDT 24
Finished Jun 08 02:52:27 PM PDT 24
Peak memory 208680 kb
Host smart-5aca68f4-cd5c-47f9-a696-1f0951240476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588069649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.588069649
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.798437614
Short name T897
Test name
Test status
Simulation time 49723486 ps
CPU time 3.06 seconds
Started Jun 08 02:52:15 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 208404 kb
Host smart-6c832485-935f-4825-8662-46f89d48d928
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798437614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.798437614
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4191993015
Short name T985
Test name
Test status
Simulation time 130274208 ps
CPU time 2.42 seconds
Started Jun 08 02:52:11 PM PDT 24
Finished Jun 08 02:52:14 PM PDT 24
Peak memory 206588 kb
Host smart-dbb6efbb-9338-40dd-886f-bbb9ae3d625a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191993015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4191993015
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3644952154
Short name T735
Test name
Test status
Simulation time 76599844 ps
CPU time 1.73 seconds
Started Jun 08 02:52:16 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 207240 kb
Host smart-fdbcc57d-d0fd-43e3-89b6-59fbc6a0583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644952154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3644952154
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1231724716
Short name T724
Test name
Test status
Simulation time 2355888012 ps
CPU time 4.23 seconds
Started Jun 08 02:52:12 PM PDT 24
Finished Jun 08 02:52:16 PM PDT 24
Peak memory 208124 kb
Host smart-8c0bf1c9-d561-4d39-9f37-6d8ea9c7f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231724716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1231724716
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.493440980
Short name T639
Test name
Test status
Simulation time 1681611655 ps
CPU time 31.34 seconds
Started Jun 08 02:52:15 PM PDT 24
Finished Jun 08 02:52:46 PM PDT 24
Peak memory 219388 kb
Host smart-18f4a906-bb67-4bbd-88c8-a4622f39a1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493440980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.493440980
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3945365220
Short name T1011
Test name
Test status
Simulation time 88016847 ps
CPU time 4.18 seconds
Started Jun 08 02:52:14 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 222392 kb
Host smart-8026cc06-3c83-4abb-85bd-8e7c2d817c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945365220 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3945365220
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2966568415
Short name T347
Test name
Test status
Simulation time 304501285 ps
CPU time 5.79 seconds
Started Jun 08 02:52:17 PM PDT 24
Finished Jun 08 02:52:23 PM PDT 24
Peak memory 213900 kb
Host smart-ff47a8ed-32cd-4b71-8fcd-73cfbc45dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966568415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2966568415
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1150677765
Short name T878
Test name
Test status
Simulation time 179150073 ps
CPU time 3.36 seconds
Started Jun 08 02:52:15 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 210712 kb
Host smart-60beaa05-7bcc-49f1-a26e-c2cef77e1fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150677765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1150677765
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.22156528
Short name T984
Test name
Test status
Simulation time 46795581 ps
CPU time 0.75 seconds
Started Jun 08 02:52:21 PM PDT 24
Finished Jun 08 02:52:22 PM PDT 24
Peak memory 205592 kb
Host smart-97826f30-2214-469e-860d-5b198d7bb31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.22156528
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2983516882
Short name T1024
Test name
Test status
Simulation time 1347505853 ps
CPU time 15.98 seconds
Started Jun 08 02:52:17 PM PDT 24
Finished Jun 08 02:52:33 PM PDT 24
Peak memory 216992 kb
Host smart-673b3596-9956-4447-a730-1c9a12696cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983516882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2983516882
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1378323317
Short name T722
Test name
Test status
Simulation time 667259566 ps
CPU time 1.95 seconds
Started Jun 08 02:52:16 PM PDT 24
Finished Jun 08 02:52:18 PM PDT 24
Peak memory 207168 kb
Host smart-f18f5960-0570-434c-94d8-1907d1e3e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378323317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1378323317
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2030226083
Short name T1033
Test name
Test status
Simulation time 573738625 ps
CPU time 10.81 seconds
Started Jun 08 02:52:20 PM PDT 24
Finished Jun 08 02:52:31 PM PDT 24
Peak memory 222176 kb
Host smart-e629dfd3-5893-4385-bca9-8a128ca90619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030226083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2030226083
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1427647375
Short name T866
Test name
Test status
Simulation time 114534929 ps
CPU time 2.54 seconds
Started Jun 08 02:52:18 PM PDT 24
Finished Jun 08 02:52:21 PM PDT 24
Peak memory 207820 kb
Host smart-af6c1cac-7459-4e5e-b8be-4ae20389d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427647375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1427647375
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.855807216
Short name T386
Test name
Test status
Simulation time 239455733 ps
CPU time 4.22 seconds
Started Jun 08 02:52:16 PM PDT 24
Finished Jun 08 02:52:21 PM PDT 24
Peak memory 209340 kb
Host smart-7c652a0e-2f76-476d-94eb-6d7957993985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855807216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.855807216
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2787670779
Short name T393
Test name
Test status
Simulation time 36080307 ps
CPU time 2.27 seconds
Started Jun 08 02:52:13 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 206552 kb
Host smart-808df7cf-360b-4780-89bf-7cb9ad515856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787670779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2787670779
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.662681021
Short name T771
Test name
Test status
Simulation time 26216140 ps
CPU time 1.92 seconds
Started Jun 08 02:52:20 PM PDT 24
Finished Jun 08 02:52:23 PM PDT 24
Peak memory 208432 kb
Host smart-8a4a3245-4551-4058-8de6-c70532e51bb0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662681021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.662681021
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4157121373
Short name T604
Test name
Test status
Simulation time 504066048 ps
CPU time 5.02 seconds
Started Jun 08 02:52:12 PM PDT 24
Finished Jun 08 02:52:17 PM PDT 24
Peak memory 206640 kb
Host smart-97564393-0f08-4109-9e3c-07915fb6e354
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157121373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4157121373
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3117318650
Short name T1030
Test name
Test status
Simulation time 241198065 ps
CPU time 3.16 seconds
Started Jun 08 02:52:17 PM PDT 24
Finished Jun 08 02:52:21 PM PDT 24
Peak memory 206676 kb
Host smart-dd8b2a2b-7385-4abc-9a42-8e25f9b43099
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117318650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3117318650
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3994422767
Short name T426
Test name
Test status
Simulation time 70213350 ps
CPU time 2.79 seconds
Started Jun 08 02:52:18 PM PDT 24
Finished Jun 08 02:52:21 PM PDT 24
Peak memory 215144 kb
Host smart-703edf6a-52fb-4bd0-b476-91d7e51ea5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994422767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3994422767
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.860594778
Short name T664
Test name
Test status
Simulation time 58932542 ps
CPU time 2.63 seconds
Started Jun 08 02:52:13 PM PDT 24
Finished Jun 08 02:52:16 PM PDT 24
Peak memory 208172 kb
Host smart-62337eb7-ffdf-4db0-b105-c443cc0b0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860594778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.860594778
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3274118881
Short name T26
Test name
Test status
Simulation time 3444848911 ps
CPU time 24.15 seconds
Started Jun 08 02:52:18 PM PDT 24
Finished Jun 08 02:52:42 PM PDT 24
Peak memory 222256 kb
Host smart-567f4b1f-3293-4043-b487-9d7e431e8697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274118881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3274118881
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2558175815
Short name T713
Test name
Test status
Simulation time 156682171 ps
CPU time 2.26 seconds
Started Jun 08 02:52:20 PM PDT 24
Finished Jun 08 02:52:23 PM PDT 24
Peak memory 209840 kb
Host smart-ad50a3ab-cf83-4daf-8a6e-391458816d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558175815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2558175815
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1157715104
Short name T575
Test name
Test status
Simulation time 286106418 ps
CPU time 1.01 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:29 PM PDT 24
Peak memory 205572 kb
Host smart-16926ec8-6ddc-465d-9269-93e2025132c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157715104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1157715104
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.745127082
Short name T351
Test name
Test status
Simulation time 135871636 ps
CPU time 2.89 seconds
Started Jun 08 02:52:24 PM PDT 24
Finished Jun 08 02:52:27 PM PDT 24
Peak memory 215160 kb
Host smart-9e177d5e-da8c-4602-b49a-d39da4c685c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745127082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.745127082
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.517977664
Short name T209
Test name
Test status
Simulation time 123308756 ps
CPU time 5.33 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:34 PM PDT 24
Peak memory 217748 kb
Host smart-1ff4536c-ba99-4377-9121-cfb408baef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517977664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.517977664
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3694413121
Short name T988
Test name
Test status
Simulation time 263716421 ps
CPU time 3.33 seconds
Started Jun 08 02:52:26 PM PDT 24
Finished Jun 08 02:52:29 PM PDT 24
Peak memory 217988 kb
Host smart-d33aedd4-78b8-4f1e-97a5-6ca6b6efdaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694413121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3694413121
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2142353602
Short name T277
Test name
Test status
Simulation time 732709601 ps
CPU time 9.22 seconds
Started Jun 08 02:52:29 PM PDT 24
Finished Jun 08 02:52:38 PM PDT 24
Peak memory 213980 kb
Host smart-342c1f97-282d-40af-bf3a-c46601762afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142353602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2142353602
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3025473026
Short name T56
Test name
Test status
Simulation time 2271155972 ps
CPU time 15.81 seconds
Started Jun 08 02:52:23 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 208876 kb
Host smart-cbd219bf-c458-4b9c-8966-82f72fab86e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025473026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3025473026
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.140603107
Short name T192
Test name
Test status
Simulation time 95405539 ps
CPU time 4.69 seconds
Started Jun 08 02:52:24 PM PDT 24
Finished Jun 08 02:52:29 PM PDT 24
Peak memory 207068 kb
Host smart-da4c5ce4-701d-443b-93c7-394045491a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140603107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.140603107
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3139228371
Short name T862
Test name
Test status
Simulation time 57097385 ps
CPU time 3 seconds
Started Jun 08 02:52:20 PM PDT 24
Finished Jun 08 02:52:23 PM PDT 24
Peak memory 207676 kb
Host smart-6b720697-f75d-437f-bcf1-66074fc721d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139228371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3139228371
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2137895415
Short name T284
Test name
Test status
Simulation time 1012279622 ps
CPU time 26.79 seconds
Started Jun 08 02:52:23 PM PDT 24
Finished Jun 08 02:52:50 PM PDT 24
Peak memory 208044 kb
Host smart-c50ee439-d01c-4b8e-93a8-bbc3e490e72d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137895415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2137895415
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1920590260
Short name T780
Test name
Test status
Simulation time 69891507 ps
CPU time 2.67 seconds
Started Jun 08 02:52:26 PM PDT 24
Finished Jun 08 02:52:28 PM PDT 24
Peak memory 207260 kb
Host smart-03162b13-2910-4d8a-8db3-27db7e6bb008
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920590260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1920590260
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4209636152
Short name T287
Test name
Test status
Simulation time 121455069 ps
CPU time 5.13 seconds
Started Jun 08 02:52:23 PM PDT 24
Finished Jun 08 02:52:28 PM PDT 24
Peak memory 208468 kb
Host smart-ceda6aae-e30d-47c8-af94-a876d06554ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209636152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4209636152
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1458208122
Short name T116
Test name
Test status
Simulation time 79726509 ps
CPU time 2.83 seconds
Started Jun 08 02:52:30 PM PDT 24
Finished Jun 08 02:52:33 PM PDT 24
Peak memory 207020 kb
Host smart-80f096a5-b65d-4786-8cbf-46c6c14c30fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458208122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1458208122
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1466252572
Short name T640
Test name
Test status
Simulation time 3849979116 ps
CPU time 8.3 seconds
Started Jun 08 02:52:17 PM PDT 24
Finished Jun 08 02:52:26 PM PDT 24
Peak memory 208492 kb
Host smart-be1c0fde-12cb-4425-aada-05c1a79d8efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466252572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1466252572
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1821044634
Short name T286
Test name
Test status
Simulation time 205871469 ps
CPU time 11.44 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 216104 kb
Host smart-22471495-2b7f-4d68-a026-299c6c388d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821044634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1821044634
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1352887249
Short name T106
Test name
Test status
Simulation time 177270085 ps
CPU time 5.86 seconds
Started Jun 08 02:52:27 PM PDT 24
Finished Jun 08 02:52:33 PM PDT 24
Peak memory 220716 kb
Host smart-eed28fa8-2e20-4beb-b963-5f16c251dd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352887249 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1352887249
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.908132112
Short name T365
Test name
Test status
Simulation time 191417896 ps
CPU time 4.73 seconds
Started Jun 08 02:52:25 PM PDT 24
Finished Jun 08 02:52:30 PM PDT 24
Peak memory 209544 kb
Host smart-bbef42b7-ed50-4a0d-baf5-31a4d2ebb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908132112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.908132112
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.746240170
Short name T701
Test name
Test status
Simulation time 149587830 ps
CPU time 2.36 seconds
Started Jun 08 02:52:27 PM PDT 24
Finished Jun 08 02:52:29 PM PDT 24
Peak memory 209780 kb
Host smart-6060c171-6a5f-4123-b196-316b7832abee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746240170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.746240170
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.351890389
Short name T1025
Test name
Test status
Simulation time 22749885 ps
CPU time 0.89 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:35 PM PDT 24
Peak memory 205524 kb
Host smart-7076a13a-6af2-4692-a8db-ccde74c7940d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351890389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.351890389
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.944263199
Short name T965
Test name
Test status
Simulation time 149582234 ps
CPU time 3.58 seconds
Started Jun 08 02:52:29 PM PDT 24
Finished Jun 08 02:52:33 PM PDT 24
Peak memory 214016 kb
Host smart-0aefafff-f0ae-4acf-857c-dcc439ee2477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944263199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.944263199
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2081956189
Short name T953
Test name
Test status
Simulation time 818594603 ps
CPU time 4.82 seconds
Started Jun 08 02:52:30 PM PDT 24
Finished Jun 08 02:52:35 PM PDT 24
Peak memory 220432 kb
Host smart-c8eae4ad-5477-48cf-87ca-9915a0adb131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081956189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2081956189
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.890588089
Short name T614
Test name
Test status
Simulation time 823552818 ps
CPU time 11.57 seconds
Started Jun 08 02:52:30 PM PDT 24
Finished Jun 08 02:52:42 PM PDT 24
Peak memory 209828 kb
Host smart-331c285d-476a-4916-952d-2fd940c333f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890588089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.890588089
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1675398334
Short name T750
Test name
Test status
Simulation time 1711672272 ps
CPU time 5.23 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:52:33 PM PDT 24
Peak memory 207800 kb
Host smart-f785dd94-d261-4183-99fc-7250162a084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675398334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1675398334
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1918023033
Short name T699
Test name
Test status
Simulation time 50259306 ps
CPU time 2.57 seconds
Started Jun 08 02:52:29 PM PDT 24
Finished Jun 08 02:52:32 PM PDT 24
Peak memory 206636 kb
Host smart-c9a79407-1fee-4c5e-bca1-d19b3c0aaa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918023033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1918023033
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.22801004
Short name T748
Test name
Test status
Simulation time 929663054 ps
CPU time 9.44 seconds
Started Jun 08 02:52:30 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 207816 kb
Host smart-cf45005e-e7d0-4f35-96d0-58f2301b9f9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.22801004
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2762043858
Short name T364
Test name
Test status
Simulation time 2777427021 ps
CPU time 37.28 seconds
Started Jun 08 02:52:28 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 207928 kb
Host smart-1e95e231-8d4a-4437-996b-6aa9900b2f2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762043858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2762043858
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2918645756
Short name T642
Test name
Test status
Simulation time 142275631 ps
CPU time 2.23 seconds
Started Jun 08 02:52:29 PM PDT 24
Finished Jun 08 02:52:31 PM PDT 24
Peak memory 208304 kb
Host smart-c931877c-7b5a-4139-bef3-3848fb87bc08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918645756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2918645756
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2098784841
Short name T747
Test name
Test status
Simulation time 24902327 ps
CPU time 1.75 seconds
Started Jun 08 02:52:32 PM PDT 24
Finished Jun 08 02:52:34 PM PDT 24
Peak memory 207412 kb
Host smart-a115c0b2-29a3-430e-9fe0-b23d723744ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098784841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2098784841
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.549438145
Short name T578
Test name
Test status
Simulation time 413450815 ps
CPU time 3.51 seconds
Started Jun 08 02:52:31 PM PDT 24
Finished Jun 08 02:52:34 PM PDT 24
Peak memory 208388 kb
Host smart-5eef3d97-f254-4670-a6c7-3cc2f3ea9ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549438145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.549438145
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2532612681
Short name T1039
Test name
Test status
Simulation time 663733238 ps
CPU time 5.73 seconds
Started Jun 08 02:52:29 PM PDT 24
Finished Jun 08 02:52:35 PM PDT 24
Peak memory 207432 kb
Host smart-07ef9f55-87da-4d57-8037-a9c7a7caf0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532612681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2532612681
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3216654616
Short name T851
Test name
Test status
Simulation time 116239450 ps
CPU time 2.25 seconds
Started Jun 08 02:52:33 PM PDT 24
Finished Jun 08 02:52:35 PM PDT 24
Peak memory 210084 kb
Host smart-5487dab3-35be-420b-9a07-cca6113fed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216654616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3216654616
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.127180393
Short name T103
Test name
Test status
Simulation time 25127006 ps
CPU time 0.76 seconds
Started Jun 08 02:52:38 PM PDT 24
Finished Jun 08 02:52:39 PM PDT 24
Peak memory 205596 kb
Host smart-e3dc21c8-dfb9-43cd-a1d1-2c089529aebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127180393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.127180393
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.331799730
Short name T420
Test name
Test status
Simulation time 166246690 ps
CPU time 4.48 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:38 PM PDT 24
Peak memory 214740 kb
Host smart-427fb783-fe38-499b-81fc-93ccd64c3884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331799730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.331799730
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2093563357
Short name T931
Test name
Test status
Simulation time 68844639 ps
CPU time 2.43 seconds
Started Jun 08 02:52:41 PM PDT 24
Finished Jun 08 02:52:44 PM PDT 24
Peak memory 213948 kb
Host smart-7005c351-68c5-467b-b096-2865baff4b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093563357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2093563357
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4117487123
Short name T809
Test name
Test status
Simulation time 1954071065 ps
CPU time 11.42 seconds
Started Jun 08 02:52:33 PM PDT 24
Finished Jun 08 02:52:44 PM PDT 24
Peak memory 207860 kb
Host smart-d13c7398-ec08-466d-8029-0c9dfb4e3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117487123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4117487123
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3044629708
Short name T1007
Test name
Test status
Simulation time 45801935 ps
CPU time 2.84 seconds
Started Jun 08 02:52:38 PM PDT 24
Finished Jun 08 02:52:41 PM PDT 24
Peak memory 207920 kb
Host smart-e4554ef8-6eb1-4905-8fdb-b761c5557438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044629708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3044629708
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1514275281
Short name T768
Test name
Test status
Simulation time 650570968 ps
CPU time 5.91 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 222184 kb
Host smart-a04a310e-be3a-4cd4-91c9-14259ae02ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514275281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1514275281
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3119453198
Short name T1054
Test name
Test status
Simulation time 156731364 ps
CPU time 2.7 seconds
Started Jun 08 02:52:36 PM PDT 24
Finished Jun 08 02:52:39 PM PDT 24
Peak memory 206704 kb
Host smart-2d43789f-eaba-4397-9f69-fea496fb30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119453198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3119453198
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2917477290
Short name T596
Test name
Test status
Simulation time 209944872 ps
CPU time 7.12 seconds
Started Jun 08 02:52:35 PM PDT 24
Finished Jun 08 02:52:42 PM PDT 24
Peak memory 208104 kb
Host smart-e43aa93f-e8ce-4c0c-95f6-014c8d1a5174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917477290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2917477290
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3709970153
Short name T982
Test name
Test status
Simulation time 585891908 ps
CPU time 5.37 seconds
Started Jun 08 02:52:33 PM PDT 24
Finished Jun 08 02:52:39 PM PDT 24
Peak memory 208356 kb
Host smart-07da59d1-d4ee-4c48-8a7d-a744afa3a325
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709970153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3709970153
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1370086772
Short name T668
Test name
Test status
Simulation time 127764884 ps
CPU time 3.37 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:38 PM PDT 24
Peak memory 206612 kb
Host smart-7e56dfce-0884-4e66-9c20-d6b2862d2c16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370086772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1370086772
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3149569814
Short name T994
Test name
Test status
Simulation time 52082896 ps
CPU time 2.86 seconds
Started Jun 08 02:52:34 PM PDT 24
Finished Jun 08 02:52:37 PM PDT 24
Peak memory 208192 kb
Host smart-c66d18b7-b7b1-4a56-99a5-fc67f1017e4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149569814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3149569814
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3792577765
Short name T729
Test name
Test status
Simulation time 25647421 ps
CPU time 1.76 seconds
Started Jun 08 02:52:38 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 207004 kb
Host smart-90356a80-5da9-4c3a-aa9d-44432d8635d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792577765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3792577765
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1988437854
Short name T700
Test name
Test status
Simulation time 50893084 ps
CPU time 2.48 seconds
Started Jun 08 02:52:35 PM PDT 24
Finished Jun 08 02:52:38 PM PDT 24
Peak memory 206424 kb
Host smart-a8d04a4f-b1c4-42f0-933b-e77edccb1c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988437854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1988437854
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1089711549
Short name T299
Test name
Test status
Simulation time 70118283 ps
CPU time 3.32 seconds
Started Jun 08 02:52:39 PM PDT 24
Finished Jun 08 02:52:42 PM PDT 24
Peak memory 208476 kb
Host smart-8bff36cd-b922-489b-93bd-29fa597ef923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089711549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1089711549
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1000180782
Short name T260
Test name
Test status
Simulation time 400260323 ps
CPU time 4.84 seconds
Started Jun 08 02:52:35 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 208848 kb
Host smart-5fbcebe9-dc9b-43b9-bad1-1685e4b40199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000180782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1000180782
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3786184090
Short name T720
Test name
Test status
Simulation time 82565562 ps
CPU time 1.72 seconds
Started Jun 08 02:52:39 PM PDT 24
Finished Jun 08 02:52:40 PM PDT 24
Peak memory 209692 kb
Host smart-4ca34352-9817-4fbd-8d3d-7537ad88c83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786184090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3786184090
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2340013520
Short name T572
Test name
Test status
Simulation time 29168473 ps
CPU time 0.77 seconds
Started Jun 08 02:52:44 PM PDT 24
Finished Jun 08 02:52:45 PM PDT 24
Peak memory 205604 kb
Host smart-2c5eb48f-90ee-4466-b29b-3749882d565a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340013520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2340013520
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3422814203
Short name T244
Test name
Test status
Simulation time 131884212 ps
CPU time 3.41 seconds
Started Jun 08 02:52:40 PM PDT 24
Finished Jun 08 02:52:43 PM PDT 24
Peak memory 214024 kb
Host smart-14ea13e8-aad8-4ae5-98f6-0b5d250c59e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422814203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3422814203
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4123780079
Short name T595
Test name
Test status
Simulation time 99222380 ps
CPU time 2.61 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:53 PM PDT 24
Peak memory 214020 kb
Host smart-2950698b-2c87-48be-8121-02e24e835730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123780079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4123780079
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3303331529
Short name T355
Test name
Test status
Simulation time 85716050 ps
CPU time 2.89 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:48 PM PDT 24
Peak memory 214064 kb
Host smart-d529d076-a1be-4f96-8aed-dcedd4a4e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303331529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3303331529
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.414658438
Short name T247
Test name
Test status
Simulation time 324404635 ps
CPU time 9.22 seconds
Started Jun 08 02:52:44 PM PDT 24
Finished Jun 08 02:52:53 PM PDT 24
Peak memory 220700 kb
Host smart-d557c693-1a8c-4c31-b052-4bfccd6175e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414658438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.414658438
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2955473985
Short name T228
Test name
Test status
Simulation time 61111166 ps
CPU time 2.84 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:53 PM PDT 24
Peak memory 214660 kb
Host smart-89079b26-d097-4de6-8400-245a53ea3c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955473985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2955473985
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.516645909
Short name T834
Test name
Test status
Simulation time 76998633 ps
CPU time 4.4 seconds
Started Jun 08 02:52:43 PM PDT 24
Finished Jun 08 02:52:48 PM PDT 24
Peak memory 218176 kb
Host smart-b32600d0-b352-4590-805c-5fa4c9a6215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516645909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.516645909
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2927590716
Short name T804
Test name
Test status
Simulation time 469872208 ps
CPU time 6.22 seconds
Started Jun 08 02:52:41 PM PDT 24
Finished Jun 08 02:52:47 PM PDT 24
Peak memory 207640 kb
Host smart-1a3b1c14-a285-4972-b44b-7effd96e8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927590716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2927590716
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2279159947
Short name T801
Test name
Test status
Simulation time 158840091 ps
CPU time 6.6 seconds
Started Jun 08 02:52:40 PM PDT 24
Finished Jun 08 02:52:47 PM PDT 24
Peak memory 207612 kb
Host smart-43948644-bc43-4aeb-8f4c-f1c5452653d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279159947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2279159947
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3076755063
Short name T770
Test name
Test status
Simulation time 241962449 ps
CPU time 8.26 seconds
Started Jun 08 02:52:39 PM PDT 24
Finished Jun 08 02:52:47 PM PDT 24
Peak memory 208336 kb
Host smart-a3d814dd-eb97-4150-9cd6-17ad25810817
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076755063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3076755063
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1627952829
Short name T826
Test name
Test status
Simulation time 380751943 ps
CPU time 8.96 seconds
Started Jun 08 02:52:39 PM PDT 24
Finished Jun 08 02:52:48 PM PDT 24
Peak memory 207532 kb
Host smart-afb4bc8d-5ece-4b2f-8150-d2eeaf6c2c5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627952829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1627952829
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2609231369
Short name T655
Test name
Test status
Simulation time 357098176 ps
CPU time 4.12 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:49 PM PDT 24
Peak memory 207888 kb
Host smart-64995784-cde8-4e21-b885-c0112674ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609231369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2609231369
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4205578651
Short name T1008
Test name
Test status
Simulation time 811097529 ps
CPU time 4.76 seconds
Started Jun 08 02:52:39 PM PDT 24
Finished Jun 08 02:52:44 PM PDT 24
Peak memory 206980 kb
Host smart-01e23972-c5f3-46c5-be1d-c5f9d1a0af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205578651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4205578651
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3191638924
Short name T385
Test name
Test status
Simulation time 260074299 ps
CPU time 7.03 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:52 PM PDT 24
Peak memory 219812 kb
Host smart-7bc25599-a6f8-49b1-8541-dc7ecd94276d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191638924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3191638924
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2940858691
Short name T598
Test name
Test status
Simulation time 339246869 ps
CPU time 5.26 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:56 PM PDT 24
Peak memory 222240 kb
Host smart-30c95944-922e-45f1-b43e-d4fffafa18bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940858691 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2940858691
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1439565478
Short name T974
Test name
Test status
Simulation time 89147717 ps
CPU time 4.71 seconds
Started Jun 08 02:52:44 PM PDT 24
Finished Jun 08 02:52:49 PM PDT 24
Peak memory 209004 kb
Host smart-b55c1cd1-04a7-4a1a-9002-1bf0e87b6f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439565478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1439565478
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.648990340
Short name T171
Test name
Test status
Simulation time 166153670 ps
CPU time 3.8 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:49 PM PDT 24
Peak memory 210156 kb
Host smart-28e8df53-b95e-48e9-b352-3fa31d3ce667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648990340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.648990340
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2705222322
Short name T625
Test name
Test status
Simulation time 15815834 ps
CPU time 0.99 seconds
Started Jun 08 02:50:57 PM PDT 24
Finished Jun 08 02:50:58 PM PDT 24
Peak memory 205704 kb
Host smart-6c4319a3-e18e-42e4-adbb-9acf0ef992bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705222322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2705222322
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.302068862
Short name T32
Test name
Test status
Simulation time 164956698 ps
CPU time 5.95 seconds
Started Jun 08 02:50:58 PM PDT 24
Finished Jun 08 02:51:04 PM PDT 24
Peak memory 222516 kb
Host smart-039f0cd7-fc81-4567-b3f4-08242db4da31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302068862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.302068862
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3989866
Short name T895
Test name
Test status
Simulation time 277283720 ps
CPU time 4.01 seconds
Started Jun 08 02:50:52 PM PDT 24
Finished Jun 08 02:50:56 PM PDT 24
Peak memory 213996 kb
Host smart-1a19f826-cfb5-4f42-b17d-8ecb72c553f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3989866
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1714627733
Short name T645
Test name
Test status
Simulation time 226392123 ps
CPU time 6.39 seconds
Started Jun 08 02:51:02 PM PDT 24
Finished Jun 08 02:51:08 PM PDT 24
Peak memory 208240 kb
Host smart-6901a74a-e013-4cc3-93e9-ede110804510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714627733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1714627733
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.762700069
Short name T867
Test name
Test status
Simulation time 225042304 ps
CPU time 3.68 seconds
Started Jun 08 02:51:02 PM PDT 24
Finished Jun 08 02:51:06 PM PDT 24
Peak memory 219572 kb
Host smart-44a879ae-def7-4cf1-b767-84cfe1a5f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762700069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.762700069
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1800148853
Short name T915
Test name
Test status
Simulation time 371545412 ps
CPU time 5.81 seconds
Started Jun 08 02:50:53 PM PDT 24
Finished Jun 08 02:50:59 PM PDT 24
Peak memory 217668 kb
Host smart-111bb0cf-c619-46af-b5f6-92b2f84106b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800148853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1800148853
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2029608163
Short name T43
Test name
Test status
Simulation time 1018323642 ps
CPU time 10.75 seconds
Started Jun 08 02:50:59 PM PDT 24
Finished Jun 08 02:51:10 PM PDT 24
Peak memory 230404 kb
Host smart-f8b1a707-628e-4a4b-9c1e-b896495cf24c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029608163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2029608163
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3005796606
Short name T868
Test name
Test status
Simulation time 462857406 ps
CPU time 3.91 seconds
Started Jun 08 02:50:54 PM PDT 24
Finished Jun 08 02:50:58 PM PDT 24
Peak memory 206584 kb
Host smart-4c6341da-3990-43d0-b6cd-aeea47e038b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005796606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3005796606
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3605267894
Short name T602
Test name
Test status
Simulation time 194782295 ps
CPU time 5.77 seconds
Started Jun 08 02:51:01 PM PDT 24
Finished Jun 08 02:51:07 PM PDT 24
Peak memory 207828 kb
Host smart-c8313545-d1f9-4ab0-ab3d-43b042ca231b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605267894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3605267894
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4221689136
Short name T656
Test name
Test status
Simulation time 113084130 ps
CPU time 2.35 seconds
Started Jun 08 02:50:54 PM PDT 24
Finished Jun 08 02:50:56 PM PDT 24
Peak memory 208288 kb
Host smart-7a425942-c718-4cd2-8f27-f9db4b344e92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221689136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4221689136
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3392182777
Short name T843
Test name
Test status
Simulation time 106355805 ps
CPU time 2.65 seconds
Started Jun 08 02:51:02 PM PDT 24
Finished Jun 08 02:51:05 PM PDT 24
Peak memory 206568 kb
Host smart-541d337c-eb71-4218-af35-8f1bbb2c68b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392182777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3392182777
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3619368770
Short name T210
Test name
Test status
Simulation time 76939879 ps
CPU time 2.37 seconds
Started Jun 08 02:50:57 PM PDT 24
Finished Jun 08 02:51:00 PM PDT 24
Peak memory 209844 kb
Host smart-637ecb31-0798-49dd-b934-c3e9caed704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619368770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3619368770
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1975652139
Short name T792
Test name
Test status
Simulation time 102987218 ps
CPU time 2.97 seconds
Started Jun 08 02:50:52 PM PDT 24
Finished Jun 08 02:50:55 PM PDT 24
Peak memory 206292 kb
Host smart-070bc047-a527-4bbc-83a5-2e20f5f01a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975652139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1975652139
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1091742138
Short name T271
Test name
Test status
Simulation time 6009718392 ps
CPU time 111.64 seconds
Started Jun 08 02:50:59 PM PDT 24
Finished Jun 08 02:52:51 PM PDT 24
Peak memory 217396 kb
Host smart-770737b6-41fe-4eb6-bd75-a1cdd5621d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091742138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1091742138
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.713978892
Short name T401
Test name
Test status
Simulation time 145824682 ps
CPU time 6.78 seconds
Started Jun 08 02:50:56 PM PDT 24
Finished Jun 08 02:51:03 PM PDT 24
Peak memory 219924 kb
Host smart-026cda71-dc04-448a-89e1-42d7118c00e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713978892 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.713978892
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4010616976
Short name T947
Test name
Test status
Simulation time 510160179 ps
CPU time 7.73 seconds
Started Jun 08 02:50:58 PM PDT 24
Finished Jun 08 02:51:06 PM PDT 24
Peak memory 209920 kb
Host smart-171767ac-c0ae-4e32-a2ac-724271272a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010616976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4010616976
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3217815486
Short name T601
Test name
Test status
Simulation time 10477367 ps
CPU time 0.86 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:51 PM PDT 24
Peak memory 205516 kb
Host smart-1313874e-6409-4ba0-9fc8-b16012e3940e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217815486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3217815486
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2459566440
Short name T883
Test name
Test status
Simulation time 807602272 ps
CPU time 10.44 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:53:03 PM PDT 24
Peak memory 213948 kb
Host smart-f286005a-1cf9-4229-8b67-2b1bcb088108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459566440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2459566440
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2015866582
Short name T73
Test name
Test status
Simulation time 1154123282 ps
CPU time 11.49 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:53:04 PM PDT 24
Peak memory 209732 kb
Host smart-a5ea302a-c24e-4036-b732-b1ad780c8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015866582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2015866582
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.675865928
Short name T399
Test name
Test status
Simulation time 7116782488 ps
CPU time 38.82 seconds
Started Jun 08 02:52:53 PM PDT 24
Finished Jun 08 02:53:32 PM PDT 24
Peak memory 214088 kb
Host smart-4570d473-2d4c-471f-bca9-7fe6b8b93555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675865928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.675865928
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1813645286
Short name T276
Test name
Test status
Simulation time 71323577 ps
CPU time 3.18 seconds
Started Jun 08 02:52:51 PM PDT 24
Finished Jun 08 02:52:54 PM PDT 24
Peak memory 211092 kb
Host smart-8dd1e2e4-30de-4576-aa01-e80a09fa71cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813645286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1813645286
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3108656472
Short name T786
Test name
Test status
Simulation time 117403081 ps
CPU time 5.91 seconds
Started Jun 08 02:52:51 PM PDT 24
Finished Jun 08 02:52:57 PM PDT 24
Peak memory 209792 kb
Host smart-83122c6a-d475-4bf1-b9f8-13e9bb34b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108656472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3108656472
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1367922469
Short name T742
Test name
Test status
Simulation time 915533777 ps
CPU time 29.67 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:53:21 PM PDT 24
Peak memory 222192 kb
Host smart-222de97d-85ba-4611-94b5-2dce1a94b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367922469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1367922469
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1603205319
Short name T410
Test name
Test status
Simulation time 239000687 ps
CPU time 4.23 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:50 PM PDT 24
Peak memory 206428 kb
Host smart-78c9e7b3-0759-413e-8ef9-4ec60fffd41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603205319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1603205319
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.357206082
Short name T944
Test name
Test status
Simulation time 211618135 ps
CPU time 2.65 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:52:47 PM PDT 24
Peak memory 208532 kb
Host smart-ea10fa01-a796-41b3-9fc0-8b3f86c1fe4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357206082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.357206082
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.332375339
Short name T972
Test name
Test status
Simulation time 1115178883 ps
CPU time 11.85 seconds
Started Jun 08 02:52:47 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 207880 kb
Host smart-f8f2dc8c-7a30-4187-ada5-5d9cdf4a9e89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332375339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.332375339
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.328444780
Short name T833
Test name
Test status
Simulation time 233073107 ps
CPU time 6.58 seconds
Started Jun 08 02:52:49 PM PDT 24
Finished Jun 08 02:52:56 PM PDT 24
Peak memory 207816 kb
Host smart-40b00bba-63ec-4236-b79b-02f02ce3bbcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328444780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.328444780
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3491377425
Short name T240
Test name
Test status
Simulation time 165006544 ps
CPU time 2.75 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:52:55 PM PDT 24
Peak memory 214312 kb
Host smart-00b7e468-3a1a-4df7-99e2-cb74b05ec6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491377425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3491377425
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.996979133
Short name T943
Test name
Test status
Simulation time 4739178999 ps
CPU time 24.61 seconds
Started Jun 08 02:52:45 PM PDT 24
Finished Jun 08 02:53:09 PM PDT 24
Peak memory 208600 kb
Host smart-bd5b46c6-b152-4a37-91fe-664b86bd17e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996979133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.996979133
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1465661703
Short name T222
Test name
Test status
Simulation time 9144714641 ps
CPU time 286.33 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:57:39 PM PDT 24
Peak memory 214916 kb
Host smart-75c5a5ee-08a8-42ec-a4e0-8ad67f4e0c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465661703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1465661703
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.4033966914
Short name T957
Test name
Test status
Simulation time 195627171 ps
CPU time 3.93 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:52:56 PM PDT 24
Peak memory 222288 kb
Host smart-2a33cea9-63f9-4c34-81fe-97fc96669f5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033966914 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.4033966914
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3191946374
Short name T841
Test name
Test status
Simulation time 435485740 ps
CPU time 9.13 seconds
Started Jun 08 02:52:50 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 207376 kb
Host smart-2413e100-79e2-488f-acf4-db703257f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191946374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3191946374
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2875641548
Short name T848
Test name
Test status
Simulation time 14595567 ps
CPU time 0.76 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:52:56 PM PDT 24
Peak memory 205580 kb
Host smart-4bf1aca7-3733-4e44-955e-ff419a34f1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875641548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2875641548
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1623634184
Short name T846
Test name
Test status
Simulation time 242652595 ps
CPU time 2.66 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 207816 kb
Host smart-a48ae987-1d96-49eb-9b53-33c0abe9b7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623634184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1623634184
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1963539073
Short name T817
Test name
Test status
Simulation time 323392230 ps
CPU time 5.12 seconds
Started Jun 08 02:52:57 PM PDT 24
Finished Jun 08 02:53:02 PM PDT 24
Peak memory 208744 kb
Host smart-c86546cc-245a-4b14-9304-c72eb53eff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963539073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1963539073
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3388191405
Short name T229
Test name
Test status
Simulation time 448329152 ps
CPU time 20.22 seconds
Started Jun 08 02:52:58 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 222180 kb
Host smart-9b9beb9e-3a72-43d5-ac36-433fcc5ea5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388191405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3388191405
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.677506184
Short name T918
Test name
Test status
Simulation time 107193009 ps
CPU time 4.7 seconds
Started Jun 08 02:52:51 PM PDT 24
Finished Jun 08 02:52:55 PM PDT 24
Peak memory 214052 kb
Host smart-e25ebc6e-958a-4759-afb8-e7062de0dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677506184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.677506184
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3115382646
Short name T111
Test name
Test status
Simulation time 176450825 ps
CPU time 4.47 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:52:57 PM PDT 24
Peak memory 208288 kb
Host smart-691e7c38-7b86-4ce4-83c8-7b7d3eefb1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115382646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3115382646
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2631593540
Short name T318
Test name
Test status
Simulation time 1212247771 ps
CPU time 27.16 seconds
Started Jun 08 02:52:53 PM PDT 24
Finished Jun 08 02:53:20 PM PDT 24
Peak memory 208128 kb
Host smart-7a4e0d18-0ebc-4942-a5c7-490628e8c2ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631593540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2631593540
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2067759753
Short name T715
Test name
Test status
Simulation time 59795058 ps
CPU time 3.18 seconds
Started Jun 08 02:52:53 PM PDT 24
Finished Jun 08 02:52:57 PM PDT 24
Peak memory 206572 kb
Host smart-a564918e-5136-49bc-a345-3a240b28e68f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067759753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2067759753
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4142497212
Short name T593
Test name
Test status
Simulation time 39333397 ps
CPU time 2.77 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:52:55 PM PDT 24
Peak memory 208228 kb
Host smart-5d70bc5b-fb60-4b3e-81cb-39db83eaef6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142497212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4142497212
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.571744822
Short name T202
Test name
Test status
Simulation time 102508081 ps
CPU time 2.83 seconds
Started Jun 08 02:52:55 PM PDT 24
Finished Jun 08 02:52:58 PM PDT 24
Peak memory 209800 kb
Host smart-00bdb25d-a8fd-45a5-8c49-04035e96afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571744822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.571744822
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2399560422
Short name T407
Test name
Test status
Simulation time 3568152188 ps
CPU time 9.5 seconds
Started Jun 08 02:52:52 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 208592 kb
Host smart-59cf3e4a-0df5-40dc-802d-9b0b3cb1709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399560422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2399560422
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.924423414
Short name T262
Test name
Test status
Simulation time 556178773 ps
CPU time 8.7 seconds
Started Jun 08 02:52:53 PM PDT 24
Finished Jun 08 02:53:02 PM PDT 24
Peak memory 220200 kb
Host smart-8bb2bfb7-2763-41a1-b7a9-83d19dee8dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924423414 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.924423414
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.644283299
Short name T820
Test name
Test status
Simulation time 702179300 ps
CPU time 18.45 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:53:15 PM PDT 24
Peak memory 217808 kb
Host smart-3185bb40-0685-45a1-972d-a230560faa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644283299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.644283299
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4030360253
Short name T416
Test name
Test status
Simulation time 58572164 ps
CPU time 2.61 seconds
Started Jun 08 02:52:59 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 209932 kb
Host smart-4cc1afd1-18be-4b4e-ada7-aed7214b5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030360253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4030360253
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2530611280
Short name T673
Test name
Test status
Simulation time 133551099 ps
CPU time 0.97 seconds
Started Jun 08 02:53:04 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 205524 kb
Host smart-1cdb9ffa-6272-496f-bcad-0eb65c9c4247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530611280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2530611280
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.89235230
Short name T289
Test name
Test status
Simulation time 121093857 ps
CPU time 2.58 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 214532 kb
Host smart-7b8992ee-7c1f-4b8f-a899-17c67c3399bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89235230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.89235230
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1687882367
Short name T6
Test name
Test status
Simulation time 494357806 ps
CPU time 3.79 seconds
Started Jun 08 02:52:59 PM PDT 24
Finished Jun 08 02:53:03 PM PDT 24
Peak memory 218360 kb
Host smart-355c223e-22f6-4a21-ac8d-ad72dbbd9898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687882367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1687882367
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2889531517
Short name T605
Test name
Test status
Simulation time 1442010909 ps
CPU time 4.37 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 208472 kb
Host smart-14f471f6-9fe2-48db-a102-06d6a75b8600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889531517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2889531517
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1161340143
Short name T378
Test name
Test status
Simulation time 656201021 ps
CPU time 8.59 seconds
Started Jun 08 02:52:57 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 214032 kb
Host smart-3c17dd7b-e37c-44de-bfd1-a27793a8b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161340143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1161340143
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.622920483
Short name T749
Test name
Test status
Simulation time 96776671 ps
CPU time 4.76 seconds
Started Jun 08 02:52:58 PM PDT 24
Finished Jun 08 02:53:03 PM PDT 24
Peak memory 209612 kb
Host smart-cb0b24e8-8b5b-44e6-a142-60e53e2334eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622920483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.622920483
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3670559847
Short name T909
Test name
Test status
Simulation time 62120986 ps
CPU time 2.4 seconds
Started Jun 08 02:52:58 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 206344 kb
Host smart-8de70ca2-1077-474d-a7e7-a1b836d031a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670559847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3670559847
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.975147031
Short name T711
Test name
Test status
Simulation time 253661941 ps
CPU time 3.15 seconds
Started Jun 08 02:52:55 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 206636 kb
Host smart-d73b6852-f1c1-400d-addd-70f1bf185028
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975147031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.975147031
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4262128539
Short name T966
Test name
Test status
Simulation time 39599965 ps
CPU time 2.76 seconds
Started Jun 08 02:52:56 PM PDT 24
Finished Jun 08 02:52:59 PM PDT 24
Peak memory 208592 kb
Host smart-6c7ad10f-b6a6-4813-9b68-8290a2549f9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262128539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4262128539
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3992798032
Short name T671
Test name
Test status
Simulation time 501256638 ps
CPU time 6.15 seconds
Started Jun 08 02:52:58 PM PDT 24
Finished Jun 08 02:53:04 PM PDT 24
Peak memory 207612 kb
Host smart-787e0f3f-f3ea-48b4-897a-eb931779e072
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992798032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3992798032
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1736141516
Short name T681
Test name
Test status
Simulation time 1788195145 ps
CPU time 13.26 seconds
Started Jun 08 02:53:04 PM PDT 24
Finished Jun 08 02:53:17 PM PDT 24
Peak memory 208672 kb
Host smart-04f6c7ad-745d-456e-9fc4-c9b6317cedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736141516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1736141516
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.193041048
Short name T795
Test name
Test status
Simulation time 27049695 ps
CPU time 2.2 seconds
Started Jun 08 02:52:59 PM PDT 24
Finished Jun 08 02:53:01 PM PDT 24
Peak memory 208388 kb
Host smart-7435e5cb-5443-4337-9c03-f06b86b0c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193041048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.193041048
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.745242117
Short name T83
Test name
Test status
Simulation time 24690906839 ps
CPU time 324.93 seconds
Started Jun 08 02:53:01 PM PDT 24
Finished Jun 08 02:58:26 PM PDT 24
Peak memory 221404 kb
Host smart-4b5b9dda-fb22-4b4f-90e2-37bdb23b6b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745242117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.745242117
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.4070588228
Short name T980
Test name
Test status
Simulation time 192123002 ps
CPU time 5.42 seconds
Started Jun 08 02:53:03 PM PDT 24
Finished Jun 08 02:53:09 PM PDT 24
Peak memory 222412 kb
Host smart-297311e2-8340-4278-b4bb-86f9b0c56261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070588228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.4070588228
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3245368634
Short name T1022
Test name
Test status
Simulation time 153520872 ps
CPU time 3.86 seconds
Started Jun 08 02:52:54 PM PDT 24
Finished Jun 08 02:52:58 PM PDT 24
Peak memory 213996 kb
Host smart-495ad78b-a547-4dee-888a-03c79a712c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245368634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3245368634
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3575757436
Short name T919
Test name
Test status
Simulation time 80759318 ps
CPU time 2.85 seconds
Started Jun 08 02:53:01 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 210188 kb
Host smart-986993be-30b9-4aed-9f48-264ae0eed5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575757436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3575757436
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.786029036
Short name T741
Test name
Test status
Simulation time 11535760 ps
CPU time 0.86 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:14 PM PDT 24
Peak memory 205576 kb
Host smart-d44ed187-8396-4aad-9130-f92eff85817b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786029036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.786029036
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4075184813
Short name T434
Test name
Test status
Simulation time 35479867 ps
CPU time 2.66 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:14 PM PDT 24
Peak memory 214132 kb
Host smart-d4f61d65-6ba0-44a5-9bd0-ac8c9e17a3fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075184813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4075184813
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2327668678
Short name T832
Test name
Test status
Simulation time 665336319 ps
CPU time 9.41 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:21 PM PDT 24
Peak memory 217792 kb
Host smart-cd824113-73ee-46d5-9826-0e82490bc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327668678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2327668678
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.269423804
Short name T113
Test name
Test status
Simulation time 250324159 ps
CPU time 3.33 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:17 PM PDT 24
Peak memory 207452 kb
Host smart-75ba544f-28ca-4e2b-b01f-5eb282b2a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269423804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.269423804
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3047841533
Short name T270
Test name
Test status
Simulation time 1499310334 ps
CPU time 11.06 seconds
Started Jun 08 02:53:12 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 213952 kb
Host smart-bde41ba6-d88a-4428-b376-8098c127c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047841533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3047841533
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1386360001
Short name T666
Test name
Test status
Simulation time 105380390 ps
CPU time 3.38 seconds
Started Jun 08 02:53:10 PM PDT 24
Finished Jun 08 02:53:14 PM PDT 24
Peak memory 218552 kb
Host smart-a958aeb5-1244-4ba4-a61e-193fffee6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386360001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1386360001
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4220036628
Short name T264
Test name
Test status
Simulation time 100572394 ps
CPU time 4.9 seconds
Started Jun 08 02:53:05 PM PDT 24
Finished Jun 08 02:53:10 PM PDT 24
Peak memory 218272 kb
Host smart-a5dda648-cbad-4837-a250-116f46e051b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220036628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4220036628
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3528203444
Short name T327
Test name
Test status
Simulation time 122816520 ps
CPU time 2.37 seconds
Started Jun 08 02:53:01 PM PDT 24
Finished Jun 08 02:53:04 PM PDT 24
Peak memory 207044 kb
Host smart-81a0add7-889f-4961-9413-90b5424b0b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528203444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3528203444
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2817017789
Short name T1023
Test name
Test status
Simulation time 505678088 ps
CPU time 14.27 seconds
Started Jun 08 02:53:02 PM PDT 24
Finished Jun 08 02:53:17 PM PDT 24
Peak memory 208692 kb
Host smart-c7f46e37-fa87-424c-8703-2ce000a5a272
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817017789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2817017789
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.319804138
Short name T819
Test name
Test status
Simulation time 261933168 ps
CPU time 8.12 seconds
Started Jun 08 02:53:03 PM PDT 24
Finished Jun 08 02:53:12 PM PDT 24
Peak memory 206504 kb
Host smart-62241692-0913-4cc0-8751-a6fd07f1a515
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319804138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.319804138
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3221117863
Short name T594
Test name
Test status
Simulation time 349711503 ps
CPU time 5.71 seconds
Started Jun 08 02:52:59 PM PDT 24
Finished Jun 08 02:53:05 PM PDT 24
Peak memory 208384 kb
Host smart-117cba6d-4f4c-45c1-b0af-0828fe47c524
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221117863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3221117863
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3278800052
Short name T201
Test name
Test status
Simulation time 73736916 ps
CPU time 3.46 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:15 PM PDT 24
Peak memory 208108 kb
Host smart-5f57e8e4-b477-4725-97ca-8ebac4b368d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278800052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3278800052
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3980108614
Short name T631
Test name
Test status
Simulation time 630360540 ps
CPU time 4.43 seconds
Started Jun 08 02:53:04 PM PDT 24
Finished Jun 08 02:53:08 PM PDT 24
Peak memory 206900 kb
Host smart-1d09d539-381d-4b8f-8d48-b8b652fa66af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980108614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3980108614
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1199501165
Short name T901
Test name
Test status
Simulation time 112448958 ps
CPU time 2.38 seconds
Started Jun 08 02:53:10 PM PDT 24
Finished Jun 08 02:53:13 PM PDT 24
Peak memory 214148 kb
Host smart-dc4e1eb4-9d07-4444-a842-cd3fb229455b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199501165 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1199501165
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.997380327
Short name T889
Test name
Test status
Simulation time 62243547 ps
CPU time 3.88 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:17 PM PDT 24
Peak memory 209100 kb
Host smart-cb1d73a9-1584-4d30-88cb-c3732c1a1bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997380327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.997380327
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3412983745
Short name T650
Test name
Test status
Simulation time 84274237 ps
CPU time 2.36 seconds
Started Jun 08 02:53:08 PM PDT 24
Finished Jun 08 02:53:11 PM PDT 24
Peak memory 209648 kb
Host smart-72c6d2e9-511d-40f5-a35a-931be4a5b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412983745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3412983745
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2411202175
Short name T803
Test name
Test status
Simulation time 68919384 ps
CPU time 0.79 seconds
Started Jun 08 02:53:12 PM PDT 24
Finished Jun 08 02:53:13 PM PDT 24
Peak memory 205572 kb
Host smart-3941be8e-bb17-46ad-b3cc-dd364884d376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411202175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2411202175
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1726964007
Short name T380
Test name
Test status
Simulation time 220008987 ps
CPU time 4.39 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:16 PM PDT 24
Peak memory 214124 kb
Host smart-59bfd794-fd16-4b7e-9cf1-261425efff36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726964007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1726964007
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1310248887
Short name T39
Test name
Test status
Simulation time 90450089 ps
CPU time 2.09 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:13 PM PDT 24
Peak memory 216308 kb
Host smart-4cd8342f-ca9c-439d-91cf-6290c520cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310248887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1310248887
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1399364463
Short name T80
Test name
Test status
Simulation time 275637431 ps
CPU time 3.15 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:16 PM PDT 24
Peak memory 208256 kb
Host smart-cb99a51c-8291-41d7-8af1-443c0cfcfbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399364463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1399364463
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3229523856
Short name T398
Test name
Test status
Simulation time 538686185 ps
CPU time 5.86 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 219528 kb
Host smart-027d8fca-a02f-4371-94bc-753e5c527f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229523856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3229523856
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2716202500
Short name T1000
Test name
Test status
Simulation time 450830010 ps
CPU time 6.23 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:19 PM PDT 24
Peak memory 209400 kb
Host smart-c59f4a95-bb24-4fca-bdc5-2560356a64c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716202500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2716202500
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.171830188
Short name T946
Test name
Test status
Simulation time 43785996 ps
CPU time 3.54 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:15 PM PDT 24
Peak memory 210176 kb
Host smart-8fd61c17-3dc2-47da-9b82-656f79718a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171830188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.171830188
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2912203577
Short name T881
Test name
Test status
Simulation time 45536693 ps
CPU time 2.33 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:13 PM PDT 24
Peak memory 206964 kb
Host smart-a14a8ac6-24be-4493-a282-eb43b48032b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912203577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2912203577
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1928144935
Short name T992
Test name
Test status
Simulation time 301383875 ps
CPU time 3.35 seconds
Started Jun 08 02:53:07 PM PDT 24
Finished Jun 08 02:53:11 PM PDT 24
Peak memory 208168 kb
Host smart-575ff695-3474-423f-a8f6-1c57558ac204
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928144935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1928144935
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2863843207
Short name T363
Test name
Test status
Simulation time 3107424006 ps
CPU time 37.95 seconds
Started Jun 08 02:53:06 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 208020 kb
Host smart-c35158db-c709-474a-afdb-5db9812c02df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863843207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2863843207
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.828368036
Short name T292
Test name
Test status
Simulation time 724974604 ps
CPU time 7.84 seconds
Started Jun 08 02:53:11 PM PDT 24
Finished Jun 08 02:53:19 PM PDT 24
Peak memory 208304 kb
Host smart-b65691fa-b001-4895-9f8f-8f93729558a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828368036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.828368036
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2294736270
Short name T787
Test name
Test status
Simulation time 150652142 ps
CPU time 3.13 seconds
Started Jun 08 02:53:15 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 215548 kb
Host smart-81102eda-7fcd-44bc-9973-03f8b033ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294736270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2294736270
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2868076159
Short name T973
Test name
Test status
Simulation time 143959631 ps
CPU time 2.3 seconds
Started Jun 08 02:53:08 PM PDT 24
Finished Jun 08 02:53:10 PM PDT 24
Peak memory 206512 kb
Host smart-42f20f0a-f4fc-4a17-b826-fc39fc92a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868076159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2868076159
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1378986344
Short name T693
Test name
Test status
Simulation time 289766339 ps
CPU time 10.64 seconds
Started Jun 08 02:53:12 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 209560 kb
Host smart-0ccbc67e-9861-44aa-adb2-da804739f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378986344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1378986344
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3615433691
Short name T802
Test name
Test status
Simulation time 51011644 ps
CPU time 2.52 seconds
Started Jun 08 02:53:10 PM PDT 24
Finished Jun 08 02:53:12 PM PDT 24
Peak memory 209928 kb
Host smart-40972436-2e33-42ab-af61-42416f5dd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615433691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3615433691
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.4224279608
Short name T929
Test name
Test status
Simulation time 13345741 ps
CPU time 0.76 seconds
Started Jun 08 02:53:19 PM PDT 24
Finished Jun 08 02:53:20 PM PDT 24
Peak memory 205524 kb
Host smart-0792d19b-e276-4300-a249-b5943b1484ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224279608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4224279608
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1404645986
Short name T439
Test name
Test status
Simulation time 8168630833 ps
CPU time 105 seconds
Started Jun 08 02:53:16 PM PDT 24
Finished Jun 08 02:55:01 PM PDT 24
Peak memory 215292 kb
Host smart-eb495ab6-cd20-4556-bc1a-234fd3f30b69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404645986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1404645986
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3215318150
Short name T910
Test name
Test status
Simulation time 640439611 ps
CPU time 3.23 seconds
Started Jun 08 02:53:18 PM PDT 24
Finished Jun 08 02:53:22 PM PDT 24
Peak memory 220780 kb
Host smart-f1a93794-f7b6-490e-9709-0f63f844a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215318150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3215318150
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1629506054
Short name T82
Test name
Test status
Simulation time 526036866 ps
CPU time 2.58 seconds
Started Jun 08 02:53:17 PM PDT 24
Finished Jun 08 02:53:19 PM PDT 24
Peak memory 208616 kb
Host smart-11d39a95-978b-4680-bfa6-39e5bba31861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629506054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1629506054
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2958456702
Short name T928
Test name
Test status
Simulation time 54145783 ps
CPU time 3.35 seconds
Started Jun 08 02:53:14 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 208676 kb
Host smart-e7a86cac-90ff-4339-a487-c6c5de6053bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958456702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2958456702
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3744363114
Short name T298
Test name
Test status
Simulation time 149983923 ps
CPU time 7.25 seconds
Started Jun 08 02:53:16 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 214052 kb
Host smart-748b32a1-8a84-4c22-8f44-a4617f4d7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744363114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3744363114
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.634218141
Short name T87
Test name
Test status
Simulation time 96599379 ps
CPU time 2.44 seconds
Started Jun 08 02:53:19 PM PDT 24
Finished Jun 08 02:53:22 PM PDT 24
Peak memory 207244 kb
Host smart-768a5bcd-6e0c-45b6-a2a7-76d0bb0e45ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634218141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.634218141
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1273370896
Short name T1060
Test name
Test status
Simulation time 98573793 ps
CPU time 4.03 seconds
Started Jun 08 02:53:13 PM PDT 24
Finished Jun 08 02:53:17 PM PDT 24
Peak memory 208268 kb
Host smart-b0801012-473f-4d9a-a4b8-5abb4b04211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273370896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1273370896
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1610969190
Short name T626
Test name
Test status
Simulation time 144548138 ps
CPU time 2.32 seconds
Started Jun 08 02:53:15 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 206628 kb
Host smart-99f30bec-7d17-4e2a-b5b5-946677f9c40d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610969190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1610969190
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3949772210
Short name T876
Test name
Test status
Simulation time 195495562 ps
CPU time 2.45 seconds
Started Jun 08 02:53:10 PM PDT 24
Finished Jun 08 02:53:12 PM PDT 24
Peak memory 208200 kb
Host smart-cb94415c-ed6a-48ff-8018-5d5808c2debd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949772210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3949772210
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1110322346
Short name T615
Test name
Test status
Simulation time 1231567121 ps
CPU time 16.41 seconds
Started Jun 08 02:53:15 PM PDT 24
Finished Jun 08 02:53:32 PM PDT 24
Peak memory 208132 kb
Host smart-ee21164a-d751-4f9b-af94-488d9db16c68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110322346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1110322346
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2823984014
Short name T685
Test name
Test status
Simulation time 349003773 ps
CPU time 10.82 seconds
Started Jun 08 02:53:18 PM PDT 24
Finished Jun 08 02:53:29 PM PDT 24
Peak memory 207972 kb
Host smart-15ed1cc5-1981-4e86-b185-498ff889b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823984014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2823984014
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2100737717
Short name T708
Test name
Test status
Simulation time 80390471 ps
CPU time 1.9 seconds
Started Jun 08 02:53:14 PM PDT 24
Finished Jun 08 02:53:16 PM PDT 24
Peak memory 205756 kb
Host smart-07061969-a93d-4e52-bd03-003641de77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100737717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2100737717
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1663482941
Short name T76
Test name
Test status
Simulation time 144873368 ps
CPU time 6.83 seconds
Started Jun 08 02:53:18 PM PDT 24
Finished Jun 08 02:53:25 PM PDT 24
Peak memory 221968 kb
Host smart-5f9050f2-8e07-4375-bcab-794ced25dc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663482941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1663482941
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1534108339
Short name T413
Test name
Test status
Simulation time 424897694 ps
CPU time 6.88 seconds
Started Jun 08 02:53:16 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 222288 kb
Host smart-2bb16ca1-af25-4c48-9b37-b095c3d984c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534108339 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1534108339
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1098447937
Short name T767
Test name
Test status
Simulation time 529236944 ps
CPU time 5.95 seconds
Started Jun 08 02:53:19 PM PDT 24
Finished Jun 08 02:53:25 PM PDT 24
Peak memory 213952 kb
Host smart-47d63c85-1962-4fb0-b699-9e0f8b33ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098447937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1098447937
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.618004545
Short name T36
Test name
Test status
Simulation time 1409625655 ps
CPU time 4.79 seconds
Started Jun 08 02:53:18 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 210444 kb
Host smart-d8e0d558-5f07-4a92-a54e-a15bf25a0ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618004545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.618004545
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1297228290
Short name T756
Test name
Test status
Simulation time 18594888 ps
CPU time 0.7 seconds
Started Jun 08 02:53:20 PM PDT 24
Finished Jun 08 02:53:21 PM PDT 24
Peak memory 205604 kb
Host smart-ce8bf594-fdbe-4298-97c0-af571d04076b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297228290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1297228290
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2848743708
Short name T986
Test name
Test status
Simulation time 106762637 ps
CPU time 3.98 seconds
Started Jun 08 02:53:22 PM PDT 24
Finished Jun 08 02:53:26 PM PDT 24
Peak memory 214264 kb
Host smart-f87a5838-bce8-43da-b371-b536de43d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848743708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2848743708
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1383233346
Short name T663
Test name
Test status
Simulation time 72037791 ps
CPU time 2.82 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 217924 kb
Host smart-fed2b132-78c2-42a9-b61b-f4199b524877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383233346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1383233346
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1669110032
Short name T256
Test name
Test status
Simulation time 792931692 ps
CPU time 7.42 seconds
Started Jun 08 02:53:22 PM PDT 24
Finished Jun 08 02:53:29 PM PDT 24
Peak memory 222168 kb
Host smart-7ec121f0-1fb2-46bb-becc-5d2d18d0ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669110032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1669110032
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.545971821
Short name T51
Test name
Test status
Simulation time 76800632 ps
CPU time 3.25 seconds
Started Jun 08 02:53:20 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 214916 kb
Host smart-64543c22-96c5-4b7b-a840-2bfeb8c22743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545971821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.545971821
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3824415584
Short name T308
Test name
Test status
Simulation time 49641026309 ps
CPU time 117.02 seconds
Started Jun 08 02:53:17 PM PDT 24
Finished Jun 08 02:55:15 PM PDT 24
Peak memory 208732 kb
Host smart-b4b3f9e1-9dac-4f68-817e-65760e313780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824415584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3824415584
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.726050073
Short name T92
Test name
Test status
Simulation time 1681827524 ps
CPU time 5.31 seconds
Started Jun 08 02:53:20 PM PDT 24
Finished Jun 08 02:53:25 PM PDT 24
Peak memory 208276 kb
Host smart-81af892c-d544-41a9-aa96-2c3a16fecc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726050073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.726050073
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3599160242
Short name T241
Test name
Test status
Simulation time 418817807 ps
CPU time 7.91 seconds
Started Jun 08 02:53:15 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 207600 kb
Host smart-662625b1-4825-42d8-a822-938b0d45156c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599160242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3599160242
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1837481440
Short name T1006
Test name
Test status
Simulation time 7637516250 ps
CPU time 79.17 seconds
Started Jun 08 02:53:16 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 208492 kb
Host smart-8ac06571-29c1-4475-ae3f-26b5bdead509
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837481440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1837481440
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4033787743
Short name T930
Test name
Test status
Simulation time 343478018 ps
CPU time 4.96 seconds
Started Jun 08 02:53:18 PM PDT 24
Finished Jun 08 02:53:23 PM PDT 24
Peak memory 206624 kb
Host smart-86a1b40c-5db4-4859-85e7-55875535f4c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033787743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4033787743
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2459068431
Short name T377
Test name
Test status
Simulation time 125627284 ps
CPU time 2.42 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 218076 kb
Host smart-e73629fe-737c-4a8e-b9a1-010b8344df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459068431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2459068431
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1686659488
Short name T3
Test name
Test status
Simulation time 325590896 ps
CPU time 3.47 seconds
Started Jun 08 02:53:14 PM PDT 24
Finished Jun 08 02:53:18 PM PDT 24
Peak memory 208148 kb
Host smart-72a76c38-7274-4f0f-98e6-9da1a7ef0fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686659488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1686659488
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.46600103
Short name T983
Test name
Test status
Simulation time 546329623 ps
CPU time 10.61 seconds
Started Jun 08 02:53:20 PM PDT 24
Finished Jun 08 02:53:31 PM PDT 24
Peak memory 208580 kb
Host smart-a86a14ea-c9c6-4f21-9087-108d8475d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46600103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.46600103
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1256211003
Short name T737
Test name
Test status
Simulation time 47100635 ps
CPU time 1.94 seconds
Started Jun 08 02:53:24 PM PDT 24
Finished Jun 08 02:53:26 PM PDT 24
Peak memory 209928 kb
Host smart-0bafe2c6-0411-41ff-8d7c-ba198370b1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256211003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1256211003
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3321809689
Short name T922
Test name
Test status
Simulation time 14851335 ps
CPU time 0.8 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:27 PM PDT 24
Peak memory 205588 kb
Host smart-f729973c-60f7-4a2f-b3c4-96f21c2595df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321809689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3321809689
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1819349600
Short name T438
Test name
Test status
Simulation time 359589474 ps
CPU time 5.51 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:33 PM PDT 24
Peak memory 213992 kb
Host smart-23b88b28-7e98-4fb0-b55b-b1bbda387737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819349600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1819349600
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2135876772
Short name T956
Test name
Test status
Simulation time 64218131 ps
CPU time 3.02 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:29 PM PDT 24
Peak memory 207332 kb
Host smart-1ec40d94-0cb6-43ba-a4d6-d1f2b4ac7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135876772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2135876772
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2990836108
Short name T648
Test name
Test status
Simulation time 82740480 ps
CPU time 2.77 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:30 PM PDT 24
Peak memory 209496 kb
Host smart-f6f0e339-15b7-453f-b9f7-694bad3c5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990836108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2990836108
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1277115708
Short name T727
Test name
Test status
Simulation time 281026663 ps
CPU time 3.11 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:29 PM PDT 24
Peak memory 217964 kb
Host smart-6db3e29c-847f-475d-afd9-ad33d52159e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277115708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1277115708
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1638439744
Short name T251
Test name
Test status
Simulation time 42700359 ps
CPU time 3.05 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:29 PM PDT 24
Peak memory 210664 kb
Host smart-3eac6b93-062a-4951-ab58-404b10535b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638439744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1638439744
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2746620837
Short name T936
Test name
Test status
Simulation time 357142819 ps
CPU time 3.2 seconds
Started Jun 08 02:53:30 PM PDT 24
Finished Jun 08 02:53:34 PM PDT 24
Peak memory 214856 kb
Host smart-0158f277-51a5-4a38-afaf-f93b0bedb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746620837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2746620837
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2599948946
Short name T429
Test name
Test status
Simulation time 128972758 ps
CPU time 4.52 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:26 PM PDT 24
Peak memory 208868 kb
Host smart-1d42c74e-562b-466c-ab4a-80fb3db24f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599948946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2599948946
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2379407970
Short name T875
Test name
Test status
Simulation time 88929936 ps
CPU time 2.71 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:24 PM PDT 24
Peak memory 206524 kb
Host smart-72fdbeb1-cf42-4d99-9aa3-4eb3edfd6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379407970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2379407970
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1119886090
Short name T775
Test name
Test status
Simulation time 15714405544 ps
CPU time 35.93 seconds
Started Jun 08 02:53:24 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 208952 kb
Host smart-26d48949-3918-4e82-a801-4cdcafd9f127
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119886090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1119886090
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.223454986
Short name T310
Test name
Test status
Simulation time 87797845 ps
CPU time 2.11 seconds
Started Jun 08 02:53:23 PM PDT 24
Finished Jun 08 02:53:25 PM PDT 24
Peak memory 206832 kb
Host smart-9ad48702-f4b6-4ebb-ae9c-1a0dcd3e9070
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223454986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.223454986
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1963239141
Short name T1062
Test name
Test status
Simulation time 82162726 ps
CPU time 4.13 seconds
Started Jun 08 02:53:21 PM PDT 24
Finished Jun 08 02:53:25 PM PDT 24
Peak memory 208528 kb
Host smart-268fc2b0-940d-48e8-b6ed-7e8cc245d1fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963239141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1963239141
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1660791404
Short name T706
Test name
Test status
Simulation time 165451938 ps
CPU time 3.81 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:31 PM PDT 24
Peak memory 209332 kb
Host smart-45a94d1f-7360-4fb5-8000-8a425350aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660791404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1660791404
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1782209140
Short name T857
Test name
Test status
Simulation time 220868061 ps
CPU time 3.36 seconds
Started Jun 08 02:53:22 PM PDT 24
Finished Jun 08 02:53:26 PM PDT 24
Peak memory 206636 kb
Host smart-45f5d296-8a5c-47c2-b32d-dc2a00418fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782209140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1782209140
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3619536176
Short name T658
Test name
Test status
Simulation time 71036369 ps
CPU time 2.44 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:30 PM PDT 24
Peak memory 207824 kb
Host smart-795c9aa1-fac4-4d93-bc1e-2e67eb3560e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619536176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3619536176
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.974842346
Short name T884
Test name
Test status
Simulation time 142188017 ps
CPU time 8.41 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:35 PM PDT 24
Peak memory 222852 kb
Host smart-5f3fac36-e5c1-4d7d-94cc-738bead0bddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974842346 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.974842346
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3437829637
Short name T831
Test name
Test status
Simulation time 1832224172 ps
CPU time 11.55 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:38 PM PDT 24
Peak memory 208452 kb
Host smart-073c9821-e5b2-45ea-9a2a-8799d18a21a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437829637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3437829637
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2429130281
Short name T61
Test name
Test status
Simulation time 526164162 ps
CPU time 8.17 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:34 PM PDT 24
Peak memory 210580 kb
Host smart-180b40d9-71f3-4cf1-99bf-4d88088cb61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429130281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2429130281
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2105912776
Short name T1049
Test name
Test status
Simulation time 49320725 ps
CPU time 0.9 seconds
Started Jun 08 02:53:30 PM PDT 24
Finished Jun 08 02:53:31 PM PDT 24
Peak memory 205768 kb
Host smart-da23a2cc-7114-4bfb-a9c7-772d451f436b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105912776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2105912776
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2678618306
Short name T955
Test name
Test status
Simulation time 255947704 ps
CPU time 2.7 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:34 PM PDT 24
Peak memory 210136 kb
Host smart-98ffa69a-c7cd-4d61-ba64-035a0f1edb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678618306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2678618306
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2704216669
Short name T682
Test name
Test status
Simulation time 169368428 ps
CPU time 2.25 seconds
Started Jun 08 02:53:30 PM PDT 24
Finished Jun 08 02:53:32 PM PDT 24
Peak memory 207532 kb
Host smart-8f840931-2768-4ed8-8239-c77a0e13d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704216669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2704216669
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2844674421
Short name T815
Test name
Test status
Simulation time 425377616 ps
CPU time 5.04 seconds
Started Jun 08 02:53:33 PM PDT 24
Finished Jun 08 02:53:38 PM PDT 24
Peak memory 218884 kb
Host smart-dc213430-8dfb-4cf6-8309-b6aed374d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844674421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2844674421
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.687605048
Short name T24
Test name
Test status
Simulation time 318094676 ps
CPU time 4.07 seconds
Started Jun 08 02:53:29 PM PDT 24
Finished Jun 08 02:53:33 PM PDT 24
Peak memory 211104 kb
Host smart-1ce78953-c7ba-4848-a0b0-b8b9eadc8588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687605048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.687605048
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2877754236
Short name T231
Test name
Test status
Simulation time 429006532 ps
CPU time 11.1 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:42 PM PDT 24
Peak memory 214000 kb
Host smart-8beebcca-c063-4b8e-bbca-127d38ab61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877754236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2877754236
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4035862108
Short name T669
Test name
Test status
Simulation time 505681114 ps
CPU time 5.97 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:37 PM PDT 24
Peak memory 208684 kb
Host smart-684680ee-ac22-4bbb-a02b-16855c187eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035862108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4035862108
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3117718345
Short name T1016
Test name
Test status
Simulation time 85132528 ps
CPU time 3.57 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:30 PM PDT 24
Peak memory 208236 kb
Host smart-4c0683d6-8df4-4748-ab77-7dc7b74cb887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117718345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3117718345
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2349627534
Short name T371
Test name
Test status
Simulation time 230943998 ps
CPU time 5.41 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:32 PM PDT 24
Peak memory 206568 kb
Host smart-659c57df-d1a2-419f-a18f-e15d6acd2afb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349627534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2349627534
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.887643127
Short name T638
Test name
Test status
Simulation time 63552625 ps
CPU time 2.89 seconds
Started Jun 08 02:53:24 PM PDT 24
Finished Jun 08 02:53:27 PM PDT 24
Peak memory 206596 kb
Host smart-2f140205-adcf-4e73-ab85-696687cc8173
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887643127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.887643127
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3447252395
Short name T961
Test name
Test status
Simulation time 111411673 ps
CPU time 4.23 seconds
Started Jun 08 02:53:27 PM PDT 24
Finished Jun 08 02:53:31 PM PDT 24
Peak memory 208180 kb
Host smart-f9abb4ec-28a2-4b99-9b42-afdd2c847e3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447252395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3447252395
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1416643001
Short name T368
Test name
Test status
Simulation time 107244218 ps
CPU time 4.4 seconds
Started Jun 08 02:53:30 PM PDT 24
Finished Jun 08 02:53:35 PM PDT 24
Peak memory 209092 kb
Host smart-0b3bc362-3979-4817-bbf2-cfff8d20ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416643001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1416643001
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1958798174
Short name T891
Test name
Test status
Simulation time 126481269 ps
CPU time 1.98 seconds
Started Jun 08 02:53:26 PM PDT 24
Finished Jun 08 02:53:28 PM PDT 24
Peak memory 207020 kb
Host smart-2eae9a6d-5064-4c07-8a6d-408a08831ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958798174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1958798174
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2577907126
Short name T263
Test name
Test status
Simulation time 2131301747 ps
CPU time 36.95 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:54:08 PM PDT 24
Peak memory 220992 kb
Host smart-34d087ed-420b-4c93-98e6-8433e329b503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577907126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2577907126
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.57910628
Short name T402
Test name
Test status
Simulation time 1045565008 ps
CPU time 3.13 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:34 PM PDT 24
Peak memory 222356 kb
Host smart-87033c5d-edb0-49e6-b9aa-d3258d0cd7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57910628 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.57910628
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2494792919
Short name T921
Test name
Test status
Simulation time 803062902 ps
CPU time 3.79 seconds
Started Jun 08 02:53:33 PM PDT 24
Finished Jun 08 02:53:37 PM PDT 24
Peak memory 208912 kb
Host smart-2e280a9b-4720-48fc-915f-e42ae7c5f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494792919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2494792919
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2911626906
Short name T704
Test name
Test status
Simulation time 59354899 ps
CPU time 1.87 seconds
Started Jun 08 02:53:29 PM PDT 24
Finished Jun 08 02:53:31 PM PDT 24
Peak memory 209588 kb
Host smart-5c569930-05dd-4a9e-a4bb-9ee4972aaddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911626906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2911626906
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4249662043
Short name T971
Test name
Test status
Simulation time 33384170 ps
CPU time 0.95 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:53:40 PM PDT 24
Peak memory 205772 kb
Host smart-4e3e9129-de35-4431-b9ff-24e54bb16df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249662043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4249662043
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3434407699
Short name T418
Test name
Test status
Simulation time 968600649 ps
CPU time 12.59 seconds
Started Jun 08 02:53:40 PM PDT 24
Finished Jun 08 02:53:53 PM PDT 24
Peak memory 214048 kb
Host smart-8d24c97e-899e-4493-af6d-d5977bbf255a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434407699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3434407699
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.974206155
Short name T937
Test name
Test status
Simulation time 5783891554 ps
CPU time 54.02 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:54:36 PM PDT 24
Peak memory 222396 kb
Host smart-6fb60c5e-f28b-4034-a7ed-0dddefeb39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974206155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.974206155
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2330671549
Short name T657
Test name
Test status
Simulation time 81135090 ps
CPU time 3.84 seconds
Started Jun 08 02:53:38 PM PDT 24
Finished Jun 08 02:53:42 PM PDT 24
Peak memory 208252 kb
Host smart-cd2195a5-73ae-4fcb-86aa-39ca6d0f425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330671549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2330671549
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4147084968
Short name T816
Test name
Test status
Simulation time 187912725 ps
CPU time 4.06 seconds
Started Jun 08 02:53:43 PM PDT 24
Finished Jun 08 02:53:48 PM PDT 24
Peak memory 207948 kb
Host smart-f4d23931-62b7-43db-ac8c-d1d000dae59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147084968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4147084968
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2440514646
Short name T392
Test name
Test status
Simulation time 25915438355 ps
CPU time 118.21 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:55:37 PM PDT 24
Peak memory 230400 kb
Host smart-7d01600d-a55d-4f43-8dd5-23ef62d29730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440514646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2440514646
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1291303962
Short name T430
Test name
Test status
Simulation time 387603041 ps
CPU time 3.98 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:53:43 PM PDT 24
Peak memory 206336 kb
Host smart-45bd8d75-68a7-4c8b-b0e4-90a2604ddbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291303962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1291303962
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2381403463
Short name T935
Test name
Test status
Simulation time 102322167 ps
CPU time 3.95 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:45 PM PDT 24
Peak memory 208956 kb
Host smart-f74acbf5-b2d2-43e3-bf3c-beb6d9f4cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381403463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2381403463
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1204004712
Short name T17
Test name
Test status
Simulation time 2985338127 ps
CPU time 5.81 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:37 PM PDT 24
Peak memory 208392 kb
Host smart-ebf543cb-22f1-4268-acef-867e74aa536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204004712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1204004712
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1953390855
Short name T894
Test name
Test status
Simulation time 1040353430 ps
CPU time 7.68 seconds
Started Jun 08 02:53:31 PM PDT 24
Finished Jun 08 02:53:39 PM PDT 24
Peak memory 208240 kb
Host smart-4cbc5edf-d17f-4d80-afc5-40c1cbd59053
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953390855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1953390855
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3962171297
Short name T825
Test name
Test status
Simulation time 1737137630 ps
CPU time 31.25 seconds
Started Jun 08 02:53:29 PM PDT 24
Finished Jun 08 02:54:01 PM PDT 24
Peak memory 207896 kb
Host smart-d83d9b50-c896-42e1-a242-c6012039c118
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962171297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3962171297
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1402717443
Short name T823
Test name
Test status
Simulation time 121540000 ps
CPU time 2.39 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:43 PM PDT 24
Peak memory 206640 kb
Host smart-20fb7e8d-25ed-4457-9adf-74fd26c38a4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402717443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1402717443
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2168608734
Short name T1034
Test name
Test status
Simulation time 939861827 ps
CPU time 6.1 seconds
Started Jun 08 02:53:38 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 208420 kb
Host smart-90848810-764d-49ef-a71a-31d593fdaaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168608734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2168608734
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4181188688
Short name T573
Test name
Test status
Simulation time 71452752 ps
CPU time 3.11 seconds
Started Jun 08 02:53:32 PM PDT 24
Finished Jun 08 02:53:35 PM PDT 24
Peak memory 207576 kb
Host smart-de612508-9461-46a2-89b8-fae9aace9688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181188688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4181188688
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2631249897
Short name T389
Test name
Test status
Simulation time 215661484 ps
CPU time 10.62 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:52 PM PDT 24
Peak memory 219928 kb
Host smart-ca9865ad-2cc3-40d7-bc8d-0964f10ddf8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631249897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2631249897
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3268230876
Short name T949
Test name
Test status
Simulation time 193722485 ps
CPU time 5.22 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 219636 kb
Host smart-c088a0d2-6d1b-4b41-b183-37f183582ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268230876 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3268230876
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.328959169
Short name T790
Test name
Test status
Simulation time 1764887752 ps
CPU time 28.94 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:54:09 PM PDT 24
Peak memory 207508 kb
Host smart-e94d1b5e-22c4-4faf-b090-bc534c8c7086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328959169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.328959169
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.193249294
Short name T586
Test name
Test status
Simulation time 33553267 ps
CPU time 0.7 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:08 PM PDT 24
Peak memory 205464 kb
Host smart-313a30f6-99da-448a-a824-40facac5a5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193249294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.193249294
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1322600073
Short name T423
Test name
Test status
Simulation time 3279701350 ps
CPU time 86.68 seconds
Started Jun 08 02:51:03 PM PDT 24
Finished Jun 08 02:52:30 PM PDT 24
Peak memory 214920 kb
Host smart-ec98fc74-6571-4028-b7bc-a84198730dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322600073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1322600073
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4030633572
Short name T989
Test name
Test status
Simulation time 39977637 ps
CPU time 1.68 seconds
Started Jun 08 02:51:02 PM PDT 24
Finished Jun 08 02:51:04 PM PDT 24
Peak memory 207200 kb
Host smart-958cb13b-0862-4831-8e97-690c0f51e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030633572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4030633572
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.53922929
Short name T379
Test name
Test status
Simulation time 1334781339 ps
CPU time 21.82 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:33 PM PDT 24
Peak memory 213972 kb
Host smart-e371681c-a5ed-40e4-999a-6ff2e3ae2bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53922929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.53922929
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3013778588
Short name T253
Test name
Test status
Simulation time 708978397 ps
CPU time 12.15 seconds
Started Jun 08 02:51:03 PM PDT 24
Finished Jun 08 02:51:15 PM PDT 24
Peak memory 213988 kb
Host smart-34ffb992-c42e-4669-a50e-6c85133f2138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013778588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3013778588
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3525038778
Short name T219
Test name
Test status
Simulation time 241060977 ps
CPU time 3.13 seconds
Started Jun 08 02:51:02 PM PDT 24
Finished Jun 08 02:51:05 PM PDT 24
Peak memory 219720 kb
Host smart-2362bc46-523c-491e-aa8f-c3a2bf41e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525038778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3525038778
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2155381593
Short name T199
Test name
Test status
Simulation time 1811794635 ps
CPU time 12.13 seconds
Started Jun 08 02:51:04 PM PDT 24
Finished Jun 08 02:51:16 PM PDT 24
Peak memory 208368 kb
Host smart-fac32be0-f0c3-44f2-98c1-2969b415f137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155381593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2155381593
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2632916649
Short name T42
Test name
Test status
Simulation time 3792405217 ps
CPU time 29.15 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:40 PM PDT 24
Peak memory 231788 kb
Host smart-f220424f-0505-45fd-840b-61a437af6b5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632916649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2632916649
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1738357443
Short name T335
Test name
Test status
Simulation time 938656629 ps
CPU time 31.48 seconds
Started Jun 08 02:50:58 PM PDT 24
Finished Jun 08 02:51:30 PM PDT 24
Peak memory 207944 kb
Host smart-73bd6be3-624e-4d21-9c27-854e5e1c6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738357443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1738357443
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3642626294
Short name T205
Test name
Test status
Simulation time 528646078 ps
CPU time 10.92 seconds
Started Jun 08 02:51:05 PM PDT 24
Finished Jun 08 02:51:16 PM PDT 24
Peak memory 207836 kb
Host smart-3335a585-c16f-455d-af6a-c5bc55128266
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642626294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3642626294
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.261497356
Short name T927
Test name
Test status
Simulation time 268613528 ps
CPU time 2.94 seconds
Started Jun 08 02:51:03 PM PDT 24
Finished Jun 08 02:51:06 PM PDT 24
Peak memory 206468 kb
Host smart-414c99d1-2acc-4be0-9ad6-6e9f192a99ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261497356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.261497356
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3399722838
Short name T207
Test name
Test status
Simulation time 3809535236 ps
CPU time 22.85 seconds
Started Jun 08 02:51:03 PM PDT 24
Finished Jun 08 02:51:26 PM PDT 24
Peak memory 208060 kb
Host smart-e78fcc9d-f665-4337-9b78-89e1fa4c1040
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399722838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3399722838
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1285623820
Short name T142
Test name
Test status
Simulation time 1019960477 ps
CPU time 11.36 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:23 PM PDT 24
Peak memory 218252 kb
Host smart-f5643dbe-d324-4c2a-9366-253d56486a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285623820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1285623820
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1778971123
Short name T606
Test name
Test status
Simulation time 72583120 ps
CPU time 2.14 seconds
Started Jun 08 02:50:57 PM PDT 24
Finished Jun 08 02:51:00 PM PDT 24
Peak memory 206380 kb
Host smart-b6d19dda-0f00-4d07-a3ee-2a35ed162c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778971123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1778971123
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.9614824
Short name T358
Test name
Test status
Simulation time 53258204 ps
CPU time 3.43 seconds
Started Jun 08 02:51:01 PM PDT 24
Finished Jun 08 02:51:05 PM PDT 24
Peak memory 207284 kb
Host smart-6d9beea6-1481-466b-a230-c32ee9617d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9614824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.9614824
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3932936835
Short name T847
Test name
Test status
Simulation time 397895672 ps
CPU time 2.32 seconds
Started Jun 08 02:51:03 PM PDT 24
Finished Jun 08 02:51:06 PM PDT 24
Peak memory 209892 kb
Host smart-a76bde81-501e-4ddb-99ea-a3e6e6712452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932936835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3932936835
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.862184575
Short name T687
Test name
Test status
Simulation time 44069813 ps
CPU time 0.95 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:42 PM PDT 24
Peak memory 205568 kb
Host smart-7330febc-4036-4370-93be-5c0e3fcaaf4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862184575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.862184575
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4086581865
Short name T422
Test name
Test status
Simulation time 1254567498 ps
CPU time 15.46 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:57 PM PDT 24
Peak memory 222264 kb
Host smart-082b2f08-2cbc-4d13-be1a-89f2d8104900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086581865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4086581865
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3012853496
Short name T635
Test name
Test status
Simulation time 244308906 ps
CPU time 2.86 seconds
Started Jun 08 02:53:39 PM PDT 24
Finished Jun 08 02:53:42 PM PDT 24
Peak memory 209568 kb
Host smart-182bf7cc-240f-4cc5-8976-297eac2af6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012853496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3012853496
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1838428502
Short name T1
Test name
Test status
Simulation time 41035760 ps
CPU time 2.66 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:53:45 PM PDT 24
Peak memory 217996 kb
Host smart-3d4a581e-a629-4d77-930d-732163a9288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838428502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1838428502
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3478116109
Short name T855
Test name
Test status
Simulation time 92962033 ps
CPU time 4.25 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:45 PM PDT 24
Peak memory 209184 kb
Host smart-fe044048-fbcf-4d77-bac0-b0502f88f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478116109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3478116109
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1089705531
Short name T200
Test name
Test status
Simulation time 97897909 ps
CPU time 4.47 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:45 PM PDT 24
Peak memory 213988 kb
Host smart-408ff6db-5bee-4102-8d7e-5d330c9d4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089705531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1089705531
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.664105804
Short name T665
Test name
Test status
Simulation time 148362114 ps
CPU time 4.51 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:53:46 PM PDT 24
Peak memory 206832 kb
Host smart-e37583ae-fa38-46ae-bb24-fd0e67b5aa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664105804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.664105804
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2417234569
Short name T799
Test name
Test status
Simulation time 3952441561 ps
CPU time 44.76 seconds
Started Jun 08 02:53:43 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 207772 kb
Host smart-8179a8b0-b360-4d26-b6e2-7275effb9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417234569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2417234569
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2286787414
Short name T678
Test name
Test status
Simulation time 8929986354 ps
CPU time 43.07 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 208324 kb
Host smart-e73847b1-a782-4d9a-9af8-c7d74df2457a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286787414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2286787414
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3406752634
Short name T746
Test name
Test status
Simulation time 166103120 ps
CPU time 6.05 seconds
Started Jun 08 02:53:38 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 207604 kb
Host smart-585fe63f-c415-4df9-ac53-83faf17a6e73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406752634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3406752634
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.4179476783
Short name T788
Test name
Test status
Simulation time 395522505 ps
CPU time 6.9 seconds
Started Jun 08 02:53:44 PM PDT 24
Finished Jun 08 02:53:51 PM PDT 24
Peak memory 208468 kb
Host smart-5662daa7-3db5-4cd5-ae27-c44c7f81e8c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179476783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4179476783
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3560264024
Short name T721
Test name
Test status
Simulation time 91453469 ps
CPU time 2.34 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:43 PM PDT 24
Peak memory 208380 kb
Host smart-8e2c16f4-9328-4f47-b212-21ff7c4d172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560264024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3560264024
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.182272992
Short name T926
Test name
Test status
Simulation time 98402056 ps
CPU time 3.87 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:45 PM PDT 24
Peak memory 206432 kb
Host smart-157d6df1-a313-4f2a-aa6d-8eade850c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182272992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.182272992
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2929065304
Short name T954
Test name
Test status
Simulation time 1223121700 ps
CPU time 31.24 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:54:13 PM PDT 24
Peak memory 220332 kb
Host smart-0451dac2-f8c3-45f2-bf7a-78ef6b1deac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929065304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2929065304
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3632517106
Short name T414
Test name
Test status
Simulation time 419920310 ps
CPU time 4.82 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:53:47 PM PDT 24
Peak memory 218172 kb
Host smart-6621879c-0708-4b49-9929-c45c30cc3eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632517106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3632517106
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1621331532
Short name T1053
Test name
Test status
Simulation time 149257551 ps
CPU time 2.44 seconds
Started Jun 08 02:53:41 PM PDT 24
Finished Jun 08 02:53:44 PM PDT 24
Peak memory 210304 kb
Host smart-c2a83e4a-97fd-42c1-8bc5-b0170cb40783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621331532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1621331532
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2558297970
Short name T634
Test name
Test status
Simulation time 27101834 ps
CPU time 0.75 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:52 PM PDT 24
Peak memory 205520 kb
Host smart-8f2d86b3-6ec3-4e3b-8abe-77b2be72d67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558297970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2558297970
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1307846743
Short name T433
Test name
Test status
Simulation time 101302201 ps
CPU time 5.87 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:52 PM PDT 24
Peak memory 214808 kb
Host smart-2b15d0c4-87dd-4417-b342-efa5bbd5bfeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307846743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1307846743
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4245282164
Short name T34
Test name
Test status
Simulation time 587227631 ps
CPU time 7.32 seconds
Started Jun 08 02:53:50 PM PDT 24
Finished Jun 08 02:53:58 PM PDT 24
Peak memory 219580 kb
Host smart-64d6667f-e45a-4d58-8845-3fd9e5af119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245282164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4245282164
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1534252683
Short name T59
Test name
Test status
Simulation time 1150527047 ps
CPU time 7.77 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:54 PM PDT 24
Peak memory 208184 kb
Host smart-4be08135-e326-45e7-92d8-249e5fa735dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534252683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1534252683
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3368495255
Short name T102
Test name
Test status
Simulation time 402564386 ps
CPU time 6.28 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:52 PM PDT 24
Peak memory 208608 kb
Host smart-fe070297-ae02-46c9-82c3-1110b18cdff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368495255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3368495255
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_random.296588404
Short name T309
Test name
Test status
Simulation time 68807005 ps
CPU time 3.43 seconds
Started Jun 08 02:53:47 PM PDT 24
Finished Jun 08 02:53:51 PM PDT 24
Peak memory 208248 kb
Host smart-0ef38fc7-ce62-46fd-92a0-0b653a9f2764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296588404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.296588404
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.44653051
Short name T793
Test name
Test status
Simulation time 230873310 ps
CPU time 3.75 seconds
Started Jun 08 02:53:42 PM PDT 24
Finished Jun 08 02:53:46 PM PDT 24
Peak memory 208364 kb
Host smart-f6eb1441-3665-4e24-9274-d30d0d90bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44653051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.44653051
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1727386602
Short name T1047
Test name
Test status
Simulation time 3424867156 ps
CPU time 64.82 seconds
Started Jun 08 02:53:44 PM PDT 24
Finished Jun 08 02:54:49 PM PDT 24
Peak memory 208152 kb
Host smart-06db03c0-5200-44d4-bef7-d75c1ad919e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727386602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1727386602
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3235194585
Short name T777
Test name
Test status
Simulation time 796173733 ps
CPU time 9.3 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:56 PM PDT 24
Peak memory 207768 kb
Host smart-4a1667e5-7e6d-40c8-a330-b109a451fdc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235194585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3235194585
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1277588435
Short name T690
Test name
Test status
Simulation time 1051844655 ps
CPU time 4.54 seconds
Started Jun 08 02:53:45 PM PDT 24
Finished Jun 08 02:53:50 PM PDT 24
Peak memory 208472 kb
Host smart-d5440871-cf42-4891-bc27-71ff3d8a19cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277588435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1277588435
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3112289155
Short name T835
Test name
Test status
Simulation time 66564762 ps
CPU time 3.06 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:56 PM PDT 24
Peak memory 207716 kb
Host smart-420439f4-6fa0-4a01-a7a0-a6e6532031d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112289155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3112289155
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.884587181
Short name T141
Test name
Test status
Simulation time 110191683 ps
CPU time 2.9 seconds
Started Jun 08 02:53:44 PM PDT 24
Finished Jun 08 02:53:47 PM PDT 24
Peak memory 206556 kb
Host smart-d75c78f4-6c06-4956-9035-20394c927b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884587181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.884587181
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1549465096
Short name T223
Test name
Test status
Simulation time 651916657 ps
CPU time 9.83 seconds
Started Jun 08 02:53:49 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 222364 kb
Host smart-f192e881-98bc-4809-ac21-4baa3c9e928a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549465096 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1549465096
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3256358182
Short name T280
Test name
Test status
Simulation time 281107599 ps
CPU time 6.45 seconds
Started Jun 08 02:53:46 PM PDT 24
Finished Jun 08 02:53:53 PM PDT 24
Peak memory 222216 kb
Host smart-411b0e0d-9c5b-4a51-9467-f41eac96793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256358182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3256358182
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4092685646
Short name T613
Test name
Test status
Simulation time 324178569 ps
CPU time 3.56 seconds
Started Jun 08 02:53:50 PM PDT 24
Finished Jun 08 02:53:53 PM PDT 24
Peak memory 210608 kb
Host smart-d8bf4d9e-96d6-4c68-89c6-58809e6a7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092685646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4092685646
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.352452428
Short name T588
Test name
Test status
Simulation time 29421422 ps
CPU time 0.78 seconds
Started Jun 08 02:53:58 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 205596 kb
Host smart-0ed99c43-d49f-4ad4-b2a3-65e58eb39bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352452428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.352452428
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4132270311
Short name T840
Test name
Test status
Simulation time 1005189763 ps
CPU time 3.8 seconds
Started Jun 08 02:53:53 PM PDT 24
Finished Jun 08 02:53:57 PM PDT 24
Peak memory 215704 kb
Host smart-26ff6cf5-fd38-4768-b1b1-1fe29925ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132270311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4132270311
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2373717682
Short name T976
Test name
Test status
Simulation time 581663466 ps
CPU time 4.37 seconds
Started Jun 08 02:53:53 PM PDT 24
Finished Jun 08 02:53:58 PM PDT 24
Peak memory 208536 kb
Host smart-251faff3-adde-4c31-acee-16d0ea3e412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373717682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2373717682
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2223639206
Short name T643
Test name
Test status
Simulation time 343556216 ps
CPU time 7.91 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 219988 kb
Host smart-961919cb-84d8-442e-b28d-e7660e1d2b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223639206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2223639206
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1688350022
Short name T88
Test name
Test status
Simulation time 242343037 ps
CPU time 10.56 seconds
Started Jun 08 02:53:48 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 215044 kb
Host smart-d4770b7a-f4c1-44e9-bd24-ee6c3499688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688350022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1688350022
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1580014807
Short name T1043
Test name
Test status
Simulation time 82529514 ps
CPU time 2.63 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:54 PM PDT 24
Peak memory 209440 kb
Host smart-298f5ea0-c360-4e29-9898-00a6cfc4bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580014807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1580014807
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3064702197
Short name T112
Test name
Test status
Simulation time 130157877 ps
CPU time 5.6 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:58 PM PDT 24
Peak memory 209864 kb
Host smart-5a3240fb-e587-4784-bfa3-5d8b340c226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064702197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3064702197
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4238255944
Short name T725
Test name
Test status
Simulation time 51406585 ps
CPU time 2.68 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:55 PM PDT 24
Peak memory 206544 kb
Host smart-ee38aca3-07e1-4162-a63b-9243234316f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238255944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4238255944
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.344588284
Short name T349
Test name
Test status
Simulation time 51284422 ps
CPU time 2.76 seconds
Started Jun 08 02:53:53 PM PDT 24
Finished Jun 08 02:53:55 PM PDT 24
Peak memory 206720 kb
Host smart-ce468753-8674-42d4-95ab-3da585bf7f4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344588284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.344588284
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3917671603
Short name T619
Test name
Test status
Simulation time 55873333 ps
CPU time 2.99 seconds
Started Jun 08 02:53:51 PM PDT 24
Finished Jun 08 02:53:54 PM PDT 24
Peak memory 206536 kb
Host smart-bf2b8b7e-b841-49fb-8356-02ca60d6a7a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917671603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3917671603
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3742949475
Short name T1052
Test name
Test status
Simulation time 624501151 ps
CPU time 3.36 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:53:56 PM PDT 24
Peak memory 206504 kb
Host smart-8f10bb9e-9b99-4a14-bbdb-ed63b9cf7eb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742949475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3742949475
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.781225771
Short name T441
Test name
Test status
Simulation time 1573649252 ps
CPU time 23.26 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:54:16 PM PDT 24
Peak memory 214028 kb
Host smart-f69c5e1d-bcfb-437d-86df-a29299321aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781225771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.781225771
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2749603262
Short name T764
Test name
Test status
Simulation time 560164542 ps
CPU time 3.28 seconds
Started Jun 08 02:53:50 PM PDT 24
Finished Jun 08 02:53:53 PM PDT 24
Peak memory 207696 kb
Host smart-a6ba89f0-3ab8-4875-a97d-1426e9cef687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749603262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2749603262
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3028486050
Short name T753
Test name
Test status
Simulation time 455129830 ps
CPU time 9.37 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 215664 kb
Host smart-4b7703a8-2088-4016-9ad4-9e9a0ee6cd6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028486050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3028486050
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1032103289
Short name T400
Test name
Test status
Simulation time 206032478 ps
CPU time 8.96 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 222368 kb
Host smart-f61fb276-d965-4f27-9738-d76abe5031c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032103289 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1032103289
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4274921356
Short name T331
Test name
Test status
Simulation time 1083984602 ps
CPU time 7.26 seconds
Started Jun 08 02:53:52 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 218060 kb
Host smart-33e0dfe7-728a-4578-83b2-0cd7dc22291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274921356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4274921356
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1226109498
Short name T417
Test name
Test status
Simulation time 89417455 ps
CPU time 1.71 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:53:58 PM PDT 24
Peak memory 209780 kb
Host smart-39977c26-b813-49f1-87d0-691ff35d2a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226109498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1226109498
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2889207303
Short name T442
Test name
Test status
Simulation time 146490886 ps
CPU time 0.82 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:53:57 PM PDT 24
Peak memory 205584 kb
Host smart-8a988abf-782e-4372-affb-b5b20d74fd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889207303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2889207303
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1558775589
Short name T942
Test name
Test status
Simulation time 107277173 ps
CPU time 3.3 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 220956 kb
Host smart-bfea7a8f-8313-4b42-b96d-25abf7a5df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558775589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1558775589
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3037112339
Short name T2
Test name
Test status
Simulation time 54181918 ps
CPU time 2.25 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 214020 kb
Host smart-6ade7d07-7c14-4cbd-b733-88b81db19858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037112339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3037112339
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.97059647
Short name T46
Test name
Test status
Simulation time 624304677 ps
CPU time 3.65 seconds
Started Jun 08 02:53:59 PM PDT 24
Finished Jun 08 02:54:03 PM PDT 24
Peak memory 214040 kb
Host smart-51f3462c-eeb2-4203-abc4-4af7f8a303e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97059647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.97059647
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.805073599
Short name T186
Test name
Test status
Simulation time 96916989 ps
CPU time 4.58 seconds
Started Jun 08 02:53:55 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 206952 kb
Host smart-e3f6d965-639a-4d09-b87d-b794efeb3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805073599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.805073599
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2565022676
Short name T695
Test name
Test status
Simulation time 243940857 ps
CPU time 3.08 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:00 PM PDT 24
Peak memory 206576 kb
Host smart-68d9ca33-522f-4f46-b66b-da22d0c7dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565022676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2565022676
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3072844995
Short name T415
Test name
Test status
Simulation time 204245948 ps
CPU time 2.95 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 206564 kb
Host smart-2e70c33f-7642-4010-b8b0-5a8503b505bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072844995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3072844995
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3527594164
Short name T406
Test name
Test status
Simulation time 1520475933 ps
CPU time 33.11 seconds
Started Jun 08 02:53:58 PM PDT 24
Finished Jun 08 02:54:31 PM PDT 24
Peak memory 207708 kb
Host smart-d72196d0-2a54-461f-8a77-bf5b894686c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527594164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3527594164
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3712019053
Short name T852
Test name
Test status
Simulation time 1791056768 ps
CPU time 27.74 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 208224 kb
Host smart-a50252a8-7697-4fbd-9d1c-46a065465dd9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712019053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3712019053
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.986958860
Short name T288
Test name
Test status
Simulation time 1954627107 ps
CPU time 12.59 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:10 PM PDT 24
Peak memory 209760 kb
Host smart-db88fce0-8428-40bc-8402-a90b870a7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986958860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.986958860
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.432769459
Short name T1048
Test name
Test status
Simulation time 251742903 ps
CPU time 3.58 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:01 PM PDT 24
Peak memory 208000 kb
Host smart-520ff44d-d59d-40b5-ba71-7c9b7620f6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432769459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.432769459
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1754067555
Short name T1031
Test name
Test status
Simulation time 992046026 ps
CPU time 3.58 seconds
Started Jun 08 02:53:57 PM PDT 24
Finished Jun 08 02:54:01 PM PDT 24
Peak memory 217232 kb
Host smart-62c4d2b8-3a3c-4d16-b7e6-1eb3532a5858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754067555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1754067555
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4027858389
Short name T811
Test name
Test status
Simulation time 385592991 ps
CPU time 10.95 seconds
Started Jun 08 02:53:55 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 206948 kb
Host smart-7a2bed86-6866-458c-8173-1a1cff11111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027858389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4027858389
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2435836431
Short name T64
Test name
Test status
Simulation time 119802117 ps
CPU time 2.88 seconds
Started Jun 08 02:53:56 PM PDT 24
Finished Jun 08 02:53:59 PM PDT 24
Peak memory 209384 kb
Host smart-5960678a-435e-430a-8edb-27f93f884de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435836431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2435836431
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4151506890
Short name T755
Test name
Test status
Simulation time 23202592 ps
CPU time 0.75 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:02 PM PDT 24
Peak memory 205572 kb
Host smart-5d277a8b-5e11-4d08-ab59-c1e147b20a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151506890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4151506890
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.460248757
Short name T387
Test name
Test status
Simulation time 27339441 ps
CPU time 2.02 seconds
Started Jun 08 02:54:03 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 216144 kb
Host smart-74f73a43-5e04-4286-a46d-5f0d42bd3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460248757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.460248757
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2989265105
Short name T888
Test name
Test status
Simulation time 368911982 ps
CPU time 5.35 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:07 PM PDT 24
Peak memory 208964 kb
Host smart-362e43e8-75fc-4045-aae7-5ad6092c3578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989265105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2989265105
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.466824255
Short name T732
Test name
Test status
Simulation time 137683511 ps
CPU time 3.12 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:04 PM PDT 24
Peak memory 209464 kb
Host smart-4cb6f799-5c1e-4650-9a07-2afcfeb32595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466824255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.466824255
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.84559313
Short name T195
Test name
Test status
Simulation time 549505348 ps
CPU time 4.92 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 222172 kb
Host smart-ea44854f-abeb-412a-a520-5c3e08104922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84559313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.84559313
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.621611099
Short name T932
Test name
Test status
Simulation time 162255711 ps
CPU time 4.78 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 207856 kb
Host smart-a2827629-6deb-45f5-9f44-d2be2c0b7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621611099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.621611099
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2650741761
Short name T917
Test name
Test status
Simulation time 15638296259 ps
CPU time 55.52 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:58 PM PDT 24
Peak memory 208540 kb
Host smart-c27be283-aa7f-4159-ba70-e023a98010d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650741761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2650741761
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2913278348
Short name T302
Test name
Test status
Simulation time 325749233 ps
CPU time 2.85 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:04 PM PDT 24
Peak memory 208404 kb
Host smart-5eaf3060-191c-47a5-90a4-0b910a7ea7df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913278348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2913278348
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3458077678
Short name T783
Test name
Test status
Simulation time 163072332 ps
CPU time 2.5 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:05 PM PDT 24
Peak memory 206568 kb
Host smart-c260d658-948b-41e0-8d3e-9482e62dec55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458077678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3458077678
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1820751586
Short name T652
Test name
Test status
Simulation time 77448923 ps
CPU time 1.63 seconds
Started Jun 08 02:53:59 PM PDT 24
Finished Jun 08 02:54:01 PM PDT 24
Peak memory 215164 kb
Host smart-3b3a725a-f6f9-4eb5-b9ed-6acbadf4faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820751586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1820751586
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1296725799
Short name T686
Test name
Test status
Simulation time 1208266907 ps
CPU time 14.3 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:16 PM PDT 24
Peak memory 207924 kb
Host smart-eb5d97a5-3a42-4eca-8367-5b6f1a706bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296725799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1296725799
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3564876227
Short name T225
Test name
Test status
Simulation time 439658030 ps
CPU time 19.29 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:22 PM PDT 24
Peak memory 215888 kb
Host smart-041957c3-fcda-4286-8bd7-6557d2cf2c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564876227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3564876227
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1766039615
Short name T226
Test name
Test status
Simulation time 304263948 ps
CPU time 13.75 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:13 PM PDT 24
Peak memory 222348 kb
Host smart-bd28270c-adab-4079-a83e-e24e2de0ed33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766039615 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1766039615
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.733071156
Short name T871
Test name
Test status
Simulation time 244976143 ps
CPU time 4.45 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:06 PM PDT 24
Peak memory 217888 kb
Host smart-7ca94734-35c2-4626-bdc8-f8e9993a23be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733071156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.733071156
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1315149355
Short name T616
Test name
Test status
Simulation time 24853262 ps
CPU time 1.56 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:01 PM PDT 24
Peak memory 209636 kb
Host smart-90a46c15-6823-42ec-8e23-46cd2fc70c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315149355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1315149355
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.397412551
Short name T859
Test name
Test status
Simulation time 14129460 ps
CPU time 0.9 seconds
Started Jun 08 02:54:06 PM PDT 24
Finished Jun 08 02:54:07 PM PDT 24
Peak memory 205596 kb
Host smart-edc79776-81ff-4097-9e5b-ebd04d6b835b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397412551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.397412551
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3501897836
Short name T234
Test name
Test status
Simulation time 2275584544 ps
CPU time 58.75 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:59 PM PDT 24
Peak memory 215060 kb
Host smart-430705c7-1f44-48f3-a2e0-cfa443981a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501897836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3501897836
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2675454250
Short name T9
Test name
Test status
Simulation time 288981759 ps
CPU time 3.46 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:09 PM PDT 24
Peak memory 209704 kb
Host smart-63ae260f-2908-420d-836a-4fbcb77295f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675454250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2675454250
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3153207562
Short name T372
Test name
Test status
Simulation time 78752925 ps
CPU time 4.02 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:04 PM PDT 24
Peak memory 208916 kb
Host smart-ae58eea2-be74-454e-8b54-7451542eaa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153207562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3153207562
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1839849188
Short name T336
Test name
Test status
Simulation time 230674751 ps
CPU time 10.43 seconds
Started Jun 08 02:54:07 PM PDT 24
Finished Jun 08 02:54:18 PM PDT 24
Peak memory 222372 kb
Host smart-4f1bebbd-8913-4e6b-b80b-42cfc12bed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839849188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1839849188
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3543799379
Short name T620
Test name
Test status
Simulation time 63238841 ps
CPU time 2.63 seconds
Started Jun 08 02:54:06 PM PDT 24
Finished Jun 08 02:54:09 PM PDT 24
Peak memory 219748 kb
Host smart-74bd231b-e4b4-46b7-b23e-3b906015f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543799379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3543799379
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.700543040
Short name T1056
Test name
Test status
Simulation time 4221892657 ps
CPU time 39.06 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:40 PM PDT 24
Peak memory 209476 kb
Host smart-1694ee60-c5d6-46ad-9384-0570d431abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700543040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.700543040
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1235887979
Short name T603
Test name
Test status
Simulation time 2334806238 ps
CPU time 16.13 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:18 PM PDT 24
Peak memory 207816 kb
Host smart-4366e64d-de86-43d0-8fd8-1481ad3fe101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235887979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1235887979
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1918263654
Short name T941
Test name
Test status
Simulation time 512595163 ps
CPU time 6.49 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:09 PM PDT 24
Peak memory 206596 kb
Host smart-86118158-debb-4968-887c-1abe634f077e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918263654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1918263654
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3236645363
Short name T907
Test name
Test status
Simulation time 44235942 ps
CPU time 2.87 seconds
Started Jun 08 02:54:00 PM PDT 24
Finished Jun 08 02:54:03 PM PDT 24
Peak memory 208524 kb
Host smart-54d08bd1-f86f-4bb8-a8f1-4e8df4641a70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236645363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3236645363
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3364076352
Short name T1037
Test name
Test status
Simulation time 3105056383 ps
CPU time 41.21 seconds
Started Jun 08 02:54:02 PM PDT 24
Finished Jun 08 02:54:44 PM PDT 24
Peak memory 208144 kb
Host smart-923450f4-8ca1-4394-a8af-c2bf09f47134
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364076352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3364076352
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3337321902
Short name T707
Test name
Test status
Simulation time 165794924 ps
CPU time 5.03 seconds
Started Jun 08 02:54:07 PM PDT 24
Finished Jun 08 02:54:12 PM PDT 24
Peak memory 209052 kb
Host smart-07c5196a-4396-47f6-b989-ca52cbf02dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337321902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3337321902
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2722785018
Short name T577
Test name
Test status
Simulation time 78168747 ps
CPU time 1.71 seconds
Started Jun 08 02:54:01 PM PDT 24
Finished Jun 08 02:54:03 PM PDT 24
Peak memory 206324 kb
Host smart-48b1e2c4-b146-49ee-a264-56d722dbd8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722785018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2722785018
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4268545612
Short name T405
Test name
Test status
Simulation time 1496693178 ps
CPU time 8.11 seconds
Started Jun 08 02:54:04 PM PDT 24
Finished Jun 08 02:54:12 PM PDT 24
Peak memory 206552 kb
Host smart-19298501-28f4-4eb2-92fa-3afc2884d02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268545612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4268545612
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.425686354
Short name T54
Test name
Test status
Simulation time 428116567 ps
CPU time 4.24 seconds
Started Jun 08 02:54:09 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 222340 kb
Host smart-2cc125d7-0fa3-45a2-b056-6f169feace2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425686354 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.425686354
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2823814451
Short name T324
Test name
Test status
Simulation time 255855897 ps
CPU time 8.94 seconds
Started Jun 08 02:54:06 PM PDT 24
Finished Jun 08 02:54:15 PM PDT 24
Peak memory 213944 kb
Host smart-48510b80-a54d-42fc-a073-b37c99d24171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823814451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2823814451
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3696113851
Short name T667
Test name
Test status
Simulation time 250731133 ps
CPU time 7.86 seconds
Started Jun 08 02:54:07 PM PDT 24
Finished Jun 08 02:54:16 PM PDT 24
Peak memory 210104 kb
Host smart-f6c6f7a3-c9fb-4788-b6cc-50270fa3a587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696113851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3696113851
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3361012701
Short name T916
Test name
Test status
Simulation time 75063039 ps
CPU time 0.93 seconds
Started Jun 08 02:54:13 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 205604 kb
Host smart-2ca9f52d-a251-4742-8949-c0c834d0aa87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361012701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3361012701
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3393409997
Short name T359
Test name
Test status
Simulation time 77441048 ps
CPU time 3.31 seconds
Started Jun 08 02:54:04 PM PDT 24
Finished Jun 08 02:54:07 PM PDT 24
Peak memory 214072 kb
Host smart-218ff169-7378-4a5d-abcd-48c5edab4f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393409997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3393409997
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2630243107
Short name T30
Test name
Test status
Simulation time 66967175 ps
CPU time 3.22 seconds
Started Jun 08 02:54:10 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 213932 kb
Host smart-3ddebe7a-916e-461a-a4eb-94ec600a6ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630243107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2630243107
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2252721031
Short name T79
Test name
Test status
Simulation time 72095613 ps
CPU time 3.52 seconds
Started Jun 08 02:54:04 PM PDT 24
Finished Jun 08 02:54:07 PM PDT 24
Peak memory 218144 kb
Host smart-be32473e-4168-4006-99d4-23a828a8123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252721031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2252721031
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1509972037
Short name T250
Test name
Test status
Simulation time 157456283 ps
CPU time 6.59 seconds
Started Jun 08 02:54:11 PM PDT 24
Finished Jun 08 02:54:18 PM PDT 24
Peak memory 213976 kb
Host smart-009a1c64-44a1-4702-9cb0-f95e73d52ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509972037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1509972037
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1058352489
Short name T341
Test name
Test status
Simulation time 78489514 ps
CPU time 3.17 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:09 PM PDT 24
Peak memory 209860 kb
Host smart-a003b66d-3920-4db3-b8ff-77d422f4e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058352489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1058352489
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3383745333
Short name T860
Test name
Test status
Simulation time 259185968 ps
CPU time 4.58 seconds
Started Jun 08 02:54:06 PM PDT 24
Finished Jun 08 02:54:10 PM PDT 24
Peak memory 213976 kb
Host smart-ea7fa8eb-306f-4f4a-97fe-8001cc1e164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383745333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3383745333
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1351087503
Short name T754
Test name
Test status
Simulation time 32956999 ps
CPU time 2.36 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:08 PM PDT 24
Peak memory 206540 kb
Host smart-7a9661b3-02e5-4613-913c-4849f0502aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351087503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1351087503
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2813725035
Short name T677
Test name
Test status
Simulation time 294828133 ps
CPU time 7.59 seconds
Started Jun 08 02:54:06 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 208344 kb
Host smart-04c41c70-b60f-4900-806e-55c368df42e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813725035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2813725035
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3814120822
Short name T879
Test name
Test status
Simulation time 28704055 ps
CPU time 2.09 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:07 PM PDT 24
Peak memory 208064 kb
Host smart-ac1425a7-7f98-4d62-80b2-a7f1daf0e0ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814120822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3814120822
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.103122966
Short name T939
Test name
Test status
Simulation time 150691540 ps
CPU time 3.07 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:08 PM PDT 24
Peak memory 206500 kb
Host smart-87b078ed-f39e-44f2-914a-9fded747744b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103122966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.103122966
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2635332754
Short name T796
Test name
Test status
Simulation time 332869084 ps
CPU time 2.95 seconds
Started Jun 08 02:54:11 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 215684 kb
Host smart-f56e7b9a-7d4c-45f9-bbb9-d2db751cfc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635332754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2635332754
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.907940049
Short name T618
Test name
Test status
Simulation time 38683816 ps
CPU time 2.58 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:08 PM PDT 24
Peak memory 208300 kb
Host smart-507fc739-2e9c-4b0e-99c0-d67a9fd9430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907940049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.907940049
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2242979166
Short name T996
Test name
Test status
Simulation time 325944743 ps
CPU time 9.8 seconds
Started Jun 08 02:54:11 PM PDT 24
Finished Jun 08 02:54:21 PM PDT 24
Peak memory 223004 kb
Host smart-78717d63-d201-4c84-8de6-0c1647168cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242979166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2242979166
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.265816702
Short name T998
Test name
Test status
Simulation time 164623873 ps
CPU time 5.52 seconds
Started Jun 08 02:54:05 PM PDT 24
Finished Jun 08 02:54:11 PM PDT 24
Peak memory 209460 kb
Host smart-69af24f1-557a-4db7-a2fe-230ac32d5d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265816702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.265816702
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.209605680
Short name T624
Test name
Test status
Simulation time 131562697 ps
CPU time 3.11 seconds
Started Jun 08 02:54:11 PM PDT 24
Finished Jun 08 02:54:14 PM PDT 24
Peak memory 209932 kb
Host smart-87880082-a69d-481a-8210-17614982e32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209605680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.209605680
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.715357274
Short name T627
Test name
Test status
Simulation time 42743423 ps
CPU time 0.72 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:21 PM PDT 24
Peak memory 205492 kb
Host smart-a3fc44ad-dc62-4682-bce4-98755d2c59eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715357274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.715357274
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.761790408
Short name T702
Test name
Test status
Simulation time 133708064 ps
CPU time 5.39 seconds
Started Jun 08 02:54:19 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 208860 kb
Host smart-84ded4a8-0707-4f0f-9111-e69ac6db6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761790408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.761790408
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.29302388
Short name T612
Test name
Test status
Simulation time 320620080 ps
CPU time 4.06 seconds
Started Jun 08 02:54:16 PM PDT 24
Finished Jun 08 02:54:20 PM PDT 24
Peak memory 222192 kb
Host smart-b1bf1a43-b45f-45e5-91f9-84065fdf2487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29302388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.29302388
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2267041572
Short name T675
Test name
Test status
Simulation time 789216072 ps
CPU time 3.87 seconds
Started Jun 08 02:54:14 PM PDT 24
Finished Jun 08 02:54:18 PM PDT 24
Peak memory 208232 kb
Host smart-b130e55f-b8dc-4127-8d3d-e542c0c5dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267041572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2267041572
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2159090048
Short name T913
Test name
Test status
Simulation time 157990025 ps
CPU time 4.37 seconds
Started Jun 08 02:54:17 PM PDT 24
Finished Jun 08 02:54:21 PM PDT 24
Peak memory 214736 kb
Host smart-16e9309b-a1d0-4d30-a64d-d42eae6f9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159090048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2159090048
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2003387272
Short name T934
Test name
Test status
Simulation time 1546479565 ps
CPU time 11.42 seconds
Started Jun 08 02:54:16 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 207632 kb
Host smart-731dfa5a-a91e-486f-85da-3e880998762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003387272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2003387272
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2274385898
Short name T733
Test name
Test status
Simulation time 57395378 ps
CPU time 2.77 seconds
Started Jun 08 02:54:10 PM PDT 24
Finished Jun 08 02:54:13 PM PDT 24
Peak memory 206568 kb
Host smart-e2dd6b83-eeaf-41f4-aa6e-08321ca805fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274385898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2274385898
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3060730106
Short name T697
Test name
Test status
Simulation time 142808376 ps
CPU time 2.66 seconds
Started Jun 08 02:54:10 PM PDT 24
Finished Jun 08 02:54:13 PM PDT 24
Peak memory 208400 kb
Host smart-03f9f4bd-6f56-4858-b7bb-0c65af7f1d08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060730106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3060730106
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2093818616
Short name T580
Test name
Test status
Simulation time 45607696 ps
CPU time 2.57 seconds
Started Jun 08 02:54:12 PM PDT 24
Finished Jun 08 02:54:15 PM PDT 24
Peak memory 206436 kb
Host smart-d57bffda-84dc-4552-ba0f-393f87010d7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093818616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2093818616
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2179746209
Short name T293
Test name
Test status
Simulation time 49728044 ps
CPU time 2.68 seconds
Started Jun 08 02:54:14 PM PDT 24
Finished Jun 08 02:54:17 PM PDT 24
Peak memory 206584 kb
Host smart-079aeb10-6f27-4f46-9bad-e63159af2f97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179746209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2179746209
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2254834636
Short name T778
Test name
Test status
Simulation time 87474393 ps
CPU time 1.73 seconds
Started Jun 08 02:54:23 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 215412 kb
Host smart-c207098f-38e2-4e55-9850-c0667c3b50a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254834636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2254834636
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2328207593
Short name T115
Test name
Test status
Simulation time 129535972 ps
CPU time 2.73 seconds
Started Jun 08 02:54:12 PM PDT 24
Finished Jun 08 02:54:15 PM PDT 24
Peak memory 208236 kb
Host smart-1f7c03fc-5947-4afc-98fe-91057bc9c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328207593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2328207593
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2592565937
Short name T68
Test name
Test status
Simulation time 520333148 ps
CPU time 8.62 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:30 PM PDT 24
Peak memory 215436 kb
Host smart-432b455e-805f-4f2e-ab5a-00a219352ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592565937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2592565937
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2192623480
Short name T592
Test name
Test status
Simulation time 90920959 ps
CPU time 3.67 seconds
Started Jun 08 02:54:22 PM PDT 24
Finished Jun 08 02:54:26 PM PDT 24
Peak memory 221648 kb
Host smart-f00f0569-aef9-4df8-846b-6104193a2594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192623480 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2192623480
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3169760403
Short name T611
Test name
Test status
Simulation time 118431736 ps
CPU time 2.45 seconds
Started Jun 08 02:54:17 PM PDT 24
Finished Jun 08 02:54:20 PM PDT 24
Peak memory 207288 kb
Host smart-cab3d1fc-7524-4e37-bf42-54559dbcde75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169760403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3169760403
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2104602694
Short name T65
Test name
Test status
Simulation time 259246366 ps
CPU time 4.23 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 210204 kb
Host smart-f66f56b4-d543-4e60-ab47-f9650a0fadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104602694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2104602694
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4272764524
Short name T1020
Test name
Test status
Simulation time 22948421 ps
CPU time 0.69 seconds
Started Jun 08 02:54:23 PM PDT 24
Finished Jun 08 02:54:24 PM PDT 24
Peak memory 205556 kb
Host smart-b3375a4d-f238-4450-af9f-c2758807c6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272764524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4272764524
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3207611413
Short name T283
Test name
Test status
Simulation time 777238903 ps
CPU time 10.33 seconds
Started Jun 08 02:54:19 PM PDT 24
Finished Jun 08 02:54:30 PM PDT 24
Peak memory 214960 kb
Host smart-017d0edf-37b3-4f3c-b09b-ab41c8f43d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207611413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3207611413
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1864629478
Short name T431
Test name
Test status
Simulation time 2024662819 ps
CPU time 7.05 seconds
Started Jun 08 02:54:22 PM PDT 24
Finished Jun 08 02:54:29 PM PDT 24
Peak memory 213960 kb
Host smart-a204e6ff-c61f-434d-abc0-b16af862f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864629478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1864629478
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1512927687
Short name T269
Test name
Test status
Simulation time 410227693 ps
CPU time 4.69 seconds
Started Jun 08 02:54:23 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 213988 kb
Host smart-b8f49b64-682a-4e2f-8a53-521c604b56a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512927687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1512927687
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.176925928
Short name T869
Test name
Test status
Simulation time 2317973527 ps
CPU time 5 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:25 PM PDT 24
Peak memory 214080 kb
Host smart-358ca352-14b8-4a52-a501-5c21ba4aecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176925928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.176925928
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3070706066
Short name T191
Test name
Test status
Simulation time 305660782 ps
CPU time 3.53 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:24 PM PDT 24
Peak memory 211272 kb
Host smart-ee863e1a-1d48-4126-b98b-8f91c48754fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070706066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3070706066
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2484921315
Short name T258
Test name
Test status
Simulation time 614891861 ps
CPU time 7.2 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:27 PM PDT 24
Peak memory 209704 kb
Host smart-d812c3bf-68ad-469b-b5bf-3b0cc7c04578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484921315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2484921315
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2533168351
Short name T885
Test name
Test status
Simulation time 186149842 ps
CPU time 3.16 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:24 PM PDT 24
Peak memory 207432 kb
Host smart-4c5b9639-2bfe-4e89-8a82-c4a8638bf558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533168351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2533168351
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2187519004
Short name T591
Test name
Test status
Simulation time 886301679 ps
CPU time 5.42 seconds
Started Jun 08 02:54:22 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 207488 kb
Host smart-491f1265-d47c-4ce3-bc25-204023d0be8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187519004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2187519004
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1180659550
Short name T374
Test name
Test status
Simulation time 223274462 ps
CPU time 7.97 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 208448 kb
Host smart-7a0d4e10-8778-4573-a8c7-13d40f35936e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180659550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1180659550
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.96848025
Short name T332
Test name
Test status
Simulation time 327741570 ps
CPU time 5.21 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:26 PM PDT 24
Peak memory 207720 kb
Host smart-6761a541-ae70-4355-931f-291c6c300181
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96848025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.96848025
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.750405839
Short name T975
Test name
Test status
Simulation time 3850491808 ps
CPU time 66.37 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:55:26 PM PDT 24
Peak memory 208308 kb
Host smart-96b15b19-5a05-41ac-8710-c0c4161251d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750405839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.750405839
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3568985741
Short name T622
Test name
Test status
Simulation time 1282182137 ps
CPU time 4.09 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:26 PM PDT 24
Peak memory 209504 kb
Host smart-9e4ea3ff-cfa0-49e7-b60e-ac8538ee99f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568985741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3568985741
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2477360269
Short name T403
Test name
Test status
Simulation time 108919173 ps
CPU time 2.88 seconds
Started Jun 08 02:54:20 PM PDT 24
Finished Jun 08 02:54:23 PM PDT 24
Peak memory 207476 kb
Host smart-fe882e80-d06e-42bb-8014-9dda47d53712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477360269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2477360269
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3829030282
Short name T873
Test name
Test status
Simulation time 96747803 ps
CPU time 7.2 seconds
Started Jun 08 02:54:23 PM PDT 24
Finished Jun 08 02:54:30 PM PDT 24
Peak memory 222356 kb
Host smart-99887653-caa4-4ddf-9940-f4901d6c0347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829030282 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3829030282
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1993480201
Short name T296
Test name
Test status
Simulation time 127516281 ps
CPU time 5.17 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:27 PM PDT 24
Peak memory 217836 kb
Host smart-77a3072d-3f82-4ef1-af88-fa71b1eb394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993480201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1993480201
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1896337247
Short name T1018
Test name
Test status
Simulation time 101729266 ps
CPU time 3.35 seconds
Started Jun 08 02:54:21 PM PDT 24
Finished Jun 08 02:54:24 PM PDT 24
Peak memory 209988 kb
Host smart-e432b8fe-1bbe-40a4-96cf-504e7be36aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896337247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1896337247
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1166072336
Short name T628
Test name
Test status
Simulation time 21436621 ps
CPU time 0.85 seconds
Started Jun 08 02:54:31 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 205544 kb
Host smart-e3b1df90-bf7e-4595-9e7e-1a9ba85018c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166072336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1166072336
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3569839870
Short name T19
Test name
Test status
Simulation time 120667910 ps
CPU time 3.06 seconds
Started Jun 08 02:54:28 PM PDT 24
Finished Jun 08 02:54:31 PM PDT 24
Peak memory 221424 kb
Host smart-e551c1e6-bda7-4bc9-90ff-c2238bb37d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569839870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3569839870
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.692620266
Short name T1001
Test name
Test status
Simulation time 1242544349 ps
CPU time 7.29 seconds
Started Jun 08 02:54:24 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 217968 kb
Host smart-e38424ae-0148-4bfe-ac0d-5c9c2bb997b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692620266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.692620266
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.778726393
Short name T301
Test name
Test status
Simulation time 422115097 ps
CPU time 6.29 seconds
Started Jun 08 02:54:27 PM PDT 24
Finished Jun 08 02:54:34 PM PDT 24
Peak memory 209380 kb
Host smart-160d0ba6-8f71-433b-ad2a-75c208b57d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778726393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.778726393
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1595220094
Short name T684
Test name
Test status
Simulation time 559198770 ps
CPU time 3.54 seconds
Started Jun 08 02:54:25 PM PDT 24
Finished Jun 08 02:54:29 PM PDT 24
Peak memory 220008 kb
Host smart-762b3cbe-f312-4605-9b88-e66743906b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595220094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1595220094
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1640603975
Short name T730
Test name
Test status
Simulation time 379856170 ps
CPU time 11.23 seconds
Started Jun 08 02:54:26 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 209684 kb
Host smart-78437b87-679d-4642-8750-6ef3bf6b03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640603975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1640603975
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1748302534
Short name T370
Test name
Test status
Simulation time 54809107 ps
CPU time 2.67 seconds
Started Jun 08 02:54:26 PM PDT 24
Finished Jun 08 02:54:29 PM PDT 24
Peak memory 206596 kb
Host smart-5b7de17b-dfe3-4217-9673-347aa155fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748302534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1748302534
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1334746294
Short name T319
Test name
Test status
Simulation time 3610074149 ps
CPU time 24.47 seconds
Started Jun 08 02:54:24 PM PDT 24
Finished Jun 08 02:54:49 PM PDT 24
Peak memory 208528 kb
Host smart-1b3e6945-4cb9-4c6b-9b3a-e01d7a26f317
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334746294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1334746294
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.225010977
Short name T752
Test name
Test status
Simulation time 1012167844 ps
CPU time 25.21 seconds
Started Jun 08 02:54:26 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 207824 kb
Host smart-fddd430f-08d3-402c-9932-1d9db038cdc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225010977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.225010977
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3141645173
Short name T1041
Test name
Test status
Simulation time 365471395 ps
CPU time 3.84 seconds
Started Jun 08 02:54:25 PM PDT 24
Finished Jun 08 02:54:29 PM PDT 24
Peak memory 206616 kb
Host smart-0febb10c-efd5-4916-83a3-02045aef33d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141645173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3141645173
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.44213867
Short name T330
Test name
Test status
Simulation time 37905752 ps
CPU time 2.31 seconds
Started Jun 08 02:54:30 PM PDT 24
Finished Jun 08 02:54:33 PM PDT 24
Peak memory 209056 kb
Host smart-9583d38e-e144-46bd-a47b-f544cc6f47e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44213867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.44213867
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3496592677
Short name T698
Test name
Test status
Simulation time 41117139 ps
CPU time 2.25 seconds
Started Jun 08 02:54:25 PM PDT 24
Finished Jun 08 02:54:28 PM PDT 24
Peak memory 206488 kb
Host smart-e114f6e0-8e36-4af7-8f60-bf924492291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496592677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3496592677
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2324333385
Short name T726
Test name
Test status
Simulation time 764653661 ps
CPU time 19.76 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 221924 kb
Host smart-322a29c0-1c96-4d64-8fa3-b3bf89f8e325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324333385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2324333385
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1135773208
Short name T297
Test name
Test status
Simulation time 156833270 ps
CPU time 4.81 seconds
Started Jun 08 02:54:27 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 207304 kb
Host smart-30fe3dcc-123f-472d-b676-1603c9439308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135773208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1135773208
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1241004646
Short name T1028
Test name
Test status
Simulation time 88658514 ps
CPU time 2.95 seconds
Started Jun 08 02:54:34 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 209916 kb
Host smart-8639b43d-452e-40a7-850b-f3c8c8a0772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241004646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1241004646
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.573376726
Short name T104
Test name
Test status
Simulation time 12923882 ps
CPU time 0.92 seconds
Started Jun 08 02:51:09 PM PDT 24
Finished Jun 08 02:51:10 PM PDT 24
Peak memory 205732 kb
Host smart-58d3ce96-503b-4afe-a346-93f1720dfb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573376726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.573376726
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2039473279
Short name T1044
Test name
Test status
Simulation time 913537428 ps
CPU time 6.56 seconds
Started Jun 08 02:51:09 PM PDT 24
Finished Jun 08 02:51:16 PM PDT 24
Peak memory 213964 kb
Host smart-2402a342-1844-45ce-bd79-81c87157ab32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039473279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2039473279
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2452019889
Short name T18
Test name
Test status
Simulation time 53059845 ps
CPU time 3.41 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:15 PM PDT 24
Peak memory 214284 kb
Host smart-b461606a-cd82-48ad-b5e1-454d8d181fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452019889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2452019889
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1442788188
Short name T321
Test name
Test status
Simulation time 75037419 ps
CPU time 3.58 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:11 PM PDT 24
Peak memory 218108 kb
Host smart-e63180b8-f39f-42a7-8ecb-7b6a576be47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442788188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1442788188
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2330544786
Short name T353
Test name
Test status
Simulation time 3850870776 ps
CPU time 17.82 seconds
Started Jun 08 02:51:09 PM PDT 24
Finished Jun 08 02:51:27 PM PDT 24
Peak memory 215956 kb
Host smart-f450dd77-1c7e-4230-a3f0-8db7a9bd7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330544786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2330544786
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1612026754
Short name T905
Test name
Test status
Simulation time 56509778 ps
CPU time 1.82 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:13 PM PDT 24
Peak memory 213920 kb
Host smart-8105941c-e4b7-4f80-8b8d-4e22992730c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612026754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1612026754
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2147630064
Short name T285
Test name
Test status
Simulation time 1639689777 ps
CPU time 21.66 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:30 PM PDT 24
Peak memory 209456 kb
Host smart-dba6e593-c214-40d1-83a8-13803df2ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147630064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2147630064
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.556671640
Short name T7
Test name
Test status
Simulation time 1994903049 ps
CPU time 12.44 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:24 PM PDT 24
Peak memory 231436 kb
Host smart-e2c12ad9-afb9-41b9-b3c4-b04f689e8bcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556671640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.556671640
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3274588636
Short name T911
Test name
Test status
Simulation time 42881175 ps
CPU time 2.72 seconds
Started Jun 08 02:51:11 PM PDT 24
Finished Jun 08 02:51:14 PM PDT 24
Peak memory 208368 kb
Host smart-b1c6511c-4f16-4b25-b673-32c4037cf75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274588636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3274588636
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4176869392
Short name T317
Test name
Test status
Simulation time 114226182 ps
CPU time 2.81 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:11 PM PDT 24
Peak memory 208684 kb
Host smart-d02ff89f-2963-4f42-97c5-dc6f08c24cfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176869392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4176869392
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1890361615
Short name T329
Test name
Test status
Simulation time 33792027 ps
CPU time 2.21 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:11 PM PDT 24
Peak memory 206924 kb
Host smart-750d935c-1050-4e59-8094-fe3db3a1672b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890361615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1890361615
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1224429156
Short name T958
Test name
Test status
Simulation time 189109595 ps
CPU time 4.54 seconds
Started Jun 08 02:51:09 PM PDT 24
Finished Jun 08 02:51:14 PM PDT 24
Peak memory 206660 kb
Host smart-6b9f22be-c791-4ff1-adc5-3f28b11077f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224429156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1224429156
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1101183009
Short name T951
Test name
Test status
Simulation time 117343473 ps
CPU time 3.27 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:12 PM PDT 24
Peak memory 207952 kb
Host smart-2a854092-25ce-4866-9c57-9cde56da07fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101183009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1101183009
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3956869718
Short name T630
Test name
Test status
Simulation time 59598200 ps
CPU time 2.07 seconds
Started Jun 08 02:51:14 PM PDT 24
Finished Jun 08 02:51:16 PM PDT 24
Peak memory 206524 kb
Host smart-1c361a08-f3cc-458a-9bc4-246a9ed83ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956869718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3956869718
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2787290880
Short name T794
Test name
Test status
Simulation time 202359468 ps
CPU time 8.89 seconds
Started Jun 08 02:51:07 PM PDT 24
Finished Jun 08 02:51:16 PM PDT 24
Peak memory 222344 kb
Host smart-29ac6338-27eb-4126-be06-ae582b18ea52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787290880 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2787290880
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.642960907
Short name T1058
Test name
Test status
Simulation time 2575048790 ps
CPU time 5.59 seconds
Started Jun 08 02:51:09 PM PDT 24
Finished Jun 08 02:51:14 PM PDT 24
Peak memory 207404 kb
Host smart-5b2426e5-e93d-4c7a-bb34-0b4753191c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642960907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.642960907
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1992026233
Short name T644
Test name
Test status
Simulation time 70595073 ps
CPU time 2.78 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:11 PM PDT 24
Peak memory 209592 kb
Host smart-609bf51d-7d23-4433-966c-29350b867fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992026233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1992026233
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1180835496
Short name T938
Test name
Test status
Simulation time 17754686 ps
CPU time 0.8 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:36 PM PDT 24
Peak memory 205584 kb
Host smart-fece2d14-d4d3-4b48-81f8-26989cfe23a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180835496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1180835496
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2748408312
Short name T361
Test name
Test status
Simulation time 720747898 ps
CPU time 12.74 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:45 PM PDT 24
Peak memory 213956 kb
Host smart-b29fdc61-4477-48e5-9741-2bc040cbae95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748408312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2748408312
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3446167333
Short name T691
Test name
Test status
Simulation time 409944270 ps
CPU time 2.72 seconds
Started Jun 08 02:54:29 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 214356 kb
Host smart-853e0baa-0e73-4786-9568-3ae4790ff58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446167333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3446167333
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4251054185
Short name T880
Test name
Test status
Simulation time 60089019 ps
CPU time 2.71 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 209388 kb
Host smart-61f70a66-7038-4aeb-9a43-ff1f4f8160fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251054185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4251054185
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1145202952
Short name T837
Test name
Test status
Simulation time 339884839 ps
CPU time 3.93 seconds
Started Jun 08 02:54:29 PM PDT 24
Finished Jun 08 02:54:33 PM PDT 24
Peak memory 218984 kb
Host smart-029a4438-561f-4f3e-8827-bc859983c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145202952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1145202952
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_random.4088127316
Short name T294
Test name
Test status
Simulation time 92761868 ps
CPU time 3.94 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:36 PM PDT 24
Peak memory 207124 kb
Host smart-ddb77766-e67a-4dab-b868-37fc2c9331e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088127316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4088127316
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3009957521
Short name T1046
Test name
Test status
Simulation time 61054989 ps
CPU time 2.78 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 206532 kb
Host smart-54295d82-5a76-4bfb-bebc-1c907e1839af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009957521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3009957521
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1471606781
Short name T649
Test name
Test status
Simulation time 73187747 ps
CPU time 2.85 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 208772 kb
Host smart-c60921c0-a310-40bf-aa44-9e107a0e6f58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471606781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1471606781
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3007571299
Short name T660
Test name
Test status
Simulation time 237489837 ps
CPU time 3.1 seconds
Started Jun 08 02:54:32 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 206660 kb
Host smart-db247755-7193-4681-89d3-36c17fe07afe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007571299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3007571299
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2696150868
Short name T854
Test name
Test status
Simulation time 785779787 ps
CPU time 6.41 seconds
Started Jun 08 02:54:30 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 207736 kb
Host smart-76a4a3bb-a3d5-4eba-bb5a-dacf20324bd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696150868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2696150868
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2762056684
Short name T877
Test name
Test status
Simulation time 64340001 ps
CPU time 2.87 seconds
Started Jun 08 02:54:29 PM PDT 24
Finished Jun 08 02:54:32 PM PDT 24
Peak memory 207752 kb
Host smart-6b216bfb-8889-4467-9997-c4047a4c2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762056684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2762056684
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3384594751
Short name T118
Test name
Test status
Simulation time 2255648853 ps
CPU time 7.58 seconds
Started Jun 08 02:54:30 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 214096 kb
Host smart-f65a52a4-fb16-4b30-b70a-9e10e9eabdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384594751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3384594751
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1578482325
Short name T641
Test name
Test status
Simulation time 424241113 ps
CPU time 6.88 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:42 PM PDT 24
Peak memory 210732 kb
Host smart-d5324270-42db-491a-86e3-21cb86010abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578482325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1578482325
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.387387025
Short name T863
Test name
Test status
Simulation time 31640172 ps
CPU time 0.78 seconds
Started Jun 08 02:54:36 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 205516 kb
Host smart-0948cad6-1e73-4e1f-8d06-8b5e19113565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387387025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.387387025
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.247412249
Short name T436
Test name
Test status
Simulation time 79269439 ps
CPU time 2.98 seconds
Started Jun 08 02:54:36 PM PDT 24
Finished Jun 08 02:54:39 PM PDT 24
Peak memory 214052 kb
Host smart-8c120c3d-039c-4f0f-8e37-320ba1d22788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247412249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.247412249
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3818620637
Short name T964
Test name
Test status
Simulation time 102460846 ps
CPU time 1.68 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 208600 kb
Host smart-7a4a7e64-42c6-4a98-be71-f6be10cd5353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818620637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3818620637
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3898421560
Short name T904
Test name
Test status
Simulation time 21966658 ps
CPU time 1.52 seconds
Started Jun 08 02:54:34 PM PDT 24
Finished Jun 08 02:54:35 PM PDT 24
Peak memory 207272 kb
Host smart-c07f097e-f062-4258-81ed-3bbc997895a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898421560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3898421560
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2817134435
Short name T979
Test name
Test status
Simulation time 924756579 ps
CPU time 7.77 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:44 PM PDT 24
Peak memory 219324 kb
Host smart-6f599b40-efff-4f9d-a3cd-716c27735983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817134435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2817134435
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2575503799
Short name T440
Test name
Test status
Simulation time 58503001 ps
CPU time 2.24 seconds
Started Jun 08 02:54:36 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 209372 kb
Host smart-d7133b7b-c229-467c-b6c9-a4d1ec87af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575503799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2575503799
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1937535486
Short name T738
Test name
Test status
Simulation time 160234899 ps
CPU time 3.01 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 207152 kb
Host smart-4e7ec097-3bfb-4f2a-bf2a-1bb7ab387543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937535486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1937535486
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.627904856
Short name T689
Test name
Test status
Simulation time 26150641 ps
CPU time 1.96 seconds
Started Jun 08 02:54:36 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 206792 kb
Host smart-5dacf91e-9c5f-4c4f-8086-faa4f4b9dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627904856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.627904856
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3064298269
Short name T348
Test name
Test status
Simulation time 210046441 ps
CPU time 3.88 seconds
Started Jun 08 02:54:38 PM PDT 24
Finished Jun 08 02:54:42 PM PDT 24
Peak memory 206480 kb
Host smart-b38623d9-a670-4ad9-b3bc-41cbb59d920a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064298269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3064298269
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.906182870
Short name T138
Test name
Test status
Simulation time 972189768 ps
CPU time 8.55 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:43 PM PDT 24
Peak memory 207888 kb
Host smart-82145573-4c45-4467-9908-1d484a550a3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906182870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.906182870
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3126291021
Short name T850
Test name
Test status
Simulation time 216341789 ps
CPU time 7.97 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:43 PM PDT 24
Peak memory 208264 kb
Host smart-3df7bfd7-af49-460a-abae-e89ecdd91ee0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126291021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3126291021
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.400250365
Short name T696
Test name
Test status
Simulation time 34205096 ps
CPU time 1.97 seconds
Started Jun 08 02:54:38 PM PDT 24
Finished Jun 08 02:54:40 PM PDT 24
Peak memory 206572 kb
Host smart-08d051ec-d99a-474b-bafb-e8b6c7818296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400250365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.400250365
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4038303072
Short name T772
Test name
Test status
Simulation time 193335494 ps
CPU time 2.48 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 208220 kb
Host smart-86d4afec-582e-4bc8-8afe-7fedb7e80290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038303072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4038303072
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.102463502
Short name T217
Test name
Test status
Simulation time 3441403030 ps
CPU time 42.06 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:55:17 PM PDT 24
Peak memory 215388 kb
Host smart-0e2f2044-9b0f-48bf-91c5-61fc757c96f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102463502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.102463502
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1830138057
Short name T1003
Test name
Test status
Simulation time 500414576 ps
CPU time 8.63 seconds
Started Jun 08 02:54:36 PM PDT 24
Finished Jun 08 02:54:45 PM PDT 24
Peak memory 222464 kb
Host smart-86070d76-2795-402d-b506-ca2ec1aa07ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830138057 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1830138057
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2930660172
Short name T728
Test name
Test status
Simulation time 65023227 ps
CPU time 2.47 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 213960 kb
Host smart-7f615586-d156-43fc-9366-bfab1d410cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930660172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2930660172
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1037108258
Short name T33
Test name
Test status
Simulation time 236686231 ps
CPU time 2.79 seconds
Started Jun 08 02:54:38 PM PDT 24
Finished Jun 08 02:54:41 PM PDT 24
Peak memory 209556 kb
Host smart-eb84cf97-36f0-4b6a-afc8-981c8733bc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037108258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1037108258
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.765538894
Short name T1035
Test name
Test status
Simulation time 26363574 ps
CPU time 0.72 seconds
Started Jun 08 02:54:43 PM PDT 24
Finished Jun 08 02:54:44 PM PDT 24
Peak memory 205612 kb
Host smart-88e018e0-02ff-4f6e-a469-b1dcc71d9b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765538894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.765538894
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.516106961
Short name T369
Test name
Test status
Simulation time 366446232 ps
CPU time 10.7 seconds
Started Jun 08 02:54:41 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 214548 kb
Host smart-acb7229f-7d81-4d9f-ba73-e2929563af24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516106961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.516106961
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.21653763
Short name T427
Test name
Test status
Simulation time 53381054 ps
CPU time 1.77 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:54:42 PM PDT 24
Peak memory 208040 kb
Host smart-906cfd3c-90bb-455b-9bb3-d1346e587a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21653763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.21653763
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.12257416
Short name T718
Test name
Test status
Simulation time 85223510 ps
CPU time 1.81 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:54:42 PM PDT 24
Peak memory 209972 kb
Host smart-6d61ef9e-31dd-4486-a83e-ad0f0f2f7fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12257416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.12257416
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3122264280
Short name T90
Test name
Test status
Simulation time 2787529863 ps
CPU time 68.39 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:55:48 PM PDT 24
Peak memory 220480 kb
Host smart-a68d034f-cafa-44fa-84c3-07a23be79e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122264280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3122264280
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.498617856
Short name T390
Test name
Test status
Simulation time 1083696255 ps
CPU time 8.54 seconds
Started Jun 08 02:54:42 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 222120 kb
Host smart-4e5e76be-de86-4025-9d53-9fef53b5d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498617856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.498617856
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1828305692
Short name T214
Test name
Test status
Simulation time 2833463417 ps
CPU time 13.32 seconds
Started Jun 08 02:54:41 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 209240 kb
Host smart-806bfb13-9b44-4792-b2c3-59aebcb16671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828305692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1828305692
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3929338095
Short name T776
Test name
Test status
Simulation time 198552086 ps
CPU time 4.79 seconds
Started Jun 08 02:54:41 PM PDT 24
Finished Jun 08 02:54:46 PM PDT 24
Peak memory 214044 kb
Host smart-6d4fc5e7-eac1-41e8-99fd-bd96d8b5c0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929338095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3929338095
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.861011740
Short name T967
Test name
Test status
Simulation time 162284211 ps
CPU time 2.46 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:37 PM PDT 24
Peak memory 206628 kb
Host smart-39b89c6a-fa5e-42c9-bf16-0667285cee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861011740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.861011740
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.612093608
Short name T629
Test name
Test status
Simulation time 720890757 ps
CPU time 8.26 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 207740 kb
Host smart-a5b00930-0e82-4490-a9f2-9a7220874315
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612093608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.612093608
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2593034872
Short name T838
Test name
Test status
Simulation time 87096574 ps
CPU time 3.76 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:40 PM PDT 24
Peak memory 206656 kb
Host smart-4935493b-37f9-4ef9-aabe-869032013254
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593034872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2593034872
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.436480987
Short name T760
Test name
Test status
Simulation time 161273245 ps
CPU time 5.1 seconds
Started Jun 08 02:54:39 PM PDT 24
Finished Jun 08 02:54:45 PM PDT 24
Peak memory 208572 kb
Host smart-4b3ac7a2-c114-4006-b9c5-7d524e13e543
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436480987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.436480987
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3111616173
Short name T188
Test name
Test status
Simulation time 82682458 ps
CPU time 3.7 seconds
Started Jun 08 02:54:39 PM PDT 24
Finished Jun 08 02:54:43 PM PDT 24
Peak memory 209036 kb
Host smart-1be2c16a-66de-4f26-9c1a-1e48b7ed3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111616173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3111616173
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2238401223
Short name T193
Test name
Test status
Simulation time 68598932 ps
CPU time 2.9 seconds
Started Jun 08 02:54:35 PM PDT 24
Finished Jun 08 02:54:38 PM PDT 24
Peak memory 207560 kb
Host smart-81517323-89ff-4835-b5a8-346637a37595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238401223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2238401223
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2091785858
Short name T360
Test name
Test status
Simulation time 595714923 ps
CPU time 20.18 seconds
Started Jun 08 02:54:42 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 215972 kb
Host smart-28cc60b0-e79a-4b0f-bd05-8e522045cf8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091785858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2091785858
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.279166918
Short name T362
Test name
Test status
Simulation time 191891263 ps
CPU time 5.23 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 208744 kb
Host smart-2e82c91a-ffc6-42c3-a692-f6c2c7a4251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279166918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.279166918
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.937792580
Short name T609
Test name
Test status
Simulation time 3897139587 ps
CPU time 12.47 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 211316 kb
Host smart-78ad235c-5b8e-478e-8f54-6181c1928699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937792580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.937792580
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1198018556
Short name T808
Test name
Test status
Simulation time 126553440 ps
CPU time 1.18 seconds
Started Jun 08 02:54:46 PM PDT 24
Finished Jun 08 02:54:47 PM PDT 24
Peak memory 205772 kb
Host smart-4339fe15-6010-47c2-88cc-3f87f5a26075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198018556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1198018556
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3950951079
Short name T304
Test name
Test status
Simulation time 57521750 ps
CPU time 3.87 seconds
Started Jun 08 02:54:46 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 213984 kb
Host smart-683e20d0-a8ff-44a0-a136-ae136b675125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950951079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3950951079
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2642001869
Short name T845
Test name
Test status
Simulation time 109630056 ps
CPU time 2.45 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:54:47 PM PDT 24
Peak memory 208704 kb
Host smart-583e811b-55d8-4487-863e-956be4a91e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642001869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2642001869
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.957089791
Short name T784
Test name
Test status
Simulation time 432398086 ps
CPU time 8.72 seconds
Started Jun 08 02:54:46 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 208992 kb
Host smart-d8e6743b-fe82-4372-b079-ccfd96929465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957089791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.957089791
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1098428529
Short name T274
Test name
Test status
Simulation time 443876388 ps
CPU time 6.18 seconds
Started Jun 08 02:54:43 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 222056 kb
Host smart-bf80adb6-e696-444f-a857-ff4da3001974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098428529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1098428529
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3829939640
Short name T791
Test name
Test status
Simulation time 60507379 ps
CPU time 4.08 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:48 PM PDT 24
Peak memory 222132 kb
Host smart-a55b6b32-fec2-4069-8fbb-f7af90d118a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829939640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3829939640
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3835919910
Short name T952
Test name
Test status
Simulation time 177872933 ps
CPU time 4.69 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 208492 kb
Host smart-7c295fb1-0418-4fd0-a6e3-e7e6bdec9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835919910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3835919910
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3709034070
Short name T617
Test name
Test status
Simulation time 138426113 ps
CPU time 2.71 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:54:43 PM PDT 24
Peak memory 206524 kb
Host smart-0880e789-9e4e-41c5-9c28-58188c7f7164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709034070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3709034070
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1132237436
Short name T717
Test name
Test status
Simulation time 174949966 ps
CPU time 5.35 seconds
Started Jun 08 02:54:38 PM PDT 24
Finished Jun 08 02:54:44 PM PDT 24
Peak memory 208452 kb
Host smart-2cba9739-e70c-4038-a6cf-182b1baaf6ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132237436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1132237436
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2487965477
Short name T719
Test name
Test status
Simulation time 199752128 ps
CPU time 4.62 seconds
Started Jun 08 02:54:39 PM PDT 24
Finished Jun 08 02:54:43 PM PDT 24
Peak memory 206660 kb
Host smart-32c1f527-6a02-4601-8d59-523044ed90c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487965477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2487965477
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2732707759
Short name T356
Test name
Test status
Simulation time 75383240 ps
CPU time 3.62 seconds
Started Jun 08 02:54:40 PM PDT 24
Finished Jun 08 02:54:44 PM PDT 24
Peak memory 208336 kb
Host smart-2dadcd71-62fc-45e3-a320-6d109920fee0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732707759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2732707759
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3687526321
Short name T203
Test name
Test status
Simulation time 200140681 ps
CPU time 2.95 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:47 PM PDT 24
Peak memory 214024 kb
Host smart-466bcdde-5547-41c1-8799-d040efbc26dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687526321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3687526321
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1232361258
Short name T829
Test name
Test status
Simulation time 1126227738 ps
CPU time 18.26 seconds
Started Jun 08 02:54:42 PM PDT 24
Finished Jun 08 02:55:01 PM PDT 24
Peak memory 207716 kb
Host smart-0ff4e64d-6975-48bc-9a9a-3a3a94cfecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232361258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1232361258
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2877566162
Short name T710
Test name
Test status
Simulation time 174051810 ps
CPU time 2.93 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:54:48 PM PDT 24
Peak memory 217792 kb
Host smart-65b7e2b3-acc0-41bb-bb88-319e414d2713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877566162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2877566162
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3120485167
Short name T311
Test name
Test status
Simulation time 193630411 ps
CPU time 5.44 seconds
Started Jun 08 02:54:44 PM PDT 24
Finished Jun 08 02:54:50 PM PDT 24
Peak memory 208784 kb
Host smart-26cc079b-5538-435b-ae72-91a5c2342268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120485167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3120485167
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2836869144
Short name T1021
Test name
Test status
Simulation time 30187179 ps
CPU time 1.78 seconds
Started Jun 08 02:54:43 PM PDT 24
Finished Jun 08 02:54:46 PM PDT 24
Peak memory 209248 kb
Host smart-1bf96d52-d830-4237-a21b-fdf47c0fbe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836869144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2836869144
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2720483545
Short name T156
Test name
Test status
Simulation time 165604180 ps
CPU time 1.02 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 205736 kb
Host smart-ae5c7d4b-720b-4479-824d-a36e610f3bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720483545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2720483545
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2726821131
Short name T242
Test name
Test status
Simulation time 4486821679 ps
CPU time 54.59 seconds
Started Jun 08 02:54:46 PM PDT 24
Finished Jun 08 02:55:40 PM PDT 24
Peak memory 214040 kb
Host smart-a39ff171-a4fb-438a-abe4-6e19e17a18b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726821131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2726821131
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1070126356
Short name T28
Test name
Test status
Simulation time 164597918 ps
CPU time 2.86 seconds
Started Jun 08 02:54:48 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 214380 kb
Host smart-3b8f7a2a-c5eb-44f8-8b21-104ad6575442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070126356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1070126356
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2140929863
Short name T874
Test name
Test status
Simulation time 62222046 ps
CPU time 2.02 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 207768 kb
Host smart-1d036508-116a-4e83-a908-1172ffa1dc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140929863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2140929863
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1585999658
Short name T110
Test name
Test status
Simulation time 496344687 ps
CPU time 6.05 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:58 PM PDT 24
Peak memory 220016 kb
Host smart-7d29f056-ef94-4efa-b84b-59703a870f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585999658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1585999658
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1879067824
Short name T882
Test name
Test status
Simulation time 102633207 ps
CPU time 3.4 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 219416 kb
Host smart-24cf092a-21b3-4f4d-91c3-af87c88c03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879067824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1879067824
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.625936415
Short name T734
Test name
Test status
Simulation time 518692884 ps
CPU time 6.78 seconds
Started Jun 08 02:54:47 PM PDT 24
Finished Jun 08 02:54:54 PM PDT 24
Peak memory 214036 kb
Host smart-d3800777-81be-49e7-ac07-7ab00b12683f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625936415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.625936415
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.224115226
Short name T963
Test name
Test status
Simulation time 1133444694 ps
CPU time 28.73 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:55:14 PM PDT 24
Peak memory 208600 kb
Host smart-776686c4-ec51-4920-9e6a-e928277a0c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224115226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.224115226
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1474757142
Short name T908
Test name
Test status
Simulation time 147952798 ps
CPU time 4.76 seconds
Started Jun 08 02:54:46 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 206504 kb
Host smart-e6feee97-f962-4094-8b61-350443e86921
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474757142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1474757142
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3875105852
Short name T902
Test name
Test status
Simulation time 106029744 ps
CPU time 4.56 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:54:49 PM PDT 24
Peak memory 206648 kb
Host smart-a7848076-afce-4a24-8782-235cede7ccc1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875105852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3875105852
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3609026669
Short name T1005
Test name
Test status
Simulation time 162038087 ps
CPU time 2.44 seconds
Started Jun 08 02:54:45 PM PDT 24
Finished Jun 08 02:54:48 PM PDT 24
Peak memory 206496 kb
Host smart-982ef379-603a-4e59-81c0-0d2c206ae6d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609026669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3609026669
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1154306947
Short name T1036
Test name
Test status
Simulation time 49072940 ps
CPU time 1.79 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 207860 kb
Host smart-d66d8990-3976-43cd-90be-b640c2a577d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154306947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1154306947
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3673394283
Short name T968
Test name
Test status
Simulation time 158013337 ps
CPU time 2.38 seconds
Started Jun 08 02:54:43 PM PDT 24
Finished Jun 08 02:54:46 PM PDT 24
Peak memory 206824 kb
Host smart-e87b11e9-1945-4369-bbb2-cdaf93df3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673394283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3673394283
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2883018237
Short name T52
Test name
Test status
Simulation time 2534229398 ps
CPU time 46.67 seconds
Started Jun 08 02:54:49 PM PDT 24
Finished Jun 08 02:55:36 PM PDT 24
Peak memory 222280 kb
Host smart-e5151e1b-f8ed-45d6-9d54-0c1a94cbc86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883018237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2883018237
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1040281795
Short name T933
Test name
Test status
Simulation time 172869317 ps
CPU time 3.5 seconds
Started Jun 08 02:54:52 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 219480 kb
Host smart-351ba338-d0d7-4473-b9ba-035403241226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040281795 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1040281795
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2613479330
Short name T268
Test name
Test status
Simulation time 1777225301 ps
CPU time 18.9 seconds
Started Jun 08 02:54:50 PM PDT 24
Finished Jun 08 02:55:10 PM PDT 24
Peak memory 208348 kb
Host smart-1d9566c4-43e7-4526-8613-cb87a03230fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613479330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2613479330
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3019577423
Short name T758
Test name
Test status
Simulation time 92620888 ps
CPU time 1.7 seconds
Started Jun 08 02:54:49 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 208344 kb
Host smart-7f84a052-8bc8-42c5-a22d-fefc57dfc9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019577423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3019577423
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1755797649
Short name T632
Test name
Test status
Simulation time 17298925 ps
CPU time 0.98 seconds
Started Jun 08 02:54:54 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 205672 kb
Host smart-0f9c5be6-8431-440c-95fa-56f7bd93cbe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755797649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1755797649
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2426857300
Short name T978
Test name
Test status
Simulation time 190410690 ps
CPU time 9.52 seconds
Started Jun 08 02:54:59 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 209864 kb
Host smart-7684ee1b-4d71-433d-bd63-cd642c8b321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426857300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2426857300
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.630429212
Short name T654
Test name
Test status
Simulation time 96628985 ps
CPU time 1.56 seconds
Started Jun 08 02:54:52 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 206772 kb
Host smart-9fd3326d-121f-4919-9885-2f78917de77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630429212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.630429212
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.531091225
Short name T248
Test name
Test status
Simulation time 1138827482 ps
CPU time 34.07 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:30 PM PDT 24
Peak memory 220620 kb
Host smart-5ccfa99f-f761-4cd5-b3c0-62971bb87a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531091225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.531091225
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_random.311152511
Short name T821
Test name
Test status
Simulation time 230292183 ps
CPU time 7.13 seconds
Started Jun 08 02:54:51 PM PDT 24
Finished Jun 08 02:54:59 PM PDT 24
Peak memory 208468 kb
Host smart-e8b0f296-e43f-4349-9814-b3bfce94cb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311152511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.311152511
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2917462086
Short name T246
Test name
Test status
Simulation time 640875247 ps
CPU time 4.5 seconds
Started Jun 08 02:54:49 PM PDT 24
Finished Jun 08 02:54:53 PM PDT 24
Peak memory 208320 kb
Host smart-214bba3b-c96e-414d-a2fc-bbe5a3552222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917462086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2917462086
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3087182846
Short name T599
Test name
Test status
Simulation time 127551124 ps
CPU time 2.48 seconds
Started Jun 08 02:54:52 PM PDT 24
Finished Jun 08 02:54:54 PM PDT 24
Peak memory 206408 kb
Host smart-68a093c0-b145-44d5-9710-8f7927b4916d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087182846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3087182846
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1399798378
Short name T813
Test name
Test status
Simulation time 214656433 ps
CPU time 2.71 seconds
Started Jun 08 02:54:52 PM PDT 24
Finished Jun 08 02:54:55 PM PDT 24
Peak memory 206664 kb
Host smart-b2cbd962-97dc-4e51-8aff-b003a03f493b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399798378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1399798378
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.684468853
Short name T844
Test name
Test status
Simulation time 67217406 ps
CPU time 3.66 seconds
Started Jun 08 02:54:49 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 208264 kb
Host smart-4fbf31bc-ce09-4145-8080-08f4507402e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684468853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.684468853
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.30321296
Short name T887
Test name
Test status
Simulation time 64023796 ps
CPU time 1.66 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:54:57 PM PDT 24
Peak memory 207656 kb
Host smart-f8a3968c-aa8e-4efd-8445-023f1ad7fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30321296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.30321296
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1411190902
Short name T582
Test name
Test status
Simulation time 178882228 ps
CPU time 2.71 seconds
Started Jun 08 02:54:48 PM PDT 24
Finished Jun 08 02:54:51 PM PDT 24
Peak memory 208340 kb
Host smart-9dc1b084-aac2-4c47-943c-48bf4f29b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411190902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1411190902
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2415445945
Short name T245
Test name
Test status
Simulation time 127580262 ps
CPU time 5.58 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:01 PM PDT 24
Peak memory 217940 kb
Host smart-610a9f5c-672b-4054-ac04-5a6859d5f5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415445945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2415445945
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1071869321
Short name T211
Test name
Test status
Simulation time 817702723 ps
CPU time 5.33 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:00 PM PDT 24
Peak memory 218668 kb
Host smart-ce874364-fc5d-43cc-933f-56f64ac1bf9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071869321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1071869321
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1506962866
Short name T428
Test name
Test status
Simulation time 90972102 ps
CPU time 2.69 seconds
Started Jun 08 02:54:49 PM PDT 24
Finished Jun 08 02:54:52 PM PDT 24
Peak memory 207292 kb
Host smart-6d117215-ef31-4731-a68c-af49ac075842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506962866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1506962866
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3880768324
Short name T903
Test name
Test status
Simulation time 188394355 ps
CPU time 4.18 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:00 PM PDT 24
Peak memory 209732 kb
Host smart-93617e94-3b59-4e26-8d3c-2bdfedceec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880768324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3880768324
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2098010104
Short name T105
Test name
Test status
Simulation time 10617680 ps
CPU time 0.71 seconds
Started Jun 08 02:55:02 PM PDT 24
Finished Jun 08 02:55:03 PM PDT 24
Peak memory 205488 kb
Host smart-8b57a5b6-fb67-43d4-918b-50caa3e71cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098010104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2098010104
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1072726954
Short name T432
Test name
Test status
Simulation time 133341209 ps
CPU time 2.99 seconds
Started Jun 08 02:54:59 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 214044 kb
Host smart-9ea9bd20-a862-4122-bcf3-98e2c1b38b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072726954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1072726954
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3095457574
Short name T29
Test name
Test status
Simulation time 101944147 ps
CPU time 2.8 seconds
Started Jun 08 02:55:01 PM PDT 24
Finished Jun 08 02:55:04 PM PDT 24
Peak memory 220316 kb
Host smart-cab587c8-746d-4708-b3bc-1d880be77472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095457574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3095457574
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.546510546
Short name T1045
Test name
Test status
Simulation time 81770535 ps
CPU time 2.87 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:07 PM PDT 24
Peak memory 209792 kb
Host smart-ee5847bd-0f92-48ea-8f16-90b80cb33f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546510546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.546510546
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.587265613
Short name T323
Test name
Test status
Simulation time 1053604752 ps
CPU time 21.3 seconds
Started Jun 08 02:55:01 PM PDT 24
Finished Jun 08 02:55:23 PM PDT 24
Peak memory 209388 kb
Host smart-4dc2bde2-e5a0-4b32-96ea-7d88c39709d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587265613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.587265613
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3133589458
Short name T670
Test name
Test status
Simulation time 2156848816 ps
CPU time 5.82 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:06 PM PDT 24
Peak memory 214056 kb
Host smart-43fd13b0-8434-42b3-a3e1-8e70d3943848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133589458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3133589458
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.306558757
Short name T806
Test name
Test status
Simulation time 305217608 ps
CPU time 6.63 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 208168 kb
Host smart-c68d70b1-e7af-4801-9387-22e46f0c7ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306558757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.306558757
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3608800855
Short name T987
Test name
Test status
Simulation time 623496384 ps
CPU time 4.76 seconds
Started Jun 08 02:54:56 PM PDT 24
Finished Jun 08 02:55:01 PM PDT 24
Peak memory 206472 kb
Host smart-cea26f48-fe5e-4f6e-b600-c6156a34a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608800855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3608800855
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2133672757
Short name T328
Test name
Test status
Simulation time 1161855348 ps
CPU time 7.86 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:03 PM PDT 24
Peak memory 207636 kb
Host smart-73d62f94-7d2f-41a4-b57a-a2ede8bc37be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133672757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2133672757
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1964065773
Short name T805
Test name
Test status
Simulation time 313933873 ps
CPU time 6.69 seconds
Started Jun 08 02:54:54 PM PDT 24
Finished Jun 08 02:55:01 PM PDT 24
Peak memory 208368 kb
Host smart-a8890b46-8b4d-4830-833b-4bd231b2ff67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964065773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1964065773
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2031455039
Short name T970
Test name
Test status
Simulation time 3646997470 ps
CPU time 47.95 seconds
Started Jun 08 02:54:55 PM PDT 24
Finished Jun 08 02:55:44 PM PDT 24
Peak memory 208008 kb
Host smart-3b6078c2-746a-49c0-8bff-541d4dc9a669
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031455039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2031455039
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3660369348
Short name T1004
Test name
Test status
Simulation time 82167973 ps
CPU time 1.8 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 215460 kb
Host smart-fbd5c8f4-b848-4c97-992a-a3a5845a102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660369348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3660369348
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.865511408
Short name T579
Test name
Test status
Simulation time 384150093 ps
CPU time 6.73 seconds
Started Jun 08 02:54:56 PM PDT 24
Finished Jun 08 02:55:03 PM PDT 24
Peak memory 206492 kb
Host smart-608efdb1-cf64-46b9-8fdb-ac3900d0e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865511408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.865511408
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.848819876
Short name T221
Test name
Test status
Simulation time 4474221486 ps
CPU time 42.81 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:43 PM PDT 24
Peak memory 216040 kb
Host smart-4de0d816-c9e5-445b-af6d-21c7e2a01eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848819876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.848819876
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3204286916
Short name T397
Test name
Test status
Simulation time 55799797 ps
CPU time 2.43 seconds
Started Jun 08 02:55:03 PM PDT 24
Finished Jun 08 02:55:06 PM PDT 24
Peak memory 222300 kb
Host smart-e1901002-4eec-40ad-b187-d3f2998088b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204286916 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3204286916
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3955530042
Short name T333
Test name
Test status
Simulation time 235802444 ps
CPU time 8.72 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 213988 kb
Host smart-80102194-93cf-4d5e-9bc1-7d9fb9785053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955530042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3955530042
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3847538872
Short name T404
Test name
Test status
Simulation time 151098993 ps
CPU time 2.08 seconds
Started Jun 08 02:55:03 PM PDT 24
Finished Jun 08 02:55:05 PM PDT 24
Peak memory 210008 kb
Host smart-7bfa6c81-3875-4bbe-a3a5-7140d872fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847538872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3847538872
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4186486018
Short name T836
Test name
Test status
Simulation time 20877063 ps
CPU time 0.84 seconds
Started Jun 08 02:55:07 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 205556 kb
Host smart-82e48a2e-fe5d-4f36-96f8-a0c50e96d09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186486018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4186486018
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2220107255
Short name T71
Test name
Test status
Simulation time 149540932 ps
CPU time 2.35 seconds
Started Jun 08 02:55:02 PM PDT 24
Finished Jun 08 02:55:05 PM PDT 24
Peak memory 221168 kb
Host smart-aaf79e74-c893-4369-acae-dc8a226963b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220107255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2220107255
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2519815652
Short name T1050
Test name
Test status
Simulation time 421412875 ps
CPU time 2.11 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:06 PM PDT 24
Peak memory 207432 kb
Host smart-c37103f5-f665-4180-aaf1-3b53a2a84c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519815652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2519815652
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3601296391
Short name T872
Test name
Test status
Simulation time 354540273 ps
CPU time 3.76 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:10 PM PDT 24
Peak memory 209020 kb
Host smart-d5bb8d95-e297-4f37-b873-3fa170770d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601296391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3601296391
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1488156016
Short name T254
Test name
Test status
Simulation time 398383537 ps
CPU time 5.28 seconds
Started Jun 08 02:55:07 PM PDT 24
Finished Jun 08 02:55:12 PM PDT 24
Peak memory 210224 kb
Host smart-99383e5d-5a24-4659-9828-1ded7b20ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488156016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1488156016
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3046648539
Short name T623
Test name
Test status
Simulation time 86257368 ps
CPU time 3.12 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:10 PM PDT 24
Peak memory 219592 kb
Host smart-6abc350f-5ab9-44ab-bf50-a9cccd1d5abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046648539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3046648539
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2025608036
Short name T886
Test name
Test status
Simulation time 213962779 ps
CPU time 3.82 seconds
Started Jun 08 02:55:01 PM PDT 24
Finished Jun 08 02:55:05 PM PDT 24
Peak memory 207556 kb
Host smart-56a52fa2-fffc-4549-b03d-5f752097d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025608036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2025608036
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2709240680
Short name T237
Test name
Test status
Simulation time 1247154263 ps
CPU time 6.46 seconds
Started Jun 08 02:55:01 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 207656 kb
Host smart-496d3a34-a147-4eb7-a29f-2ae450c507ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709240680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2709240680
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.666314382
Short name T303
Test name
Test status
Simulation time 62917273 ps
CPU time 2.97 seconds
Started Jun 08 02:54:59 PM PDT 24
Finished Jun 08 02:55:02 PM PDT 24
Peak memory 208392 kb
Host smart-66825614-58fb-469d-b65c-5997e470f1f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666314382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.666314382
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1551849172
Short name T117
Test name
Test status
Simulation time 244844381 ps
CPU time 3.2 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:04 PM PDT 24
Peak memory 208796 kb
Host smart-67ededdb-62a6-42b9-af31-617d74912e8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551849172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1551849172
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.680437715
Short name T716
Test name
Test status
Simulation time 29582010 ps
CPU time 2.14 seconds
Started Jun 08 02:55:03 PM PDT 24
Finished Jun 08 02:55:05 PM PDT 24
Peak memory 208060 kb
Host smart-0347bdf7-2469-4c9f-83e9-9ebdad22ffc2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680437715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.680437715
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3677596093
Short name T411
Test name
Test status
Simulation time 351720959 ps
CPU time 4.14 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:09 PM PDT 24
Peak memory 210076 kb
Host smart-eb135d9f-e10a-4bea-ad27-3ea0f5d17179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677596093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3677596093
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1751654625
Short name T91
Test name
Test status
Simulation time 251182969 ps
CPU time 6.28 seconds
Started Jun 08 02:55:00 PM PDT 24
Finished Jun 08 02:55:07 PM PDT 24
Peak memory 208268 kb
Host smart-4b64bcfb-9571-42ef-849e-fefeefbbe90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751654625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1751654625
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.485214797
Short name T769
Test name
Test status
Simulation time 117422097 ps
CPU time 5.15 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:11 PM PDT 24
Peak memory 222412 kb
Host smart-6cdec2bf-e033-4a6a-887d-527124d1c1b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485214797 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.485214797
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.897201494
Short name T84
Test name
Test status
Simulation time 3890204313 ps
CPU time 69.5 seconds
Started Jun 08 02:55:07 PM PDT 24
Finished Jun 08 02:56:17 PM PDT 24
Peak memory 209380 kb
Host smart-bacf9327-1fd7-43f2-8760-3c3b3eabce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897201494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.897201494
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2214318577
Short name T683
Test name
Test status
Simulation time 558427946 ps
CPU time 2.23 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:06 PM PDT 24
Peak memory 209372 kb
Host smart-96f6c5ce-2cee-441e-8524-b4842d21fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214318577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2214318577
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1515830197
Short name T995
Test name
Test status
Simulation time 20564621 ps
CPU time 0.8 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:55:11 PM PDT 24
Peak memory 205592 kb
Host smart-9a31f80a-4c24-4152-b1f8-1df17115f061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515830197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1515830197
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.104882672
Short name T435
Test name
Test status
Simulation time 48141192 ps
CPU time 3.41 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:10 PM PDT 24
Peak memory 213976 kb
Host smart-351f070b-5a93-4b01-9e36-695e0807e819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104882672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.104882672
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.117352850
Short name T218
Test name
Test status
Simulation time 101453075 ps
CPU time 2.39 seconds
Started Jun 08 02:55:08 PM PDT 24
Finished Jun 08 02:55:11 PM PDT 24
Peak memory 214492 kb
Host smart-f9b51687-da05-4b9e-a694-b5b13eb6ed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117352850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.117352850
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.412666020
Short name T53
Test name
Test status
Simulation time 23929152 ps
CPU time 1.6 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 207268 kb
Host smart-a3e21cf8-2ce5-4367-ba3c-92345c63f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412666020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.412666020
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.369465522
Short name T94
Test name
Test status
Simulation time 483588340 ps
CPU time 4.78 seconds
Started Jun 08 02:55:11 PM PDT 24
Finished Jun 08 02:55:16 PM PDT 24
Peak memory 213976 kb
Host smart-f6049c27-4fb5-458d-830e-b43ff545caa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369465522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.369465522
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1600097090
Short name T255
Test name
Test status
Simulation time 183055037 ps
CPU time 7.61 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:55:18 PM PDT 24
Peak memory 209440 kb
Host smart-88b2c369-671a-4b49-b74d-e69b24de3a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600097090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1600097090
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2456697682
Short name T381
Test name
Test status
Simulation time 102381297 ps
CPU time 4.88 seconds
Started Jun 08 02:55:12 PM PDT 24
Finished Jun 08 02:55:17 PM PDT 24
Peak memory 219876 kb
Host smart-efe32527-2f5e-4a40-9076-779406adf27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456697682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2456697682
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1963244701
Short name T864
Test name
Test status
Simulation time 956727974 ps
CPU time 27.6 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:34 PM PDT 24
Peak memory 208536 kb
Host smart-db359a07-f60b-43fb-ba83-ff24730fc178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963244701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1963244701
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.730662179
Short name T822
Test name
Test status
Simulation time 148568121 ps
CPU time 2.57 seconds
Started Jun 08 02:55:05 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 208112 kb
Host smart-5c219a99-06ba-435b-872f-a3dcbd5c33bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730662179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.730662179
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3007258878
Short name T1051
Test name
Test status
Simulation time 93338145 ps
CPU time 2.05 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 208436 kb
Host smart-13c70cad-19bc-4a47-b098-4620a9c90aea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007258878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3007258878
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4213015490
Short name T357
Test name
Test status
Simulation time 188611293 ps
CPU time 5.81 seconds
Started Jun 08 02:55:07 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 208100 kb
Host smart-c4991160-ac6b-4c0c-8bf4-53b082bc0f9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213015490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4213015490
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3280631731
Short name T744
Test name
Test status
Simulation time 27781158 ps
CPU time 1.91 seconds
Started Jun 08 02:55:06 PM PDT 24
Finished Jun 08 02:55:08 PM PDT 24
Peak memory 206592 kb
Host smart-f2c145bb-92cb-4056-ae1f-772ac8d1bfd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280631731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3280631731
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1815590019
Short name T827
Test name
Test status
Simulation time 54482722 ps
CPU time 1.99 seconds
Started Jun 08 02:55:11 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 207780 kb
Host smart-409ce390-9021-4e7b-8332-e01ded5f7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815590019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1815590019
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3611107802
Short name T920
Test name
Test status
Simulation time 199186409 ps
CPU time 5.87 seconds
Started Jun 08 02:55:04 PM PDT 24
Finished Jun 08 02:55:10 PM PDT 24
Peak memory 207876 kb
Host smart-90084e44-1199-411c-9372-33f8f93d847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611107802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3611107802
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2965277287
Short name T383
Test name
Test status
Simulation time 3796134524 ps
CPU time 37.45 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:55:48 PM PDT 24
Peak memory 221768 kb
Host smart-808c1d3b-55f1-40ef-bc38-7ff312245527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965277287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2965277287
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2404105403
Short name T740
Test name
Test status
Simulation time 855879478 ps
CPU time 6.75 seconds
Started Jun 08 02:55:16 PM PDT 24
Finished Jun 08 02:55:23 PM PDT 24
Peak memory 222400 kb
Host smart-1c4185e6-94a6-4230-9a67-1b22342dbea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404105403 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2404105403
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.77420790
Short name T824
Test name
Test status
Simulation time 296689244 ps
CPU time 2.93 seconds
Started Jun 08 02:55:09 PM PDT 24
Finished Jun 08 02:55:12 PM PDT 24
Peak memory 209920 kb
Host smart-78fa8ce7-f5af-4937-99bd-85d51640337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77420790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.77420790
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1304609019
Short name T830
Test name
Test status
Simulation time 79239820 ps
CPU time 2.33 seconds
Started Jun 08 02:55:11 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 209656 kb
Host smart-f909a7e3-0f62-4625-8f49-d6bda10d0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304609019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1304609019
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.167413909
Short name T585
Test name
Test status
Simulation time 21201119 ps
CPU time 1.05 seconds
Started Jun 08 02:55:16 PM PDT 24
Finished Jun 08 02:55:17 PM PDT 24
Peak memory 205796 kb
Host smart-5db99485-9e39-436f-ba7c-347cb7c8a9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167413909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.167413909
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.504303913
Short name T37
Test name
Test status
Simulation time 30698827 ps
CPU time 1.92 seconds
Started Jun 08 02:55:14 PM PDT 24
Finished Jun 08 02:55:16 PM PDT 24
Peak memory 208352 kb
Host smart-184a6138-f66b-4f4b-aba5-27ca9d30c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504303913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.504303913
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1810258030
Short name T810
Test name
Test status
Simulation time 11530711827 ps
CPU time 38.74 seconds
Started Jun 08 02:55:09 PM PDT 24
Finished Jun 08 02:55:48 PM PDT 24
Peak memory 214076 kb
Host smart-9fd630b9-88f3-47cc-b8e6-a11e8752715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810258030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1810258030
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2496108371
Short name T101
Test name
Test status
Simulation time 205800470 ps
CPU time 5.06 seconds
Started Jun 08 02:55:12 PM PDT 24
Finished Jun 08 02:55:17 PM PDT 24
Peak memory 214020 kb
Host smart-af66a70c-b5b3-4c33-87bf-abdf11761a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496108371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2496108371
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2658208999
Short name T314
Test name
Test status
Simulation time 9480399734 ps
CPU time 42.66 seconds
Started Jun 08 02:55:14 PM PDT 24
Finished Jun 08 02:55:57 PM PDT 24
Peak memory 222128 kb
Host smart-8e24a0bc-2f51-4e98-8fec-bb4ac1736b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658208999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2658208999
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2287842862
Short name T1063
Test name
Test status
Simulation time 407398590 ps
CPU time 3.89 seconds
Started Jun 08 02:55:11 PM PDT 24
Finished Jun 08 02:55:15 PM PDT 24
Peak memory 214048 kb
Host smart-03dd05c5-08a2-4ef2-a945-bc4e0ddd5a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287842862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2287842862
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.708984996
Short name T731
Test name
Test status
Simulation time 11477960741 ps
CPU time 28.83 seconds
Started Jun 08 02:55:12 PM PDT 24
Finished Jun 08 02:55:41 PM PDT 24
Peak memory 209452 kb
Host smart-600436ff-66b8-489d-b571-1b1719fa9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708984996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.708984996
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3777380542
Short name T765
Test name
Test status
Simulation time 9408957473 ps
CPU time 57.62 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:56:08 PM PDT 24
Peak memory 208680 kb
Host smart-6fc39d29-7ed5-4376-a2f8-d7c5d19f3782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777380542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3777380542
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4216565996
Short name T950
Test name
Test status
Simulation time 133652543 ps
CPU time 2.05 seconds
Started Jun 08 02:55:11 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 208276 kb
Host smart-f3895515-605a-439d-bff3-5e5c5db8e5ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216565996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4216565996
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.475802055
Short name T206
Test name
Test status
Simulation time 255559127 ps
CPU time 6.78 seconds
Started Jun 08 02:55:12 PM PDT 24
Finished Jun 08 02:55:19 PM PDT 24
Peak memory 207604 kb
Host smart-62ab544d-2a79-406d-808e-8d4c9cca7556
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475802055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.475802055
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2971737159
Short name T714
Test name
Test status
Simulation time 229337838 ps
CPU time 3.24 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:55:13 PM PDT 24
Peak memory 208332 kb
Host smart-47fa15c5-2538-4b0d-911e-f0a407796b46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971737159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2971737159
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3420362044
Short name T89
Test name
Test status
Simulation time 380253229 ps
CPU time 4.07 seconds
Started Jun 08 02:55:14 PM PDT 24
Finished Jun 08 02:55:18 PM PDT 24
Peak memory 209680 kb
Host smart-7046e428-a6a6-4d11-8dc3-70d7be7fae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420362044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3420362044
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.9186968
Short name T584
Test name
Test status
Simulation time 187286518 ps
CPU time 5 seconds
Started Jun 08 02:55:10 PM PDT 24
Finished Jun 08 02:55:15 PM PDT 24
Peak memory 208224 kb
Host smart-bd7c09a4-e681-4a94-a11b-c428921c16e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9186968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.9186968
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.632362210
Short name T346
Test name
Test status
Simulation time 650633484 ps
CPU time 14.04 seconds
Started Jun 08 02:55:18 PM PDT 24
Finished Jun 08 02:55:32 PM PDT 24
Peak memory 222264 kb
Host smart-968511b9-c3aa-4897-b427-1653647b6409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632362210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.632362210
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2072184535
Short name T870
Test name
Test status
Simulation time 1011377926 ps
CPU time 7.58 seconds
Started Jun 08 02:55:13 PM PDT 24
Finished Jun 08 02:55:21 PM PDT 24
Peak memory 217820 kb
Host smart-07fa0140-9774-4861-b3e9-28574e3f14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072184535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2072184535
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3941751837
Short name T175
Test name
Test status
Simulation time 522401585 ps
CPU time 12.82 seconds
Started Jun 08 02:55:13 PM PDT 24
Finished Jun 08 02:55:26 PM PDT 24
Peak memory 209948 kb
Host smart-4a00e7e8-fdca-49aa-8a85-6d2003dd3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941751837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3941751837
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1351657609
Short name T914
Test name
Test status
Simulation time 113815383 ps
CPU time 0.83 seconds
Started Jun 08 02:51:18 PM PDT 24
Finished Jun 08 02:51:19 PM PDT 24
Peak memory 205584 kb
Host smart-c5e9cb3a-42a2-4e23-8157-93e5da193796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351657609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1351657609
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3253334660
Short name T892
Test name
Test status
Simulation time 69569849 ps
CPU time 3.37 seconds
Started Jun 08 02:51:15 PM PDT 24
Finished Jun 08 02:51:19 PM PDT 24
Peak memory 215000 kb
Host smart-7ae8bbec-81bd-4a04-8431-4ac0152a43b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253334660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3253334660
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1241788227
Short name T27
Test name
Test status
Simulation time 223335919 ps
CPU time 4.09 seconds
Started Jun 08 02:51:18 PM PDT 24
Finished Jun 08 02:51:22 PM PDT 24
Peak memory 222548 kb
Host smart-2d9007d0-d6f2-4761-a8b7-35e3f57f8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241788227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1241788227
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2928596015
Short name T367
Test name
Test status
Simulation time 356696400 ps
CPU time 10.06 seconds
Started Jun 08 02:51:12 PM PDT 24
Finished Jun 08 02:51:22 PM PDT 24
Peak memory 218000 kb
Host smart-6d49caf6-f7b5-498f-b9bb-6307671f507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928596015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2928596015
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1125272291
Short name T22
Test name
Test status
Simulation time 175456307 ps
CPU time 5.28 seconds
Started Jun 08 02:51:13 PM PDT 24
Finished Jun 08 02:51:18 PM PDT 24
Peak memory 218680 kb
Host smart-2bf9f5ef-08b3-468f-a46b-653b8f03a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125272291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1125272291
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3811624448
Short name T759
Test name
Test status
Simulation time 116701674 ps
CPU time 4.27 seconds
Started Jun 08 02:51:16 PM PDT 24
Finished Jun 08 02:51:21 PM PDT 24
Peak memory 214284 kb
Host smart-452f43fe-c361-47b2-8d73-13882122c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811624448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3811624448
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2447334129
Short name T196
Test name
Test status
Simulation time 570377623 ps
CPU time 7.51 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:15 PM PDT 24
Peak memory 206520 kb
Host smart-82294b79-d8f4-4783-9245-d609dbb3f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447334129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2447334129
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4178185878
Short name T136
Test name
Test status
Simulation time 401551788 ps
CPU time 3.77 seconds
Started Jun 08 02:51:14 PM PDT 24
Finished Jun 08 02:51:18 PM PDT 24
Peak memory 208648 kb
Host smart-c1e32ff0-674d-4f2d-ac4d-257ba677aa49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178185878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4178185878
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.416844437
Short name T781
Test name
Test status
Simulation time 36189997 ps
CPU time 2.51 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:11 PM PDT 24
Peak memory 206548 kb
Host smart-bbe70a31-f3d6-414c-a017-69f7f761b762
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416844437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.416844437
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1959566591
Short name T680
Test name
Test status
Simulation time 215803359 ps
CPU time 6.16 seconds
Started Jun 08 02:51:13 PM PDT 24
Finished Jun 08 02:51:20 PM PDT 24
Peak memory 208244 kb
Host smart-ba9a60a5-50ff-422a-a459-b612857fb4eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959566591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1959566591
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.838890359
Short name T789
Test name
Test status
Simulation time 88962716 ps
CPU time 3.69 seconds
Started Jun 08 02:51:17 PM PDT 24
Finished Jun 08 02:51:21 PM PDT 24
Peak memory 209792 kb
Host smart-0736275b-923b-46b5-ac28-3bfa80f31b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838890359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.838890359
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3494803701
Short name T583
Test name
Test status
Simulation time 656935350 ps
CPU time 3.83 seconds
Started Jun 08 02:51:08 PM PDT 24
Finished Jun 08 02:51:12 PM PDT 24
Peak memory 208140 kb
Host smart-df815ed2-356d-4779-8339-5b551cc73d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494803701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3494803701
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2509978073
Short name T313
Test name
Test status
Simulation time 553422578 ps
CPU time 14.21 seconds
Started Jun 08 02:51:18 PM PDT 24
Finished Jun 08 02:51:32 PM PDT 24
Peak memory 222216 kb
Host smart-133c477a-9152-4e47-979b-7f2bc0c7f601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509978073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2509978073
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3559353578
Short name T948
Test name
Test status
Simulation time 654477382 ps
CPU time 6.27 seconds
Started Jun 08 02:51:13 PM PDT 24
Finished Jun 08 02:51:19 PM PDT 24
Peak memory 209772 kb
Host smart-a9d808cb-2997-48d3-8fb2-365c79cb2f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559353578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3559353578
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3843026255
Short name T647
Test name
Test status
Simulation time 202675309 ps
CPU time 2.71 seconds
Started Jun 08 02:51:18 PM PDT 24
Finished Jun 08 02:51:21 PM PDT 24
Peak memory 210464 kb
Host smart-51abc05d-653e-493e-bdd1-59c927d67607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843026255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3843026255
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3103999432
Short name T709
Test name
Test status
Simulation time 28175479 ps
CPU time 0.82 seconds
Started Jun 08 02:51:29 PM PDT 24
Finished Jun 08 02:51:30 PM PDT 24
Peak memory 205596 kb
Host smart-5073e6bf-00aa-46cd-9361-aecbe62b22f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103999432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3103999432
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2679573638
Short name T382
Test name
Test status
Simulation time 88267120 ps
CPU time 4.95 seconds
Started Jun 08 02:51:23 PM PDT 24
Finished Jun 08 02:51:28 PM PDT 24
Peak memory 213976 kb
Host smart-84b1dd3f-4a8d-4055-b6d0-0ebe1990406f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679573638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2679573638
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3161798209
Short name T779
Test name
Test status
Simulation time 82035326 ps
CPU time 1.92 seconds
Started Jun 08 02:51:28 PM PDT 24
Finished Jun 08 02:51:30 PM PDT 24
Peak memory 208820 kb
Host smart-b3ebc764-7242-459b-a528-81e3cfe0f70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161798209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3161798209
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4159042803
Short name T376
Test name
Test status
Simulation time 177580761 ps
CPU time 5.21 seconds
Started Jun 08 02:51:27 PM PDT 24
Finished Jun 08 02:51:32 PM PDT 24
Peak memory 214036 kb
Host smart-c43a0468-1165-4575-a097-f345d9e9814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159042803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4159042803
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1816221756
Short name T373
Test name
Test status
Simulation time 242906132 ps
CPU time 6.13 seconds
Started Jun 08 02:51:27 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 210912 kb
Host smart-c261c91e-69d7-4b75-811d-e345da39fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816221756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1816221756
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2911131079
Short name T44
Test name
Test status
Simulation time 74154987 ps
CPU time 2.78 seconds
Started Jun 08 02:51:27 PM PDT 24
Finished Jun 08 02:51:30 PM PDT 24
Peak memory 207532 kb
Host smart-dca2d80b-6ca4-4b34-94bd-cb5ec5c7af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911131079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2911131079
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2995465055
Short name T4
Test name
Test status
Simulation time 26658908 ps
CPU time 2.2 seconds
Started Jun 08 02:51:23 PM PDT 24
Finished Jun 08 02:51:26 PM PDT 24
Peak memory 207216 kb
Host smart-752d7d45-d65f-482e-9ba2-7891e2f014df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995465055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2995465055
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2389406524
Short name T295
Test name
Test status
Simulation time 311560574 ps
CPU time 2.9 seconds
Started Jun 08 02:51:22 PM PDT 24
Finished Jun 08 02:51:25 PM PDT 24
Peak memory 206508 kb
Host smart-ce35562d-ad62-4d9f-b970-5e46aed86ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389406524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2389406524
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3035569923
Short name T621
Test name
Test status
Simulation time 189259684 ps
CPU time 5.43 seconds
Started Jun 08 02:51:23 PM PDT 24
Finished Jun 08 02:51:29 PM PDT 24
Peak memory 208260 kb
Host smart-8b397966-83ac-4681-b501-57f754093b50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035569923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3035569923
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2994147968
Short name T751
Test name
Test status
Simulation time 40943833 ps
CPU time 2.41 seconds
Started Jun 08 02:51:21 PM PDT 24
Finished Jun 08 02:51:23 PM PDT 24
Peak memory 206396 kb
Host smart-be7ee920-6837-4d01-8644-b6d90a33ae20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994147968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2994147968
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2440841468
Short name T85
Test name
Test status
Simulation time 147411935 ps
CPU time 2.41 seconds
Started Jun 08 02:51:23 PM PDT 24
Finished Jun 08 02:51:25 PM PDT 24
Peak memory 206516 kb
Host smart-b0fc480d-7ad6-4dad-9645-dccf9d572cc1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440841468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2440841468
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1872241505
Short name T925
Test name
Test status
Simulation time 284504112 ps
CPU time 3.2 seconds
Started Jun 08 02:51:30 PM PDT 24
Finished Jun 08 02:51:33 PM PDT 24
Peak memory 209124 kb
Host smart-e5bc0d72-b4e4-47b5-b17f-6a5f0801872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872241505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1872241505
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3642434985
Short name T1009
Test name
Test status
Simulation time 222063221 ps
CPU time 5.09 seconds
Started Jun 08 02:51:17 PM PDT 24
Finished Jun 08 02:51:23 PM PDT 24
Peak memory 207324 kb
Host smart-5d934ce7-b30a-4a5b-b587-678991735fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642434985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3642434985
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.707323826
Short name T861
Test name
Test status
Simulation time 1077509624 ps
CPU time 13.18 seconds
Started Jun 08 02:51:29 PM PDT 24
Finished Jun 08 02:51:43 PM PDT 24
Peak memory 208240 kb
Host smart-918c8865-f095-4fbf-817a-37c20ecde120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707323826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.707323826
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2906535801
Short name T272
Test name
Test status
Simulation time 635376843 ps
CPU time 7.81 seconds
Started Jun 08 02:51:26 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 218204 kb
Host smart-5e1a64ff-af17-4609-82de-da8b0ec2b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906535801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2906535801
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3025360581
Short name T607
Test name
Test status
Simulation time 42843749 ps
CPU time 2.66 seconds
Started Jun 08 02:51:31 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 209980 kb
Host smart-7ae6b827-abe9-44c8-b8f3-b6ef85097a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025360581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3025360581
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.137535905
Short name T800
Test name
Test status
Simulation time 16406010 ps
CPU time 0.7 seconds
Started Jun 08 02:51:31 PM PDT 24
Finished Jun 08 02:51:32 PM PDT 24
Peak memory 205604 kb
Host smart-2dd40e66-8d49-4a65-82ef-e9f9350e07a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137535905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.137535905
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1155289602
Short name T306
Test name
Test status
Simulation time 76335669 ps
CPU time 4.36 seconds
Started Jun 08 02:51:29 PM PDT 24
Finished Jun 08 02:51:34 PM PDT 24
Peak memory 214568 kb
Host smart-fbe1b603-cbcd-472a-9153-feaf46e765ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155289602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1155289602
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1325240552
Short name T31
Test name
Test status
Simulation time 106778238 ps
CPU time 4.34 seconds
Started Jun 08 02:51:31 PM PDT 24
Finished Jun 08 02:51:36 PM PDT 24
Peak memory 220692 kb
Host smart-af67d72b-c2cc-4a88-9d1c-79fa8986ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325240552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1325240552
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3065750248
Short name T674
Test name
Test status
Simulation time 136787112 ps
CPU time 2.38 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 209708 kb
Host smart-ed4363d5-fa87-4d8d-b46a-8897addfbfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065750248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3065750248
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2512876660
Short name T384
Test name
Test status
Simulation time 384760898 ps
CPU time 3.63 seconds
Started Jun 08 02:51:31 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 208404 kb
Host smart-61b99efe-7bab-4ad0-b200-69510436909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512876660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2512876660
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1047964865
Short name T1061
Test name
Test status
Simulation time 766370455 ps
CPU time 3.71 seconds
Started Jun 08 02:51:33 PM PDT 24
Finished Jun 08 02:51:37 PM PDT 24
Peak memory 222164 kb
Host smart-af5824b1-c6b4-409e-a78a-12136ab0379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047964865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1047964865
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1422479428
Short name T945
Test name
Test status
Simulation time 47325666 ps
CPU time 3 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 207096 kb
Host smart-ced7ceb3-4f38-4610-ac03-d74af92d43ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422479428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1422479428
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3280714653
Short name T342
Test name
Test status
Simulation time 65364922 ps
CPU time 4.11 seconds
Started Jun 08 02:51:28 PM PDT 24
Finished Jun 08 02:51:32 PM PDT 24
Peak memory 218928 kb
Host smart-3cb0c55d-2b82-4069-bd2e-c055d3fdef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280714653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3280714653
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1013241529
Short name T15
Test name
Test status
Simulation time 225148670 ps
CPU time 2.87 seconds
Started Jun 08 02:51:29 PM PDT 24
Finished Jun 08 02:51:32 PM PDT 24
Peak memory 208160 kb
Host smart-6683c087-5cf9-41b9-9ac0-6ccd390de4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013241529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1013241529
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2509693303
Short name T1032
Test name
Test status
Simulation time 6175430238 ps
CPU time 36.73 seconds
Started Jun 08 02:51:28 PM PDT 24
Finished Jun 08 02:52:05 PM PDT 24
Peak memory 208756 kb
Host smart-08b093fa-87bc-42d2-a407-3da9e3f9af5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509693303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2509693303
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1016135942
Short name T991
Test name
Test status
Simulation time 1150701735 ps
CPU time 8.65 seconds
Started Jun 08 02:51:28 PM PDT 24
Finished Jun 08 02:51:37 PM PDT 24
Peak memory 207572 kb
Host smart-fd5df3f4-92e8-44af-9132-215b94d839ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016135942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1016135942
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4049217048
Short name T853
Test name
Test status
Simulation time 159911149 ps
CPU time 5.1 seconds
Started Jun 08 02:51:27 PM PDT 24
Finished Jun 08 02:51:33 PM PDT 24
Peak memory 207520 kb
Host smart-04693a62-a571-4905-bfe7-7c6c153361b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049217048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4049217048
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3254396367
Short name T636
Test name
Test status
Simulation time 106699057 ps
CPU time 3.94 seconds
Started Jun 08 02:51:34 PM PDT 24
Finished Jun 08 02:51:38 PM PDT 24
Peak memory 215380 kb
Host smart-b10fdce4-6e0e-48ea-842a-afb4274d7864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254396367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3254396367
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2655817154
Short name T842
Test name
Test status
Simulation time 3778896100 ps
CPU time 40.53 seconds
Started Jun 08 02:51:28 PM PDT 24
Finished Jun 08 02:52:09 PM PDT 24
Peak memory 207548 kb
Host smart-4f7c5211-c7e6-4f90-8e95-1d657bf54fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655817154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2655817154
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1286895553
Short name T1010
Test name
Test status
Simulation time 1143499986 ps
CPU time 42.68 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:52:15 PM PDT 24
Peak memory 215444 kb
Host smart-f22b1c84-c52d-4659-b7f5-0537dd07746f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286895553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1286895553
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1002653896
Short name T1055
Test name
Test status
Simulation time 255369057 ps
CPU time 6.23 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:39 PM PDT 24
Peak memory 219816 kb
Host smart-05ff4590-4f2b-4443-933f-cf443dd7b00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002653896 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1002653896
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3563524321
Short name T856
Test name
Test status
Simulation time 108179498 ps
CPU time 3.91 seconds
Started Jun 08 02:51:36 PM PDT 24
Finished Jun 08 02:51:40 PM PDT 24
Peak memory 209508 kb
Host smart-5d17560b-a9d0-4541-82e9-f9a73fddc72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563524321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3563524321
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2852198366
Short name T1013
Test name
Test status
Simulation time 376445423 ps
CPU time 2.35 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 210104 kb
Host smart-57f88dee-4534-497d-9aab-6e3e5345111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852198366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2852198366
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2332957204
Short name T743
Test name
Test status
Simulation time 14420033 ps
CPU time 0.74 seconds
Started Jun 08 02:51:41 PM PDT 24
Finished Jun 08 02:51:42 PM PDT 24
Peak memory 205592 kb
Host smart-d56ac876-b638-46b6-a7f6-aa75f396c02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332957204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2332957204
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1149308634
Short name T320
Test name
Test status
Simulation time 372650892 ps
CPU time 4.38 seconds
Started Jun 08 02:51:35 PM PDT 24
Finished Jun 08 02:51:40 PM PDT 24
Peak memory 214044 kb
Host smart-f8e8b259-297b-4824-99e8-bdfe1e5e00d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149308634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1149308634
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2231169346
Short name T10
Test name
Test status
Simulation time 285138408 ps
CPU time 4.34 seconds
Started Jun 08 02:51:38 PM PDT 24
Finished Jun 08 02:51:43 PM PDT 24
Peak memory 210268 kb
Host smart-60a94138-7b8a-47eb-8b01-19cded0f5116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231169346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2231169346
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1780654711
Short name T72
Test name
Test status
Simulation time 39263841 ps
CPU time 2.61 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 219288 kb
Host smart-a3804fe5-15d9-46cd-a03d-5eb539634f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780654711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1780654711
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1010574070
Short name T96
Test name
Test status
Simulation time 350539756 ps
CPU time 3.85 seconds
Started Jun 08 02:51:40 PM PDT 24
Finished Jun 08 02:51:44 PM PDT 24
Peak memory 219976 kb
Host smart-8a7d83ad-00c0-4d98-9e36-d35029c85cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010574070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1010574070
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.934569713
Short name T100
Test name
Test status
Simulation time 520734145 ps
CPU time 13.11 seconds
Started Jun 08 02:51:39 PM PDT 24
Finished Jun 08 02:51:52 PM PDT 24
Peak memory 213960 kb
Host smart-ce8c4846-69a8-4d7f-a593-c1adbaddb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934569713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.934569713
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3839756185
Short name T672
Test name
Test status
Simulation time 102043804 ps
CPU time 2.17 seconds
Started Jun 08 02:51:35 PM PDT 24
Finished Jun 08 02:51:38 PM PDT 24
Peak memory 217460 kb
Host smart-0cef187c-8b56-4a4d-b9d5-ca9ac7728fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839756185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3839756185
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4054652377
Short name T1029
Test name
Test status
Simulation time 622834625 ps
CPU time 7.71 seconds
Started Jun 08 02:51:33 PM PDT 24
Finished Jun 08 02:51:41 PM PDT 24
Peak memory 209472 kb
Host smart-7172c0c3-4ddb-421a-96f5-de50ee19ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054652377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4054652377
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2996437215
Short name T1027
Test name
Test status
Simulation time 238531553 ps
CPU time 2.7 seconds
Started Jun 08 02:51:33 PM PDT 24
Finished Jun 08 02:51:36 PM PDT 24
Peak memory 207152 kb
Host smart-4cc8f662-2f6a-4ae9-a110-ef2403e5ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996437215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2996437215
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.293771403
Short name T906
Test name
Test status
Simulation time 1050064995 ps
CPU time 10.22 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:42 PM PDT 24
Peak memory 208472 kb
Host smart-d0a41e0a-48c9-4f9f-8330-b0e1ef8c5e98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293771403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.293771403
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3494881570
Short name T773
Test name
Test status
Simulation time 245913320 ps
CPU time 7.53 seconds
Started Jun 08 02:51:33 PM PDT 24
Finished Jun 08 02:51:40 PM PDT 24
Peak memory 208648 kb
Host smart-55f36e47-1d3e-413b-8db8-ceb5837a6e26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494881570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3494881570
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.760837129
Short name T412
Test name
Test status
Simulation time 45401544 ps
CPU time 2.5 seconds
Started Jun 08 02:51:32 PM PDT 24
Finished Jun 08 02:51:35 PM PDT 24
Peak memory 207264 kb
Host smart-6a92f831-5da5-4a1e-b47f-4df58e6001c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760837129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.760837129
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1710684867
Short name T290
Test name
Test status
Simulation time 153974690 ps
CPU time 2.82 seconds
Started Jun 08 02:51:35 PM PDT 24
Finished Jun 08 02:51:38 PM PDT 24
Peak memory 209164 kb
Host smart-76533fdb-459f-4172-bc06-94ff8b0e6d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710684867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1710684867
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.983100485
Short name T960
Test name
Test status
Simulation time 427659838 ps
CPU time 3.25 seconds
Started Jun 08 02:51:34 PM PDT 24
Finished Jun 08 02:51:37 PM PDT 24
Peak memory 206980 kb
Host smart-596bf5f9-a378-477f-8ef6-a94683135bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983100485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.983100485
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1476976640
Short name T216
Test name
Test status
Simulation time 3209135197 ps
CPU time 73.73 seconds
Started Jun 08 02:51:36 PM PDT 24
Finished Jun 08 02:52:50 PM PDT 24
Peak memory 220608 kb
Host smart-aaa76ea6-6027-481d-a8cf-1dad12a75037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476976640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1476976640
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2911934609
Short name T1014
Test name
Test status
Simulation time 1114203852 ps
CPU time 3.96 seconds
Started Jun 08 02:51:44 PM PDT 24
Finished Jun 08 02:51:49 PM PDT 24
Peak memory 222408 kb
Host smart-2b295503-8284-41c5-a54d-ef1b15279909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911934609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2911934609
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.113602937
Short name T893
Test name
Test status
Simulation time 76888546 ps
CPU time 4.42 seconds
Started Jun 08 02:51:38 PM PDT 24
Finished Jun 08 02:51:43 PM PDT 24
Peak memory 214200 kb
Host smart-4063549c-1b8b-4717-abbe-25040ee562a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113602937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.113602937
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.818054681
Short name T168
Test name
Test status
Simulation time 51818943 ps
CPU time 1.56 seconds
Started Jun 08 02:51:37 PM PDT 24
Finished Jun 08 02:51:38 PM PDT 24
Peak memory 209776 kb
Host smart-d858d8dc-20b3-4857-95a8-2d822d3317fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818054681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.818054681
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2676235216
Short name T679
Test name
Test status
Simulation time 31550561 ps
CPU time 0.83 seconds
Started Jun 08 02:51:53 PM PDT 24
Finished Jun 08 02:51:54 PM PDT 24
Peak memory 205580 kb
Host smart-41eb3dc0-8fad-4e5e-aa02-e2075fdc33fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676235216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2676235216
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3423620369
Short name T394
Test name
Test status
Simulation time 2791584578 ps
CPU time 68.38 seconds
Started Jun 08 02:51:43 PM PDT 24
Finished Jun 08 02:52:52 PM PDT 24
Peak memory 222216 kb
Host smart-fb9405f5-4e44-45f8-a806-511c4ac898de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423620369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3423620369
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1744858940
Short name T1059
Test name
Test status
Simulation time 296904257 ps
CPU time 10.54 seconds
Started Jun 08 02:51:41 PM PDT 24
Finished Jun 08 02:51:52 PM PDT 24
Peak memory 222400 kb
Host smart-2d656bd9-139d-4959-8fb3-e3d7bc45b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744858940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1744858940
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3907866245
Short name T597
Test name
Test status
Simulation time 566420737 ps
CPU time 4.18 seconds
Started Jun 08 02:51:42 PM PDT 24
Finished Jun 08 02:51:47 PM PDT 24
Peak memory 209384 kb
Host smart-821c4502-208e-4df2-8261-b258d81bc1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907866245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3907866245
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3174378900
Short name T99
Test name
Test status
Simulation time 361151665 ps
CPU time 4.75 seconds
Started Jun 08 02:51:42 PM PDT 24
Finished Jun 08 02:51:47 PM PDT 24
Peak memory 214024 kb
Host smart-6d244a04-14c6-4373-8e9b-ef32080a0462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174378900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3174378900
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4045935428
Short name T688
Test name
Test status
Simulation time 159765275 ps
CPU time 3.01 seconds
Started Jun 08 02:51:45 PM PDT 24
Finished Jun 08 02:51:48 PM PDT 24
Peak memory 208876 kb
Host smart-7932b5ff-dfb7-47ec-8d7c-1ec416ab6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045935428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4045935428
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2290450128
Short name T676
Test name
Test status
Simulation time 1324464899 ps
CPU time 15.28 seconds
Started Jun 08 02:51:41 PM PDT 24
Finished Jun 08 02:51:57 PM PDT 24
Peak memory 208800 kb
Host smart-0f63dd53-04bc-496d-80b4-6d3a378bb883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290450128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2290450128
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1282916805
Short name T661
Test name
Test status
Simulation time 24550627 ps
CPU time 2.09 seconds
Started Jun 08 02:51:41 PM PDT 24
Finished Jun 08 02:51:43 PM PDT 24
Peak memory 208452 kb
Host smart-cce7580a-26ff-41c7-a395-381fffce74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282916805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1282916805
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3357876868
Short name T705
Test name
Test status
Simulation time 809212746 ps
CPU time 17.36 seconds
Started Jun 08 02:51:45 PM PDT 24
Finished Jun 08 02:52:02 PM PDT 24
Peak memory 208068 kb
Host smart-a3aaae99-6b17-4a48-828c-41c830fa9011
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357876868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3357876868
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.238104509
Short name T574
Test name
Test status
Simulation time 116516133 ps
CPU time 3.38 seconds
Started Jun 08 02:51:43 PM PDT 24
Finished Jun 08 02:51:46 PM PDT 24
Peak memory 206524 kb
Host smart-e0e228c6-62df-4e03-bbb5-a0a4285677c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238104509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.238104509
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3059472547
Short name T890
Test name
Test status
Simulation time 39318531 ps
CPU time 1.72 seconds
Started Jun 08 02:51:42 PM PDT 24
Finished Jun 08 02:51:44 PM PDT 24
Peak memory 206580 kb
Host smart-14d00bd6-594c-47ea-a02b-adc2810149fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059472547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3059472547
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3581587552
Short name T326
Test name
Test status
Simulation time 91211857 ps
CPU time 4.47 seconds
Started Jun 08 02:51:52 PM PDT 24
Finished Jun 08 02:51:57 PM PDT 24
Peak memory 208704 kb
Host smart-c6e5a51e-c271-4ca5-8e2b-397a8a49d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581587552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3581587552
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1566616506
Short name T981
Test name
Test status
Simulation time 56979773 ps
CPU time 2.73 seconds
Started Jun 08 02:51:41 PM PDT 24
Finished Jun 08 02:51:44 PM PDT 24
Peak memory 207860 kb
Host smart-09e174f9-a278-4257-9a1a-27d980fc988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566616506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1566616506
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3027167687
Short name T78
Test name
Test status
Simulation time 39509823206 ps
CPU time 262.53 seconds
Started Jun 08 02:51:50 PM PDT 24
Finished Jun 08 02:56:12 PM PDT 24
Peak memory 216100 kb
Host smart-60bf3a00-9df3-464f-8c66-a8ce144aeb85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027167687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3027167687
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3441646355
Short name T409
Test name
Test status
Simulation time 729364312 ps
CPU time 11.35 seconds
Started Jun 08 02:51:42 PM PDT 24
Finished Jun 08 02:51:54 PM PDT 24
Peak memory 208012 kb
Host smart-0baf6afc-f154-4dd7-a065-59c2d7da3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441646355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3441646355
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1121680535
Short name T797
Test name
Test status
Simulation time 71034543 ps
CPU time 1.39 seconds
Started Jun 08 02:51:49 PM PDT 24
Finished Jun 08 02:51:50 PM PDT 24
Peak memory 209260 kb
Host smart-62c0c969-2358-4633-8ec7-c04c668e3047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121680535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1121680535
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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