Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::sideload_clear_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	45	0	0.00
Crosses	210	210	0	0.00

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	2	0	0.00	100	1	1	2
aes_sl_avail_cp	2	2	0	0.00	100	1	1	2
kmac_sl_avail	2	2	0	0.00	100	1	1	2
kmac_sl_avail_cp	2	2	0	0.00	100	1	1	2
op	5	5	0	0.00	100	1	1	0
op_cp	5	5	0	0.00	100	1	1	0
otbn_sl_avail	2	2	0	0.00	100	1	1	2
otbn_sl_avail_cp	2	2	0	0.00	100	1	1	2
regwen_cp	2	2	0	0.00	100	1	1	2
sideload_clear	8	8	0	0.00	100	1	1	8
sideload_clear_cp	5	5	0	0.00	100	1	1	0
state	4	4	0	0.00	100	1	1	0
state_cp	4	4	0	0.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	160	160	0	0.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	40	0	0.00	100	1	1	0
sideload_clear_x_regwen_cross	10	10	0	0.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for aes_sl_avail

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for aes_sl_avail_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for kmac_sl_avail

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for kmac_sl_avail_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	5	0	0.00

Automatically Generated Bins for op

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeAdvance]	0	1	1
auto[OpDpeErase]	0	1	1
auto[OpDpeGenSwOut]	0	1	1
auto[OpDpeGenHwOut]	0	1	1
auto[OpDpeDisable]	0	1	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	5	0	0.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeAdvance]	0	1	1
auto[OpDpeErase]	0	1	1
auto[OpDpeGenSwOut]	0	1	1
auto[OpDpeGenHwOut]	0	1	1
auto[OpDpeDisable]	0	1	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for otbn_sl_avail

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for otbn_sl_avail_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for regwen_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	8	0	0.00

Automatically Generated Bins for sideload_clear

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[7]]	--	--	8

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	5	0	0.00

User Defined Bins for sideload_clear_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
clear_all	0	1	1
clear_one[1]	0	1	1
clear_one[2]	0	1	1
clear_one[3]	0	1	1
clear_none	0	1	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	4	0	0.00

Automatically Generated Bins for state

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeReset]	0	1	1
auto[StWorkDpeAvailable]	0	1	1
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	4	0	0.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeReset]	0	1	1
auto[StWorkDpeAvailable]	0	1	1
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	160	0	0.00	160

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
*	*	*	--	--	160

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	40	0	0.00	40

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
*	*	*	*	--	--	40

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	10	0	0.00	10

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Uncovered bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	10