Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
73.67 97.17 89.51 57.52 61.54 93.92 98.34 17.67


Total test records in report: 308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3800535371 Jan 22 12:23:04 PM PST 24 Jan 22 12:23:33 PM PST 24 164800324 ps
T257 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.616274042 Jan 22 12:22:30 PM PST 24 Jan 22 12:23:00 PM PST 24 164644969 ps
T79 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2323912538 Jan 22 12:22:54 PM PST 24 Jan 22 12:23:26 PM PST 24 116776711 ps
T258 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1288574808 Jan 22 12:22:49 PM PST 24 Jan 22 12:23:21 PM PST 24 81698840 ps
T259 /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2977280142 Jan 22 12:22:52 PM PST 24 Jan 22 12:23:22 PM PST 24 12426305 ps
T260 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.33044642 Jan 22 12:21:40 PM PST 24 Jan 22 12:21:47 PM PST 24 75445428 ps
T261 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3746609156 Jan 22 12:38:52 PM PST 24 Jan 22 12:38:54 PM PST 24 174110264 ps
T262 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.3680737814 Jan 22 12:22:57 PM PST 24 Jan 22 12:23:27 PM PST 24 63258058 ps
T263 /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3776446776 Jan 22 12:23:07 PM PST 24 Jan 22 12:23:32 PM PST 24 25532211 ps
T264 /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2687466198 Jan 22 12:42:49 PM PST 24 Jan 22 12:42:51 PM PST 24 35663004 ps
T265 /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1904964366 Jan 22 12:23:07 PM PST 24 Jan 22 12:23:32 PM PST 24 81163137 ps
T266 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.4023138874 Jan 22 12:46:22 PM PST 24 Jan 22 12:46:25 PM PST 24 71657709 ps
T267 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1916270791 Jan 22 12:22:34 PM PST 24 Jan 22 12:23:05 PM PST 24 135838380 ps
T76 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4064425751 Jan 22 12:22:20 PM PST 24 Jan 22 12:22:44 PM PST 24 348473618 ps
T268 /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.96071445 Jan 22 12:22:48 PM PST 24 Jan 22 12:23:19 PM PST 24 50241148 ps
T269 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1771157811 Jan 22 12:22:49 PM PST 24 Jan 22 12:23:22 PM PST 24 446221358 ps
T270 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.3919050944 Jan 22 12:22:29 PM PST 24 Jan 22 12:23:00 PM PST 24 426195820 ps
T271 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1442299402 Jan 22 12:22:41 PM PST 24 Jan 22 12:23:15 PM PST 24 150763033 ps
T272 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.616308556 Jan 22 12:30:58 PM PST 24 Jan 22 12:31:07 PM PST 24 164683754 ps
T273 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2049688948 Jan 22 12:22:42 PM PST 24 Jan 22 12:23:16 PM PST 24 112242763 ps
T274 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.277251815 Jan 22 12:22:30 PM PST 24 Jan 22 12:23:00 PM PST 24 53601260 ps
T275 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2739826460 Jan 22 12:31:05 PM PST 24 Jan 22 12:31:12 PM PST 24 43630584 ps
T276 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2961688040 Jan 22 12:20:41 PM PST 24 Jan 22 12:20:46 PM PST 24 22384589 ps
T277 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1636980585 Jan 22 12:22:31 PM PST 24 Jan 22 12:23:01 PM PST 24 75205923 ps
T278 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.2309117044 Jan 22 12:23:29 PM PST 24 Jan 22 12:23:53 PM PST 24 14363872 ps
T279 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.258304530 Jan 22 12:16:37 PM PST 24 Jan 22 12:16:43 PM PST 24 75445544 ps
T280 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.1874303850 Jan 22 12:22:38 PM PST 24 Jan 22 12:23:09 PM PST 24 22637636 ps
T281 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2653882925 Jan 22 01:22:46 PM PST 24 Jan 22 01:22:47 PM PST 24 24516718 ps
T282 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1443878435 Jan 22 12:22:54 PM PST 24 Jan 22 12:23:23 PM PST 24 112455530 ps
T283 /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1996400313 Jan 22 12:22:35 PM PST 24 Jan 22 12:23:07 PM PST 24 215283685 ps
T284 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.4055482718 Jan 22 12:23:11 PM PST 24 Jan 22 12:23:37 PM PST 24 703461678 ps
T285 /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2562854603 Jan 22 01:10:02 PM PST 24 Jan 22 01:10:22 PM PST 24 12395270 ps
T286 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.324314691 Jan 22 12:22:54 PM PST 24 Jan 22 12:23:25 PM PST 24 459038455 ps
T287 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.176969326 Jan 22 12:23:26 PM PST 24 Jan 22 12:23:50 PM PST 24 12213553 ps
T77 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.2619533973 Jan 22 12:22:36 PM PST 24 Jan 22 12:23:14 PM PST 24 433293888 ps
T288 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.3165799459 Jan 22 12:23:05 PM PST 24 Jan 22 12:23:31 PM PST 24 148522933 ps
T289 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1114059677 Jan 22 12:22:35 PM PST 24 Jan 22 12:23:07 PM PST 24 83124541 ps
T290 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.758280207 Jan 22 12:23:03 PM PST 24 Jan 22 12:23:30 PM PST 24 12174236 ps
T291 /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3842854623 Jan 22 12:23:28 PM PST 24 Jan 22 12:23:52 PM PST 24 24165776 ps
T292 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.2423526907 Jan 22 12:22:18 PM PST 24 Jan 22 12:22:41 PM PST 24 42358414 ps
T293 /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2980125825 Jan 22 12:23:40 PM PST 24 Jan 22 12:24:01 PM PST 24 49650072 ps
T294 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1751694456 Jan 22 12:37:50 PM PST 24 Jan 22 12:37:56 PM PST 24 186561483 ps
T295 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.338919932 Jan 22 12:22:32 PM PST 24 Jan 22 12:23:03 PM PST 24 181666303 ps
T296 /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.3818110410 Jan 22 12:23:30 PM PST 24 Jan 22 12:23:54 PM PST 24 13350678 ps
T297 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3653677554 Jan 22 12:22:53 PM PST 24 Jan 22 12:23:28 PM PST 24 764868932 ps
T74 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.4180165143 Jan 22 12:20:41 PM PST 24 Jan 22 12:20:48 PM PST 24 352867731 ps
T298 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.114408824 Jan 22 12:23:06 PM PST 24 Jan 22 12:23:33 PM PST 24 571000229 ps
T299 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.600520593 Jan 22 12:22:57 PM PST 24 Jan 22 12:23:30 PM PST 24 533205716 ps
T300 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2810689764 Jan 22 12:23:27 PM PST 24 Jan 22 12:23:50 PM PST 24 14082571 ps
T301 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3039200308 Jan 22 12:22:35 PM PST 24 Jan 22 12:23:07 PM PST 24 332190594 ps
T80 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2712317916 Jan 22 12:23:07 PM PST 24 Jan 22 12:23:39 PM PST 24 894841882 ps
T302 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1748437424 Jan 22 12:22:37 PM PST 24 Jan 22 12:23:09 PM PST 24 210918694 ps
T303 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1339457505 Jan 22 12:22:29 PM PST 24 Jan 22 12:22:59 PM PST 24 96909631 ps
T304 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2961311183 Jan 22 12:41:24 PM PST 24 Jan 22 12:41:26 PM PST 24 75265533 ps
T305 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3468936416 Jan 22 12:22:35 PM PST 24 Jan 22 12:23:08 PM PST 24 196756020 ps
T306 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.3109630702 Jan 22 12:51:27 PM PST 24 Jan 22 12:51:29 PM PST 24 32281755 ps
T307 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.845277729 Jan 22 12:22:53 PM PST 24 Jan 22 12:23:24 PM PST 24 303303628 ps
T308 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.1963930642 Jan 22 12:22:53 PM PST 24 Jan 22 12:23:22 PM PST 24 110418106 ps

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.3567196958
Short name T5
Test name
Test status
Simulation time 102791846 ps
CPU time 2.51 seconds
Started Jan 22 04:37:02 PM PST 24
Finished Jan 22 04:37:05 PM PST 24
Peak memory 205284 kb
Host smart-e2127282-1d9f-413c-b204-adafc1fec761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567196958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.3567196958
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.1181708594
Short name T9
Test name
Test status
Simulation time 1414273223 ps
CPU time 20.38 seconds
Started Jan 22 04:35:36 PM PST 24
Finished Jan 22 04:35:57 PM PST 24
Peak memory 234184 kb
Host smart-9a3dd889-9071-47d9-8d3d-17d491c6a86d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181708594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.1181708594
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.304370817
Short name T53
Test name
Test status
Simulation time 365521239 ps
CPU time 5.75 seconds
Started Jan 22 12:15:44 PM PST 24
Finished Jan 22 12:15:58 PM PST 24
Peak memory 213936 kb
Host smart-18301eb6-a1be-48aa-b773-17f238482529
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304370817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.304370817
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.4242840488
Short name T4
Test name
Test status
Simulation time 177905551 ps
CPU time 2.81 seconds
Started Jan 22 04:36:38 PM PST 24
Finished Jan 22 04:36:41 PM PST 24
Peak memory 206968 kb
Host smart-67939dd3-bb3b-4464-af7f-e23ecfeeff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242840488 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.4242840488
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2267320052
Short name T31
Test name
Test status
Simulation time 184423023 ps
CPU time 6.1 seconds
Started Jan 22 12:22:33 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 213680 kb
Host smart-c0b0e807-6438-4b6b-a965-57a8e0487cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267320052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
2267320052
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3827564972
Short name T61
Test name
Test status
Simulation time 404057313 ps
CPU time 4.18 seconds
Started Jan 22 01:04:17 PM PST 24
Finished Jan 22 01:04:22 PM PST 24
Peak memory 213920 kb
Host smart-95771ace-20bb-4707-8554-56ddd2444d2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827564972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.3827564972
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.3410523996
Short name T7
Test name
Test status
Simulation time 162171488 ps
CPU time 3.1 seconds
Started Jan 22 04:35:29 PM PST 24
Finished Jan 22 04:35:32 PM PST 24
Peak memory 205220 kb
Host smart-fbae729f-a5cb-403b-93cf-2d1242c0e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410523996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.3410523996
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3712314262
Short name T6
Test name
Test status
Simulation time 386675124 ps
CPU time 2.97 seconds
Started Jan 22 04:39:50 PM PST 24
Finished Jan 22 04:39:54 PM PST 24
Peak memory 206768 kb
Host smart-b9afa4b8-c26f-4e76-8502-a35165cdf738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712314262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3712314262
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.961792753
Short name T94
Test name
Test status
Simulation time 2148342163 ps
CPU time 17.44 seconds
Started Jan 22 04:36:32 PM PST 24
Finished Jan 22 04:36:50 PM PST 24
Peak memory 206728 kb
Host smart-fc1d1345-f559-4349-a160-b28e0ac12411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961792753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.961792753
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.1248987813
Short name T83
Test name
Test status
Simulation time 37519090 ps
CPU time 0.7 seconds
Started Jan 22 12:23:32 PM PST 24
Finished Jan 22 12:23:56 PM PST 24
Peak memory 205232 kb
Host smart-e7f62168-486a-4c7c-8bac-6564c65a4ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248987813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
1248987813
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.4234354798
Short name T46
Test name
Test status
Simulation time 195077969 ps
CPU time 3.67 seconds
Started Jan 22 12:23:03 PM PST 24
Finished Jan 22 12:23:33 PM PST 24
Peak memory 213348 kb
Host smart-f1f17aff-fd23-4615-979d-161a5d00f69e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234354798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.4234354798
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.1038297364
Short name T150
Test name
Test status
Simulation time 314748509 ps
CPU time 2.71 seconds
Started Jan 22 04:36:54 PM PST 24
Finished Jan 22 04:36:57 PM PST 24
Peak memory 205224 kb
Host smart-40004038-f39f-433c-9062-da6fe3428986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038297364 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.1038297364
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.1428216126
Short name T18
Test name
Test status
Simulation time 178018459 ps
CPU time 0.97 seconds
Started Jan 22 04:35:22 PM PST 24
Finished Jan 22 04:35:24 PM PST 24
Peak memory 204356 kb
Host smart-9fc4f401-53ae-4293-9d70-82683d28c719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428216126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.1
428216126
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1733597178
Short name T114
Test name
Test status
Simulation time 487165637 ps
CPU time 3.22 seconds
Started Jan 22 05:29:36 PM PST 24
Finished Jan 22 05:29:40 PM PST 24
Peak memory 205336 kb
Host smart-b4fe8110-0515-4b0b-b6b9-4698d70dd96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733597178 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1733597178
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.290618554
Short name T1
Test name
Test status
Simulation time 2478726828 ps
CPU time 19.16 seconds
Started Jan 22 04:36:16 PM PST 24
Finished Jan 22 04:36:36 PM PST 24
Peak memory 206976 kb
Host smart-61612dba-6cf2-4e6c-968e-51809965e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290618554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.290618554
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3715952582
Short name T91
Test name
Test status
Simulation time 96775434 ps
CPU time 3.08 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:08 PM PST 24
Peak memory 205368 kb
Host smart-682832f4-349c-4d9b-ac3e-01590ddf10d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715952582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3715952582
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.1484748178
Short name T158
Test name
Test status
Simulation time 119048618 ps
CPU time 2.87 seconds
Started Jan 22 04:35:29 PM PST 24
Finished Jan 22 04:35:32 PM PST 24
Peak memory 205372 kb
Host smart-33bad680-fd01-4823-a1bc-80f5db93b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484748178 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.1484748178
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3936415521
Short name T89
Test name
Test status
Simulation time 645486151 ps
CPU time 3.78 seconds
Started Jan 22 04:35:37 PM PST 24
Finished Jan 22 04:35:42 PM PST 24
Peak memory 206284 kb
Host smart-10b896f4-c81c-434e-a63a-92557ad2dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936415521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3936415521
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2642939644
Short name T81
Test name
Test status
Simulation time 425488870 ps
CPU time 5.61 seconds
Started Jan 22 12:22:48 PM PST 24
Finished Jan 22 12:23:25 PM PST 24
Peak memory 213528 kb
Host smart-4d347b3c-ec48-4ad2-876a-eeb0b6a74f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642939644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2642939644
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3084206597
Short name T86
Test name
Test status
Simulation time 160560470 ps
CPU time 3.21 seconds
Started Jan 22 04:36:53 PM PST 24
Finished Jan 22 04:36:57 PM PST 24
Peak memory 207288 kb
Host smart-13cf0eae-f185-481e-abf0-26249fa3e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084206597 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3084206597
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2128313652
Short name T75
Test name
Test status
Simulation time 184859421 ps
CPU time 4.56 seconds
Started Jan 22 12:22:26 PM PST 24
Finished Jan 22 12:22:59 PM PST 24
Peak memory 214428 kb
Host smart-e9cb2378-3f9b-4131-9a80-a1088ef18207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128313652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.2128313652
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3525181234
Short name T37
Test name
Test status
Simulation time 277487432 ps
CPU time 4.01 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:12 PM PST 24
Peak memory 213244 kb
Host smart-895e63dc-0c41-4a1f-a3bf-71e5ef5cb015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525181234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3525181234
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2542630420
Short name T34
Test name
Test status
Simulation time 115334507 ps
CPU time 2.91 seconds
Started Jan 22 12:40:31 PM PST 24
Finished Jan 22 12:40:35 PM PST 24
Peak memory 213200 kb
Host smart-1934e9c0-476d-4468-8dc8-fe90e618f451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542630420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2542630420
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.3761828835
Short name T47
Test name
Test status
Simulation time 142204544 ps
CPU time 2.51 seconds
Started Jan 22 12:43:23 PM PST 24
Finished Jan 22 12:43:27 PM PST 24
Peak memory 213456 kb
Host smart-f4e274fa-51fb-4b03-8817-8b7db847a7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761828835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.3
761828835
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.135645843
Short name T206
Test name
Test status
Simulation time 10197113 ps
CPU time 0.85 seconds
Started Jan 22 12:50:06 PM PST 24
Finished Jan 22 12:50:08 PM PST 24
Peak memory 205108 kb
Host smart-42db6641-3bd9-462c-a15c-4590d10d2861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135645843 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.135645843
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.2975057585
Short name T26
Test name
Test status
Simulation time 880513529 ps
CPU time 9.69 seconds
Started Jan 22 04:35:32 PM PST 24
Finished Jan 22 04:35:42 PM PST 24
Peak memory 232644 kb
Host smart-d8eb0c11-95e6-4c02-a0b5-224c58b09d0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975057585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.2975057585
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.4180165143
Short name T74
Test name
Test status
Simulation time 352867731 ps
CPU time 2.7 seconds
Started Jan 22 12:20:41 PM PST 24
Finished Jan 22 12:20:48 PM PST 24
Peak memory 213140 kb
Host smart-aa10f6c9-d95e-46a4-8348-ea3f16654d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180165143 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.4180165143
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1528971727
Short name T33
Test name
Test status
Simulation time 214101376 ps
CPU time 7.61 seconds
Started Jan 22 12:22:33 PM PST 24
Finished Jan 22 12:23:10 PM PST 24
Peak memory 214676 kb
Host smart-49114ab9-bf85-438a-9a0a-320632f5e887
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528971727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1528971727
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.541297985
Short name T73
Test name
Test status
Simulation time 124155966 ps
CPU time 4.35 seconds
Started Jan 22 12:41:13 PM PST 24
Finished Jan 22 12:41:18 PM PST 24
Peak memory 214576 kb
Host smart-8d752c5f-d9d1-48f1-a0ce-0a984961e1ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541297985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe
_tl_intg_err.541297985
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.2398127834
Short name T21
Test name
Test status
Simulation time 299917780 ps
CPU time 3.64 seconds
Started Jan 22 12:22:37 PM PST 24
Finished Jan 22 12:23:11 PM PST 24
Peak memory 214776 kb
Host smart-cfbf5b54-6092-46cd-b253-2b4b9b883ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398127834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.2398127834
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2712317916
Short name T80
Test name
Test status
Simulation time 894841882 ps
CPU time 8.31 seconds
Started Jan 22 12:23:07 PM PST 24
Finished Jan 22 12:23:39 PM PST 24
Peak memory 215008 kb
Host smart-f8bf2e8f-5a99-48e3-b61b-e8248858b90d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712317916 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.2712317916
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.258304530
Short name T279
Test name
Test status
Simulation time 75445544 ps
CPU time 1.53 seconds
Started Jan 22 12:16:37 PM PST 24
Finished Jan 22 12:16:43 PM PST 24
Peak memory 218620 kb
Host smart-d0f2bcb0-db33-4692-a4ca-526f925d51e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258304530 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.258304530
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.1460957844
Short name T99
Test name
Test status
Simulation time 895780836 ps
CPU time 5.53 seconds
Started Jan 22 04:35:47 PM PST 24
Finished Jan 22 04:35:56 PM PST 24
Peak memory 207484 kb
Host smart-ea765cb9-28ed-4bb2-883d-d0a76e3abae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460957844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.1460957844
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3271433510
Short name T90
Test name
Test status
Simulation time 231481316 ps
CPU time 6.04 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:11 PM PST 24
Peak memory 207168 kb
Host smart-d2aa5558-6603-4938-9ffd-0598a70359fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271433510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3271433510
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.317522725
Short name T88
Test name
Test status
Simulation time 44296715 ps
CPU time 1.91 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:07 PM PST 24
Peak memory 205628 kb
Host smart-9a048144-1243-454b-afc5-4a5e7b00c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317522725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.317522725
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.106471162
Short name T87
Test name
Test status
Simulation time 1542893942 ps
CPU time 14.08 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:14 PM PST 24
Peak memory 206312 kb
Host smart-b659bedf-3925-40aa-8460-53a3d116ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106471162 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.106471162
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.2245474900
Short name T20
Test name
Test status
Simulation time 35485290 ps
CPU time 2.28 seconds
Started Jan 22 04:58:57 PM PST 24
Finished Jan 22 04:59:00 PM PST 24
Peak memory 206768 kb
Host smart-61e2167e-e0c5-491b-9749-b2d85a96d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245474900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.2245474900
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.1322891492
Short name T169
Test name
Test status
Simulation time 1218254276 ps
CPU time 9.02 seconds
Started Jan 22 12:15:31 PM PST 24
Finished Jan 22 12:15:43 PM PST 24
Peak memory 205452 kb
Host smart-2df5cdd1-e99f-4c0f-808f-c62f52d8e98f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322891492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.1322891492
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2413691140
Short name T183
Test name
Test status
Simulation time 886386169 ps
CPU time 11.63 seconds
Started Jan 22 12:15:30 PM PST 24
Finished Jan 22 12:15:44 PM PST 24
Peak memory 205336 kb
Host smart-82006bcf-ac1f-4e84-8c57-dacd9ebf3702
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413691140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2413691140
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.988223766
Short name T44
Test name
Test status
Simulation time 22373414 ps
CPU time 0.95 seconds
Started Jan 22 12:15:36 PM PST 24
Finished Jan 22 12:15:43 PM PST 24
Peak memory 204596 kb
Host smart-b1f5224e-e0b3-4b22-a27b-650572c34fd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988223766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_hw_reset.988223766
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3746609156
Short name T261
Test name
Test status
Simulation time 174110264 ps
CPU time 1.08 seconds
Started Jan 22 12:38:52 PM PST 24
Finished Jan 22 12:38:54 PM PST 24
Peak memory 205224 kb
Host smart-dd041c06-036d-4db7-9323-de255e156eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746609156 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3
746609156
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.4058583213
Short name T115
Test name
Test status
Simulation time 119247459 ps
CPU time 0.78 seconds
Started Jan 22 01:11:15 PM PST 24
Finished Jan 22 01:11:16 PM PST 24
Peak memory 205140 kb
Host smart-a458387a-d2db-425c-8c93-8cf0b608ca7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058583213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.4
058583213
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2357062528
Short name T170
Test name
Test status
Simulation time 21810062 ps
CPU time 1.26 seconds
Started Jan 22 12:49:50 PM PST 24
Finished Jan 22 12:49:52 PM PST 24
Peak memory 205276 kb
Host smart-c1b38e1c-b43a-4c62-bce1-61921214dd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357062528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2357062528
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.2931553144
Short name T39
Test name
Test status
Simulation time 171504970 ps
CPU time 1.51 seconds
Started Jan 22 12:46:33 PM PST 24
Finished Jan 22 12:46:36 PM PST 24
Peak memory 213968 kb
Host smart-48575cdc-80ef-4ad9-ad0c-fe6984cb19d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931553144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.2931553144
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1315734165
Short name T253
Test name
Test status
Simulation time 177116213 ps
CPU time 2.62 seconds
Started Jan 22 12:52:11 PM PST 24
Finished Jan 22 12:52:16 PM PST 24
Peak memory 205404 kb
Host smart-7a96f5dc-50d2-4e98-bccf-6a0e16e70f61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315734165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.1315734165
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.3607813569
Short name T237
Test name
Test status
Simulation time 615998161 ps
CPU time 11.44 seconds
Started Jan 22 01:03:49 PM PST 24
Finished Jan 22 01:04:01 PM PST 24
Peak memory 205312 kb
Host smart-b08c80a3-48a4-4209-9826-1661675d634b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607813569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.3607813569
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2045289841
Short name T59
Test name
Test status
Simulation time 20867279 ps
CPU time 1 seconds
Started Jan 22 12:15:45 PM PST 24
Finished Jan 22 12:15:53 PM PST 24
Peak memory 205284 kb
Host smart-309fe6a3-08d2-4c8b-b0c9-ef64a07b9158
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045289841 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2045289841
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1777764867
Short name T57
Test name
Test status
Simulation time 35845211 ps
CPU time 0.97 seconds
Started Jan 22 12:41:42 PM PST 24
Finished Jan 22 12:41:45 PM PST 24
Peak memory 205192 kb
Host smart-99a6d09b-7f50-4e63-8d87-d5b179673fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777764867 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.1777764867
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2961688040
Short name T276
Test name
Test status
Simulation time 22384589 ps
CPU time 0.81 seconds
Started Jan 22 12:20:41 PM PST 24
Finished Jan 22 12:20:46 PM PST 24
Peak memory 204740 kb
Host smart-c62427de-d866-4a8c-ba28-2374a0afa6c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961688040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
961688040
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.952410425
Short name T219
Test name
Test status
Simulation time 89027775 ps
CPU time 1.35 seconds
Started Jan 22 12:33:14 PM PST 24
Finished Jan 22 12:33:17 PM PST 24
Peak memory 205488 kb
Host smart-b3c296f5-841b-4b3e-b594-0cc77715a625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952410425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.952410425
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.3371656884
Short name T54
Test name
Test status
Simulation time 117692782 ps
CPU time 1.22 seconds
Started Jan 22 12:16:37 PM PST 24
Finished Jan 22 12:16:43 PM PST 24
Peak memory 213980 kb
Host smart-0d1f21a7-ed4a-4e6b-a95e-35b70442cff7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371656884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.3371656884
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1751694456
Short name T294
Test name
Test status
Simulation time 186561483 ps
CPU time 4.71 seconds
Started Jan 22 12:37:50 PM PST 24
Finished Jan 22 12:37:56 PM PST 24
Peak memory 213892 kb
Host smart-cc4ae0bf-f166-49d5-b813-0afa540677df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751694456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1751694456
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.33044642
Short name T260
Test name
Test status
Simulation time 75445428 ps
CPU time 2 seconds
Started Jan 22 12:21:40 PM PST 24
Finished Jan 22 12:21:47 PM PST 24
Peak memory 213360 kb
Host smart-7b11679c-ae89-4b39-a886-cdd89fb87f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33044642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.33044642
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.646023857
Short name T40
Test name
Test status
Simulation time 257474148 ps
CPU time 1.04 seconds
Started Jan 22 12:22:37 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 213248 kb
Host smart-5a8fed98-b0b1-4ab4-aef4-82738a645d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646023857 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.646023857
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.1675806819
Short name T197
Test name
Test status
Simulation time 45865959 ps
CPU time 1.06 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 205148 kb
Host smart-4e21f898-83e3-4ef7-8500-dbe3861f00d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675806819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
1675806819
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1565434759
Short name T246
Test name
Test status
Simulation time 46517807 ps
CPU time 0.85 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:22:59 PM PST 24
Peak memory 204736 kb
Host smart-9d1bbe58-900b-4507-a37c-ae71149b98f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565434759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
1565434759
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.449479148
Short name T60
Test name
Test status
Simulation time 23035024 ps
CPU time 1.23 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 205108 kb
Host smart-0652db48-8e56-4a61-99eb-6df879d8f4a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449479148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_dpe_same_csr_outstanding.449479148
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.3919040221
Short name T51
Test name
Test status
Simulation time 65475443 ps
CPU time 1.47 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 213784 kb
Host smart-44bbba31-f6f8-44a7-bfed-b82bde0ba6ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919040221 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.3919040221
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1208550639
Short name T226
Test name
Test status
Simulation time 133982601 ps
CPU time 4.06 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 213596 kb
Host smart-56500116-55aa-42fe-b050-d4dd3a92b3be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208550639 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1208550639
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.1788438675
Short name T180
Test name
Test status
Simulation time 46967541 ps
CPU time 1.1 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 205172 kb
Host smart-3b4fee7c-7f16-4dc0-9396-9ca2bd2f33fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788438675 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.1788438675
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.2198908622
Short name T66
Test name
Test status
Simulation time 59762003 ps
CPU time 0.91 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 204896 kb
Host smart-1743ce19-0aec-4470-b63f-b2dc5c2ae670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198908622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
2198908622
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1126969596
Short name T43
Test name
Test status
Simulation time 20807887 ps
CPU time 0.72 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 204788 kb
Host smart-243c0530-fe13-43cb-b06a-adc7427c0a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126969596 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1126969596
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1996400313
Short name T283
Test name
Test status
Simulation time 215283685 ps
CPU time 1.22 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 205080 kb
Host smart-219b12c9-4906-49fc-85a5-a9fe76f8bb64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996400313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1996400313
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1114059677
Short name T289
Test name
Test status
Simulation time 83124541 ps
CPU time 2.15 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 221848 kb
Host smart-c5c3f366-18e8-453c-bc22-b521d23eaab5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114059677 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1114059677
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1080536514
Short name T208
Test name
Test status
Simulation time 539838054 ps
CPU time 5.22 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 213552 kb
Host smart-03f7ac05-9803-4afd-ab94-fa19b154bcca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080536514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1080536514
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2835092493
Short name T244
Test name
Test status
Simulation time 44919214 ps
CPU time 2.63 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:24 PM PST 24
Peak memory 216616 kb
Host smart-963ca89d-8345-4f2e-9792-251f8f4675fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835092493 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2835092493
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3183047245
Short name T41
Test name
Test status
Simulation time 21279694 ps
CPU time 1.19 seconds
Started Jan 22 12:22:52 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 220908 kb
Host smart-2d149d85-a358-44bd-ab29-39a4c054b9b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183047245 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3183047245
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.1963930642
Short name T308
Test name
Test status
Simulation time 110418106 ps
CPU time 0.85 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 204840 kb
Host smart-06c69aaa-1cf3-45e4-941a-e0523d1bad4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963930642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
1963930642
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.96071445
Short name T268
Test name
Test status
Simulation time 50241148 ps
CPU time 0.85 seconds
Started Jan 22 12:22:48 PM PST 24
Finished Jan 22 12:23:19 PM PST 24
Peak memory 204928 kb
Host smart-484ca638-b617-420e-8faa-fc78321ee7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96071445 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.96071445
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.3787734225
Short name T242
Test name
Test status
Simulation time 30294760 ps
CPU time 1.6 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:23 PM PST 24
Peak memory 205208 kb
Host smart-2189c216-8357-4d74-b3d3-13394f84a18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787734225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.3787734225
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1333642146
Short name T173
Test name
Test status
Simulation time 115621400 ps
CPU time 3.22 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 217912 kb
Host smart-716afb3d-99fe-4d4c-938d-7da4a41b8381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333642146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1333642146
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3653677554
Short name T297
Test name
Test status
Simulation time 764868932 ps
CPU time 7 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:28 PM PST 24
Peak memory 213132 kb
Host smart-4057ec21-11cc-40e3-9140-0c0eca93eda2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653677554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3653677554
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1916270791
Short name T267
Test name
Test status
Simulation time 135838380 ps
CPU time 1.93 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 215404 kb
Host smart-44cd417b-cee2-4078-be90-47c7f7f48cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916270791 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
1916270791
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3244615651
Short name T202
Test name
Test status
Simulation time 48709980 ps
CPU time 1.01 seconds
Started Jan 22 12:22:57 PM PST 24
Finished Jan 22 12:23:27 PM PST 24
Peak memory 205196 kb
Host smart-135d8215-5aab-4adf-a522-2d85364c9bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244615651 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.3244615651
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1288574808
Short name T258
Test name
Test status
Simulation time 81698840 ps
CPU time 1.22 seconds
Started Jan 22 12:22:49 PM PST 24
Finished Jan 22 12:23:21 PM PST 24
Peak memory 204796 kb
Host smart-ce713ef5-21ed-4f05-a608-ef714aeaccde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288574808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1288574808
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.633704617
Short name T235
Test name
Test status
Simulation time 13766525 ps
CPU time 0.78 seconds
Started Jan 22 12:22:37 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 204936 kb
Host smart-3b283b23-d74a-4645-9088-2aa99607b111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633704617 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.633704617
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.375972373
Short name T188
Test name
Test status
Simulation time 451543664 ps
CPU time 1.55 seconds
Started Jan 22 12:22:48 PM PST 24
Finished Jan 22 12:23:19 PM PST 24
Peak memory 205200 kb
Host smart-bfae4871-c421-4de9-a9fb-6ed867d2a849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375972373 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_dpe_same_csr_outstanding.375972373
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1748437424
Short name T302
Test name
Test status
Simulation time 210918694 ps
CPU time 1.47 seconds
Started Jan 22 12:22:37 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 213704 kb
Host smart-2a7f0e1b-68fc-438c-a4b7-7e9e9597b9ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748437424 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1748437424
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3258294424
Short name T227
Test name
Test status
Simulation time 281300615 ps
CPU time 2.37 seconds
Started Jan 22 12:22:52 PM PST 24
Finished Jan 22 12:23:23 PM PST 24
Peak memory 213648 kb
Host smart-379f1455-2fe7-42fe-b3b8-354774e16103
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258294424 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3258294424
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.845277729
Short name T307
Test name
Test status
Simulation time 303303628 ps
CPU time 2.87 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:24 PM PST 24
Peak memory 213428 kb
Host smart-82fd7895-8d12-4a73-ad13-2d9b7f055996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845277729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.845277729
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1795174153
Short name T32
Test name
Test status
Simulation time 292144208 ps
CPU time 3.36 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:25 PM PST 24
Peak memory 205284 kb
Host smart-3cacc602-9abd-4a07-9651-27bb69f1f10d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795174153 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.1795174153
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1443878435
Short name T282
Test name
Test status
Simulation time 112455530 ps
CPU time 1.12 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:23 PM PST 24
Peak memory 213500 kb
Host smart-2ee15b97-abcd-4980-b537-39fbce32406a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443878435 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1443878435
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.45268970
Short name T191
Test name
Test status
Simulation time 316133065 ps
CPU time 1.31 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:23 PM PST 24
Peak memory 204680 kb
Host smart-68fac57e-8522-45c4-b527-96702f5b8716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45268970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.45268970
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2033418113
Short name T251
Test name
Test status
Simulation time 12457447 ps
CPU time 0.83 seconds
Started Jan 22 12:22:40 PM PST 24
Finished Jan 22 12:23:13 PM PST 24
Peak memory 204884 kb
Host smart-83307eb2-fa2d-4050-b707-e77df022f018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033418113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2033418113
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.493351633
Short name T84
Test name
Test status
Simulation time 84449556 ps
CPU time 3.04 seconds
Started Jan 22 12:22:58 PM PST 24
Finished Jan 22 12:23:29 PM PST 24
Peak memory 205120 kb
Host smart-67782f90-3ab0-4321-b6a0-a3da286f24ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493351633 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.493351633
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1442299402
Short name T271
Test name
Test status
Simulation time 150763033 ps
CPU time 2.39 seconds
Started Jan 22 12:22:41 PM PST 24
Finished Jan 22 12:23:15 PM PST 24
Peak memory 213776 kb
Host smart-424c5237-b4be-4f72-b474-0d63f96e174a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442299402 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.1442299402
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1964171224
Short name T63
Test name
Test status
Simulation time 46968063 ps
CPU time 2.29 seconds
Started Jan 22 12:22:50 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 218972 kb
Host smart-2b5117f7-d92b-4e00-bbde-ac3f391965bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964171224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1964171224
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1771157811
Short name T269
Test name
Test status
Simulation time 446221358 ps
CPU time 2.84 seconds
Started Jan 22 12:22:49 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 216156 kb
Host smart-15aa1f93-1a37-4211-9859-675ec7ed9835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771157811 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1771157811
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.3680737814
Short name T262
Test name
Test status
Simulation time 63258058 ps
CPU time 1.28 seconds
Started Jan 22 12:22:57 PM PST 24
Finished Jan 22 12:23:27 PM PST 24
Peak memory 213348 kb
Host smart-42bf35a6-0a03-4c98-acff-66cc43495c3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680737814 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.3680737814
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2619428957
Short name T58
Test name
Test status
Simulation time 88922043 ps
CPU time 1.34 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:24 PM PST 24
Peak memory 205176 kb
Host smart-cfd658fb-35b1-4ced-a7f7-189a1f61f3be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619428957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2619428957
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3774981934
Short name T209
Test name
Test status
Simulation time 27479394 ps
CPU time 0.71 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 204948 kb
Host smart-952913af-2775-4ac7-b540-279067a0eb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774981934 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3774981934
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2143793278
Short name T172
Test name
Test status
Simulation time 34062532 ps
CPU time 1.3 seconds
Started Jan 22 12:22:57 PM PST 24
Finished Jan 22 12:23:27 PM PST 24
Peak memory 205128 kb
Host smart-7cb37d38-e278-4bce-a8af-c19233a5e938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143793278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2143793278
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.600520593
Short name T299
Test name
Test status
Simulation time 533205716 ps
CPU time 3.83 seconds
Started Jan 22 12:22:57 PM PST 24
Finished Jan 22 12:23:30 PM PST 24
Peak memory 213352 kb
Host smart-972a23f2-9589-4171-9108-c2767f60aceb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600520593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.600520593
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.324314691
Short name T286
Test name
Test status
Simulation time 459038455 ps
CPU time 2.96 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:25 PM PST 24
Peak memory 213784 kb
Host smart-65644124-416d-4f56-b529-44298cb06936
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324314691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.324314691
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.3459193890
Short name T45
Test name
Test status
Simulation time 103558251 ps
CPU time 1.85 seconds
Started Jan 22 12:22:53 PM PST 24
Finished Jan 22 12:23:24 PM PST 24
Peak memory 215696 kb
Host smart-66f1d3b1-346f-4201-ab7e-ae3eb0349336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459193890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
3459193890
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.32796196
Short name T192
Test name
Test status
Simulation time 176770651 ps
CPU time 2.38 seconds
Started Jan 22 12:22:58 PM PST 24
Finished Jan 22 12:23:28 PM PST 24
Peak memory 214352 kb
Host smart-b560dcbe-99c1-4268-8953-7559bdc07a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_
tl_intg_err.32796196
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.3165799459
Short name T288
Test name
Test status
Simulation time 148522933 ps
CPU time 1.22 seconds
Started Jan 22 12:23:05 PM PST 24
Finished Jan 22 12:23:31 PM PST 24
Peak memory 205252 kb
Host smart-ce0a4e36-7e90-47a5-8ce2-254af13e226f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165799459 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.3165799459
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.3481165947
Short name T220
Test name
Test status
Simulation time 248953286 ps
CPU time 1.03 seconds
Started Jan 22 12:23:03 PM PST 24
Finished Jan 22 12:23:30 PM PST 24
Peak memory 204112 kb
Host smart-4053ccf3-be17-4e01-9fd1-8127753f0cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481165947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
3481165947
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.758280207
Short name T290
Test name
Test status
Simulation time 12174236 ps
CPU time 0.85 seconds
Started Jan 22 12:23:03 PM PST 24
Finished Jan 22 12:23:30 PM PST 24
Peak memory 204808 kb
Host smart-f9fa938d-4ad8-49bd-902f-f3092e34896d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758280207 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.758280207
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.155445341
Short name T232
Test name
Test status
Simulation time 17548648 ps
CPU time 1.24 seconds
Started Jan 22 12:23:05 PM PST 24
Finished Jan 22 12:23:31 PM PST 24
Peak memory 205248 kb
Host smart-201d0fb7-b7b5-439b-94b3-ed263ab100bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155445341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_dpe_same_csr_outstanding.155445341
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2049688948
Short name T273
Test name
Test status
Simulation time 112242763 ps
CPU time 1.42 seconds
Started Jan 22 12:22:42 PM PST 24
Finished Jan 22 12:23:16 PM PST 24
Peak memory 213736 kb
Host smart-553ae323-679e-4c1a-b5e1-e4954dbcb627
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049688948 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2049688948
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.240903157
Short name T48
Test name
Test status
Simulation time 65854135 ps
CPU time 2.88 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:25 PM PST 24
Peak memory 218888 kb
Host smart-aa1458f8-576b-4732-9b6b-3e99c594882c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240903157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.240903157
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.658540912
Short name T248
Test name
Test status
Simulation time 374225962 ps
CPU time 3.67 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:26 PM PST 24
Peak memory 221092 kb
Host smart-d8f8abe2-552f-40ac-bce5-ee0bde72e23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658540912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.658540912
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.3997135015
Short name T222
Test name
Test status
Simulation time 21661583 ps
CPU time 1.27 seconds
Started Jan 22 12:23:03 PM PST 24
Finished Jan 22 12:23:30 PM PST 24
Peak memory 212716 kb
Host smart-e585606a-4f69-43be-a1ce-0b13805e9e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997135015 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.3997135015
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.3188640152
Short name T200
Test name
Test status
Simulation time 22436637 ps
CPU time 1.06 seconds
Started Jan 22 12:23:03 PM PST 24
Finished Jan 22 12:23:30 PM PST 24
Peak memory 205112 kb
Host smart-3ec04f70-2297-49ab-8380-08484951827c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188640152 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
3188640152
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2977280142
Short name T259
Test name
Test status
Simulation time 12426305 ps
CPU time 0.72 seconds
Started Jan 22 12:22:52 PM PST 24
Finished Jan 22 12:23:22 PM PST 24
Peak memory 204952 kb
Host smart-43d2f868-1110-45d7-abec-0454055a19eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977280142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2977280142
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.854293532
Short name T85
Test name
Test status
Simulation time 42298792 ps
CPU time 1.9 seconds
Started Jan 22 12:23:05 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 205248 kb
Host smart-fbd2809b-4c80-452a-96d9-4f5ec780630f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854293532 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_dpe_same_csr_outstanding.854293532
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.623404626
Short name T167
Test name
Test status
Simulation time 49499311 ps
CPU time 1.35 seconds
Started Jan 22 12:23:05 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 213828 kb
Host smart-acf53852-4ce2-4698-8f11-6e7ae307ddcc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623404626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym
gr_dpe_shadow_reg_errors.623404626
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.1215681082
Short name T49
Test name
Test status
Simulation time 981426536 ps
CPU time 5.37 seconds
Started Jan 22 12:22:49 PM PST 24
Finished Jan 22 12:23:25 PM PST 24
Peak memory 213712 kb
Host smart-3510e30a-1eef-44e8-80b7-276c85118e16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215681082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.1215681082
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.114408824
Short name T298
Test name
Test status
Simulation time 571000229 ps
CPU time 2.4 seconds
Started Jan 22 12:23:06 PM PST 24
Finished Jan 22 12:23:33 PM PST 24
Peak memory 215596 kb
Host smart-648294b3-a913-4d98-b96c-01dcd117e96b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114408824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.114408824
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.3638530294
Short name T23
Test name
Test status
Simulation time 198470562 ps
CPU time 5.15 seconds
Started Jan 22 12:23:05 PM PST 24
Finished Jan 22 12:23:36 PM PST 24
Peak memory 214352 kb
Host smart-b9e20c07-a366-4d45-8157-9906918ed424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638530294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.3638530294
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.241031061
Short name T207
Test name
Test status
Simulation time 447093457 ps
CPU time 1.25 seconds
Started Jan 22 12:23:06 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 213316 kb
Host smart-824bf995-d35c-4bbd-9480-f4c3af87a7ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241031061 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.241031061
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3208223941
Short name T185
Test name
Test status
Simulation time 68871526 ps
CPU time 1.17 seconds
Started Jan 22 12:23:07 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 205156 kb
Host smart-753e57b5-ca7f-427c-b8d9-59d68922044e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208223941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3208223941
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1904964366
Short name T265
Test name
Test status
Simulation time 81163137 ps
CPU time 0.81 seconds
Started Jan 22 12:23:07 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 204988 kb
Host smart-0ad024a9-a534-4db3-93bc-a0ffecb04403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904964366 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1904964366
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.2370048296
Short name T243
Test name
Test status
Simulation time 52753056 ps
CPU time 2.03 seconds
Started Jan 22 12:23:02 PM PST 24
Finished Jan 22 12:23:31 PM PST 24
Peak memory 205168 kb
Host smart-de77c400-bc87-47f6-888e-6444afa0784b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370048296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.2370048296
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1301811175
Short name T67
Test name
Test status
Simulation time 479171332 ps
CPU time 3.74 seconds
Started Jan 22 12:56:42 PM PST 24
Finished Jan 22 12:56:47 PM PST 24
Peak memory 213932 kb
Host smart-207a3429-ccac-48e1-9b00-4644507e9e51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301811175 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1301811175
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.4124166804
Short name T245
Test name
Test status
Simulation time 1462761558 ps
CPU time 3.86 seconds
Started Jan 22 12:37:16 PM PST 24
Finished Jan 22 12:37:22 PM PST 24
Peak memory 213832 kb
Host smart-24ce6c75-a74c-43d6-957e-b18121e51868
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124166804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.4124166804
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1471824071
Short name T36
Test name
Test status
Simulation time 47710647 ps
CPU time 1.46 seconds
Started Jan 22 12:52:07 PM PST 24
Finished Jan 22 12:52:10 PM PST 24
Peak memory 215760 kb
Host smart-77a09399-8019-43eb-a462-d1ada2d4cd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471824071 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1471824071
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2323912538
Short name T79
Test name
Test status
Simulation time 116776711 ps
CPU time 4 seconds
Started Jan 22 12:22:54 PM PST 24
Finished Jan 22 12:23:26 PM PST 24
Peak memory 213364 kb
Host smart-c8b158e8-6d1a-4a2c-b23c-3dbce700a954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323912538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.2323912538
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.815808195
Short name T42
Test name
Test status
Simulation time 23863243 ps
CPU time 1.06 seconds
Started Jan 22 12:41:34 PM PST 24
Finished Jan 22 12:41:40 PM PST 24
Peak memory 205288 kb
Host smart-066a20a3-f7cd-4630-be12-ae82475c7610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815808195 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.815808195
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.257526264
Short name T195
Test name
Test status
Simulation time 148040658 ps
CPU time 1 seconds
Started Jan 22 12:23:20 PM PST 24
Finished Jan 22 12:23:44 PM PST 24
Peak memory 204656 kb
Host smart-a7eb8dc8-a0d2-4ff4-8204-a5b811ba198e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257526264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.257526264
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2687466198
Short name T264
Test name
Test status
Simulation time 35663004 ps
CPU time 0.75 seconds
Started Jan 22 12:42:49 PM PST 24
Finished Jan 22 12:42:51 PM PST 24
Peak memory 205084 kb
Host smart-1bf09ec9-a5ee-4e4c-a359-c0e119a062fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687466198 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2687466198
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.4055482718
Short name T284
Test name
Test status
Simulation time 703461678 ps
CPU time 3.31 seconds
Started Jan 22 12:23:11 PM PST 24
Finished Jan 22 12:23:37 PM PST 24
Peak memory 205124 kb
Host smart-d8d44ced-9078-4315-9f0b-bb54042921f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055482718 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.4055482718
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2266187537
Short name T224
Test name
Test status
Simulation time 143116799 ps
CPU time 2.33 seconds
Started Jan 22 12:23:04 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 213772 kb
Host smart-7f0f3132-ad48-4a21-9781-e42f56c79628
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266187537 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2266187537
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3800535371
Short name T256
Test name
Test status
Simulation time 164800324 ps
CPU time 2.65 seconds
Started Jan 22 12:23:04 PM PST 24
Finished Jan 22 12:23:33 PM PST 24
Peak memory 213764 kb
Host smart-a1ad40bc-90c6-457f-aa2e-4c5d84b8075a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800535371 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3800535371
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.452458530
Short name T30
Test name
Test status
Simulation time 34904016 ps
CPU time 1.7 seconds
Started Jan 22 12:23:16 PM PST 24
Finished Jan 22 12:23:40 PM PST 24
Peak memory 221584 kb
Host smart-c424603b-c620-4180-9c5c-25a80a10e24b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452458530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.452458530
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.397935642
Short name T205
Test name
Test status
Simulation time 176881258 ps
CPU time 3.18 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:23:02 PM PST 24
Peak memory 204568 kb
Host smart-cb223600-2088-436f-8284-851271cbb558
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397935642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.397935642
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3078087147
Short name T204
Test name
Test status
Simulation time 1160181097 ps
CPU time 5.63 seconds
Started Jan 22 12:15:45 PM PST 24
Finished Jan 22 12:15:59 PM PST 24
Peak memory 205444 kb
Host smart-ba8d88d2-c53d-42db-9cb6-902f5ce74846
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078087147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3078087147
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2653882925
Short name T281
Test name
Test status
Simulation time 24516718 ps
CPU time 0.94 seconds
Started Jan 22 01:22:46 PM PST 24
Finished Jan 22 01:22:47 PM PST 24
Peak memory 205132 kb
Host smart-762b550b-dc03-41be-8700-38ce59bd9082
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653882925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2653882925
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2739826460
Short name T275
Test name
Test status
Simulation time 43630584 ps
CPU time 0.94 seconds
Started Jan 22 12:31:05 PM PST 24
Finished Jan 22 12:31:12 PM PST 24
Peak memory 205060 kb
Host smart-53d5cdc4-c2bf-49a3-ae9b-79f9fa854a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739826460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
739826460
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2188296561
Short name T199
Test name
Test status
Simulation time 12865181 ps
CPU time 0.76 seconds
Started Jan 22 12:33:34 PM PST 24
Finished Jan 22 12:33:38 PM PST 24
Peak memory 204916 kb
Host smart-48659e00-c216-4997-a98b-f4abc2d5ae25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188296561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
188296561
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.616308556
Short name T272
Test name
Test status
Simulation time 164683754 ps
CPU time 1.49 seconds
Started Jan 22 12:30:58 PM PST 24
Finished Jan 22 12:31:07 PM PST 24
Peak memory 213736 kb
Host smart-bb3afb39-ed08-432e-b9b4-af769bf4891e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616308556 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymg
r_dpe_shadow_reg_errors.616308556
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.3739654817
Short name T217
Test name
Test status
Simulation time 21529386 ps
CPU time 1.68 seconds
Started Jan 22 12:17:49 PM PST 24
Finished Jan 22 12:17:52 PM PST 24
Peak memory 213704 kb
Host smart-24915583-8cc2-4aad-a858-c4ca204ea4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739654817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.3
739654817
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.1790706228
Short name T35
Test name
Test status
Simulation time 282022271 ps
CPU time 3.06 seconds
Started Jan 22 12:20:41 PM PST 24
Finished Jan 22 12:20:48 PM PST 24
Peak memory 213148 kb
Host smart-b1d82d2b-9384-44db-b5d4-32d9ccd17b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790706228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.1790706228
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.1428415955
Short name T186
Test name
Test status
Simulation time 11506528 ps
CPU time 0.66 seconds
Started Jan 22 12:23:20 PM PST 24
Finished Jan 22 12:23:43 PM PST 24
Peak memory 204732 kb
Host smart-6b411a86-464d-4f3e-b69f-2aee7348550e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428415955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
1428415955
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.3109630702
Short name T306
Test name
Test status
Simulation time 32281755 ps
CPU time 0.81 seconds
Started Jan 22 12:51:27 PM PST 24
Finished Jan 22 12:51:29 PM PST 24
Peak memory 204996 kb
Host smart-f5d87df4-af66-4653-baa9-6f7aaf597950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109630702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
3109630702
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3776446776
Short name T263
Test name
Test status
Simulation time 25532211 ps
CPU time 0.67 seconds
Started Jan 22 12:23:07 PM PST 24
Finished Jan 22 12:23:32 PM PST 24
Peak memory 204976 kb
Host smart-bc84e508-8bb6-4a8d-9fca-65f148ea99c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776446776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3776446776
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3727790357
Short name T240
Test name
Test status
Simulation time 47061075 ps
CPU time 0.77 seconds
Started Jan 22 12:34:51 PM PST 24
Finished Jan 22 12:34:56 PM PST 24
Peak memory 204992 kb
Host smart-888eda4f-ebfd-4964-85b0-e8d5f5a4f0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727790357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3727790357
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.1297404271
Short name T241
Test name
Test status
Simulation time 15003618 ps
CPU time 0.69 seconds
Started Jan 22 12:35:12 PM PST 24
Finished Jan 22 12:35:15 PM PST 24
Peak memory 204852 kb
Host smart-2b352eb1-c312-476f-a6e0-9f7fa3d168b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297404271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
1297404271
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2532883439
Short name T236
Test name
Test status
Simulation time 50918890 ps
CPU time 0.7 seconds
Started Jan 22 12:23:23 PM PST 24
Finished Jan 22 12:23:47 PM PST 24
Peak memory 205184 kb
Host smart-2b73e5c8-ee83-462a-bc8d-980623f67d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532883439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2532883439
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3360510288
Short name T116
Test name
Test status
Simulation time 41840033 ps
CPU time 0.75 seconds
Started Jan 22 12:23:25 PM PST 24
Finished Jan 22 12:23:49 PM PST 24
Peak memory 205184 kb
Host smart-9527fc41-5b50-4024-923b-c6870013d687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360510288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3360510288
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.329792944
Short name T250
Test name
Test status
Simulation time 12589270 ps
CPU time 0.69 seconds
Started Jan 22 12:23:23 PM PST 24
Finished Jan 22 12:23:46 PM PST 24
Peak memory 204944 kb
Host smart-f0ca6d76-4b57-42f2-a3dd-33f178f2d298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329792944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.329792944
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2168937307
Short name T196
Test name
Test status
Simulation time 35966205 ps
CPU time 0.76 seconds
Started Jan 22 12:23:18 PM PST 24
Finished Jan 22 12:23:42 PM PST 24
Peak memory 204964 kb
Host smart-894bc066-befe-4f29-a5c1-744fa55fdd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168937307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2168937307
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.1517440520
Short name T184
Test name
Test status
Simulation time 24648122 ps
CPU time 0.73 seconds
Started Jan 22 12:23:24 PM PST 24
Finished Jan 22 12:23:48 PM PST 24
Peak memory 204912 kb
Host smart-62da3861-032c-4d72-bf4c-a24bb74544d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517440520 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
1517440520
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3058417979
Short name T238
Test name
Test status
Simulation time 285980424 ps
CPU time 5.34 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:23:04 PM PST 24
Peak memory 204688 kb
Host smart-86b83674-8c7e-4f2a-800b-7c535cec3b5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058417979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.3058417979
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1634320053
Short name T181
Test name
Test status
Simulation time 261135933 ps
CPU time 9.36 seconds
Started Jan 22 12:22:32 PM PST 24
Finished Jan 22 12:23:10 PM PST 24
Peak memory 205144 kb
Host smart-e25d5a04-4ad5-4070-993d-4b007a3f0c4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634320053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1634320053
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.3776636102
Short name T52
Test name
Test status
Simulation time 24828407 ps
CPU time 0.92 seconds
Started Jan 22 12:22:27 PM PST 24
Finished Jan 22 12:22:56 PM PST 24
Peak memory 205136 kb
Host smart-b7dc64ab-a6e0-4987-93f2-a35b5ee9d0b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776636102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.3776636102
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.2423526907
Short name T292
Test name
Test status
Simulation time 42358414 ps
CPU time 1.51 seconds
Started Jan 22 12:22:18 PM PST 24
Finished Jan 22 12:22:41 PM PST 24
Peak memory 213412 kb
Host smart-3515b8d9-5344-433d-b97f-8a54b168b3b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423526907 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.2423526907
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3592528318
Short name T218
Test name
Test status
Simulation time 14319361 ps
CPU time 0.88 seconds
Started Jan 22 12:22:29 PM PST 24
Finished Jan 22 12:22:58 PM PST 24
Peak memory 204832 kb
Host smart-6093659f-f2a2-47a1-a0ce-f5e4c75d92e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592528318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.3
592528318
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3604054887
Short name T171
Test name
Test status
Simulation time 47956126 ps
CPU time 0.83 seconds
Started Jan 22 12:22:26 PM PST 24
Finished Jan 22 12:22:55 PM PST 24
Peak memory 204880 kb
Host smart-e508b515-b68f-4984-bc79-2172ea2ad94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604054887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
604054887
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2600660666
Short name T229
Test name
Test status
Simulation time 132824333 ps
CPU time 1.35 seconds
Started Jan 22 12:22:21 PM PST 24
Finished Jan 22 12:22:44 PM PST 24
Peak memory 205420 kb
Host smart-7ea18b57-d40e-4929-b709-bc278bb2c05e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600660666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2600660666
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.1182215223
Short name T175
Test name
Test status
Simulation time 534520159 ps
CPU time 3.73 seconds
Started Jan 22 12:22:21 PM PST 24
Finished Jan 22 12:22:47 PM PST 24
Peak memory 213948 kb
Host smart-ba17fd03-c12a-46ca-951c-f9d0ea4c5df4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182215223 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.1182215223
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3720004763
Short name T190
Test name
Test status
Simulation time 466523321 ps
CPU time 10.9 seconds
Started Jan 22 12:22:26 PM PST 24
Finished Jan 22 12:23:05 PM PST 24
Peak memory 213636 kb
Host smart-e58da90b-525e-4c40-9700-473bf998cd86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720004763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3720004763
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1637697571
Short name T198
Test name
Test status
Simulation time 87364473 ps
CPU time 1.88 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:01 PM PST 24
Peak memory 213160 kb
Host smart-b8d3c1a1-a7d0-4964-a7f2-aa1ae02d66aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637697571 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
637697571
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.772382650
Short name T230
Test name
Test status
Simulation time 13738167 ps
CPU time 0.72 seconds
Started Jan 22 12:23:18 PM PST 24
Finished Jan 22 12:23:42 PM PST 24
Peak memory 204960 kb
Host smart-679a86d9-d0e4-4314-bd27-e4c3c0ffb909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772382650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.772382650
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1143792380
Short name T174
Test name
Test status
Simulation time 35865034 ps
CPU time 0.84 seconds
Started Jan 22 12:23:25 PM PST 24
Finished Jan 22 12:23:49 PM PST 24
Peak memory 205172 kb
Host smart-363106cb-d57e-4972-a037-535b459ca386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143792380 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1143792380
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.3462354490
Short name T221
Test name
Test status
Simulation time 8582015 ps
CPU time 0.8 seconds
Started Jan 22 12:23:24 PM PST 24
Finished Jan 22 12:23:48 PM PST 24
Peak memory 204872 kb
Host smart-89d353f6-0fc5-4625-98ab-4fb9ba780819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462354490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
3462354490
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3992672229
Short name T211
Test name
Test status
Simulation time 40527141 ps
CPU time 0.83 seconds
Started Jan 22 12:23:24 PM PST 24
Finished Jan 22 12:23:48 PM PST 24
Peak memory 204964 kb
Host smart-bced6167-5d99-467d-a94e-a916cadf3281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992672229 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3992672229
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3842854623
Short name T291
Test name
Test status
Simulation time 24165776 ps
CPU time 0.74 seconds
Started Jan 22 12:23:28 PM PST 24
Finished Jan 22 12:23:52 PM PST 24
Peak memory 204952 kb
Host smart-a414edf9-b0b9-44ed-b4b2-ea354e3e8fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842854623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
3842854623
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.2309117044
Short name T278
Test name
Test status
Simulation time 14363872 ps
CPU time 0.69 seconds
Started Jan 22 12:23:29 PM PST 24
Finished Jan 22 12:23:53 PM PST 24
Peak memory 205000 kb
Host smart-4299471c-d5c6-42f6-b6d2-a39189b87fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309117044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
2309117044
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.502464148
Short name T179
Test name
Test status
Simulation time 33207642 ps
CPU time 0.8 seconds
Started Jan 22 12:23:24 PM PST 24
Finished Jan 22 12:23:48 PM PST 24
Peak memory 204924 kb
Host smart-9dc24dec-75c9-442d-adb8-72ee35c235db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502464148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.502464148
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2810689764
Short name T300
Test name
Test status
Simulation time 14082571 ps
CPU time 0.73 seconds
Started Jan 22 12:23:27 PM PST 24
Finished Jan 22 12:23:50 PM PST 24
Peak memory 204996 kb
Host smart-dc5baef3-d1fa-482d-aaa1-20c2729e0721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810689764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
2810689764
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.2321705178
Short name T216
Test name
Test status
Simulation time 42648763 ps
CPU time 0.8 seconds
Started Jan 22 12:23:30 PM PST 24
Finished Jan 22 12:23:54 PM PST 24
Peak memory 204968 kb
Host smart-df9e75b0-875a-4bea-8d27-238ed45cb629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321705178 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
2321705178
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.190017346
Short name T225
Test name
Test status
Simulation time 12041113 ps
CPU time 0.69 seconds
Started Jan 22 12:23:38 PM PST 24
Finished Jan 22 12:24:00 PM PST 24
Peak memory 204996 kb
Host smart-2ac643e5-abfe-4a4c-af9c-9f87cad5dfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190017346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.190017346
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2186056657
Short name T223
Test name
Test status
Simulation time 426516877 ps
CPU time 3.29 seconds
Started Jan 22 12:22:27 PM PST 24
Finished Jan 22 12:22:58 PM PST 24
Peak memory 205424 kb
Host smart-575c7f00-c8fc-4aba-b238-5ccd6e2458d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186056657 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2186056657
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.687020599
Short name T176
Test name
Test status
Simulation time 350863257 ps
CPU time 8.99 seconds
Started Jan 22 12:22:23 PM PST 24
Finished Jan 22 12:22:55 PM PST 24
Peak memory 205404 kb
Host smart-b82cc1a4-551a-4c0b-9bd2-754f3832b9f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687020599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_bit_bash.687020599
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.616274042
Short name T257
Test name
Test status
Simulation time 164644969 ps
CPU time 1.36 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 204984 kb
Host smart-09bbc5fd-01e9-4f49-a1bb-b066b7ba72a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616274042 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_hw_reset.616274042
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.4222784387
Short name T178
Test name
Test status
Simulation time 58483245 ps
CPU time 1.04 seconds
Started Jan 22 12:22:29 PM PST 24
Finished Jan 22 12:22:58 PM PST 24
Peak memory 205264 kb
Host smart-a97ac3da-f82e-4970-8872-cc38ba43cdd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222784387 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.4222784387
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1339457505
Short name T303
Test name
Test status
Simulation time 96909631 ps
CPU time 1.19 seconds
Started Jan 22 12:22:29 PM PST 24
Finished Jan 22 12:22:59 PM PST 24
Peak memory 205200 kb
Host smart-7972ee85-0277-42e0-b099-b22851cd75d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339457505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
339457505
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.685344257
Short name T165
Test name
Test status
Simulation time 16498324 ps
CPU time 0.79 seconds
Started Jan 22 12:22:28 PM PST 24
Finished Jan 22 12:22:56 PM PST 24
Peak memory 204924 kb
Host smart-18d2a075-3616-498d-9e46-68c157466512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685344257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.685344257
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1241183683
Short name T187
Test name
Test status
Simulation time 94351885 ps
CPU time 2.04 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 204656 kb
Host smart-8a97c4ca-785b-4074-a62b-c11213a28855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241183683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1241183683
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.277251815
Short name T274
Test name
Test status
Simulation time 53601260 ps
CPU time 1.44 seconds
Started Jan 22 12:22:30 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 213460 kb
Host smart-2fa91aba-a9c8-401d-ab24-af2cd9e3860a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277251815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.277251815
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1999605956
Short name T213
Test name
Test status
Simulation time 1470363677 ps
CPU time 8.32 seconds
Started Jan 22 12:22:14 PM PST 24
Finished Jan 22 12:22:44 PM PST 24
Peak memory 213764 kb
Host smart-1cf2a0aa-0466-4160-b884-a8eb296b9595
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999605956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1999605956
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2564440186
Short name T38
Test name
Test status
Simulation time 304694618 ps
CPU time 5.16 seconds
Started Jan 22 12:22:26 PM PST 24
Finished Jan 22 12:22:59 PM PST 24
Peak memory 216712 kb
Host smart-391f795a-bfb7-4bb3-9f7c-f9b5b64b1527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564440186 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
564440186
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.805894770
Short name T82
Test name
Test status
Simulation time 149421024 ps
CPU time 2.29 seconds
Started Jan 22 12:22:27 PM PST 24
Finished Jan 22 12:22:57 PM PST 24
Peak memory 205380 kb
Host smart-06b9f8b8-13fe-47a5-b8df-16303c3bc477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805894770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_
tl_intg_err.805894770
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.176969326
Short name T287
Test name
Test status
Simulation time 12213553 ps
CPU time 0.74 seconds
Started Jan 22 12:23:26 PM PST 24
Finished Jan 22 12:23:50 PM PST 24
Peak memory 205196 kb
Host smart-f3550315-cef3-4ef5-90f0-01c67132e632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176969326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.176969326
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2980125825
Short name T293
Test name
Test status
Simulation time 49650072 ps
CPU time 0.85 seconds
Started Jan 22 12:23:40 PM PST 24
Finished Jan 22 12:24:01 PM PST 24
Peak memory 204976 kb
Host smart-8df12316-ca82-40a0-b087-6f9af2f8bd75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980125825 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2980125825
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2721946726
Short name T56
Test name
Test status
Simulation time 123964160 ps
CPU time 0.84 seconds
Started Jan 22 12:23:30 PM PST 24
Finished Jan 22 12:23:54 PM PST 24
Peak memory 204920 kb
Host smart-c8904d90-1305-4f03-8112-a5aeb8f4cc04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721946726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2721946726
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1950171895
Short name T182
Test name
Test status
Simulation time 16899900 ps
CPU time 0.72 seconds
Started Jan 22 12:23:32 PM PST 24
Finished Jan 22 12:23:56 PM PST 24
Peak memory 204952 kb
Host smart-ee672f3f-17b3-4f5d-afa5-5be4d0687d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950171895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1950171895
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1980502322
Short name T231
Test name
Test status
Simulation time 34763970 ps
CPU time 0.76 seconds
Started Jan 22 12:23:31 PM PST 24
Finished Jan 22 12:23:56 PM PST 24
Peak memory 205228 kb
Host smart-506576df-5bfd-4149-b69f-8eb5b0ae890f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980502322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1980502322
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.3818110410
Short name T296
Test name
Test status
Simulation time 13350678 ps
CPU time 0.71 seconds
Started Jan 22 12:23:30 PM PST 24
Finished Jan 22 12:23:54 PM PST 24
Peak memory 204936 kb
Host smart-42addb74-ee89-4168-a5d2-16a8c5ced33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818110410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
3818110410
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3973577372
Short name T252
Test name
Test status
Simulation time 35659561 ps
CPU time 0.69 seconds
Started Jan 22 12:23:36 PM PST 24
Finished Jan 22 12:23:58 PM PST 24
Peak memory 205024 kb
Host smart-2ec349bd-09b5-458f-ae04-b36dba851b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973577372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3973577372
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.2187540260
Short name T239
Test name
Test status
Simulation time 41851259 ps
CPU time 0.68 seconds
Started Jan 22 12:23:34 PM PST 24
Finished Jan 22 12:23:57 PM PST 24
Peak memory 204988 kb
Host smart-b8d54424-cd49-4cc6-89db-738d18881926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187540260 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
2187540260
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.1697151660
Short name T210
Test name
Test status
Simulation time 44197272 ps
CPU time 0.71 seconds
Started Jan 22 12:23:36 PM PST 24
Finished Jan 22 12:23:59 PM PST 24
Peak memory 204992 kb
Host smart-1dea4fcc-cc23-4e3c-ac3c-df780ca7b8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697151660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
1697151660
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.1874303850
Short name T280
Test name
Test status
Simulation time 22637636 ps
CPU time 1.12 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 205244 kb
Host smart-260e2d95-df80-4c2d-893d-c98f3f53a8af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874303850 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.1874303850
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.3496611326
Short name T214
Test name
Test status
Simulation time 48757171 ps
CPU time 1.37 seconds
Started Jan 22 12:22:27 PM PST 24
Finished Jan 22 12:22:56 PM PST 24
Peak memory 205424 kb
Host smart-68b6ab14-1d7b-40ee-9866-4821ee209cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496611326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.3
496611326
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3048036424
Short name T72
Test name
Test status
Simulation time 8830016 ps
CPU time 0.84 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 204968 kb
Host smart-53558d2b-40ab-4480-9b80-23b6571ef48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048036424 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
048036424
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2193021618
Short name T247
Test name
Test status
Simulation time 72539283 ps
CPU time 2.9 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:11 PM PST 24
Peak memory 205156 kb
Host smart-8a5d8fcf-2081-4f6e-ad8a-3886d7c798c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193021618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.2193021618
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3042561870
Short name T177
Test name
Test status
Simulation time 134678470 ps
CPU time 2.75 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:11 PM PST 24
Peak memory 213516 kb
Host smart-52f18179-5d66-4d9e-924a-537b87dfee0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042561870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3042561870
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.4246471421
Short name T254
Test name
Test status
Simulation time 280495237 ps
CPU time 4.72 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 213608 kb
Host smart-48e89fa0-f36c-49c1-ae8c-7e53585727e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246471421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.4246471421
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.3919050944
Short name T270
Test name
Test status
Simulation time 426195820 ps
CPU time 2.85 seconds
Started Jan 22 12:22:29 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 213376 kb
Host smart-14a8ea95-929e-4593-8285-dd20526a6f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919050944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.3
919050944
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2213847777
Short name T233
Test name
Test status
Simulation time 59291671 ps
CPU time 1.71 seconds
Started Jan 22 12:39:17 PM PST 24
Finished Jan 22 12:39:25 PM PST 24
Peak memory 213488 kb
Host smart-d551fe97-52c9-4e79-923a-d2b53e6d1051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213847777 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2213847777
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2391263361
Short name T193
Test name
Test status
Simulation time 52890492 ps
CPU time 0.98 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 205072 kb
Host smart-1962d519-c75a-4060-8dad-dc2ba2435de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391263361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
391263361
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.900090205
Short name T168
Test name
Test status
Simulation time 102681962 ps
CPU time 0.75 seconds
Started Jan 22 12:22:32 PM PST 24
Finished Jan 22 12:23:02 PM PST 24
Peak memory 204140 kb
Host smart-7451914c-71a2-429a-ac2c-869b76f06a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900090205 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.900090205
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2339885857
Short name T215
Test name
Test status
Simulation time 81521494 ps
CPU time 1.92 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:10 PM PST 24
Peak memory 205152 kb
Host smart-63736302-a75d-4d07-a578-d03f053e158b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339885857 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.2339885857
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1865076113
Short name T166
Test name
Test status
Simulation time 137388275 ps
CPU time 2.02 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 213636 kb
Host smart-b66c47b0-e349-4593-8a71-38688abb8ab6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865076113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1865076113
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.213649440
Short name T255
Test name
Test status
Simulation time 3633018393 ps
CPU time 8.61 seconds
Started Jan 22 12:22:29 PM PST 24
Finished Jan 22 12:23:06 PM PST 24
Peak memory 220096 kb
Host smart-c72453ca-4499-4ab9-8b98-64c248ac43e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213649440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.213649440
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3468936416
Short name T305
Test name
Test status
Simulation time 196756020 ps
CPU time 2.56 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 213436 kb
Host smart-e0c1b942-d5dc-49c6-b8d6-9aba804f75ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468936416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.3
468936416
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4064425751
Short name T76
Test name
Test status
Simulation time 348473618 ps
CPU time 2.75 seconds
Started Jan 22 12:22:20 PM PST 24
Finished Jan 22 12:22:44 PM PST 24
Peak memory 214268 kb
Host smart-c5ac58fb-ebac-4a3f-814f-d89c79649622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064425751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.4064425751
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.4023138874
Short name T266
Test name
Test status
Simulation time 71657709 ps
CPU time 1.09 seconds
Started Jan 22 12:46:22 PM PST 24
Finished Jan 22 12:46:25 PM PST 24
Peak memory 205316 kb
Host smart-8f4fdadf-443d-4a21-9eab-f1594584bae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023138874 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.4023138874
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1253690395
Short name T203
Test name
Test status
Simulation time 27265609 ps
CPU time 1.04 seconds
Started Jan 22 12:22:38 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 205012 kb
Host smart-2071b923-e605-496f-97f6-7e8870c57936
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253690395 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1
253690395
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.668825346
Short name T71
Test name
Test status
Simulation time 18478363 ps
CPU time 0.7 seconds
Started Jan 22 12:38:57 PM PST 24
Finished Jan 22 12:38:59 PM PST 24
Peak memory 205116 kb
Host smart-e7ab8ad1-acb6-4de9-86e1-7c2e0618d519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668825346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.668825346
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1270356874
Short name T249
Test name
Test status
Simulation time 66553003 ps
CPU time 1.77 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:06 PM PST 24
Peak memory 205136 kb
Host smart-bdaaed32-b897-45c7-9803-d38c39e4e5fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270356874 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1270356874
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.338919932
Short name T295
Test name
Test status
Simulation time 181666303 ps
CPU time 2.32 seconds
Started Jan 22 12:22:32 PM PST 24
Finished Jan 22 12:23:03 PM PST 24
Peak memory 213040 kb
Host smart-5805919f-8fec-4d5b-9555-fe6f065c2a52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338919932 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymg
r_dpe_shadow_reg_errors.338919932
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3204106900
Short name T64
Test name
Test status
Simulation time 114967613 ps
CPU time 3.18 seconds
Started Jan 22 12:22:32 PM PST 24
Finished Jan 22 12:23:03 PM PST 24
Peak memory 214076 kb
Host smart-4044e89e-7095-4ba5-b12d-03b9025fc0e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204106900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3204106900
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2449385515
Short name T22
Test name
Test status
Simulation time 448467801 ps
CPU time 4.11 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:03 PM PST 24
Peak memory 213748 kb
Host smart-ee437759-1ba0-407f-925b-5198a72e982d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449385515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
449385515
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1905468643
Short name T78
Test name
Test status
Simulation time 171675164 ps
CPU time 4.14 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:10 PM PST 24
Peak memory 213324 kb
Host smart-1d1bdf9c-efb8-4a8f-86a3-f62a1a2ba4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905468643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1905468643
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2961311183
Short name T304
Test name
Test status
Simulation time 75265533 ps
CPU time 1.41 seconds
Started Jan 22 12:41:24 PM PST 24
Finished Jan 22 12:41:26 PM PST 24
Peak memory 205440 kb
Host smart-ea4bf0ed-233a-44be-a83f-38992cae6259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961311183 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2961311183
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1636980585
Short name T277
Test name
Test status
Simulation time 75205923 ps
CPU time 1.04 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:01 PM PST 24
Peak memory 204720 kb
Host smart-976611b6-9a93-40c2-994f-837270b4f0ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636980585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
636980585
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2562854603
Short name T285
Test name
Test status
Simulation time 12395270 ps
CPU time 0.74 seconds
Started Jan 22 01:10:02 PM PST 24
Finished Jan 22 01:10:22 PM PST 24
Peak memory 205076 kb
Host smart-3158e259-6706-4388-ac3d-96072fdc897e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562854603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2
562854603
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.2942054312
Short name T62
Test name
Test status
Simulation time 658271505 ps
CPU time 2.52 seconds
Started Jan 22 12:22:23 PM PST 24
Finished Jan 22 12:22:50 PM PST 24
Peak memory 205148 kb
Host smart-7f4d50c1-49ef-4d5f-99cd-ef3a9790ee65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942054312 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.2942054312
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1519661336
Short name T228
Test name
Test status
Simulation time 35107701 ps
CPU time 1.64 seconds
Started Jan 22 12:22:31 PM PST 24
Finished Jan 22 12:23:00 PM PST 24
Peak memory 214004 kb
Host smart-f382fa04-8b99-41a7-a168-bd44e1da8669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519661336 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1519661336
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.122761563
Short name T189
Test name
Test status
Simulation time 321769854 ps
CPU time 4.02 seconds
Started Jan 22 12:22:32 PM PST 24
Finished Jan 22 12:23:04 PM PST 24
Peak memory 214012 kb
Host smart-2fc4ba96-acdf-40bd-bd8b-3988d33a8b30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122761563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.122761563
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.227016597
Short name T194
Test name
Test status
Simulation time 124217952 ps
CPU time 2.43 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 221568 kb
Host smart-d192a29b-930b-4d3f-9c7a-0bc4c4f7ab81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227016597 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.227016597
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3050176651
Short name T201
Test name
Test status
Simulation time 172512701 ps
CPU time 1.99 seconds
Started Jan 22 12:22:34 PM PST 24
Finished Jan 22 12:23:06 PM PST 24
Peak memory 213332 kb
Host smart-6cb04815-cbb1-44dd-a3a0-0ce16ec81257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050176651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3050176651
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3303703191
Short name T118
Test name
Test status
Simulation time 94180060 ps
CPU time 1.16 seconds
Started Jan 22 12:22:37 PM PST 24
Finished Jan 22 12:23:09 PM PST 24
Peak memory 205236 kb
Host smart-d428a5ee-8d28-4074-a4d8-f42373a73899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303703191 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.3303703191
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.1869315888
Short name T234
Test name
Test status
Simulation time 50782773 ps
CPU time 0.97 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 204956 kb
Host smart-cef5ae2f-aa35-4924-995e-386798fab51c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869315888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.1
869315888
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1814580510
Short name T55
Test name
Test status
Simulation time 8790154 ps
CPU time 0.78 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:06 PM PST 24
Peak memory 204856 kb
Host smart-a8d4fd55-385d-4ef1-a459-a0573556ad1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814580510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.1
814580510
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.3406789805
Short name T65
Test name
Test status
Simulation time 37847541 ps
CPU time 2.05 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 205152 kb
Host smart-53bcbafb-3093-4c4f-8fe4-d34fc4a4570e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406789805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.3406789805
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1115875871
Short name T50
Test name
Test status
Simulation time 125529224 ps
CPU time 2.48 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:08 PM PST 24
Peak memory 213736 kb
Host smart-4fa0158d-fa04-404f-b226-819184c69fa5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115875871 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1115875871
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1692394169
Short name T212
Test name
Test status
Simulation time 2004085175 ps
CPU time 3.46 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:10 PM PST 24
Peak memory 213668 kb
Host smart-8b6b047b-2ea1-483d-992b-afec8fb09f4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692394169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1692394169
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3039200308
Short name T301
Test name
Test status
Simulation time 332190594 ps
CPU time 1.85 seconds
Started Jan 22 12:22:35 PM PST 24
Finished Jan 22 12:23:07 PM PST 24
Peak memory 213296 kb
Host smart-79bd9ea0-428d-4c66-84a6-501dc85186cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039200308 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
039200308
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.2619533973
Short name T77
Test name
Test status
Simulation time 433293888 ps
CPU time 7.98 seconds
Started Jan 22 12:22:36 PM PST 24
Finished Jan 22 12:23:14 PM PST 24
Peak memory 213284 kb
Host smart-009dd2df-3603-4545-89dd-9d9f2a5c36f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619533973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.2619533973
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2231901895
Short name T25
Test name
Test status
Simulation time 1070925092 ps
CPU time 8.86 seconds
Started Jan 22 04:35:24 PM PST 24
Finished Jan 22 04:35:33 PM PST 24
Peak memory 232304 kb
Host smart-9c512987-0369-4125-8204-51dc5423e2d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231901895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2231901895
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.653865726
Short name T147
Test name
Test status
Simulation time 277522351 ps
CPU time 7.12 seconds
Started Jan 22 04:35:26 PM PST 24
Finished Jan 22 04:35:33 PM PST 24
Peak memory 205472 kb
Host smart-2f6e30b8-78cf-4e9d-93d9-b481966a96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653865726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.653865726
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.717242550
Short name T151
Test name
Test status
Simulation time 47417243 ps
CPU time 0.79 seconds
Started Jan 22 04:35:23 PM PST 24
Finished Jan 22 04:35:24 PM PST 24
Peak memory 204484 kb
Host smart-faed6a63-9a1b-4412-84f6-928e2c51eba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717242550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.717242550
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2859562042
Short name T10
Test name
Test status
Simulation time 344515761 ps
CPU time 10.59 seconds
Started Jan 22 04:35:22 PM PST 24
Finished Jan 22 04:35:33 PM PST 24
Peak memory 232320 kb
Host smart-28ff0377-bbe8-44b5-b1bb-65edac65daeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859562042 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2859562042
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2004825367
Short name T105
Test name
Test status
Simulation time 5726271779 ps
CPU time 26.54 seconds
Started Jan 22 04:35:22 PM PST 24
Finished Jan 22 04:35:49 PM PST 24
Peak memory 207024 kb
Host smart-0985f1ee-b0a7-4aa9-9499-032a806eb9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004825367 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2004825367
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.3320111499
Short name T142
Test name
Test status
Simulation time 10036258 ps
CPU time 0.72 seconds
Started Jan 22 04:49:32 PM PST 24
Finished Jan 22 04:49:33 PM PST 24
Peak memory 204396 kb
Host smart-d86a6a0a-c0de-4e29-84fb-63346761e3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320111499 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
3320111499
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.1029245208
Short name T13
Test name
Test status
Simulation time 24276383 ps
CPU time 1.86 seconds
Started Jan 22 04:35:42 PM PST 24
Finished Jan 22 04:35:44 PM PST 24
Peak memory 205292 kb
Host smart-eaaa6def-288f-4fa4-b32d-5495e3926e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029245208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.1029245208
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.1388127030
Short name T120
Test name
Test status
Simulation time 45833422 ps
CPU time 0.73 seconds
Started Jan 22 04:35:44 PM PST 24
Finished Jan 22 04:35:46 PM PST 24
Peak memory 204420 kb
Host smart-0dd1c3e7-d3e8-4357-9033-c4d666cbacff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388127030 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
1388127030
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.802303675
Short name T70
Test name
Test status
Simulation time 12476102943 ps
CPU time 20.86 seconds
Started Jan 22 04:35:48 PM PST 24
Finished Jan 22 04:36:12 PM PST 24
Peak memory 206532 kb
Host smart-cf08b4e1-c22e-40d6-96cc-f4ddf5e5e7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802303675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.802303675
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1429133188
Short name T126
Test name
Test status
Simulation time 46656375 ps
CPU time 0.78 seconds
Started Jan 22 05:47:00 PM PST 24
Finished Jan 22 05:47:07 PM PST 24
Peak memory 204432 kb
Host smart-41906246-4e90-4be9-84a3-08bf5168431e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429133188 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1429133188
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2026473197
Short name T107
Test name
Test status
Simulation time 63789416 ps
CPU time 2.22 seconds
Started Jan 22 05:50:21 PM PST 24
Finished Jan 22 05:50:26 PM PST 24
Peak memory 205236 kb
Host smart-be56f4f0-f173-4a47-a2e3-bc9a7e976f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026473197 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2026473197
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.214672883
Short name T124
Test name
Test status
Simulation time 129936018 ps
CPU time 0.8 seconds
Started Jan 22 04:35:43 PM PST 24
Finished Jan 22 04:35:44 PM PST 24
Peak memory 204364 kb
Host smart-f1c6b936-c821-4695-aff5-b3615ea66aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214672883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.214672883
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3156616324
Short name T69
Test name
Test status
Simulation time 2442320313 ps
CPU time 12.55 seconds
Started Jan 22 04:35:42 PM PST 24
Finished Jan 22 04:35:55 PM PST 24
Peak memory 206264 kb
Host smart-c1ad4deb-8be6-4477-b4d6-9230a0e885b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156616324 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3156616324
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3524831230
Short name T125
Test name
Test status
Simulation time 13796809 ps
CPU time 0.78 seconds
Started Jan 22 04:35:57 PM PST 24
Finished Jan 22 04:35:59 PM PST 24
Peak memory 204300 kb
Host smart-fa4fb678-302f-469e-9f7f-9fd468f47423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524831230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3524831230
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.510157567
Short name T16
Test name
Test status
Simulation time 10543805 ps
CPU time 0.83 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:06 PM PST 24
Peak memory 204524 kb
Host smart-37f134b6-84ae-4633-a3dd-755b88428905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510157567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.510157567
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1006949202
Short name T3
Test name
Test status
Simulation time 25174440 ps
CPU time 0.92 seconds
Started Jan 22 04:48:28 PM PST 24
Finished Jan 22 04:48:29 PM PST 24
Peak memory 204520 kb
Host smart-88e06175-298b-4a7d-9ea4-179768ec3ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006949202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1006949202
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2981119940
Short name T136
Test name
Test status
Simulation time 13852877 ps
CPU time 0.72 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:05 PM PST 24
Peak memory 204384 kb
Host smart-0c5205f7-6c5c-4383-ba48-e83a3ceac48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981119940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2981119940
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3812616230
Short name T14
Test name
Test status
Simulation time 109206798 ps
CPU time 3.33 seconds
Started Jan 22 04:36:03 PM PST 24
Finished Jan 22 04:36:07 PM PST 24
Peak memory 206028 kb
Host smart-8643293f-6d07-4811-ab81-ad10cd28ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812616230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3812616230
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.1850795922
Short name T139
Test name
Test status
Simulation time 21871059 ps
CPU time 0.91 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:05 PM PST 24
Peak memory 204388 kb
Host smart-ea72a551-8f40-4cd4-a73c-47e0e3faa2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850795922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
1850795922
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.4088448350
Short name T102
Test name
Test status
Simulation time 116455636 ps
CPU time 2.73 seconds
Started Jan 22 04:36:04 PM PST 24
Finished Jan 22 04:36:07 PM PST 24
Peak memory 205340 kb
Host smart-37dbb3ff-699a-42e6-98a1-2fd9f4bc749e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088448350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.4088448350
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.1752293073
Short name T137
Test name
Test status
Simulation time 231208217 ps
CPU time 0.89 seconds
Started Jan 22 04:35:57 PM PST 24
Finished Jan 22 04:36:00 PM PST 24
Peak memory 204436 kb
Host smart-a3c591b1-b7d6-429a-8f1e-808674970c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752293073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
1752293073
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1094814088
Short name T146
Test name
Test status
Simulation time 19346128 ps
CPU time 1.02 seconds
Started Jan 22 04:35:29 PM PST 24
Finished Jan 22 04:35:30 PM PST 24
Peak memory 204616 kb
Host smart-b6411c60-fd4d-44c4-8ff9-f5dbeab4d109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094814088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
094814088
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.1695758662
Short name T144
Test name
Test status
Simulation time 57476810 ps
CPU time 1.01 seconds
Started Jan 22 04:36:03 PM PST 24
Finished Jan 22 04:36:05 PM PST 24
Peak memory 204524 kb
Host smart-c0112011-ac99-44c6-b4e6-c2c936b72868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695758662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
1695758662
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.2449858017
Short name T8
Test name
Test status
Simulation time 313892130 ps
CPU time 3.54 seconds
Started Jan 22 04:36:03 PM PST 24
Finished Jan 22 04:36:07 PM PST 24
Peak memory 206408 kb
Host smart-80bc59f1-64d7-42cf-a699-020baa084287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449858017 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.2449858017
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2662583121
Short name T28
Test name
Test status
Simulation time 61051545 ps
CPU time 0.76 seconds
Started Jan 22 04:36:02 PM PST 24
Finished Jan 22 04:36:04 PM PST 24
Peak memory 204436 kb
Host smart-3d82679f-937a-444a-a600-68fff445ef75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662583121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2662583121
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1770975416
Short name T97
Test name
Test status
Simulation time 163375628 ps
CPU time 2.51 seconds
Started Jan 22 04:36:01 PM PST 24
Finished Jan 22 04:36:05 PM PST 24
Peak memory 205252 kb
Host smart-f55ab757-f8de-4784-b5c8-306be111355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770975416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1770975416
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2617632252
Short name T121
Test name
Test status
Simulation time 94272479 ps
CPU time 0.77 seconds
Started Jan 22 04:36:09 PM PST 24
Finished Jan 22 04:36:11 PM PST 24
Peak memory 204352 kb
Host smart-572ad70d-2a7f-4e26-9623-8effa6e4dc5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617632252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2617632252
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.211010464
Short name T108
Test name
Test status
Simulation time 5310700088 ps
CPU time 21.78 seconds
Started Jan 22 04:36:03 PM PST 24
Finished Jan 22 04:36:26 PM PST 24
Peak memory 206424 kb
Host smart-82e0a0be-d308-42cb-854f-560bd088486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211010464 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.211010464
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.2110512066
Short name T131
Test name
Test status
Simulation time 148135240 ps
CPU time 0.88 seconds
Started Jan 22 04:36:13 PM PST 24
Finished Jan 22 04:36:16 PM PST 24
Peak memory 204340 kb
Host smart-d1567eac-c01a-49eb-bcf5-2e9aeb87a6ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110512066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
2110512066
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.3516660879
Short name T155
Test name
Test status
Simulation time 23784072 ps
CPU time 0.99 seconds
Started Jan 22 04:36:11 PM PST 24
Finished Jan 22 04:36:16 PM PST 24
Peak memory 204432 kb
Host smart-ce2a3154-9371-4062-bdb9-af44fedbb25f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516660879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
3516660879
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1936283542
Short name T19
Test name
Test status
Simulation time 54696839 ps
CPU time 0.83 seconds
Started Jan 22 04:36:14 PM PST 24
Finished Jan 22 04:36:16 PM PST 24
Peak memory 204344 kb
Host smart-ddae6aad-b94d-4d0c-b9de-01c02a8d1596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936283542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1936283542
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.3471533163
Short name T24
Test name
Test status
Simulation time 67480821 ps
CPU time 2.33 seconds
Started Jan 22 04:36:11 PM PST 24
Finished Jan 22 04:36:18 PM PST 24
Peak memory 207164 kb
Host smart-d0f5bc65-d285-4261-9ac4-35ed15c29773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471533163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.3471533163
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.813088237
Short name T148
Test name
Test status
Simulation time 30371422 ps
CPU time 0.82 seconds
Started Jan 22 04:36:16 PM PST 24
Finished Jan 22 04:36:18 PM PST 24
Peak memory 204420 kb
Host smart-354fde4e-233d-486e-aec5-52a797b4b206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813088237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.813088237
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2614611754
Short name T162
Test name
Test status
Simulation time 656265211 ps
CPU time 3.89 seconds
Started Jan 22 04:36:14 PM PST 24
Finished Jan 22 04:36:19 PM PST 24
Peak memory 207020 kb
Host smart-55a95953-39b7-4ff2-bb9a-423be60f6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614611754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2614611754
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.300657003
Short name T133
Test name
Test status
Simulation time 69747105 ps
CPU time 0.85 seconds
Started Jan 22 04:36:30 PM PST 24
Finished Jan 22 04:36:31 PM PST 24
Peak memory 204380 kb
Host smart-d6c985ac-ccd1-43ba-9b6f-2e6ee792c71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300657003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.300657003
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.709540355
Short name T110
Test name
Test status
Simulation time 188122292 ps
CPU time 3.41 seconds
Started Jan 22 04:36:10 PM PST 24
Finished Jan 22 04:36:14 PM PST 24
Peak memory 206888 kb
Host smart-9d7c2b45-0ce6-4adc-a44d-df4df92eb047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709540355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.709540355
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.4046727104
Short name T161
Test name
Test status
Simulation time 18162317 ps
CPU time 0.78 seconds
Started Jan 22 04:36:20 PM PST 24
Finished Jan 22 04:36:21 PM PST 24
Peak memory 204480 kb
Host smart-49f052da-d6d4-4dd5-8b55-a1a63672da52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046727104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
4046727104
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.2714915072
Short name T100
Test name
Test status
Simulation time 37545660 ps
CPU time 2.28 seconds
Started Jan 22 04:36:19 PM PST 24
Finished Jan 22 04:36:22 PM PST 24
Peak memory 205144 kb
Host smart-1e99c84e-c921-49a6-82d6-af73aa50371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714915072 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.2714915072
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.644214144
Short name T153
Test name
Test status
Simulation time 19465983 ps
CPU time 0.87 seconds
Started Jan 22 04:36:21 PM PST 24
Finished Jan 22 04:36:22 PM PST 24
Peak memory 204420 kb
Host smart-f2f2f8e7-2ccf-4950-b7bb-1e6df582aa7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644214144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.644214144
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.1067859872
Short name T93
Test name
Test status
Simulation time 621953046 ps
CPU time 3.57 seconds
Started Jan 22 04:36:18 PM PST 24
Finished Jan 22 04:36:24 PM PST 24
Peak memory 206392 kb
Host smart-b7019508-43eb-4620-be21-5a5740a922fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067859872 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.1067859872
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.3258330922
Short name T117
Test name
Test status
Simulation time 30661653 ps
CPU time 0.8 seconds
Started Jan 22 04:35:31 PM PST 24
Finished Jan 22 04:35:32 PM PST 24
Peak memory 204284 kb
Host smart-88218738-a295-4f0a-8d81-6a0ee0e04ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258330922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.3
258330922
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1958046023
Short name T96
Test name
Test status
Simulation time 129804602 ps
CPU time 2.86 seconds
Started Jan 22 04:35:31 PM PST 24
Finished Jan 22 04:35:35 PM PST 24
Peak memory 207052 kb
Host smart-e3ab9262-ac24-47d1-ae37-a86f4c96db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958046023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1958046023
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.4122895396
Short name T119
Test name
Test status
Simulation time 14681323 ps
CPU time 0.92 seconds
Started Jan 22 04:36:21 PM PST 24
Finished Jan 22 04:36:23 PM PST 24
Peak memory 204612 kb
Host smart-2865acb3-414a-49dc-abe1-a36940544782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122895396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
4122895396
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.1912134472
Short name T143
Test name
Test status
Simulation time 39371159 ps
CPU time 0.74 seconds
Started Jan 22 04:36:19 PM PST 24
Finished Jan 22 04:36:21 PM PST 24
Peak memory 204352 kb
Host smart-0e53271d-8a34-400f-8481-eb4a968d94c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912134472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
1912134472
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.484763838
Short name T68
Test name
Test status
Simulation time 321939882 ps
CPU time 3.16 seconds
Started Jan 22 05:20:06 PM PST 24
Finished Jan 22 05:20:10 PM PST 24
Peak memory 205312 kb
Host smart-7935b445-d67a-406a-84aa-2e8dbea3cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484763838 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.484763838
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2987121618
Short name T130
Test name
Test status
Simulation time 40728542 ps
CPU time 0.84 seconds
Started Jan 22 04:56:39 PM PST 24
Finished Jan 22 04:56:42 PM PST 24
Peak memory 204400 kb
Host smart-9f29fd99-a90f-4af3-80fe-02b9219443db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987121618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2987121618
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.3238588983
Short name T160
Test name
Test status
Simulation time 134081699 ps
CPU time 3.1 seconds
Started Jan 22 04:36:18 PM PST 24
Finished Jan 22 04:36:23 PM PST 24
Peak memory 206224 kb
Host smart-ebed28d7-7fce-4dd1-9b7b-2c1bba172dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238588983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.3238588983
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.465605431
Short name T132
Test name
Test status
Simulation time 64769686 ps
CPU time 1.03 seconds
Started Jan 22 04:36:32 PM PST 24
Finished Jan 22 04:36:34 PM PST 24
Peak memory 204464 kb
Host smart-3ba53ace-f8c1-4387-8cca-04ce96165d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465605431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.465605431
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.4017493932
Short name T103
Test name
Test status
Simulation time 477769754 ps
CPU time 3.28 seconds
Started Jan 22 04:58:37 PM PST 24
Finished Jan 22 04:58:45 PM PST 24
Peak memory 207048 kb
Host smart-8ee55658-2a1a-4dab-8435-63ec24cc3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017493932 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.4017493932
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.4142939477
Short name T140
Test name
Test status
Simulation time 53713270 ps
CPU time 0.86 seconds
Started Jan 22 04:36:34 PM PST 24
Finished Jan 22 04:36:36 PM PST 24
Peak memory 204528 kb
Host smart-94bf9f38-c4ea-4890-8c38-86dc1a5c1132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142939477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
4142939477
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.2101062409
Short name T112
Test name
Test status
Simulation time 1786978306 ps
CPU time 14 seconds
Started Jan 22 04:36:31 PM PST 24
Finished Jan 22 04:36:46 PM PST 24
Peak memory 206180 kb
Host smart-cbb2bdca-82c4-4d3f-8df3-01a02c0d458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101062409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.2101062409
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.956735278
Short name T134
Test name
Test status
Simulation time 20256264 ps
CPU time 0.78 seconds
Started Jan 22 04:36:34 PM PST 24
Finished Jan 22 04:36:35 PM PST 24
Peak memory 204348 kb
Host smart-19f3e40b-df1d-44fd-b962-9f3b9910d430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956735278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.956735278
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.604409564
Short name T92
Test name
Test status
Simulation time 67660529 ps
CPU time 2.77 seconds
Started Jan 22 04:36:32 PM PST 24
Finished Jan 22 04:36:35 PM PST 24
Peak memory 206692 kb
Host smart-bce40687-3f03-4ba8-9f17-052ebf9b8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604409564 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.604409564
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.3044718642
Short name T2
Test name
Test status
Simulation time 32314573 ps
CPU time 0.74 seconds
Started Jan 22 04:36:38 PM PST 24
Finished Jan 22 04:36:39 PM PST 24
Peak memory 204516 kb
Host smart-37f7cea5-2768-40a9-bfbf-cc3a1d1eda01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044718642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
3044718642
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1775087708
Short name T101
Test name
Test status
Simulation time 329708352 ps
CPU time 7.44 seconds
Started Jan 22 04:36:32 PM PST 24
Finished Jan 22 04:36:40 PM PST 24
Peak memory 206416 kb
Host smart-1dda692a-6bdc-4a1d-917a-a48edd42450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775087708 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1775087708
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.2097883585
Short name T17
Test name
Test status
Simulation time 44040367 ps
CPU time 0.88 seconds
Started Jan 22 04:36:39 PM PST 24
Finished Jan 22 04:36:41 PM PST 24
Peak memory 204352 kb
Host smart-c3added4-4e29-4f07-844e-2869f31ab18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097883585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
2097883585
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2805455172
Short name T113
Test name
Test status
Simulation time 149574208 ps
CPU time 2.67 seconds
Started Jan 22 04:36:40 PM PST 24
Finished Jan 22 04:36:43 PM PST 24
Peak memory 205484 kb
Host smart-11e428bc-da47-40de-ab06-3ba5081f36a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805455172 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2805455172
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.2778893236
Short name T122
Test name
Test status
Simulation time 17219867 ps
CPU time 0.72 seconds
Started Jan 22 04:36:38 PM PST 24
Finished Jan 22 04:36:39 PM PST 24
Peak memory 204516 kb
Host smart-e093f23e-1285-46fa-bdb4-8cf0f5b84420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778893236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
2778893236
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.2647019888
Short name T95
Test name
Test status
Simulation time 281243972 ps
CPU time 3.1 seconds
Started Jan 22 04:36:41 PM PST 24
Finished Jan 22 04:36:44 PM PST 24
Peak memory 205448 kb
Host smart-07134ecf-7a97-40c1-a70a-8316084221cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647019888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.2647019888
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1929287797
Short name T138
Test name
Test status
Simulation time 35261402 ps
CPU time 0.72 seconds
Started Jan 22 04:49:22 PM PST 24
Finished Jan 22 04:49:23 PM PST 24
Peak memory 204256 kb
Host smart-a5ab7e4e-5fc7-4d74-b2d3-ebb6408d4034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929287797 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1929287797
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2603460487
Short name T163
Test name
Test status
Simulation time 12031301 ps
CPU time 0.72 seconds
Started Jan 22 04:35:33 PM PST 24
Finished Jan 22 04:35:34 PM PST 24
Peak memory 204304 kb
Host smart-1acf228e-09d2-4851-9305-236774ac756b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603460487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
603460487
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.2413582435
Short name T11
Test name
Test status
Simulation time 1926940763 ps
CPU time 41.12 seconds
Started Jan 22 04:35:31 PM PST 24
Finished Jan 22 04:36:13 PM PST 24
Peak memory 236336 kb
Host smart-e109dd10-eea7-42f4-9320-e910f1d0db1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413582435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2413582435
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.1242045540
Short name T98
Test name
Test status
Simulation time 123609375 ps
CPU time 2.57 seconds
Started Jan 22 04:35:28 PM PST 24
Finished Jan 22 04:35:31 PM PST 24
Peak memory 205132 kb
Host smart-48de2452-5c43-412f-ad83-a80e04d89fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242045540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.1242045540
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.4131084553
Short name T127
Test name
Test status
Simulation time 14051352 ps
CPU time 0.95 seconds
Started Jan 22 04:37:02 PM PST 24
Finished Jan 22 04:37:03 PM PST 24
Peak memory 204584 kb
Host smart-18afce0f-63c3-45bc-96fa-e846a1bd014d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131084553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
4131084553
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3542608329
Short name T109
Test name
Test status
Simulation time 901293590 ps
CPU time 16.65 seconds
Started Jan 22 04:36:58 PM PST 24
Finished Jan 22 04:37:15 PM PST 24
Peak memory 206816 kb
Host smart-b1587a8a-738b-4a57-87e0-eb8f24cf224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542608329 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3542608329
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3909954217
Short name T149
Test name
Test status
Simulation time 22489688 ps
CPU time 0.81 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:01 PM PST 24
Peak memory 204424 kb
Host smart-f7c0f873-4a84-4c66-86b7-36b535d5d5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909954217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3909954217
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.1629266279
Short name T152
Test name
Test status
Simulation time 20155793 ps
CPU time 0.85 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:01 PM PST 24
Peak memory 204420 kb
Host smart-32ffd081-6567-4745-b0de-67174b96e65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629266279 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
1629266279
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2517322068
Short name T27
Test name
Test status
Simulation time 58747479 ps
CPU time 0.75 seconds
Started Jan 22 04:37:02 PM PST 24
Finished Jan 22 04:37:04 PM PST 24
Peak memory 204388 kb
Host smart-50032396-8fe1-40c5-9626-cb4ffbf491bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517322068 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2517322068
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2449286432
Short name T29
Test name
Test status
Simulation time 30555168 ps
CPU time 0.77 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:01 PM PST 24
Peak memory 204380 kb
Host smart-211cb905-a0d8-4cdf-8eb2-03e3ba8340a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449286432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2449286432
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2438449530
Short name T111
Test name
Test status
Simulation time 5644095091 ps
CPU time 35.7 seconds
Started Jan 22 04:36:52 PM PST 24
Finished Jan 22 04:37:29 PM PST 24
Peak memory 207568 kb
Host smart-809af5ae-e255-4bf7-b0c0-bbdbefdefba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438449530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2438449530
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3073517486
Short name T123
Test name
Test status
Simulation time 117319781 ps
CPU time 0.87 seconds
Started Jan 22 04:36:58 PM PST 24
Finished Jan 22 04:37:00 PM PST 24
Peak memory 204148 kb
Host smart-fc6cf4cd-8f57-4cb3-b097-42fa511d26e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073517486 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3073517486
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1521728054
Short name T106
Test name
Test status
Simulation time 54316775 ps
CPU time 2.43 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:04 PM PST 24
Peak memory 207052 kb
Host smart-a65e7d02-f2c0-43ae-b174-0b5f1a4aa431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521728054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1521728054
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.2075812376
Short name T156
Test name
Test status
Simulation time 26326808 ps
CPU time 0.79 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:02 PM PST 24
Peak memory 204420 kb
Host smart-3603b7a7-d8b3-4735-bc08-831d642ecc0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075812376 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
2075812376
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.937305796
Short name T12
Test name
Test status
Simulation time 38335954 ps
CPU time 2.25 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:03 PM PST 24
Peak memory 205192 kb
Host smart-0d0c5521-8a2b-46c6-b215-4db54379f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937305796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.937305796
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1870011925
Short name T145
Test name
Test status
Simulation time 12357403 ps
CPU time 0.73 seconds
Started Jan 22 04:37:00 PM PST 24
Finished Jan 22 04:37:01 PM PST 24
Peak memory 204380 kb
Host smart-cf7b51f3-8316-4235-a781-115c94dbcb5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870011925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1870011925
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.3850849113
Short name T15
Test name
Test status
Simulation time 12930573 ps
CPU time 0.74 seconds
Started Jan 22 04:37:02 PM PST 24
Finished Jan 22 04:37:04 PM PST 24
Peak memory 204516 kb
Host smart-68e9869e-d34a-446a-b9b1-02ae8cba9a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850849113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
3850849113
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.584785729
Short name T141
Test name
Test status
Simulation time 12627240 ps
CPU time 0.78 seconds
Started Jan 22 04:37:03 PM PST 24
Finished Jan 22 04:37:04 PM PST 24
Peak memory 204480 kb
Host smart-f3cca968-249b-4dad-b0c1-a788df464107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584785729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.584785729
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.2102528857
Short name T154
Test name
Test status
Simulation time 62503703 ps
CPU time 2.46 seconds
Started Jan 22 04:37:07 PM PST 24
Finished Jan 22 04:37:10 PM PST 24
Peak memory 207500 kb
Host smart-78e7a6e2-229b-440f-aef4-c07b6ca268a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102528857 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.2102528857
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.1943008962
Short name T159
Test name
Test status
Simulation time 23520788 ps
CPU time 0.76 seconds
Started Jan 22 04:35:31 PM PST 24
Finished Jan 22 04:35:32 PM PST 24
Peak memory 204284 kb
Host smart-6d222fa9-2d5a-4c31-8df9-4a95884f5578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943008962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.1
943008962
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.572381140
Short name T157
Test name
Test status
Simulation time 15935867 ps
CPU time 0.94 seconds
Started Jan 22 04:35:41 PM PST 24
Finished Jan 22 04:35:42 PM PST 24
Peak memory 204476 kb
Host smart-7d70252e-96e9-4051-bd7e-afeecb167764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572381140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.572381140
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.3026532019
Short name T135
Test name
Test status
Simulation time 17866204 ps
CPU time 0.98 seconds
Started Jan 22 04:35:33 PM PST 24
Finished Jan 22 04:35:35 PM PST 24
Peak memory 204468 kb
Host smart-1c13c21d-018d-422e-96b7-46d1df5064a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026532019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.3
026532019
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.2715938080
Short name T164
Test name
Test status
Simulation time 717622474 ps
CPU time 2.29 seconds
Started Jan 22 04:35:40 PM PST 24
Finished Jan 22 04:35:43 PM PST 24
Peak memory 205132 kb
Host smart-730e6f04-04e4-4409-9150-32fed9d3d885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715938080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.2715938080
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2246175407
Short name T128
Test name
Test status
Simulation time 35790804 ps
CPU time 0.78 seconds
Started Jan 22 04:35:37 PM PST 24
Finished Jan 22 04:35:39 PM PST 24
Peak memory 204356 kb
Host smart-2cdab7da-2a1e-401b-88d1-7dd73c55b463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246175407 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
246175407
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3076165895
Short name T104
Test name
Test status
Simulation time 250993399 ps
CPU time 3.09 seconds
Started Jan 22 04:35:36 PM PST 24
Finished Jan 22 04:35:40 PM PST 24
Peak memory 206976 kb
Host smart-0e0b05c9-71e5-4e94-9a48-bae67d8e4f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076165895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3076165895
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1028640184
Short name T129
Test name
Test status
Simulation time 85612857 ps
CPU time 0.88 seconds
Started Jan 22 04:35:42 PM PST 24
Finished Jan 22 04:35:43 PM PST 24
Peak memory 204516 kb
Host smart-ba977977-c295-4f9b-b5c6-14a391a301e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028640184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
028640184
Directory /workspace/9.keymgr_dpe_alert_test/latest
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