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 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T44,T45
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T43,T54,T50

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T43,T54,T50
1	0	0	Covered	T7,T8,T9

 LINE       126
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T43,T54,T50
0	1	0	Covered	T23,T24,T44
1	0	0	Covered	T23,T44,T45

 LINE       126
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T43,T44

 LINE       479
 EXPRESSION (start_we & cfg_regwen_qs)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       510
 EXPRESSION (control_shadowed_we & cfg_regwen_qs)
             ---------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       659
 EXPRESSION (sideload_clear_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       718
 EXPRESSION (reseed_interval_shadowed_we & reseed_interval_regwen_qs)
             -------------1-------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       779
 EXPRESSION (slot_policy_we & slot_policy_regwen_qs)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       886
 EXPRESSION (sw_binding_0_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       918
 EXPRESSION (sw_binding_1_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       950
 EXPRESSION (sw_binding_2_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       982
 EXPRESSION (sw_binding_3_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1014
 EXPRESSION (sw_binding_4_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1046
 EXPRESSION (sw_binding_5_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1078
 EXPRESSION (sw_binding_6_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1110
 EXPRESSION (sw_binding_7_we & sw_binding_regwen_qs)
             -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1142
 EXPRESSION (salt_0_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1174
 EXPRESSION (salt_1_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1206
 EXPRESSION (salt_2_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1238
 EXPRESSION (salt_3_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1270
 EXPRESSION (salt_4_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1302
 EXPRESSION (salt_5_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1334
 EXPRESSION (salt_6_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1366
 EXPRESSION (salt_7_we & cfg_regwen_qs)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T55,T68,T69

 LINE       1398
 EXPRESSION (key_version_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       1449
 EXPRESSION (max_key_ver_shadowed_we & max_key_ver_regwen_qs)
             -----------1-----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       2718
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_INTR_STATE_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2719
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_INTR_ENABLE_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2720
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_INTR_TEST_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2721
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_ALERT_TEST_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2722
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_CFG_REGWEN_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2723
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_START_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2724
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_CONTROL_SHADOWED_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2725
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SIDELOAD_CLEAR_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2726
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_RESEED_INTERVAL_REGWEN_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2727
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_RESEED_INTERVAL_SHADOWED_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2728
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SLOT_POLICY_REGWEN_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2729
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SLOT_POLICY_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2730
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_REGWEN_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2731
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2732
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2733
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2734
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2735
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2736
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2737
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2738
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_BINDING_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2739
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2740
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2741
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_2_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2742
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_3_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2743
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_4_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2744
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_5_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2745
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_6_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2746
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SALT_7_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T16

 LINE       2747
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_KEY_VERSION_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2748
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_MAX_KEY_VER_REGWEN_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       2749
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_MAX_KEY_VER_SHADOWED_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2750
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2751
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2752
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_2_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2753
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_3_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2754
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_4_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2755
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_5_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2756
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_6_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2757
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE0_OUTPUT_7_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2758
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2759
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2760
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_2_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2761
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_3_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2762
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_4_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2763
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_5_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2764
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_6_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2765
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_SW_SHARE1_OUTPUT_7_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       2766
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_WORKING_STATE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2767
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_OP_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2768
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_ERR_CODE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2769
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_FAULT_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2770
 EXPRESSION (reg_addr == keymgr_dpe_reg_pkg::KEYMGR_DPE_DEBUG_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       2773
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2773
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2777
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[52] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T43

 LINE       2777
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1111 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b0011 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
53 (addr_hit[52] & ((\|(4'...	Covered	T4,T5,T6
52 (addr_hit[51] & ((\|(4'...	Covered	T4,T5,T6
51 (addr_hit[50] & ((\|(4'...	Covered	T4,T5,T6
50 (addr_hit[49] & ((\|(4'...	Covered	T4,T5,T16
49 (addr_hit[48] & ((\|(4'...	Covered	T4,T5,T6
48 (addr_hit[47] & ((\|(4'...	Covered	T3,T4,T5
47 (addr_hit[46] & ((\|(4'...	Covered	T4,T5,T6
46 (addr_hit[45] & ((\|(4'...	Covered	T4,T5,T6
45 (addr_hit[44] & ((\|(4'...	Covered	T3,T4,T5
44 (addr_hit[43] & ((\|(4'...	Covered	T4,T5,T6
43 (addr_hit[42] & ((\|(4'...	Covered	T4,T5,T6
42 (addr_hit[41] & ((\|(4'...	Covered	T4,T5,T6
41 (addr_hit[40] & ((\|(4'...	Covered	T4,T5,T6
40 (addr_hit[39] & ((\|(4'...	Covered	T4,T5,T6
39 (addr_hit[38] & ((\|(4'...	Covered	T3,T4,T5
38 (addr_hit[37] & ((\|(4'...	Covered	T3,T4,T5
37 (addr_hit[36] & ((\|(4'...	Covered	T3,T4,T5
36 (addr_hit[35] & ((\|(4'...	Covered	T4,T5,T6
35 (addr_hit[34] & ((\|(4'...	Covered	T4,T5,T6
34 (addr_hit[33] & ((\|(4'...	Covered	T4,T5,T6
33 (addr_hit[32] & ((\|(4'...	Covered	T3,T4,T5
32 (addr_hit[31] & ((\|(4'...	Covered	T4,T5,T19
31 (addr_hit[30] & ((\|(4'...	Covered	T4,T5,T27
30 (addr_hit[29] & ((\|(4'...	Covered	T4,T5,T16
29 (addr_hit[28] & ((\|(4'...	Covered	T4,T5,T16
28 (addr_hit[27] & ((\|(4'...	Covered	T3,T4,T5
27 (addr_hit[26] & ((\|(4'...	Covered	T3,T4,T5
26 (addr_hit[25] & ((\|(4'...	Covered	T4,T5,T16
25 (addr_hit[24] & ((\|(4'...	Covered	T4,T5,T16
24 (addr_hit[23] & ((\|(4'...	Covered	T4,T5,T16
23 (addr_hit[22] & ((\|(4'...	Covered	T3,T4,T5
22 (addr_hit[21] & ((\|(4'...	Covered	T3,T4,T5
21 (addr_hit[20] & ((\|(4'...	Covered	T4,T5,T16
20 (addr_hit[19] & ((\|(4'...	Covered	T3,T4,T5
19 (addr_hit[18] & ((\|(4'...	Covered	T4,T5,T16
18 (addr_hit[17] & ((\|(4'...	Covered	T3,T4,T5
17 (addr_hit[16] & ((\|(4'...	Covered	T3,T4,T5
16 (addr_hit[15] & ((\|(4'...	Covered	T4,T5,T19
15 (addr_hit[14] & ((\|(4'...	Covered	T4,T5,T19
14 (addr_hit[13] & ((\|(4'...	Covered	T4,T5,T16
13 (addr_hit[12] & ((\|(4'...	Covered	T4,T5,T19
12 (addr_hit[11] & ((\|(4'...	Covered	T4,T5,T16
11 (addr_hit[10] & ((\|(4'...	Covered	T4,T5,T19
10 (addr_hit[9] & ((\|(4'b...	Covered	T4,T5,T42
9 (addr_hit[8] & ((\|(4'b...	Covered	T4,T5,T19
8 (addr_hit[7] & ((\|(4'b...	Covered	T4,T5,T16
7 (addr_hit[6] & ((\|(4'b...	Covered	T4,T5,T16
6 (addr_hit[5] & ((\|(4'b...	Covered	T4,T5,T16
5 (addr_hit[4] & ((\|(4'b...	Covered	T4,T5,T19
4 (addr_hit[3] & ((\|(4'b...	Covered	T4,T5,T16
3 (addr_hit[2] & ((\|(4'b...	Covered	T4,T5,T19
2 (addr_hit[1] & ((\|(4'b...	Covered	T4,T5,T16
1 (addr_hit[0] & ((\|(4'b...	Covered	T2,T21,T4

 LINE       2777
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T21,T4

 LINE       2777
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T19
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       2777
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T27,T29
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T16
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T27
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T19
1	1	Covered	T4,T5,T27

 LINE       2777
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T19

 LINE       2777
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       2777
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       2777
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2777
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2834
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T44,T76
1	1	1	Covered	T4,T5,T6

 LINE       2837
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T47,T48,T77
1	1	1	Covered	T4,T6,T10

 LINE       2840
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T19
1	1	0	Covered	T44,T45,T48
1	1	1	Covered	T78,T79,T51