Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
73.72 97.18 89.63 57.52 61.54 93.92 98.34 17.92


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.1721436367 Jan 25 01:11:55 PM PST 24 Jan 25 01:11:57 PM PST 24 20177720 ps
T258 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.1004993260 Jan 25 01:09:40 PM PST 24 Jan 25 01:09:48 PM PST 24 50569858 ps
T259 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.3367617064 Jan 25 01:10:56 PM PST 24 Jan 25 01:11:06 PM PST 24 380207091 ps
T260 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1472902348 Jan 25 01:12:24 PM PST 24 Jan 25 01:12:29 PM PST 24 269319095 ps
T261 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2761230956 Jan 25 01:12:19 PM PST 24 Jan 25 01:12:21 PM PST 24 15225854 ps
T262 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.216337213 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:29 PM PST 24 49394118 ps
T263 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3502518069 Jan 25 01:12:27 PM PST 24 Jan 25 01:12:34 PM PST 24 12510982 ps
T264 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1749365360 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:29 PM PST 24 11563750 ps
T265 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.3365087370 Jan 25 01:11:42 PM PST 24 Jan 25 01:11:45 PM PST 24 29384246 ps
T266 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.4002465048 Jan 25 01:09:45 PM PST 24 Jan 25 01:09:54 PM PST 24 96584467 ps
T267 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2733383985 Jan 25 01:11:03 PM PST 24 Jan 25 01:11:16 PM PST 24 778770246 ps
T268 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3361514960 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:29 PM PST 24 17336808 ps
T269 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2856696330 Jan 25 01:12:26 PM PST 24 Jan 25 01:12:30 PM PST 24 38085593 ps
T82 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.851681672 Jan 25 01:11:29 PM PST 24 Jan 25 01:11:39 PM PST 24 228396264 ps
T270 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2268741717 Jan 25 01:11:00 PM PST 24 Jan 25 01:11:06 PM PST 24 37041085 ps
T90 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.3695616665 Jan 25 01:12:20 PM PST 24 Jan 25 01:12:26 PM PST 24 599691643 ps
T271 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.132928753 Jan 25 01:09:55 PM PST 24 Jan 25 01:10:01 PM PST 24 63450899 ps
T272 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2450955587 Jan 25 01:12:24 PM PST 24 Jan 25 01:12:27 PM PST 24 168589082 ps
T273 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.3119537294 Jan 25 01:11:24 PM PST 24 Jan 25 01:11:29 PM PST 24 105965473 ps
T274 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.370728982 Jan 25 01:10:59 PM PST 24 Jan 25 01:11:06 PM PST 24 25411733 ps
T275 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.4019492564 Jan 25 01:12:29 PM PST 24 Jan 25 01:12:35 PM PST 24 12770446 ps
T276 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3629154836 Jan 25 01:11:29 PM PST 24 Jan 25 01:11:32 PM PST 24 105820496 ps
T89 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.771815607 Jan 25 01:09:46 PM PST 24 Jan 25 01:09:57 PM PST 24 220923010 ps
T277 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.1204570127 Jan 25 01:10:58 PM PST 24 Jan 25 01:11:07 PM PST 24 140229613 ps
T278 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1004246257 Jan 25 01:09:40 PM PST 24 Jan 25 01:09:47 PM PST 24 27404938 ps
T279 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3542591951 Jan 25 01:09:55 PM PST 24 Jan 25 01:10:01 PM PST 24 127868362 ps
T280 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.4005964127 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:29 PM PST 24 13625812 ps
T281 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2282344471 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:33 PM PST 24 416763998 ps
T87 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3999781444 Jan 25 01:11:28 PM PST 24 Jan 25 01:11:33 PM PST 24 654028737 ps
T282 /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.716814284 Jan 25 01:12:24 PM PST 24 Jan 25 01:12:26 PM PST 24 11180546 ps
T283 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1497856585 Jan 25 01:09:49 PM PST 24 Jan 25 01:09:56 PM PST 24 157851433 ps
T284 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4193701544 Jan 25 01:09:48 PM PST 24 Jan 25 01:09:59 PM PST 24 316524069 ps
T285 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3249622015 Jan 25 01:10:57 PM PST 24 Jan 25 01:11:05 PM PST 24 86741520 ps
T92 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2533185769 Jan 25 01:12:26 PM PST 24 Jan 25 01:12:34 PM PST 24 131060779 ps
T286 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2531102360 Jan 25 01:10:57 PM PST 24 Jan 25 01:11:05 PM PST 24 55000215 ps
T287 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2408315991 Jan 25 01:09:47 PM PST 24 Jan 25 01:09:55 PM PST 24 29040034 ps
T288 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.899514736 Jan 25 01:12:17 PM PST 24 Jan 25 01:12:19 PM PST 24 28427598 ps
T289 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1404314055 Jan 25 01:12:02 PM PST 24 Jan 25 01:12:04 PM PST 24 13415992 ps
T290 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.4094981790 Jan 25 01:09:44 PM PST 24 Jan 25 01:09:52 PM PST 24 125632702 ps
T291 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2697171520 Jan 25 01:11:22 PM PST 24 Jan 25 01:11:25 PM PST 24 59737846 ps
T292 /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.719642270 Jan 25 01:12:28 PM PST 24 Jan 25 01:12:34 PM PST 24 19949362 ps
T91 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2490040325 Jan 25 01:11:28 PM PST 24 Jan 25 01:11:35 PM PST 24 104660977 ps
T293 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2569992330 Jan 25 01:11:29 PM PST 24 Jan 25 01:11:32 PM PST 24 24530228 ps
T294 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1163043748 Jan 25 01:12:29 PM PST 24 Jan 25 01:12:36 PM PST 24 11238264 ps
T295 /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2414334939 Jan 25 01:11:52 PM PST 24 Jan 25 01:11:56 PM PST 24 189386820 ps
T296 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3365870957 Jan 25 01:09:44 PM PST 24 Jan 25 01:09:51 PM PST 24 108243779 ps
T297 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2734165016 Jan 25 01:09:47 PM PST 24 Jan 25 01:09:56 PM PST 24 380962932 ps
T298 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3766919678 Jan 25 01:12:23 PM PST 24 Jan 25 01:12:25 PM PST 24 21188731 ps
T299 /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.266237692 Jan 25 01:09:42 PM PST 24 Jan 25 01:09:48 PM PST 24 40593964 ps
T300 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.1446564344 Jan 25 01:12:25 PM PST 24 Jan 25 01:12:29 PM PST 24 10363310 ps
T301 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2001407668 Jan 25 01:09:49 PM PST 24 Jan 25 01:10:03 PM PST 24 238594697 ps
T302 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.4081333352 Jan 25 01:12:33 PM PST 24 Jan 25 01:12:39 PM PST 24 56243740 ps
T303 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1690040622 Jan 25 01:11:25 PM PST 24 Jan 25 01:11:28 PM PST 24 65983988 ps
T304 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2126214138 Jan 25 01:11:23 PM PST 24 Jan 25 01:11:27 PM PST 24 69369661 ps
T305 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3982891924 Jan 25 01:12:38 PM PST 24 Jan 25 01:12:49 PM PST 24 349502669 ps
T306 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.534838031 Jan 25 01:09:40 PM PST 24 Jan 25 01:09:48 PM PST 24 116487320 ps
T307 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2503142728 Jan 25 01:11:24 PM PST 24 Jan 25 01:11:30 PM PST 24 391453772 ps
T308 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.1738912180 Jan 25 01:09:45 PM PST 24 Jan 25 01:09:53 PM PST 24 36594086 ps
T309 /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2394436024 Jan 25 01:09:47 PM PST 24 Jan 25 01:09:54 PM PST 24 61755235 ps
T310 /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.2823913841 Jan 25 01:12:24 PM PST 24 Jan 25 01:12:26 PM PST 24 38002590 ps

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.4151431254
Short name T4
Test name
Test status
Simulation time 596321990 ps
CPU time 3.93 seconds
Started Jan 25 01:05:42 PM PST 24
Finished Jan 25 01:05:55 PM PST 24
Peak memory 206916 kb
Host smart-b4c870d5-365d-46b1-9a18-44490ba91a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151431254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.4151431254
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3891041863
Short name T56
Test name
Test status
Simulation time 125579064 ps
CPU time 3.19 seconds
Started Jan 25 01:10:57 PM PST 24
Finished Jan 25 01:11:07 PM PST 24
Peak memory 213864 kb
Host smart-8f764869-6226-42ca-a75c-f15f0daffa0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891041863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3891041863
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.4218020695
Short name T7
Test name
Test status
Simulation time 552404320 ps
CPU time 7.87 seconds
Started Jan 25 01:05:11 PM PST 24
Finished Jan 25 01:05:29 PM PST 24
Peak memory 227356 kb
Host smart-46bacf99-c1ec-48ed-b2c9-a4c773b00fd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218020695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.4218020695
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.232597292
Short name T27
Test name
Test status
Simulation time 676183482 ps
CPU time 6.32 seconds
Started Jan 25 01:04:33 PM PST 24
Finished Jan 25 01:04:44 PM PST 24
Peak memory 206572 kb
Host smart-a4848ce1-fe9d-4d5e-841f-976fc794e731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232597292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.232597292
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1689141355
Short name T48
Test name
Test status
Simulation time 1669659567 ps
CPU time 3.43 seconds
Started Jan 25 01:09:57 PM PST 24
Finished Jan 25 01:10:04 PM PST 24
Peak memory 213576 kb
Host smart-44604324-7f15-4e0c-9f1a-71312310f3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689141355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
689141355
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1017296058
Short name T26
Test name
Test status
Simulation time 247483738 ps
CPU time 5.9 seconds
Started Jan 25 01:05:19 PM PST 24
Finished Jan 25 01:05:35 PM PST 24
Peak memory 205464 kb
Host smart-c89e4a25-9260-4398-8042-edbe452d494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017296058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1017296058
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.2350273501
Short name T25
Test name
Test status
Simulation time 96161048 ps
CPU time 3.37 seconds
Started Jan 25 01:06:40 PM PST 24
Finished Jan 25 01:06:46 PM PST 24
Peak memory 206904 kb
Host smart-b7c0ef1b-8ed3-448b-a980-96e822143ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350273501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.2350273501
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.3491581328
Short name T126
Test name
Test status
Simulation time 24622347 ps
CPU time 0.71 seconds
Started Jan 25 01:04:30 PM PST 24
Finished Jan 25 01:04:37 PM PST 24
Peak memory 204344 kb
Host smart-e800d5f4-c867-420b-9fbd-aa79281f573c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491581328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.3
491581328
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.2609109018
Short name T86
Test name
Test status
Simulation time 110919425 ps
CPU time 4.58 seconds
Started Jan 25 01:11:17 PM PST 24
Finished Jan 25 01:11:23 PM PST 24
Peak memory 213444 kb
Host smart-4f2df12d-3c8d-4d0e-b045-7ade61558a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609109018 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.2609109018
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.2130171696
Short name T122
Test name
Test status
Simulation time 79856231 ps
CPU time 1.88 seconds
Started Jan 25 01:05:54 PM PST 24
Finished Jan 25 01:06:08 PM PST 24
Peak memory 205856 kb
Host smart-62fe414f-626f-4dee-b41f-50f9857b5164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130171696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.2130171696
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1384103974
Short name T75
Test name
Test status
Simulation time 97555760 ps
CPU time 2.03 seconds
Started Jan 25 01:10:57 PM PST 24
Finished Jan 25 01:11:06 PM PST 24
Peak memory 213768 kb
Host smart-a0f7c534-4cc2-4ffd-a67f-8338ef2c2231
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384103974 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1384103974
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.504350300
Short name T79
Test name
Test status
Simulation time 21491590 ps
CPU time 0.75 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 205020 kb
Host smart-6de22eb2-541c-4d09-9039-416eb6a7d28c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504350300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.504350300
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3304780220
Short name T40
Test name
Test status
Simulation time 760207197 ps
CPU time 3.04 seconds
Started Jan 25 01:05:47 PM PST 24
Finished Jan 25 01:06:02 PM PST 24
Peak memory 207088 kb
Host smart-d961ac13-66b9-4d88-a0ff-a35b07f94bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304780220 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3304780220
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.3870403433
Short name T38
Test name
Test status
Simulation time 7961197262 ps
CPU time 18.76 seconds
Started Jan 25 01:06:09 PM PST 24
Finished Jan 25 01:06:36 PM PST 24
Peak memory 206448 kb
Host smart-b1e67ed0-5ebf-4810-b2fd-97b67d1faa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870403433 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.3870403433
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.2730322956
Short name T101
Test name
Test status
Simulation time 4359914053 ps
CPU time 6.87 seconds
Started Jan 25 01:07:23 PM PST 24
Finished Jan 25 01:07:31 PM PST 24
Peak memory 206412 kb
Host smart-3ecc334f-bf56-43d8-af48-4467e2cf656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730322956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.2730322956
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.416876968
Short name T228
Test name
Test status
Simulation time 149921132 ps
CPU time 2.38 seconds
Started Jan 25 01:11:57 PM PST 24
Finished Jan 25 01:12:00 PM PST 24
Peak memory 213596 kb
Host smart-894d1a98-7617-426b-80db-061927442dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416876968 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.416876968
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2490040325
Short name T91
Test name
Test status
Simulation time 104660977 ps
CPU time 4.72 seconds
Started Jan 25 01:11:28 PM PST 24
Finished Jan 25 01:11:35 PM PST 24
Peak memory 214616 kb
Host smart-3af20fea-2f0c-4b54-b6ec-2fdf971d2e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490040325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.2490040325
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2221590988
Short name T29
Test name
Test status
Simulation time 170132231 ps
CPU time 3.33 seconds
Started Jan 25 01:04:26 PM PST 24
Finished Jan 25 01:04:31 PM PST 24
Peak memory 206936 kb
Host smart-9cb376d7-d616-44ca-a15d-b6cb171acd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221590988 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2221590988
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.511345490
Short name T111
Test name
Test status
Simulation time 32299017 ps
CPU time 1.74 seconds
Started Jan 25 02:17:37 PM PST 24
Finished Jan 25 02:18:05 PM PST 24
Peak memory 205204 kb
Host smart-923c42ae-dfed-4ae7-b93d-8e60a7e6b2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511345490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.511345490
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.1292094703
Short name T103
Test name
Test status
Simulation time 759009114 ps
CPU time 4.05 seconds
Started Jan 25 01:16:56 PM PST 24
Finished Jan 25 01:17:08 PM PST 24
Peak memory 207036 kb
Host smart-2083504b-59b1-4c60-9921-30f10a8e697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292094703 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.1292094703
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.3080288163
Short name T5
Test name
Test status
Simulation time 1000288810 ps
CPU time 19.35 seconds
Started Jan 25 01:05:26 PM PST 24
Finished Jan 25 01:05:54 PM PST 24
Peak memory 207700 kb
Host smart-64c60098-3e3a-4ddd-8252-c6bddf418110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080288163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.3080288163
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.771815607
Short name T89
Test name
Test status
Simulation time 220923010 ps
CPU time 5.07 seconds
Started Jan 25 01:09:46 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 214732 kb
Host smart-286be764-2177-48dc-a013-99f31f664711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771815607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_
tl_intg_err.771815607
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.3695616665
Short name T90
Test name
Test status
Simulation time 599691643 ps
CPU time 4.96 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 213392 kb
Host smart-597ad825-821d-4beb-9022-51021229b7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695616665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.3695616665
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.1298801750
Short name T109
Test name
Test status
Simulation time 59557820 ps
CPU time 2.41 seconds
Started Jan 25 01:06:17 PM PST 24
Finished Jan 25 01:06:27 PM PST 24
Peak memory 206532 kb
Host smart-0a7365c1-adec-4293-8ce1-1216a1aa5671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298801750 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.1298801750
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.3924664054
Short name T8
Test name
Test status
Simulation time 846254930 ps
CPU time 10.64 seconds
Started Jan 25 01:04:32 PM PST 24
Finished Jan 25 01:04:48 PM PST 24
Peak memory 227684 kb
Host smart-bb9cb212-8fad-4eee-85e6-d9897c59e5ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924664054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.3924664054
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.725680550
Short name T93
Test name
Test status
Simulation time 113521225 ps
CPU time 4.22 seconds
Started Jan 25 01:12:38 PM PST 24
Finished Jan 25 01:12:43 PM PST 24
Peak memory 205488 kb
Host smart-d8ed074c-a47e-4196-9a99-80ccccbf4de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725680550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.725680550
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.2319871608
Short name T85
Test name
Test status
Simulation time 198173384 ps
CPU time 5.14 seconds
Started Jan 25 01:11:03 PM PST 24
Finished Jan 25 01:11:14 PM PST 24
Peak memory 214660 kb
Host smart-dd6c2410-1280-4378-ab3c-62d2787a22c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319871608 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.2319871608
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1004246257
Short name T278
Test name
Test status
Simulation time 27404938 ps
CPU time 1.87 seconds
Started Jan 25 01:09:40 PM PST 24
Finished Jan 25 01:09:47 PM PST 24
Peak memory 213560 kb
Host smart-740a4d5b-680e-467a-9a57-ffcf424b66ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004246257 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1004246257
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.4179459157
Short name T104
Test name
Test status
Simulation time 1619492351 ps
CPU time 3.71 seconds
Started Jan 25 01:05:54 PM PST 24
Finished Jan 25 01:06:10 PM PST 24
Peak memory 207252 kb
Host smart-c279c3fd-7724-44e2-8462-80812dced097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179459157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.4179459157
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.574909410
Short name T83
Test name
Test status
Simulation time 371081480 ps
CPU time 2.61 seconds
Started Jan 25 01:11:25 PM PST 24
Finished Jan 25 01:11:30 PM PST 24
Peak memory 213776 kb
Host smart-f044a6dd-2b71-4134-9ec2-15f66d8f71f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574909410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe
_tl_intg_err.574909410
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1703716514
Short name T50
Test name
Test status
Simulation time 1008696520 ps
CPU time 5.58 seconds
Started Jan 25 01:11:45 PM PST 24
Finished Jan 25 01:11:52 PM PST 24
Peak memory 214492 kb
Host smart-63d8de48-b6c7-4b24-933e-91e7d0109467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703716514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.1703716514
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2533185769
Short name T92
Test name
Test status
Simulation time 131060779 ps
CPU time 4.66 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:34 PM PST 24
Peak memory 214664 kb
Host smart-18cb32ba-3507-4b3c-bcbc-da74fc6a97de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533185769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.2533185769
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.771571487
Short name T76
Test name
Test status
Simulation time 92650125 ps
CPU time 4.53 seconds
Started Jan 25 01:09:46 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 213400 kb
Host smart-d6fb7943-6227-4fc5-9ec4-5c7a155bf978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771571487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_
tl_intg_err.771571487
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2528772604
Short name T88
Test name
Test status
Simulation time 430839632 ps
CPU time 4.18 seconds
Started Jan 25 01:11:01 PM PST 24
Finished Jan 25 01:11:10 PM PST 24
Peak memory 213628 kb
Host smart-b433f422-c5b7-46f0-99eb-13478f12b77b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528772604 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2528772604
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.3903378383
Short name T168
Test name
Test status
Simulation time 21217984 ps
CPU time 0.69 seconds
Started Jan 25 01:11:22 PM PST 24
Finished Jan 25 01:11:25 PM PST 24
Peak memory 205016 kb
Host smart-a6aa0df3-5f70-42b9-8c97-e80dcfeef5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903378383 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
3903378383
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.2541533955
Short name T15
Test name
Test status
Simulation time 286779257 ps
CPU time 3.16 seconds
Started Jan 25 01:05:08 PM PST 24
Finished Jan 25 01:05:24 PM PST 24
Peak memory 206884 kb
Host smart-fb51e48b-2c84-468c-b375-2792642371a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541533955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.2541533955
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.1313561251
Short name T119
Test name
Test status
Simulation time 105911091 ps
CPU time 1.91 seconds
Started Jan 25 01:05:29 PM PST 24
Finished Jan 25 01:05:42 PM PST 24
Peak memory 205896 kb
Host smart-2ae84d40-d58c-4738-9234-1fc99cbd3b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313561251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.1313561251
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.4213270567
Short name T110
Test name
Test status
Simulation time 82270229 ps
CPU time 3.25 seconds
Started Jan 25 01:05:44 PM PST 24
Finished Jan 25 01:05:58 PM PST 24
Peak memory 206544 kb
Host smart-63011449-34f9-4243-9fb0-a2caa9fd7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213270567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.4213270567
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.2852321452
Short name T10
Test name
Test status
Simulation time 103317562 ps
CPU time 2.83 seconds
Started Jan 25 01:06:12 PM PST 24
Finished Jan 25 01:06:22 PM PST 24
Peak memory 205296 kb
Host smart-ac10e8a9-f783-4df2-89e1-5b0d3783a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852321452 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.2852321452
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3477307973
Short name T114
Test name
Test status
Simulation time 526491975 ps
CPU time 8.44 seconds
Started Jan 25 01:06:11 PM PST 24
Finished Jan 25 01:06:27 PM PST 24
Peak memory 206700 kb
Host smart-2ed33961-ace1-4320-bb1e-57aa2475aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477307973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3477307973
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.800080352
Short name T105
Test name
Test status
Simulation time 2871468937 ps
CPU time 16.46 seconds
Started Jan 25 01:06:42 PM PST 24
Finished Jan 25 01:07:02 PM PST 24
Peak memory 206212 kb
Host smart-5209d21f-ace4-40d7-a80c-64eef5fd33d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800080352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.800080352
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.3870121557
Short name T112
Test name
Test status
Simulation time 192629375 ps
CPU time 2.29 seconds
Started Jan 25 01:06:42 PM PST 24
Finished Jan 25 01:06:47 PM PST 24
Peak memory 205692 kb
Host smart-4e3e344f-442e-496c-953b-37b9bd8bceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870121557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.3870121557
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.105255616
Short name T106
Test name
Test status
Simulation time 120663079 ps
CPU time 2.23 seconds
Started Jan 25 01:06:49 PM PST 24
Finished Jan 25 01:06:55 PM PST 24
Peak memory 205380 kb
Host smart-07dbb6a5-2a0a-47be-a8a1-3a6f9e2f742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105255616 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.105255616
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3352818853
Short name T108
Test name
Test status
Simulation time 338720431 ps
CPU time 2.93 seconds
Started Jan 25 01:05:11 PM PST 24
Finished Jan 25 01:05:24 PM PST 24
Peak memory 207088 kb
Host smart-4f26d360-c92e-43b1-919f-e630babd0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352818853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3352818853
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.2492568808
Short name T102
Test name
Test status
Simulation time 211223332 ps
CPU time 1.74 seconds
Started Jan 25 01:05:11 PM PST 24
Finished Jan 25 01:05:23 PM PST 24
Peak memory 205236 kb
Host smart-b4f69fb9-48a3-4dfc-bf24-a57fddc12ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492568808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.2492568808
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3170795912
Short name T33
Test name
Test status
Simulation time 1425907126 ps
CPU time 18.02 seconds
Started Jan 25 01:04:36 PM PST 24
Finished Jan 25 01:04:59 PM PST 24
Peak memory 232156 kb
Host smart-6b875ee4-b0ac-4887-bd4e-39477da0b89b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170795912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3170795912
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.534838031
Short name T306
Test name
Test status
Simulation time 116487320 ps
CPU time 3.59 seconds
Started Jan 25 01:09:40 PM PST 24
Finished Jan 25 01:09:48 PM PST 24
Peak memory 205228 kb
Host smart-49827cc5-dabe-47fc-9019-c82fe5f2ade7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534838031 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.534838031
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.287548519
Short name T172
Test name
Test status
Simulation time 103025817 ps
CPU time 4.55 seconds
Started Jan 25 01:09:45 PM PST 24
Finished Jan 25 01:09:55 PM PST 24
Peak memory 205316 kb
Host smart-d287ee91-b6af-4c04-992e-0edd6bbd2011
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287548519 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_bit_bash.287548519
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.399663593
Short name T174
Test name
Test status
Simulation time 71964054 ps
CPU time 0.91 seconds
Started Jan 25 01:09:43 PM PST 24
Finished Jan 25 01:09:49 PM PST 24
Peak memory 205036 kb
Host smart-c1e08279-d2de-4c6d-b111-c480ded8af3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399663593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_hw_reset.399663593
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2100599033
Short name T247
Test name
Test status
Simulation time 235905727 ps
CPU time 1.28 seconds
Started Jan 25 01:09:48 PM PST 24
Finished Jan 25 01:09:56 PM PST 24
Peak memory 205300 kb
Host smart-18789701-4be7-4022-82f2-e7407c82cd2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100599033 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
100599033
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2394436024
Short name T309
Test name
Test status
Simulation time 61755235 ps
CPU time 0.72 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 205120 kb
Host smart-fc50b319-da13-4ab2-8946-7e3d3267d515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394436024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
394436024
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.1738912180
Short name T308
Test name
Test status
Simulation time 36594086 ps
CPU time 1.9 seconds
Started Jan 25 01:09:45 PM PST 24
Finished Jan 25 01:09:53 PM PST 24
Peak memory 204840 kb
Host smart-24bc3ec7-1a6d-44a8-bbe3-b010c74372bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738912180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.1738912180
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.266237692
Short name T299
Test name
Test status
Simulation time 40593964 ps
CPU time 1.52 seconds
Started Jan 25 01:09:42 PM PST 24
Finished Jan 25 01:09:48 PM PST 24
Peak memory 213764 kb
Host smart-b70009fb-c7d4-472d-986f-0dbaef9d2ad3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266237692 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg
r_dpe_shadow_reg_errors.266237692
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2509819861
Short name T249
Test name
Test status
Simulation time 422420617 ps
CPU time 5.38 seconds
Started Jan 25 01:09:40 PM PST 24
Finished Jan 25 01:09:49 PM PST 24
Peak memory 213772 kb
Host smart-f76eb404-afce-4240-bd9b-f37aefc7c6c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509819861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2509819861
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.1004993260
Short name T258
Test name
Test status
Simulation time 50569858 ps
CPU time 3.45 seconds
Started Jan 25 01:09:40 PM PST 24
Finished Jan 25 01:09:48 PM PST 24
Peak memory 221720 kb
Host smart-78929c9b-d59c-48e0-8f4a-9c3365439647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004993260 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.1
004993260
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1613999946
Short name T43
Test name
Test status
Simulation time 179591707 ps
CPU time 6.92 seconds
Started Jan 25 01:09:44 PM PST 24
Finished Jan 25 01:09:56 PM PST 24
Peak memory 213444 kb
Host smart-1b8b7471-0afb-4047-b709-69a434ff3a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613999946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1613999946
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.798213404
Short name T98
Test name
Test status
Simulation time 508051232 ps
CPU time 3.02 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:56 PM PST 24
Peak memory 205352 kb
Host smart-98ae83bd-9a7d-4840-a6f9-5befba1cff08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798213404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_aliasing.798213404
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2803456299
Short name T196
Test name
Test status
Simulation time 1763418316 ps
CPU time 9.76 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:10:03 PM PST 24
Peak memory 205268 kb
Host smart-51f304a0-e2e7-4421-aecd-a5d1e3cf1be1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803456299 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.2803456299
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2836142914
Short name T213
Test name
Test status
Simulation time 16065905 ps
CPU time 1.1 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 205284 kb
Host smart-62345742-aab7-46fb-b9a7-d35561f848b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836142914 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2836142914
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3590297764
Short name T226
Test name
Test status
Simulation time 13704031 ps
CPU time 1 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:55 PM PST 24
Peak memory 205560 kb
Host smart-4da3aa3a-88af-4ac9-86b5-6f4c713e0403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590297764 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3590297764
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3652123069
Short name T66
Test name
Test status
Simulation time 11765231 ps
CPU time 1.08 seconds
Started Jan 25 01:09:46 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 205268 kb
Host smart-859aedbf-f435-4ba0-bcc3-c70d458d2ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652123069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.3
652123069
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1603223491
Short name T169
Test name
Test status
Simulation time 10462767 ps
CPU time 0.67 seconds
Started Jan 25 01:09:41 PM PST 24
Finished Jan 25 01:09:47 PM PST 24
Peak memory 205016 kb
Host smart-f22a6105-ea15-4556-bca6-694408133062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603223491 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1
603223491
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2734165016
Short name T297
Test name
Test status
Simulation time 380962932 ps
CPU time 2.3 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:56 PM PST 24
Peak memory 205492 kb
Host smart-81723847-aac3-46fd-bb13-04135876b9c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734165016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.2734165016
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2350997618
Short name T243
Test name
Test status
Simulation time 67763114 ps
CPU time 2.05 seconds
Started Jan 25 01:09:44 PM PST 24
Finished Jan 25 01:09:52 PM PST 24
Peak memory 213860 kb
Host smart-7db499ca-fd91-485e-8a6c-2a7f996648a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350997618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2350997618
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.4002465048
Short name T266
Test name
Test status
Simulation time 96584467 ps
CPU time 2.56 seconds
Started Jan 25 01:09:45 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 213376 kb
Host smart-ceee5a3a-0b67-4f5e-8b60-bc6f02b6a6e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002465048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.4002465048
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2212027592
Short name T80
Test name
Test status
Simulation time 38462359 ps
CPU time 2.61 seconds
Started Jan 25 01:09:44 PM PST 24
Finished Jan 25 01:09:53 PM PST 24
Peak memory 221124 kb
Host smart-9b5584ed-f45a-4fef-899a-2babce3500ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212027592 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.2
212027592
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2126214138
Short name T304
Test name
Test status
Simulation time 69369661 ps
CPU time 1.03 seconds
Started Jan 25 01:11:23 PM PST 24
Finished Jan 25 01:11:27 PM PST 24
Peak memory 215708 kb
Host smart-fb035830-948d-4a09-8b92-409e2a8fe24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126214138 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2126214138
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2994869836
Short name T191
Test name
Test status
Simulation time 14180514 ps
CPU time 1.06 seconds
Started Jan 25 01:11:22 PM PST 24
Finished Jan 25 01:11:25 PM PST 24
Peak memory 205288 kb
Host smart-22e9f4e8-d8df-4a5c-a8c9-a62b0dce1416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994869836 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2994869836
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.932271728
Short name T78
Test name
Test status
Simulation time 76294606 ps
CPU time 0.74 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:27 PM PST 24
Peak memory 205124 kb
Host smart-7f22f95b-c470-4658-bfe2-6f9dbf40bf45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932271728 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.932271728
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3697025928
Short name T71
Test name
Test status
Simulation time 19079332 ps
CPU time 1.2 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:32 PM PST 24
Peak memory 205252 kb
Host smart-cb834be1-fee9-4ae7-8b8a-98d32ce5fef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697025928 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.3697025928
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.745312620
Short name T100
Test name
Test status
Simulation time 81554078 ps
CPU time 1.43 seconds
Started Jan 25 01:11:22 PM PST 24
Finished Jan 25 01:11:25 PM PST 24
Peak memory 213920 kb
Host smart-5710aebd-13b2-4a52-9bbc-97f7288aa564
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745312620 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keym
gr_dpe_shadow_reg_errors.745312620
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2503142728
Short name T307
Test name
Test status
Simulation time 391453772 ps
CPU time 4.03 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:30 PM PST 24
Peak memory 213956 kb
Host smart-c2fb7792-5dd3-4d19-a99a-35e362b6cd3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503142728 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2503142728
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.3142564089
Short name T23
Test name
Test status
Simulation time 218725694 ps
CPU time 2.45 seconds
Started Jan 25 01:11:25 PM PST 24
Finished Jan 25 01:11:30 PM PST 24
Peak memory 214480 kb
Host smart-c2124538-1ff9-43a1-a843-fb7e57c502a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142564089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
3142564089
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3838741212
Short name T97
Test name
Test status
Simulation time 63038503 ps
CPU time 1.29 seconds
Started Jan 25 01:11:28 PM PST 24
Finished Jan 25 01:11:32 PM PST 24
Peak memory 205304 kb
Host smart-e8458c4a-fcdb-4e5c-b2bb-5350903d0197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838741212 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3838741212
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1690040622
Short name T303
Test name
Test status
Simulation time 65983988 ps
CPU time 1.07 seconds
Started Jan 25 01:11:25 PM PST 24
Finished Jan 25 01:11:28 PM PST 24
Peak memory 205208 kb
Host smart-93e7baed-5424-4f8b-b5fe-41048f20d147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690040622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1690040622
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2875784844
Short name T216
Test name
Test status
Simulation time 91171751 ps
CPU time 3.35 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:40 PM PST 24
Peak memory 205188 kb
Host smart-906febb9-e0e7-4510-9985-9b4dadb56c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875784844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2875784844
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1903760874
Short name T224
Test name
Test status
Simulation time 57783817 ps
CPU time 1.67 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:28 PM PST 24
Peak memory 213800 kb
Host smart-1d91731a-dff2-428e-96fe-4133ae099d86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903760874 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1903760874
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.309796187
Short name T178
Test name
Test status
Simulation time 370591665 ps
CPU time 5.08 seconds
Started Jan 25 01:11:23 PM PST 24
Finished Jan 25 01:11:31 PM PST 24
Peak memory 219652 kb
Host smart-b393edd9-6a06-432d-a1e6-ceaf62a8cb3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309796187 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.309796187
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.193086360
Short name T238
Test name
Test status
Simulation time 53420470 ps
CPU time 1.54 seconds
Started Jan 25 01:11:25 PM PST 24
Finished Jan 25 01:11:29 PM PST 24
Peak memory 205252 kb
Host smart-db5265fe-05ae-49a1-85e7-86e873a7f49b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193086360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.193086360
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3999781444
Short name T87
Test name
Test status
Simulation time 654028737 ps
CPU time 2.88 seconds
Started Jan 25 01:11:28 PM PST 24
Finished Jan 25 01:11:33 PM PST 24
Peak memory 213508 kb
Host smart-aa515329-5df9-4083-ba13-fdf7fd198a21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999781444 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3999781444
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.1721436367
Short name T257
Test name
Test status
Simulation time 20177720 ps
CPU time 1.22 seconds
Started Jan 25 01:11:55 PM PST 24
Finished Jan 25 01:11:57 PM PST 24
Peak memory 221304 kb
Host smart-ccf6599e-fd88-4825-8b77-7188db830ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721436367 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.1721436367
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.6084784
Short name T99
Test name
Test status
Simulation time 25248299 ps
CPU time 0.91 seconds
Started Jan 25 01:11:44 PM PST 24
Finished Jan 25 01:11:46 PM PST 24
Peak memory 205052 kb
Host smart-562c0ff9-8816-4627-a480-adca4a63c99b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6084784 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.6084784
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2359050165
Short name T184
Test name
Test status
Simulation time 17335973 ps
CPU time 0.71 seconds
Started Jan 25 01:11:55 PM PST 24
Finished Jan 25 01:11:57 PM PST 24
Peak memory 205128 kb
Host smart-792a5d10-f6fd-4e4f-8ee5-36910ae8a5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359050165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2359050165
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2414334939
Short name T295
Test name
Test status
Simulation time 189386820 ps
CPU time 3.12 seconds
Started Jan 25 01:11:52 PM PST 24
Finished Jan 25 01:11:56 PM PST 24
Peak memory 205208 kb
Host smart-07254b83-88e1-4ac2-bf86-5c71e51a7c2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414334939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.2414334939
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1667527597
Short name T214
Test name
Test status
Simulation time 29028687 ps
CPU time 1.28 seconds
Started Jan 25 01:11:22 PM PST 24
Finished Jan 25 01:11:25 PM PST 24
Peak memory 213792 kb
Host smart-d96d6980-13e0-4169-9529-c2e190223183
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667527597 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1667527597
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1776891994
Short name T219
Test name
Test status
Simulation time 116521026 ps
CPU time 5.52 seconds
Started Jan 25 01:11:28 PM PST 24
Finished Jan 25 01:11:36 PM PST 24
Peak memory 213696 kb
Host smart-03773d41-fe19-4a47-83d3-a19229862e2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776891994 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1776891994
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1221892118
Short name T222
Test name
Test status
Simulation time 111490343 ps
CPU time 1.89 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:34 PM PST 24
Peak memory 213576 kb
Host smart-8c8a01df-0143-4221-a39b-e7083791bb18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221892118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
1221892118
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1404314055
Short name T289
Test name
Test status
Simulation time 13415992 ps
CPU time 0.82 seconds
Started Jan 25 01:12:02 PM PST 24
Finished Jan 25 01:12:04 PM PST 24
Peak memory 205192 kb
Host smart-f428b5c7-15a1-4331-82a5-0349fa23dac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404314055 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1404314055
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.32753748
Short name T197
Test name
Test status
Simulation time 35086601 ps
CPU time 1 seconds
Started Jan 25 01:11:44 PM PST 24
Finished Jan 25 01:11:47 PM PST 24
Peak memory 205316 kb
Host smart-1928c142-c82b-435b-ab7e-e67559bd4ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.32753748
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1375783494
Short name T236
Test name
Test status
Simulation time 59520539 ps
CPU time 0.74 seconds
Started Jan 25 01:11:43 PM PST 24
Finished Jan 25 01:11:45 PM PST 24
Peak memory 205236 kb
Host smart-d47e1ad8-6b9e-4c28-bf85-9addd73eac35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375783494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1375783494
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.3365087370
Short name T265
Test name
Test status
Simulation time 29384246 ps
CPU time 1.72 seconds
Started Jan 25 01:11:42 PM PST 24
Finished Jan 25 01:11:45 PM PST 24
Peak memory 205244 kb
Host smart-720c952f-7176-4db1-8222-0923bded74b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365087370 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.3365087370
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1033232233
Short name T57
Test name
Test status
Simulation time 85172421 ps
CPU time 2.58 seconds
Started Jan 25 01:11:44 PM PST 24
Finished Jan 25 01:11:48 PM PST 24
Peak memory 213860 kb
Host smart-dae325cc-4192-40db-aa3e-a608e0b41ba2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033232233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1033232233
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3057990227
Short name T241
Test name
Test status
Simulation time 561201823 ps
CPU time 9.23 seconds
Started Jan 25 01:11:44 PM PST 24
Finished Jan 25 01:11:55 PM PST 24
Peak memory 213720 kb
Host smart-0a0b7d11-8b22-46d7-a2cf-82ee6b962821
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057990227 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3057990227
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.3974351310
Short name T94
Test name
Test status
Simulation time 237030682 ps
CPU time 2.68 seconds
Started Jan 25 01:11:54 PM PST 24
Finished Jan 25 01:11:58 PM PST 24
Peak memory 213628 kb
Host smart-dd07fc7e-a3ad-49ff-a18e-ebb423d42550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974351310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
3974351310
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.2694335620
Short name T22
Test name
Test status
Simulation time 161995671 ps
CPU time 1.22 seconds
Started Jan 25 01:12:21 PM PST 24
Finished Jan 25 01:12:24 PM PST 24
Peak memory 213604 kb
Host smart-2f70f6cf-60ac-49e7-98ea-683ec8245520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694335620 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.2694335620
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.3271582995
Short name T246
Test name
Test status
Simulation time 30083848 ps
CPU time 0.93 seconds
Started Jan 25 01:12:21 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 205160 kb
Host smart-17b8fd17-3df3-47e9-95b9-f6a1787e8673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271582995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
3271582995
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2761230956
Short name T261
Test name
Test status
Simulation time 15225854 ps
CPU time 0.85 seconds
Started Jan 25 01:12:19 PM PST 24
Finished Jan 25 01:12:21 PM PST 24
Peak memory 205440 kb
Host smart-51a80beb-31db-42fc-8b07-854483e4e3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761230956 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2761230956
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.71576655
Short name T215
Test name
Test status
Simulation time 246509653 ps
CPU time 1.56 seconds
Started Jan 25 01:12:17 PM PST 24
Finished Jan 25 01:12:19 PM PST 24
Peak memory 205212 kb
Host smart-01ae3a24-98f6-44cb-8c2e-9a0a7dd7feea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71576655 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ke
ymgr_dpe_same_csr_outstanding.71576655
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2965837858
Short name T220
Test name
Test status
Simulation time 798025402 ps
CPU time 2.25 seconds
Started Jan 25 01:11:46 PM PST 24
Finished Jan 25 01:11:49 PM PST 24
Peak memory 213916 kb
Host smart-6e883283-5adc-46f8-a0e8-8ecf2c69b24a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965837858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2965837858
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.641793753
Short name T70
Test name
Test status
Simulation time 261444697 ps
CPU time 5.43 seconds
Started Jan 25 01:11:57 PM PST 24
Finished Jan 25 01:12:03 PM PST 24
Peak memory 213964 kb
Host smart-dc47a1bc-4834-4e10-8711-500b9da46640
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641793753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.641793753
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1024616079
Short name T227
Test name
Test status
Simulation time 58184714 ps
CPU time 1.27 seconds
Started Jan 25 01:12:21 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 205228 kb
Host smart-5084c3e8-358a-452f-91bb-7981fdd26c91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024616079 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1024616079
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.899514736
Short name T288
Test name
Test status
Simulation time 28427598 ps
CPU time 1.02 seconds
Started Jan 25 01:12:17 PM PST 24
Finished Jan 25 01:12:19 PM PST 24
Peak memory 205304 kb
Host smart-b48ee40a-b028-486b-a322-4f6e49edc3fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899514736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.899514736
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3441558054
Short name T211
Test name
Test status
Simulation time 28603220 ps
CPU time 0.76 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:28 PM PST 24
Peak memory 205096 kb
Host smart-eebfbba4-0b43-4c25-91c1-982d306a0e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441558054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3441558054
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3688996984
Short name T209
Test name
Test status
Simulation time 174402780 ps
CPU time 1.35 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:32 PM PST 24
Peak memory 205280 kb
Host smart-2c226881-e008-4f01-99bf-bae45894c4bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688996984 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3688996984
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2980146093
Short name T198
Test name
Test status
Simulation time 44345341 ps
CPU time 1.82 seconds
Started Jan 25 01:12:18 PM PST 24
Finished Jan 25 01:12:21 PM PST 24
Peak memory 214004 kb
Host smart-5de486e2-1965-4e11-a51d-29b1fd4654a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980146093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2980146093
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.2944137183
Short name T234
Test name
Test status
Simulation time 219922270 ps
CPU time 2.41 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 213884 kb
Host smart-c42cbe47-99da-4f85-ac2d-fff177cea09a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944137183 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.2944137183
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.4081333352
Short name T302
Test name
Test status
Simulation time 56243740 ps
CPU time 2.31 seconds
Started Jan 25 01:12:33 PM PST 24
Finished Jan 25 01:12:39 PM PST 24
Peak memory 214288 kb
Host smart-08b491c3-c623-4a31-82e4-c3b910c6bfcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081333352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
4081333352
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.1638301050
Short name T232
Test name
Test status
Simulation time 100075527 ps
CPU time 2.19 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:24 PM PST 24
Peak memory 214468 kb
Host smart-2dff250b-d7a0-4138-acf9-707a859d0209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638301050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.1638301050
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.289029538
Short name T201
Test name
Test status
Simulation time 95524940 ps
CPU time 1.22 seconds
Started Jan 25 01:12:19 PM PST 24
Finished Jan 25 01:12:22 PM PST 24
Peak memory 205452 kb
Host smart-8a08fbe8-5c1a-4589-a499-64f0fc494721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289029538 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.289029538
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1749365360
Short name T264
Test name
Test status
Simulation time 11563750 ps
CPU time 0.8 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205112 kb
Host smart-3580f6c4-c726-4cc4-ad77-8ca9e0eca5f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749365360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1749365360
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.701970884
Short name T52
Test name
Test status
Simulation time 11534138 ps
CPU time 0.7 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 205004 kb
Host smart-97e91d36-226e-4c09-be58-c095eee968f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701970884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.701970884
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2450955587
Short name T272
Test name
Test status
Simulation time 168589082 ps
CPU time 1.4 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:27 PM PST 24
Peak memory 205496 kb
Host smart-ae28ab6b-674b-44cb-a7dc-12417c8e6c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450955587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.2450955587
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.121307461
Short name T64
Test name
Test status
Simulation time 78729384 ps
CPU time 1.57 seconds
Started Jan 25 01:12:23 PM PST 24
Finished Jan 25 01:12:27 PM PST 24
Peak memory 213848 kb
Host smart-ffa90b1e-2414-45a7-b043-348a4b94e5cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121307461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keym
gr_dpe_shadow_reg_errors.121307461
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3804174931
Short name T72
Test name
Test status
Simulation time 228481473 ps
CPU time 3.02 seconds
Started Jan 25 01:12:17 PM PST 24
Finished Jan 25 01:12:21 PM PST 24
Peak memory 213872 kb
Host smart-35680dd4-c884-421b-863c-0f0b68b7a519
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804174931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3804174931
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.3755830453
Short name T233
Test name
Test status
Simulation time 540215380 ps
CPU time 3.6 seconds
Started Jan 25 01:12:18 PM PST 24
Finished Jan 25 01:12:24 PM PST 24
Peak memory 213500 kb
Host smart-c77d6409-8d01-49b6-95e4-9a903dbaa0af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755830453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
3755830453
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.98718293
Short name T45
Test name
Test status
Simulation time 45215811 ps
CPU time 1.76 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 213764 kb
Host smart-e7e4cafc-8b54-4d73-8739-582645068467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98718293 -assert nopostproc +UVM_TESTNAME=k
eymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.98718293
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2838125334
Short name T253
Test name
Test status
Simulation time 101769320 ps
CPU time 1.07 seconds
Started Jan 25 01:12:23 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 205340 kb
Host smart-c07860b5-62e0-44dd-9f42-79cb98975745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838125334 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2838125334
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3181201803
Short name T199
Test name
Test status
Simulation time 9719738 ps
CPU time 0.71 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:22 PM PST 24
Peak memory 205056 kb
Host smart-28c3742d-d05e-4916-9042-9aaa40ba8999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181201803 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3181201803
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.2512518588
Short name T61
Test name
Test status
Simulation time 183706921 ps
CPU time 2.07 seconds
Started Jan 25 01:12:23 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 205320 kb
Host smart-b31c3ca4-2ded-40c9-a65d-385e4846184e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512518588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.2512518588
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.904391706
Short name T237
Test name
Test status
Simulation time 152354706 ps
CPU time 1.64 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 213824 kb
Host smart-f735f918-cf4d-4e77-9324-ffef46647f6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904391706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym
gr_dpe_shadow_reg_errors.904391706
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2893865450
Short name T256
Test name
Test status
Simulation time 787732777 ps
CPU time 5.42 seconds
Started Jan 25 01:12:21 PM PST 24
Finished Jan 25 01:12:27 PM PST 24
Peak memory 213824 kb
Host smart-c6c5fe2c-729a-4540-bec2-2c35be03f45d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893865450 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2893865450
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1256188881
Short name T47
Test name
Test status
Simulation time 139169885 ps
CPU time 4.8 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 216044 kb
Host smart-8a146e81-f75b-473e-aae7-297ca1eaa4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256188881 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
1256188881
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1505776945
Short name T81
Test name
Test status
Simulation time 880862685 ps
CPU time 5.7 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:27 PM PST 24
Peak memory 213488 kb
Host smart-0844652e-e5cb-4054-8e6c-d4695e6970af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505776945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1505776945
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3510839685
Short name T254
Test name
Test status
Simulation time 146574478 ps
CPU time 1.25 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:33 PM PST 24
Peak memory 213492 kb
Host smart-497c1608-4e9d-43c7-8449-6531fa39bd52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510839685 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3510839685
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3766919678
Short name T298
Test name
Test status
Simulation time 21188731 ps
CPU time 0.95 seconds
Started Jan 25 01:12:23 PM PST 24
Finished Jan 25 01:12:25 PM PST 24
Peak memory 205268 kb
Host smart-521b4699-98f0-4f19-b9cc-1c7572e03dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766919678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3766919678
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.2823913841
Short name T310
Test name
Test status
Simulation time 38002590 ps
CPU time 0.69 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 205096 kb
Host smart-1cd60dca-1eea-49c4-aaef-c1b8cb16a02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823913841 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
2823913841
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.480271221
Short name T185
Test name
Test status
Simulation time 306489536 ps
CPU time 1.94 seconds
Started Jan 25 01:12:38 PM PST 24
Finished Jan 25 01:12:41 PM PST 24
Peak memory 205284 kb
Host smart-b9cd4dde-a24e-4da1-9333-8eaca28d7e93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480271221 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.k
eymgr_dpe_same_csr_outstanding.480271221
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1521243795
Short name T218
Test name
Test status
Simulation time 101896999 ps
CPU time 2.05 seconds
Started Jan 25 01:12:18 PM PST 24
Finished Jan 25 01:12:21 PM PST 24
Peak memory 214028 kb
Host smart-278753bb-d6d6-41be-bcdb-bf0481f5a4ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521243795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1521243795
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2430891392
Short name T55
Test name
Test status
Simulation time 125082965 ps
CPU time 4.51 seconds
Started Jan 25 01:12:23 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 214052 kb
Host smart-6b053e94-7d85-4f10-aa19-db1cdc422532
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430891392 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2430891392
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.3875345905
Short name T44
Test name
Test status
Simulation time 155060953 ps
CPU time 2.43 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:31 PM PST 24
Peak memory 216924 kb
Host smart-08d1d355-aca5-4c6d-8083-3d889e1fc719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875345905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
3875345905
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2282344471
Short name T281
Test name
Test status
Simulation time 416763998 ps
CPU time 4.38 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:33 PM PST 24
Peak memory 214520 kb
Host smart-8a123a6d-83b7-4ba2-a606-5c4d08c5b3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282344471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.2282344471
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.2782603855
Short name T182
Test name
Test status
Simulation time 25011479 ps
CPU time 1.09 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205412 kb
Host smart-f8aca9b6-fc45-4dfa-bb28-ce2af69ab4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782603855 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.2782603855
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1163043748
Short name T294
Test name
Test status
Simulation time 11238264 ps
CPU time 0.85 seconds
Started Jan 25 01:12:29 PM PST 24
Finished Jan 25 01:12:36 PM PST 24
Peak memory 205124 kb
Host smart-b1efe9d8-d8a2-4ea3-8e48-4890b1f7b74b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163043748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
1163043748
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.829820635
Short name T250
Test name
Test status
Simulation time 21513185 ps
CPU time 0.94 seconds
Started Jan 25 01:12:38 PM PST 24
Finished Jan 25 01:12:41 PM PST 24
Peak memory 205328 kb
Host smart-df25fd8d-faf6-49f0-acf1-7f8bb0bc88b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829820635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.829820635
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1472902348
Short name T260
Test name
Test status
Simulation time 269319095 ps
CPU time 2.24 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205316 kb
Host smart-7ae05d3f-58c6-42c3-bd51-60c231037d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472902348 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.1472902348
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.1262040297
Short name T225
Test name
Test status
Simulation time 225249557 ps
CPU time 2.2 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 213852 kb
Host smart-702bf4ef-108d-4c43-804d-fd3214f6974b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262040297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.1262040297
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3982891924
Short name T305
Test name
Test status
Simulation time 349502669 ps
CPU time 9.64 seconds
Started Jan 25 01:12:38 PM PST 24
Finished Jan 25 01:12:49 PM PST 24
Peak memory 213804 kb
Host smart-8e407bb7-cfc0-40ed-97ec-9b8f49dab50d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982891924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3982891924
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2033613972
Short name T245
Test name
Test status
Simulation time 76770294 ps
CPU time 1.45 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:27 PM PST 24
Peak memory 221692 kb
Host smart-69673995-f243-4008-a42f-fe94702d4cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033613972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
2033613972
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.3795977839
Short name T186
Test name
Test status
Simulation time 77300422 ps
CPU time 4.54 seconds
Started Jan 25 01:09:51 PM PST 24
Finished Jan 25 01:10:02 PM PST 24
Peak memory 205320 kb
Host smart-60cd369d-b479-48e7-91a4-cd639fc0b725
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795977839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.3795977839
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3144003480
Short name T212
Test name
Test status
Simulation time 107791888 ps
CPU time 4.49 seconds
Started Jan 25 01:09:53 PM PST 24
Finished Jan 25 01:10:03 PM PST 24
Peak memory 205340 kb
Host smart-d9823b79-761f-4d48-abb4-bd5413cf02a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144003480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3144003480
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.1612670161
Short name T239
Test name
Test status
Simulation time 102933274 ps
CPU time 1.26 seconds
Started Jan 25 01:09:50 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 205340 kb
Host smart-9523f238-d608-4812-9a32-8e1c3babd164
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612670161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.1612670161
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3542591951
Short name T279
Test name
Test status
Simulation time 127868362 ps
CPU time 1.65 seconds
Started Jan 25 01:09:55 PM PST 24
Finished Jan 25 01:10:01 PM PST 24
Peak memory 213584 kb
Host smart-cbee351f-4594-427b-9620-e1af2f172ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542591951 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.3542591951
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2408315991
Short name T287
Test name
Test status
Simulation time 29040034 ps
CPU time 1.07 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:55 PM PST 24
Peak memory 205248 kb
Host smart-b1a81c37-aca5-416c-8044-80a4d465fc17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408315991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
408315991
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1098569097
Short name T210
Test name
Test status
Simulation time 12776392 ps
CPU time 0.72 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 205068 kb
Host smart-5a3b7d0f-9aa4-45ba-8764-15531582d665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098569097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.1
098569097
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2101723837
Short name T60
Test name
Test status
Simulation time 161888403 ps
CPU time 2.13 seconds
Started Jan 25 01:09:49 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 205196 kb
Host smart-2da9a830-450e-4997-993e-8d47591a54d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101723837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.2101723837
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3638219164
Short name T202
Test name
Test status
Simulation time 312610212 ps
CPU time 2.48 seconds
Started Jan 25 01:09:46 PM PST 24
Finished Jan 25 01:09:55 PM PST 24
Peak memory 213840 kb
Host smart-d0d59637-5219-4d6d-94b5-71af23f691da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638219164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3638219164
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4193701544
Short name T284
Test name
Test status
Simulation time 316524069 ps
CPU time 4.79 seconds
Started Jan 25 01:09:48 PM PST 24
Finished Jan 25 01:09:59 PM PST 24
Peak memory 214060 kb
Host smart-96221503-271b-4b76-bd74-9d98b47b478f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193701544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4193701544
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2960990092
Short name T46
Test name
Test status
Simulation time 236862614 ps
CPU time 1.9 seconds
Started Jan 25 01:09:50 PM PST 24
Finished Jan 25 01:09:58 PM PST 24
Peak memory 213508 kb
Host smart-ee4c7f77-d99a-40e9-bf13-67381664ab2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960990092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.2
960990092
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.4125734500
Short name T59
Test name
Test status
Simulation time 23731369 ps
CPU time 0.72 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205068 kb
Host smart-8af5d23f-539f-4d5c-b5ae-396f2b79d67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125734500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
4125734500
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.942964461
Short name T204
Test name
Test status
Simulation time 33726315 ps
CPU time 0.92 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:31 PM PST 24
Peak memory 205224 kb
Host smart-c90f56be-624f-4774-9852-af5702c3f230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942964461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.942964461
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.4240617725
Short name T95
Test name
Test status
Simulation time 9735146 ps
CPU time 0.81 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205088 kb
Host smart-60431966-7dfc-43d5-9148-043c9b00c64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240617725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
4240617725
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3706681534
Short name T125
Test name
Test status
Simulation time 10945785 ps
CPU time 0.68 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205032 kb
Host smart-2c3257cb-0939-4871-819b-4e395f583f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706681534 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3706681534
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.716814284
Short name T282
Test name
Test status
Simulation time 11180546 ps
CPU time 0.68 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:26 PM PST 24
Peak memory 205160 kb
Host smart-2a770fb5-dcef-4a00-9ba1-eace76d8560a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716814284 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.716814284
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.1800985132
Short name T62
Test name
Test status
Simulation time 24273632 ps
CPU time 0.77 seconds
Started Jan 25 01:12:24 PM PST 24
Finished Jan 25 01:12:28 PM PST 24
Peak memory 205072 kb
Host smart-f4d2e8ce-6ba8-420c-b6a0-b0d4978d771e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800985132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
1800985132
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.1446564344
Short name T300
Test name
Test status
Simulation time 10363310 ps
CPU time 0.85 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205096 kb
Host smart-c6cb6f48-c7dd-423d-a302-e096447048b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446564344 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
1446564344
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3411381569
Short name T235
Test name
Test status
Simulation time 10202226 ps
CPU time 0.76 seconds
Started Jan 25 01:12:20 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 205096 kb
Host smart-ecb7719e-6488-4cc0-b76a-51b7e278d47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411381569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
3411381569
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.4005964127
Short name T280
Test name
Test status
Simulation time 13625812 ps
CPU time 0.79 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205052 kb
Host smart-b13f8858-cc21-453e-af1c-a63e3b0b5e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005964127 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
4005964127
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3053272351
Short name T231
Test name
Test status
Simulation time 228622856 ps
CPU time 5.38 seconds
Started Jan 25 01:09:55 PM PST 24
Finished Jan 25 01:10:05 PM PST 24
Peak memory 205292 kb
Host smart-7656b503-668a-45c9-ab87-632a52a98047
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053272351 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.3053272351
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.2704706039
Short name T208
Test name
Test status
Simulation time 1220380730 ps
CPU time 12.39 seconds
Started Jan 25 01:09:53 PM PST 24
Finished Jan 25 01:10:11 PM PST 24
Peak memory 205316 kb
Host smart-b9d1317e-f479-401a-b91b-30d91ad88f86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704706039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.2704706039
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.2505032571
Short name T221
Test name
Test status
Simulation time 113276497 ps
CPU time 1.28 seconds
Started Jan 25 01:09:55 PM PST 24
Finished Jan 25 01:10:01 PM PST 24
Peak memory 205224 kb
Host smart-07f69053-0668-4def-9061-d9b7e0d78f66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505032571 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.2505032571
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3365870957
Short name T296
Test name
Test status
Simulation time 108243779 ps
CPU time 1.23 seconds
Started Jan 25 01:09:44 PM PST 24
Finished Jan 25 01:09:51 PM PST 24
Peak memory 213676 kb
Host smart-34013f58-fcdf-43b9-85d1-e537ff6a6756
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365870957 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.3365870957
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.132928753
Short name T271
Test name
Test status
Simulation time 63450899 ps
CPU time 1.04 seconds
Started Jan 25 01:09:55 PM PST 24
Finished Jan 25 01:10:01 PM PST 24
Peak memory 205196 kb
Host smart-a8a9d1d8-1e01-4f81-a58c-c2a0a8a15613
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132928753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.132928753
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2326821010
Short name T96
Test name
Test status
Simulation time 21222249 ps
CPU time 0.7 seconds
Started Jan 25 01:09:46 PM PST 24
Finished Jan 25 01:09:53 PM PST 24
Peak memory 205020 kb
Host smart-70946855-5a81-4650-8bc2-c15da047ed2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326821010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.2
326821010
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.644727870
Short name T229
Test name
Test status
Simulation time 113565144 ps
CPU time 1.99 seconds
Started Jan 25 01:09:55 PM PST 24
Finished Jan 25 01:10:02 PM PST 24
Peak memory 205192 kb
Host smart-ffcc2258-57f9-4b68-849f-9e5b1a580d03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644727870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.ke
ymgr_dpe_same_csr_outstanding.644727870
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.327006714
Short name T74
Test name
Test status
Simulation time 58042485 ps
CPU time 1.93 seconds
Started Jan 25 01:09:49 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 213880 kb
Host smart-83b5e0fe-f809-4280-beb0-3fed73570627
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327006714 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymg
r_dpe_shadow_reg_errors.327006714
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2001407668
Short name T301
Test name
Test status
Simulation time 238594697 ps
CPU time 8.29 seconds
Started Jan 25 01:09:49 PM PST 24
Finished Jan 25 01:10:03 PM PST 24
Peak memory 213808 kb
Host smart-9bf0a406-a077-45eb-bca3-0bef297ea780
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001407668 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2001407668
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3067097004
Short name T206
Test name
Test status
Simulation time 436458176 ps
CPU time 3.31 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:57 PM PST 24
Peak memory 214500 kb
Host smart-ec5fa302-7524-4ff5-9642-c8792f0c501a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067097004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3067097004
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1477545053
Short name T53
Test name
Test status
Simulation time 14381725 ps
CPU time 0.87 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:32 PM PST 24
Peak memory 205072 kb
Host smart-2c0d55da-a909-4e2c-8485-27605e620819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477545053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
1477545053
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.4058317064
Short name T73
Test name
Test status
Simulation time 12437450 ps
CPU time 0.73 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:32 PM PST 24
Peak memory 205092 kb
Host smart-599942c7-68c7-42bd-8059-90d16ca82cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058317064 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
4058317064
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.3047973115
Short name T181
Test name
Test status
Simulation time 24924948 ps
CPU time 0.67 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 205068 kb
Host smart-14f70c24-ff80-48a6-955d-a0f24d79dd65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047973115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
3047973115
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3334198937
Short name T180
Test name
Test status
Simulation time 19765832 ps
CPU time 0.71 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 205092 kb
Host smart-1434511d-59e8-4dda-93f6-73f879d78364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334198937 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3334198937
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.719642270
Short name T292
Test name
Test status
Simulation time 19949362 ps
CPU time 0.86 seconds
Started Jan 25 01:12:28 PM PST 24
Finished Jan 25 01:12:34 PM PST 24
Peak memory 205024 kb
Host smart-a8da1799-f3ed-44cb-9ce8-dfa16d71a9d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719642270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.719642270
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3178369039
Short name T240
Test name
Test status
Simulation time 10032159 ps
CPU time 0.71 seconds
Started Jan 25 01:12:27 PM PST 24
Finished Jan 25 01:12:33 PM PST 24
Peak memory 205080 kb
Host smart-309b984f-a7be-4cd4-93e0-b9de39455a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178369039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3178369039
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.4285043731
Short name T248
Test name
Test status
Simulation time 32262651 ps
CPU time 0.71 seconds
Started Jan 25 01:12:27 PM PST 24
Finished Jan 25 01:12:33 PM PST 24
Peak memory 205112 kb
Host smart-b260ec88-2a52-4015-9549-83ed1db1b3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285043731 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
4285043731
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3502518069
Short name T263
Test name
Test status
Simulation time 12510982 ps
CPU time 0.89 seconds
Started Jan 25 01:12:27 PM PST 24
Finished Jan 25 01:12:34 PM PST 24
Peak memory 205084 kb
Host smart-8f1f4ac9-9da7-467d-b2d6-3714be5a44c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502518069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3502518069
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.1113039924
Short name T207
Test name
Test status
Simulation time 48211002 ps
CPU time 0.84 seconds
Started Jan 25 01:12:28 PM PST 24
Finished Jan 25 01:12:35 PM PST 24
Peak memory 205148 kb
Host smart-2d4b824d-6bde-4de6-a350-a3407be461ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113039924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
1113039924
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2689326992
Short name T170
Test name
Test status
Simulation time 35389459 ps
CPU time 0.73 seconds
Started Jan 25 01:12:27 PM PST 24
Finished Jan 25 01:12:34 PM PST 24
Peak memory 205080 kb
Host smart-e2364b72-250f-4f9c-8008-7b6cd0a1980d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689326992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2689326992
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2809419567
Short name T171
Test name
Test status
Simulation time 314878352 ps
CPU time 5.32 seconds
Started Jan 25 01:11:04 PM PST 24
Finished Jan 25 01:11:14 PM PST 24
Peak memory 205272 kb
Host smart-0c650b26-952b-4656-9921-3d2ad2ad87fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809419567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2809419567
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.4031240912
Short name T200
Test name
Test status
Simulation time 430957180 ps
CPU time 11.16 seconds
Started Jan 25 01:09:52 PM PST 24
Finished Jan 25 01:10:10 PM PST 24
Peak memory 205240 kb
Host smart-c35cf252-228d-4ce7-8a79-090f34a2e594
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031240912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.4031240912
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.1630217389
Short name T193
Test name
Test status
Simulation time 37871294 ps
CPU time 1.04 seconds
Started Jan 25 01:09:53 PM PST 24
Finished Jan 25 01:10:00 PM PST 24
Peak memory 205384 kb
Host smart-26a76315-da16-4472-98f6-137d37003f51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630217389 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.1630217389
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.149067871
Short name T189
Test name
Test status
Simulation time 42291948 ps
CPU time 0.94 seconds
Started Jan 25 01:11:04 PM PST 24
Finished Jan 25 01:11:10 PM PST 24
Peak memory 205128 kb
Host smart-b4a332fb-9e69-4987-8687-4df86f594831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149067871 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.149067871
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.2926541287
Short name T58
Test name
Test status
Simulation time 11311753 ps
CPU time 1.01 seconds
Started Jan 25 01:09:56 PM PST 24
Finished Jan 25 01:10:01 PM PST 24
Peak memory 205292 kb
Host smart-cd3f9590-751a-447b-88e2-5e8361519837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926541287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.2
926541287
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1497856585
Short name T283
Test name
Test status
Simulation time 157851433 ps
CPU time 0.69 seconds
Started Jan 25 01:09:49 PM PST 24
Finished Jan 25 01:09:56 PM PST 24
Peak memory 205076 kb
Host smart-b35725f8-22bd-49e7-924d-b750e17146ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497856585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
497856585
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4118632301
Short name T192
Test name
Test status
Simulation time 57414862 ps
CPU time 1.92 seconds
Started Jan 25 01:11:03 PM PST 24
Finished Jan 25 01:11:10 PM PST 24
Peak memory 205208 kb
Host smart-d30c51f6-16d0-478d-a675-275fe3dc69a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118632301 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.4118632301
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.4094981790
Short name T290
Test name
Test status
Simulation time 125632702 ps
CPU time 1.89 seconds
Started Jan 25 01:09:44 PM PST 24
Finished Jan 25 01:09:52 PM PST 24
Peak memory 213764 kb
Host smart-87072d12-0b5d-4fe9-b3ad-c5400ca7c707
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094981790 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.4094981790
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.719480781
Short name T69
Test name
Test status
Simulation time 126697385 ps
CPU time 3.3 seconds
Started Jan 25 01:10:23 PM PST 24
Finished Jan 25 01:10:34 PM PST 24
Peak memory 213952 kb
Host smart-7ee377e7-1fe7-42ab-854c-618e3207dc95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719480781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.719480781
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3073886112
Short name T49
Test name
Test status
Simulation time 99438589 ps
CPU time 2.14 seconds
Started Jan 25 01:09:53 PM PST 24
Finished Jan 25 01:10:01 PM PST 24
Peak memory 213584 kb
Host smart-eca04530-c1ce-41b3-b873-622b014f8f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073886112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
073886112
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.1432287493
Short name T84
Test name
Test status
Simulation time 776769943 ps
CPU time 4.13 seconds
Started Jan 25 01:09:43 PM PST 24
Finished Jan 25 01:09:52 PM PST 24
Peak memory 214512 kb
Host smart-d79f03d8-ec34-42cd-b91b-b0ec195cb923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432287493 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.1432287493
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2856696330
Short name T269
Test name
Test status
Simulation time 38085593 ps
CPU time 0.68 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:30 PM PST 24
Peak memory 205104 kb
Host smart-3d5e2304-f0ad-46f0-a197-ca33cf102e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856696330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
2856696330
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.4019492564
Short name T275
Test name
Test status
Simulation time 12770446 ps
CPU time 0.71 seconds
Started Jan 25 01:12:29 PM PST 24
Finished Jan 25 01:12:35 PM PST 24
Peak memory 205104 kb
Host smart-3df2bf3c-0080-4c61-af64-005d16f0805d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019492564 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
4019492564
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.4020854092
Short name T223
Test name
Test status
Simulation time 12455273 ps
CPU time 0.85 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205100 kb
Host smart-f3a53c2b-dfbf-4b18-a959-bb3e359214bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020854092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
4020854092
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.216337213
Short name T262
Test name
Test status
Simulation time 49394118 ps
CPU time 0.69 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205092 kb
Host smart-00b9cc6c-d1f9-474e-aaaa-769cc3a8cdf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216337213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.216337213
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.376325771
Short name T177
Test name
Test status
Simulation time 84106161 ps
CPU time 0.71 seconds
Started Jan 25 01:12:21 PM PST 24
Finished Jan 25 01:12:23 PM PST 24
Peak memory 205096 kb
Host smart-63378c40-c555-4331-881f-90049dee3f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376325771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.376325771
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1440060020
Short name T194
Test name
Test status
Simulation time 11747370 ps
CPU time 0.84 seconds
Started Jan 25 01:12:29 PM PST 24
Finished Jan 25 01:12:35 PM PST 24
Peak memory 205148 kb
Host smart-527a05a2-60ee-4366-be57-f4e1f8a8cfeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440060020 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1440060020
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.3010051562
Short name T203
Test name
Test status
Simulation time 57304169 ps
CPU time 0.72 seconds
Started Jan 25 01:12:26 PM PST 24
Finished Jan 25 01:12:32 PM PST 24
Peak memory 205100 kb
Host smart-50ee570a-067a-40ac-8cf9-7602a9a9bdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010051562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
3010051562
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3056263761
Short name T217
Test name
Test status
Simulation time 12876218 ps
CPU time 0.7 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205128 kb
Host smart-81c1bcbe-9edb-453e-be22-ab406bfa6b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056263761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3056263761
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3361514960
Short name T268
Test name
Test status
Simulation time 17336808 ps
CPU time 0.72 seconds
Started Jan 25 01:12:25 PM PST 24
Finished Jan 25 01:12:29 PM PST 24
Peak memory 205080 kb
Host smart-f580864d-b50e-47d6-b965-aaf1c7607e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361514960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
3361514960
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2941016220
Short name T183
Test name
Test status
Simulation time 20083373 ps
CPU time 0.8 seconds
Started Jan 25 01:12:22 PM PST 24
Finished Jan 25 01:12:25 PM PST 24
Peak memory 205056 kb
Host smart-721c177c-990d-4363-83a0-985df30c3f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941016220 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
2941016220
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2531102360
Short name T286
Test name
Test status
Simulation time 55000215 ps
CPU time 1.57 seconds
Started Jan 25 01:10:57 PM PST 24
Finished Jan 25 01:11:05 PM PST 24
Peak memory 217832 kb
Host smart-736f73ad-6531-411e-9910-5627f29de7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531102360 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2531102360
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.3979104437
Short name T190
Test name
Test status
Simulation time 35077877 ps
CPU time 0.9 seconds
Started Jan 25 01:10:58 PM PST 24
Finished Jan 25 01:11:05 PM PST 24
Peak memory 205036 kb
Host smart-51b65c84-77cc-458d-987f-52e83cba67b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979104437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.3
979104437
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2268741717
Short name T270
Test name
Test status
Simulation time 37041085 ps
CPU time 0.84 seconds
Started Jan 25 01:11:00 PM PST 24
Finished Jan 25 01:11:06 PM PST 24
Peak memory 205004 kb
Host smart-7d1ef47b-ff87-4603-9f00-fbcdcbe2cb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268741717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
268741717
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3249622015
Short name T285
Test name
Test status
Simulation time 86741520 ps
CPU time 1.96 seconds
Started Jan 25 01:10:57 PM PST 24
Finished Jan 25 01:11:05 PM PST 24
Peak memory 205224 kb
Host smart-6a02d644-86c3-40d0-84a9-f624490ecca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249622015 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3249622015
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.3367617064
Short name T259
Test name
Test status
Simulation time 380207091 ps
CPU time 2.59 seconds
Started Jan 25 01:10:56 PM PST 24
Finished Jan 25 01:11:06 PM PST 24
Peak memory 213576 kb
Host smart-7dcc6781-e2d9-4cea-94d2-440625721e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367617064 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.3
367617064
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.370728982
Short name T274
Test name
Test status
Simulation time 25411733 ps
CPU time 1.45 seconds
Started Jan 25 01:10:59 PM PST 24
Finished Jan 25 01:11:06 PM PST 24
Peak memory 213684 kb
Host smart-6a76c29e-d654-4ec0-a592-11e3940ddea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370728982 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.370728982
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.3726290650
Short name T251
Test name
Test status
Simulation time 30684122 ps
CPU time 0.8 seconds
Started Jan 25 01:11:02 PM PST 24
Finished Jan 25 01:11:09 PM PST 24
Peak memory 205056 kb
Host smart-031a29f9-3eb3-4a1e-8f97-1d48eb3d6a0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726290650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.3
726290650
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.3626684224
Short name T51
Test name
Test status
Simulation time 47901135 ps
CPU time 0.84 seconds
Started Jan 25 01:10:58 PM PST 24
Finished Jan 25 01:11:04 PM PST 24
Peak memory 205036 kb
Host smart-20b79ced-2406-49a5-8e33-9a882bd144f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626684224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.3
626684224
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2911722882
Short name T242
Test name
Test status
Simulation time 139379695 ps
CPU time 2.04 seconds
Started Jan 25 01:10:57 PM PST 24
Finished Jan 25 01:11:05 PM PST 24
Peak memory 205288 kb
Host smart-6c1ec451-d446-4e26-8b91-83b93efbac96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911722882 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.2911722882
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1392630884
Short name T65
Test name
Test status
Simulation time 300219002 ps
CPU time 2.68 seconds
Started Jan 25 01:10:59 PM PST 24
Finished Jan 25 01:11:07 PM PST 24
Peak memory 213892 kb
Host smart-fa45286b-3d9b-45a0-af23-1c10aca79058
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392630884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1392630884
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2733383985
Short name T267
Test name
Test status
Simulation time 778770246 ps
CPU time 7.65 seconds
Started Jan 25 01:11:03 PM PST 24
Finished Jan 25 01:11:16 PM PST 24
Peak memory 213956 kb
Host smart-2e2dc4fe-8d39-4ea0-bf52-2116044bd300
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733383985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2733383985
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.1204570127
Short name T277
Test name
Test status
Simulation time 140229613 ps
CPU time 3.2 seconds
Started Jan 25 01:10:58 PM PST 24
Finished Jan 25 01:11:07 PM PST 24
Peak memory 213596 kb
Host smart-5fc8deb0-49e6-43aa-9f26-d3579fb6fcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204570127 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.1
204570127
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2382809899
Short name T24
Test name
Test status
Simulation time 90548171 ps
CPU time 1.7 seconds
Started Jan 25 01:11:21 PM PST 24
Finished Jan 25 01:11:24 PM PST 24
Peak memory 213744 kb
Host smart-860d9422-ff5a-4d23-8e6a-02e3cb134792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382809899 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.2382809899
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2467626475
Short name T252
Test name
Test status
Simulation time 21898762 ps
CPU time 1.03 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:28 PM PST 24
Peak memory 205088 kb
Host smart-1534e8af-7847-4f24-b399-e4791454e38e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467626475 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
467626475
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1877989236
Short name T179
Test name
Test status
Simulation time 27919329 ps
CPU time 0.81 seconds
Started Jan 25 01:11:23 PM PST 24
Finished Jan 25 01:11:26 PM PST 24
Peak memory 205052 kb
Host smart-54dde7a1-69e6-4002-8631-b40e80b2e5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877989236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.1
877989236
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3544247932
Short name T205
Test name
Test status
Simulation time 181553073 ps
CPU time 1.95 seconds
Started Jan 25 01:11:25 PM PST 24
Finished Jan 25 01:11:29 PM PST 24
Peak memory 205280 kb
Host smart-3faa131c-74f0-44f5-9ee9-373a34b38daa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544247932 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.3544247932
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2004322839
Short name T244
Test name
Test status
Simulation time 220968641 ps
CPU time 2.54 seconds
Started Jan 25 01:11:23 PM PST 24
Finished Jan 25 01:11:28 PM PST 24
Peak memory 213812 kb
Host smart-73edebee-93f3-492f-9990-f91231806229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004322839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2004322839
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.832038084
Short name T187
Test name
Test status
Simulation time 145085544 ps
CPU time 5.99 seconds
Started Jan 25 01:11:23 PM PST 24
Finished Jan 25 01:11:31 PM PST 24
Peak memory 213936 kb
Host smart-11d208d6-d870-485b-b2b0-fd93cb299621
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832038084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.832038084
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.601495655
Short name T188
Test name
Test status
Simulation time 208607461 ps
CPU time 2.04 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:29 PM PST 24
Peak memory 215868 kb
Host smart-8ff08f79-5615-4eb7-8a79-2b13ecc1ac96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601495655 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.601495655
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2697171520
Short name T291
Test name
Test status
Simulation time 59737846 ps
CPU time 1.26 seconds
Started Jan 25 01:11:22 PM PST 24
Finished Jan 25 01:11:25 PM PST 24
Peak memory 213612 kb
Host smart-f45ecfaa-0176-4245-ac43-33dc3d401d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697171520 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2697171520
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.770302982
Short name T68
Test name
Test status
Simulation time 111384361 ps
CPU time 0.85 seconds
Started Jan 25 01:11:19 PM PST 24
Finished Jan 25 01:11:22 PM PST 24
Peak memory 205028 kb
Host smart-a0cb30ec-cc00-4aeb-a163-76df8fce67ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770302982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.770302982
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.3551226132
Short name T255
Test name
Test status
Simulation time 45336532 ps
CPU time 0.74 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:37 PM PST 24
Peak memory 205072 kb
Host smart-e52b686c-9f1c-4520-9194-9b3c9c072982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551226132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.3
551226132
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.2534283219
Short name T63
Test name
Test status
Simulation time 28522912 ps
CPU time 1.6 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:33 PM PST 24
Peak memory 205200 kb
Host smart-c4289b63-5ce0-4678-a97f-7965b56d221c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534283219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.2534283219
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.3633607136
Short name T230
Test name
Test status
Simulation time 78927380 ps
CPU time 1.33 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:38 PM PST 24
Peak memory 213580 kb
Host smart-f5c89ec8-f352-49b2-9a6d-4e6830d24536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633607136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.3633607136
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.1763940509
Short name T173
Test name
Test status
Simulation time 205601270 ps
CPU time 2.55 seconds
Started Jan 25 01:11:20 PM PST 24
Finished Jan 25 01:11:24 PM PST 24
Peak memory 213868 kb
Host smart-23b3221f-68e1-4a9a-8469-07c8ec76f9d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763940509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.1763940509
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3650432086
Short name T176
Test name
Test status
Simulation time 462574233 ps
CPU time 3.11 seconds
Started Jan 25 01:11:20 PM PST 24
Finished Jan 25 01:11:24 PM PST 24
Peak memory 213468 kb
Host smart-869a1aab-83e5-452a-8c0b-f28bfecd7062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650432086 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
650432086
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3626316670
Short name T54
Test name
Test status
Simulation time 339737316 ps
CPU time 2.54 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:39 PM PST 24
Peak memory 214304 kb
Host smart-a9ba0796-41d3-4915-b1ce-aa355755367c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626316670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3626316670
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3629154836
Short name T276
Test name
Test status
Simulation time 105820496 ps
CPU time 1.23 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:32 PM PST 24
Peak memory 205344 kb
Host smart-de9885e9-663c-403d-b791-338e087bf5da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629154836 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.3629154836
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2569992330
Short name T293
Test name
Test status
Simulation time 24530228 ps
CPU time 1.13 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:32 PM PST 24
Peak memory 204824 kb
Host smart-483deaac-aee4-41b5-b5d9-c5a896778f32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569992330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.2
569992330
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1694856251
Short name T175
Test name
Test status
Simulation time 82593375 ps
CPU time 0.79 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:27 PM PST 24
Peak memory 205080 kb
Host smart-00ab5d1c-53bf-4ec5-b70f-648bc12eeed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694856251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.1
694856251
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.3119537294
Short name T273
Test name
Test status
Simulation time 105965473 ps
CPU time 1.75 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:29 PM PST 24
Peak memory 205316 kb
Host smart-46181a6d-44e8-46dd-b211-824e1da8ab71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119537294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.3119537294
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.2768398582
Short name T195
Test name
Test status
Simulation time 274172862 ps
CPU time 2.73 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:39 PM PST 24
Peak memory 213848 kb
Host smart-386cb8f4-8984-4ad7-ac7b-c1fdcc7d52a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768398582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.2768398582
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3634021393
Short name T67
Test name
Test status
Simulation time 376669623 ps
CPU time 2.81 seconds
Started Jan 25 01:11:35 PM PST 24
Finished Jan 25 01:11:39 PM PST 24
Peak memory 213920 kb
Host smart-fea955c8-93be-4b15-be88-f289d785a771
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634021393 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3634021393
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.4048615441
Short name T77
Test name
Test status
Simulation time 1052488588 ps
CPU time 2.24 seconds
Started Jan 25 01:11:24 PM PST 24
Finished Jan 25 01:11:29 PM PST 24
Peak memory 221708 kb
Host smart-03db521e-2c42-484b-9bd6-97e1ed732ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048615441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.4
048615441
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.851681672
Short name T82
Test name
Test status
Simulation time 228396264 ps
CPU time 7.55 seconds
Started Jan 25 01:11:29 PM PST 24
Finished Jan 25 01:11:39 PM PST 24
Peak memory 213504 kb
Host smart-f92f60c2-9180-4342-902f-f6c58b5713c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851681672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_
tl_intg_err.851681672
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.3827357587
Short name T146
Test name
Test status
Simulation time 25671873 ps
CPU time 0.91 seconds
Started Jan 25 01:04:25 PM PST 24
Finished Jan 25 01:04:27 PM PST 24
Peak memory 204364 kb
Host smart-a8e654ac-20f6-4a40-9f29-576bef4f5a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827357587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.3
827357587
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.387052856
Short name T9
Test name
Test status
Simulation time 455415334 ps
CPU time 9.55 seconds
Started Jan 25 01:04:30 PM PST 24
Finished Jan 25 01:04:46 PM PST 24
Peak memory 232772 kb
Host smart-95ffaa3e-a74c-4a6f-889c-010fb0b06b75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387052856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.387052856
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.4177393129
Short name T41
Test name
Test status
Simulation time 47518839 ps
CPU time 0.77 seconds
Started Jan 25 01:05:09 PM PST 24
Finished Jan 25 01:05:22 PM PST 24
Peak memory 204336 kb
Host smart-2a07086e-7ef3-4d03-bd8c-eddca8b2d59a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177393129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
4177393129
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.559111483
Short name T18
Test name
Test status
Simulation time 28390672 ps
CPU time 0.77 seconds
Started Jan 25 01:05:05 PM PST 24
Finished Jan 25 01:05:12 PM PST 24
Peak memory 204288 kb
Host smart-7d25f664-8d51-4f9c-b766-e108774f6676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559111483 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.559111483
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1420695620
Short name T160
Test name
Test status
Simulation time 17975317 ps
CPU time 0.72 seconds
Started Jan 25 02:59:43 PM PST 24
Finished Jan 25 02:59:52 PM PST 24
Peak memory 204332 kb
Host smart-55486194-d2d1-4e86-9a29-4e17760afaa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420695620 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1420695620
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3756199361
Short name T117
Test name
Test status
Simulation time 102113339 ps
CPU time 3.58 seconds
Started Jan 25 01:05:10 PM PST 24
Finished Jan 25 01:05:24 PM PST 24
Peak memory 207084 kb
Host smart-80109a0d-948b-43ee-934d-b750b913e4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756199361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3756199361
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.3220784919
Short name T137
Test name
Test status
Simulation time 14268222 ps
CPU time 0.91 seconds
Started Jan 25 02:23:56 PM PST 24
Finished Jan 25 02:24:25 PM PST 24
Peak memory 204592 kb
Host smart-4d8b7de3-314b-4bfc-bde1-3da4aefd7cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220784919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
3220784919
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3871014036
Short name T152
Test name
Test status
Simulation time 12398696 ps
CPU time 0.82 seconds
Started Jan 25 01:05:20 PM PST 24
Finished Jan 25 01:05:30 PM PST 24
Peak memory 204312 kb
Host smart-46ef63c8-3a11-4a39-b746-7f8657e9fd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871014036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3871014036
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.373056264
Short name T11
Test name
Test status
Simulation time 434423996 ps
CPU time 2.23 seconds
Started Jan 25 02:11:46 PM PST 24
Finished Jan 25 02:12:09 PM PST 24
Peak memory 205196 kb
Host smart-bc1a0d8d-821a-4389-aeb4-d240039c15d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373056264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.373056264
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.3584410065
Short name T130
Test name
Test status
Simulation time 51998588 ps
CPU time 0.9 seconds
Started Jan 25 01:05:21 PM PST 24
Finished Jan 25 01:05:31 PM PST 24
Peak memory 204328 kb
Host smart-698a2099-680a-44de-bddc-bda08f7cbae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584410065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
3584410065
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.1880828142
Short name T116
Test name
Test status
Simulation time 1151411697 ps
CPU time 5.35 seconds
Started Jan 25 01:05:23 PM PST 24
Finished Jan 25 01:05:36 PM PST 24
Peak memory 206932 kb
Host smart-171c07ea-d8a6-4fd9-a7fe-52dbe7f19cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880828142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.1880828142
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.146007623
Short name T165
Test name
Test status
Simulation time 10800715 ps
CPU time 0.69 seconds
Started Jan 25 01:05:22 PM PST 24
Finished Jan 25 01:05:31 PM PST 24
Peak memory 204364 kb
Host smart-1cabccdc-a1f1-43b7-a10e-c81afb12f005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146007623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.146007623
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2976928057
Short name T139
Test name
Test status
Simulation time 43453675 ps
CPU time 0.81 seconds
Started Jan 25 01:32:49 PM PST 24
Finished Jan 25 01:32:52 PM PST 24
Peak memory 204336 kb
Host smart-0615ee43-312a-42ed-8912-92203f136f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976928057 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2976928057
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.108094147
Short name T120
Test name
Test status
Simulation time 192845956 ps
CPU time 2.34 seconds
Started Jan 25 01:05:25 PM PST 24
Finished Jan 25 01:05:34 PM PST 24
Peak memory 207120 kb
Host smart-a2c82244-97ce-45bd-9852-f006ddaf4b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108094147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.108094147
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.685709027
Short name T161
Test name
Test status
Simulation time 105810900 ps
CPU time 0.97 seconds
Started Jan 25 01:05:25 PM PST 24
Finished Jan 25 01:05:33 PM PST 24
Peak memory 204548 kb
Host smart-9b663763-70f6-4d6d-a7f1-add78ccf1ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685709027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.685709027
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.3913169379
Short name T20
Test name
Test status
Simulation time 30385729 ps
CPU time 0.75 seconds
Started Jan 25 01:05:23 PM PST 24
Finished Jan 25 01:05:32 PM PST 24
Peak memory 204356 kb
Host smart-a360648c-e518-4ebd-b5c1-e0f728da7e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913169379 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
3913169379
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2012517086
Short name T30
Test name
Test status
Simulation time 216280366 ps
CPU time 4.59 seconds
Started Jan 25 01:05:27 PM PST 24
Finished Jan 25 01:05:40 PM PST 24
Peak memory 207160 kb
Host smart-9ca5f40d-efcc-448b-8bdf-47fd22116e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012517086 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2012517086
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.2812868241
Short name T157
Test name
Test status
Simulation time 22950346 ps
CPU time 0.76 seconds
Started Jan 25 01:04:25 PM PST 24
Finished Jan 25 01:04:28 PM PST 24
Peak memory 204312 kb
Host smart-16eb2273-7a37-4744-b23d-899823707886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812868241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.2
812868241
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.364577558
Short name T107
Test name
Test status
Simulation time 747937859 ps
CPU time 10.7 seconds
Started Jan 25 01:04:28 PM PST 24
Finished Jan 25 01:04:44 PM PST 24
Peak memory 207048 kb
Host smart-642927ef-dfcb-46ad-a8a1-f251ff02a49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364577558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.364577558
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3788008157
Short name T158
Test name
Test status
Simulation time 16058241 ps
CPU time 0.82 seconds
Started Jan 25 01:05:43 PM PST 24
Finished Jan 25 01:05:55 PM PST 24
Peak memory 204596 kb
Host smart-696fe80b-0c2d-44cb-b19b-cace797cf043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788008157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3788008157
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1903364163
Short name T143
Test name
Test status
Simulation time 39946289 ps
CPU time 0.84 seconds
Started Jan 25 01:05:44 PM PST 24
Finished Jan 25 01:05:56 PM PST 24
Peak memory 204384 kb
Host smart-5b062d36-a5b0-4166-a9d8-a64918f4afec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903364163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1903364163
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.2243962326
Short name T151
Test name
Test status
Simulation time 105957676 ps
CPU time 2.62 seconds
Started Jan 25 01:05:47 PM PST 24
Finished Jan 25 01:06:00 PM PST 24
Peak memory 206560 kb
Host smart-8dd243c4-b171-4930-aa52-d9b531323320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243962326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.2243962326
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2598613433
Short name T140
Test name
Test status
Simulation time 15663001 ps
CPU time 0.92 seconds
Started Jan 25 01:05:50 PM PST 24
Finished Jan 25 01:06:01 PM PST 24
Peak memory 204516 kb
Host smart-d19721fa-1130-47e8-9e24-1058a833d206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598613433 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2598613433
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3852268073
Short name T42
Test name
Test status
Simulation time 18470961 ps
CPU time 0.77 seconds
Started Jan 25 01:05:47 PM PST 24
Finished Jan 25 01:05:58 PM PST 24
Peak memory 204336 kb
Host smart-598f62d5-0138-4a82-b248-0abb7ad2a3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852268073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3852268073
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.1634893683
Short name T35
Test name
Test status
Simulation time 79889200 ps
CPU time 1.67 seconds
Started Jan 25 01:05:52 PM PST 24
Finished Jan 25 01:06:05 PM PST 24
Peak memory 205728 kb
Host smart-6bd747e8-6605-427e-9a4f-ac65b7f5d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634893683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.1634893683
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1217348824
Short name T150
Test name
Test status
Simulation time 37267544 ps
CPU time 0.7 seconds
Started Jan 25 01:05:47 PM PST 24
Finished Jan 25 01:05:59 PM PST 24
Peak memory 204412 kb
Host smart-2c840d13-b531-4caa-b64e-42349dcdd75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217348824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1217348824
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.3229788927
Short name T164
Test name
Test status
Simulation time 27932704 ps
CPU time 0.95 seconds
Started Jan 25 01:05:45 PM PST 24
Finished Jan 25 01:05:57 PM PST 24
Peak memory 204432 kb
Host smart-596374cb-3d7b-4783-9857-407b410791af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229788927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
3229788927
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1496033158
Short name T13
Test name
Test status
Simulation time 74313888 ps
CPU time 2.13 seconds
Started Jan 25 01:05:46 PM PST 24
Finished Jan 25 01:05:59 PM PST 24
Peak memory 205312 kb
Host smart-d1298913-5595-40c7-8438-888f39507477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496033158 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1496033158
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.3655597477
Short name T21
Test name
Test status
Simulation time 84019734 ps
CPU time 1 seconds
Started Jan 25 01:05:54 PM PST 24
Finished Jan 25 01:06:07 PM PST 24
Peak memory 204544 kb
Host smart-6dffbe8a-ccca-4a72-85e4-c5a0376c9c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655597477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
3655597477
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1288093913
Short name T167
Test name
Test status
Simulation time 37776306 ps
CPU time 0.78 seconds
Started Jan 25 01:05:54 PM PST 24
Finished Jan 25 01:06:07 PM PST 24
Peak memory 204356 kb
Host smart-31793acc-3c5c-452c-9894-b4dbd137e507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288093913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1288093913
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2063527675
Short name T156
Test name
Test status
Simulation time 15152644 ps
CPU time 0.72 seconds
Started Jan 25 02:04:10 PM PST 24
Finished Jan 25 02:04:35 PM PST 24
Peak memory 204372 kb
Host smart-e8275879-d081-4256-87ad-931b2432cc6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063527675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2063527675
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.231684129
Short name T28
Test name
Test status
Simulation time 161534830 ps
CPU time 2.32 seconds
Started Jan 25 01:05:54 PM PST 24
Finished Jan 25 01:06:09 PM PST 24
Peak memory 205596 kb
Host smart-26d5ad74-fdfd-45e1-bbb9-17cc64a7857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231684129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.231684129
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.1920950028
Short name T153
Test name
Test status
Simulation time 95914721 ps
CPU time 0.96 seconds
Started Jan 25 01:06:13 PM PST 24
Finished Jan 25 01:06:21 PM PST 24
Peak memory 204496 kb
Host smart-5073eee3-8979-453e-ae27-e7d7f27f1c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920950028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
1920950028
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.628053844
Short name T138
Test name
Test status
Simulation time 40434985 ps
CPU time 0.85 seconds
Started Jan 25 01:04:36 PM PST 24
Finished Jan 25 01:04:43 PM PST 24
Peak memory 204360 kb
Host smart-fcb0bd32-8017-45a3-8973-d78a291a1e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628053844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.628053844
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.85961737
Short name T34
Test name
Test status
Simulation time 563835328 ps
CPU time 14.99 seconds
Started Jan 25 01:04:22 PM PST 24
Finished Jan 25 01:04:38 PM PST 24
Peak memory 227424 kb
Host smart-1af4dad7-1700-44cd-a096-60db9962950f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85961737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.85961737
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2550399294
Short name T124
Test name
Test status
Simulation time 118348948 ps
CPU time 2.62 seconds
Started Jan 25 01:04:23 PM PST 24
Finished Jan 25 01:04:27 PM PST 24
Peak memory 206852 kb
Host smart-d1e70855-d71a-4b5b-b4e4-1766b1f161ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550399294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2550399294
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3424916307
Short name T132
Test name
Test status
Simulation time 15607289 ps
CPU time 0.81 seconds
Started Jan 25 01:06:18 PM PST 24
Finished Jan 25 01:06:26 PM PST 24
Peak memory 204264 kb
Host smart-e23fc159-0754-4db1-83a5-e1b3f333ecec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424916307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3424916307
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.944158454
Short name T127
Test name
Test status
Simulation time 64729511 ps
CPU time 0.75 seconds
Started Jan 25 01:06:09 PM PST 24
Finished Jan 25 01:06:18 PM PST 24
Peak memory 204392 kb
Host smart-64560430-0d6c-44c0-be19-72341356c83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944158454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.944158454
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.4116172539
Short name T6
Test name
Test status
Simulation time 562051847 ps
CPU time 12.11 seconds
Started Jan 25 01:06:10 PM PST 24
Finished Jan 25 01:06:30 PM PST 24
Peak memory 207020 kb
Host smart-fae040ad-4314-40d8-ac02-a9495bff42f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116172539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.4116172539
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.1364984451
Short name T17
Test name
Test status
Simulation time 19328765 ps
CPU time 0.76 seconds
Started Jan 25 01:06:11 PM PST 24
Finished Jan 25 01:06:19 PM PST 24
Peak memory 204616 kb
Host smart-2b01d1b5-25bd-483b-8fa6-5e829e81cc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364984451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
1364984451
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.1504138711
Short name T144
Test name
Test status
Simulation time 48096061 ps
CPU time 0.79 seconds
Started Jan 25 01:06:09 PM PST 24
Finished Jan 25 01:06:18 PM PST 24
Peak memory 204344 kb
Host smart-2f53ae79-1ed7-4b44-954c-cca2d071f1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504138711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
1504138711
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.155577263
Short name T121
Test name
Test status
Simulation time 35592274 ps
CPU time 2.3 seconds
Started Jan 25 01:06:18 PM PST 24
Finished Jan 25 01:06:27 PM PST 24
Peak memory 205320 kb
Host smart-23cce7e9-d05a-4e69-883d-b2021c6c656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155577263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.155577263
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.4287569701
Short name T37
Test name
Test status
Simulation time 12245844 ps
CPU time 0.72 seconds
Started Jan 25 01:06:17 PM PST 24
Finished Jan 25 01:06:25 PM PST 24
Peak memory 204352 kb
Host smart-8ba07632-0a74-4f7a-8a51-ac73ef89cb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287569701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
4287569701
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.2107721644
Short name T19
Test name
Test status
Simulation time 86838841 ps
CPU time 0.81 seconds
Started Jan 25 01:06:47 PM PST 24
Finished Jan 25 01:06:51 PM PST 24
Peak memory 204376 kb
Host smart-c17e26ac-c5ad-46bd-8866-00afa0483d9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107721644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
2107721644
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.666725644
Short name T136
Test name
Test status
Simulation time 17813180 ps
CPU time 0.74 seconds
Started Jan 25 01:06:43 PM PST 24
Finished Jan 25 01:06:47 PM PST 24
Peak memory 204364 kb
Host smart-bfeb21e4-dba1-4df0-a814-ce332bc5b9b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666725644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.666725644
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.1221383309
Short name T145
Test name
Test status
Simulation time 32550677 ps
CPU time 0.85 seconds
Started Jan 25 01:06:43 PM PST 24
Finished Jan 25 01:06:48 PM PST 24
Peak memory 204316 kb
Host smart-4e6818f6-1719-4df2-97b7-84396d985fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221383309 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
1221383309
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.1070769061
Short name T31
Test name
Test status
Simulation time 95029225 ps
CPU time 2.88 seconds
Started Jan 25 01:06:47 PM PST 24
Finished Jan 25 01:06:54 PM PST 24
Peak memory 205444 kb
Host smart-6f87f94a-2eae-4682-a911-98f842e925b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070769061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1070769061
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1840603631
Short name T128
Test name
Test status
Simulation time 32747124 ps
CPU time 0.75 seconds
Started Jan 25 01:06:40 PM PST 24
Finished Jan 25 01:06:43 PM PST 24
Peak memory 204412 kb
Host smart-fcf23190-99ff-4bfe-a261-5a4299813d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840603631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1840603631
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.3774302290
Short name T159
Test name
Test status
Simulation time 1120539956 ps
CPU time 10.13 seconds
Started Jan 25 01:06:42 PM PST 24
Finished Jan 25 01:06:55 PM PST 24
Peak memory 206836 kb
Host smart-aed2b831-672b-4d37-8b04-a67de6897a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774302290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.3774302290
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.2365815828
Short name T149
Test name
Test status
Simulation time 43214557 ps
CPU time 0.85 seconds
Started Jan 25 01:06:42 PM PST 24
Finished Jan 25 01:06:45 PM PST 24
Peak memory 204316 kb
Host smart-6d39a452-1b91-41c2-85aa-90db781e0bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365815828 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
2365815828
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.3170215959
Short name T32
Test name
Test status
Simulation time 68612998 ps
CPU time 2.7 seconds
Started Jan 25 01:06:43 PM PST 24
Finished Jan 25 01:06:50 PM PST 24
Peak memory 206384 kb
Host smart-0b460294-6dca-4e94-9660-b62b009df38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170215959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.3170215959
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2194810140
Short name T148
Test name
Test status
Simulation time 16375059 ps
CPU time 0.92 seconds
Started Jan 25 01:05:07 PM PST 24
Finished Jan 25 01:05:16 PM PST 24
Peak memory 204544 kb
Host smart-49edc55f-764b-4034-b20d-d015651b3cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194810140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
194810140
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.733426749
Short name T14
Test name
Test status
Simulation time 258516363 ps
CPU time 2.78 seconds
Started Jan 25 01:04:36 PM PST 24
Finished Jan 25 01:04:45 PM PST 24
Peak memory 207248 kb
Host smart-a87e4cfa-76fe-4446-b835-1f92ea3c78ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733426749 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.733426749
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.227661872
Short name T1
Test name
Test status
Simulation time 26121650 ps
CPU time 0.73 seconds
Started Jan 25 01:06:45 PM PST 24
Finished Jan 25 01:06:49 PM PST 24
Peak memory 204252 kb
Host smart-cf0c14a5-0139-40b7-b92a-0cd088dffe46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227661872 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.227661872
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3581102275
Short name T2
Test name
Test status
Simulation time 12013635 ps
CPU time 0.89 seconds
Started Jan 25 01:06:49 PM PST 24
Finished Jan 25 01:06:53 PM PST 24
Peak memory 204408 kb
Host smart-947e6860-7c5c-40f4-9bee-fb359dd40b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581102275 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3581102275
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.1611934725
Short name T154
Test name
Test status
Simulation time 13593201 ps
CPU time 0.7 seconds
Started Jan 25 01:06:44 PM PST 24
Finished Jan 25 01:06:49 PM PST 24
Peak memory 204312 kb
Host smart-8cccb65e-aa62-4601-9988-eef22cd1b48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611934725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
1611934725
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1830510339
Short name T115
Test name
Test status
Simulation time 25182324 ps
CPU time 1.74 seconds
Started Jan 25 01:06:45 PM PST 24
Finished Jan 25 01:06:50 PM PST 24
Peak memory 205500 kb
Host smart-35c25ce0-de62-45f0-90b1-76acb4355346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830510339 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1830510339
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2004747050
Short name T3
Test name
Test status
Simulation time 9509362 ps
CPU time 0.72 seconds
Started Jan 25 01:06:49 PM PST 24
Finished Jan 25 01:06:52 PM PST 24
Peak memory 204408 kb
Host smart-987f0608-2bd5-41f7-96f9-33e456825cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004747050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2004747050
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.4008499773
Short name T162
Test name
Test status
Simulation time 101820620 ps
CPU time 2.3 seconds
Started Jan 25 01:06:43 PM PST 24
Finished Jan 25 01:06:48 PM PST 24
Peak memory 206344 kb
Host smart-3ab662fc-f689-430f-ba79-4b28d4ed421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008499773 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.4008499773
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.1690798170
Short name T133
Test name
Test status
Simulation time 24767302 ps
CPU time 0.85 seconds
Started Jan 25 01:06:44 PM PST 24
Finished Jan 25 01:06:48 PM PST 24
Peak memory 204420 kb
Host smart-5e4c1aff-2392-492a-b734-b001acb71a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690798170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
1690798170
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.389788763
Short name T147
Test name
Test status
Simulation time 164109518 ps
CPU time 0.77 seconds
Started Jan 25 01:07:26 PM PST 24
Finished Jan 25 01:07:28 PM PST 24
Peak memory 204392 kb
Host smart-c73b00a8-d467-45ec-99ce-b955c2f083c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389788763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.389788763
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1477012630
Short name T118
Test name
Test status
Simulation time 3087941352 ps
CPU time 39.28 seconds
Started Jan 25 01:06:47 PM PST 24
Finished Jan 25 01:07:30 PM PST 24
Peak memory 206808 kb
Host smart-fba1f2fd-b281-46d1-bd51-13422721f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477012630 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1477012630
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3807387213
Short name T135
Test name
Test status
Simulation time 20901723 ps
CPU time 0.83 seconds
Started Jan 25 01:07:26 PM PST 24
Finished Jan 25 01:07:28 PM PST 24
Peak memory 204392 kb
Host smart-e84c3bc2-1ef7-4f97-9617-81552791819b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807387213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3807387213
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.4098004906
Short name T113
Test name
Test status
Simulation time 636407261 ps
CPU time 6.54 seconds
Started Jan 25 01:07:23 PM PST 24
Finished Jan 25 01:07:30 PM PST 24
Peak memory 206600 kb
Host smart-806cd653-ee67-4e20-ad6b-5821f6431cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098004906 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.4098004906
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.2864372980
Short name T39
Test name
Test status
Simulation time 17587924 ps
CPU time 0.67 seconds
Started Jan 25 01:07:25 PM PST 24
Finished Jan 25 01:07:27 PM PST 24
Peak memory 204392 kb
Host smart-197abcc7-ad33-499b-a8bc-b79f0a0a5ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864372980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
2864372980
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3219421734
Short name T155
Test name
Test status
Simulation time 1120188935 ps
CPU time 6.12 seconds
Started Jan 25 01:07:22 PM PST 24
Finished Jan 25 01:07:29 PM PST 24
Peak memory 207032 kb
Host smart-a169c4d3-82d7-44dc-bdef-2c3c83f2ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219421734 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3219421734
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.4238832250
Short name T166
Test name
Test status
Simulation time 43853098 ps
CPU time 0.83 seconds
Started Jan 25 01:07:32 PM PST 24
Finished Jan 25 01:07:35 PM PST 24
Peak memory 204288 kb
Host smart-43f8036f-1aa1-49a0-bfb5-6a69194ad81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238832250 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
4238832250
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.4167333529
Short name T129
Test name
Test status
Simulation time 23824400 ps
CPU time 0.88 seconds
Started Jan 25 01:07:33 PM PST 24
Finished Jan 25 01:07:35 PM PST 24
Peak memory 204304 kb
Host smart-4fc2a881-1a94-493c-992a-3f1928bbdd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167333529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
4167333529
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.1837701247
Short name T123
Test name
Test status
Simulation time 198858792 ps
CPU time 2.42 seconds
Started Jan 25 01:07:32 PM PST 24
Finished Jan 25 01:07:36 PM PST 24
Peak memory 207116 kb
Host smart-1ac0d85b-4fe7-426f-954c-015f4ba2c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837701247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.1837701247
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.3592267559
Short name T134
Test name
Test status
Simulation time 65232247 ps
CPU time 0.72 seconds
Started Jan 25 01:05:01 PM PST 24
Finished Jan 25 01:05:05 PM PST 24
Peak memory 204368 kb
Host smart-2340809a-f3b9-4c96-b4c4-0382c7c1ea13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592267559 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.3
592267559
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.266549579
Short name T131
Test name
Test status
Simulation time 8784374 ps
CPU time 0.79 seconds
Started Jan 25 01:09:47 PM PST 24
Finished Jan 25 01:09:54 PM PST 24
Peak memory 204388 kb
Host smart-905655a1-de7e-41f5-bb25-423aad0b971e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266549579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.266549579
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.3746797754
Short name T141
Test name
Test status
Simulation time 65213690 ps
CPU time 0.81 seconds
Started Jan 25 03:09:55 PM PST 24
Finished Jan 25 03:09:59 PM PST 24
Peak memory 204596 kb
Host smart-3792251c-e1e1-4e5d-b16f-75d6ad96b497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746797754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.3
746797754
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.3254613673
Short name T163
Test name
Test status
Simulation time 629481233 ps
CPU time 3.44 seconds
Started Jan 25 02:18:15 PM PST 24
Finished Jan 25 02:18:43 PM PST 24
Peak memory 205312 kb
Host smart-15a453ce-554a-48ca-b328-6e835d87334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254613673 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.3254613673
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.1245319079
Short name T36
Test name
Test status
Simulation time 12653313 ps
CPU time 0.86 seconds
Started Jan 25 01:05:09 PM PST 24
Finished Jan 25 01:05:22 PM PST 24
Peak memory 204376 kb
Host smart-152ea5b7-3528-4ed7-a5ca-f7795c3bb144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245319079 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.1
245319079
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.281486798
Short name T16
Test name
Test status
Simulation time 51972307 ps
CPU time 2 seconds
Started Jan 25 02:29:37 PM PST 24
Finished Jan 25 02:30:01 PM PST 24
Peak memory 206572 kb
Host smart-646e03f8-81c4-412c-868e-e31e484448e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281486798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.281486798
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.2837305263
Short name T142
Test name
Test status
Simulation time 48935993 ps
CPU time 0.81 seconds
Started Jan 25 01:44:40 PM PST 24
Finished Jan 25 01:44:49 PM PST 24
Peak memory 204344 kb
Host smart-fea8aafb-bfe6-49f7-94f2-ee3609d3f291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837305263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.2
837305263
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3833085481
Short name T12
Test name
Test status
Simulation time 32516455 ps
CPU time 2.01 seconds
Started Jan 25 01:27:28 PM PST 24
Finished Jan 25 01:27:40 PM PST 24
Peak memory 205352 kb
Host smart-1b49fb25-5213-4ab4-abc4-07b091697129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833085481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3833085481
Directory /workspace/9.keymgr_dpe_smoke/latest
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