Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.69 90.67 57.52 76.92 94.90 98.34 17.78


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2975483170 Feb 01 01:18:46 PM PST 24 Feb 01 01:18:51 PM PST 24 29977025 ps
T61 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1140384736 Feb 01 01:19:56 PM PST 24 Feb 01 01:20:09 PM PST 24 122956271 ps
T256 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.334859142 Feb 01 01:19:33 PM PST 24 Feb 01 01:19:48 PM PST 24 197596555 ps
T257 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1645119796 Feb 01 01:19:16 PM PST 24 Feb 01 01:19:25 PM PST 24 214392663 ps
T258 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2018731802 Feb 01 01:19:59 PM PST 24 Feb 01 01:20:10 PM PST 24 492297919 ps
T259 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3777601862 Feb 01 01:19:45 PM PST 24 Feb 01 01:19:58 PM PST 24 80892612 ps
T260 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.809368810 Feb 01 01:19:09 PM PST 24 Feb 01 01:19:14 PM PST 24 121852319 ps
T261 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.715480616 Feb 01 01:19:11 PM PST 24 Feb 01 01:19:18 PM PST 24 1249289856 ps
T262 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.637419288 Feb 01 01:19:53 PM PST 24 Feb 01 01:20:06 PM PST 24 66374341 ps
T263 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.1386063147 Feb 01 01:18:32 PM PST 24 Feb 01 01:18:37 PM PST 24 420663037 ps
T56 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.656454927 Feb 01 01:19:31 PM PST 24 Feb 01 01:19:40 PM PST 24 987989630 ps
T59 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3917201355 Feb 01 01:19:11 PM PST 24 Feb 01 01:19:20 PM PST 24 707343563 ps
T264 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.3366366465 Feb 01 01:18:45 PM PST 24 Feb 01 01:18:59 PM PST 24 666626441 ps
T265 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3265860388 Feb 01 01:22:52 PM PST 24 Feb 01 01:22:53 PM PST 24 70841963 ps
T266 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3378690699 Feb 01 01:19:32 PM PST 24 Feb 01 01:19:43 PM PST 24 96832939 ps
T267 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.977624648 Feb 01 01:19:14 PM PST 24 Feb 01 01:19:24 PM PST 24 253510574 ps
T268 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1523249121 Feb 01 01:19:11 PM PST 24 Feb 01 01:19:19 PM PST 24 205862494 ps
T269 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1052389449 Feb 01 01:19:17 PM PST 24 Feb 01 01:19:26 PM PST 24 28303261 ps
T270 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2649196288 Feb 01 01:19:50 PM PST 24 Feb 01 01:20:02 PM PST 24 26626111 ps
T271 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1419005961 Feb 01 01:19:12 PM PST 24 Feb 01 01:19:18 PM PST 24 174026952 ps
T272 /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.217966763 Feb 01 01:18:47 PM PST 24 Feb 01 01:18:51 PM PST 24 72476422 ps
T273 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.250674078 Feb 01 01:19:16 PM PST 24 Feb 01 01:19:27 PM PST 24 168068806 ps
T274 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1301388813 Feb 01 01:19:07 PM PST 24 Feb 01 01:19:11 PM PST 24 52368616 ps
T275 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1484623436 Feb 01 01:18:49 PM PST 24 Feb 01 01:19:01 PM PST 24 548818632 ps
T276 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1595267661 Feb 01 01:19:47 PM PST 24 Feb 01 01:19:59 PM PST 24 138832519 ps
T277 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.230211375 Feb 01 01:18:35 PM PST 24 Feb 01 01:18:42 PM PST 24 236742498 ps
T278 /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.3989294614 Feb 01 01:22:43 PM PST 24 Feb 01 01:22:44 PM PST 24 27963654 ps
T279 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.354392516 Feb 01 01:18:46 PM PST 24 Feb 01 01:18:54 PM PST 24 93644418 ps
T280 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2578518628 Feb 01 01:19:46 PM PST 24 Feb 01 01:20:00 PM PST 24 137953569 ps
T281 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3659634408 Feb 01 01:18:48 PM PST 24 Feb 01 01:18:55 PM PST 24 70577142 ps
T282 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.2582167550 Feb 01 01:19:58 PM PST 24 Feb 01 01:20:10 PM PST 24 232962292 ps
T283 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.151908044 Feb 01 01:19:33 PM PST 24 Feb 01 01:19:45 PM PST 24 29275197 ps
T284 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.670465229 Feb 01 01:18:46 PM PST 24 Feb 01 01:18:50 PM PST 24 143951098 ps
T285 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1614826340 Feb 01 01:18:44 PM PST 24 Feb 01 01:18:50 PM PST 24 43074999 ps
T286 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.4050369321 Feb 01 01:19:31 PM PST 24 Feb 01 01:19:37 PM PST 24 62633219 ps
T287 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.115029457 Feb 01 01:18:45 PM PST 24 Feb 01 01:18:51 PM PST 24 70641797 ps
T288 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3246019432 Feb 01 01:19:51 PM PST 24 Feb 01 01:20:09 PM PST 24 201555743 ps
T289 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2308441291 Feb 01 01:19:11 PM PST 24 Feb 01 01:19:17 PM PST 24 160620844 ps
T290 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1670347113 Feb 01 01:23:44 PM PST 24 Feb 01 01:24:09 PM PST 24 28118863 ps
T291 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2275028511 Feb 01 01:19:53 PM PST 24 Feb 01 01:20:06 PM PST 24 131557064 ps
T292 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3354629672 Feb 01 01:23:13 PM PST 24 Feb 01 01:23:29 PM PST 24 13214567 ps
T293 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2363755845 Feb 01 01:19:12 PM PST 24 Feb 01 01:19:22 PM PST 24 1816050556 ps
T294 /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.303638066 Feb 01 01:19:55 PM PST 24 Feb 01 01:20:07 PM PST 24 37184818 ps
T295 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.2918717858 Feb 01 01:19:29 PM PST 24 Feb 01 01:19:33 PM PST 24 845303765 ps
T296 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.182576658 Feb 01 01:18:50 PM PST 24 Feb 01 01:18:57 PM PST 24 148081027 ps
T297 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.1751988409 Feb 01 01:18:46 PM PST 24 Feb 01 01:18:50 PM PST 24 42954327 ps
T298 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.580738338 Feb 01 01:19:12 PM PST 24 Feb 01 01:19:17 PM PST 24 89463242 ps
T299 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.1563641569 Feb 01 01:20:04 PM PST 24 Feb 01 01:20:12 PM PST 24 138027763 ps
T300 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1622668123 Feb 01 01:18:46 PM PST 24 Feb 01 01:18:59 PM PST 24 341714643 ps
T301 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2493648130 Feb 01 01:19:12 PM PST 24 Feb 01 01:19:16 PM PST 24 21050273 ps
T302 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.3012431275 Feb 01 01:19:15 PM PST 24 Feb 01 01:19:23 PM PST 24 18098594 ps
T303 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1620903914 Feb 01 01:19:49 PM PST 24 Feb 01 01:20:01 PM PST 24 61760875 ps
T304 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1166667284 Feb 01 01:19:50 PM PST 24 Feb 01 01:20:02 PM PST 24 98940560 ps
T57 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3727917650 Feb 01 01:18:49 PM PST 24 Feb 01 01:19:00 PM PST 24 360575126 ps
T305 /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3520775508 Feb 01 01:22:56 PM PST 24 Feb 01 01:23:07 PM PST 24 17204517 ps
T306 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.3328306456 Feb 01 01:19:52 PM PST 24 Feb 01 01:20:06 PM PST 24 82604954 ps
T307 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3362904969 Feb 01 01:19:16 PM PST 24 Feb 01 01:19:27 PM PST 24 296888206 ps
T308 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2875643609 Feb 01 01:19:12 PM PST 24 Feb 01 01:19:16 PM PST 24 201474322 ps
T309 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1683966772 Feb 01 01:19:08 PM PST 24 Feb 01 01:19:12 PM PST 24 452579382 ps

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.4113645379
Short name T10
Test name
Test status
Simulation time 5085016641 ps
CPU time 42.69 seconds
Started Feb 01 01:38:25 PM PST 24
Finished Feb 01 01:39:22 PM PST 24
Peak memory 207812 kb
Host smart-fc46ef7f-81ee-4cd8-8aa0-e22bbf1c37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113645379 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.4113645379
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.96985460
Short name T22
Test name
Test status
Simulation time 6667929594 ps
CPU time 14.13 seconds
Started Feb 01 01:38:28 PM PST 24
Finished Feb 01 01:38:58 PM PST 24
Peak memory 233600 kb
Host smart-9163f275-b3dc-40b3-b074-00245f8256e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96985460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.96985460
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3141015776
Short name T20
Test name
Test status
Simulation time 105359831 ps
CPU time 3.51 seconds
Started Feb 01 01:19:09 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 214060 kb
Host smart-482a3852-0f97-442f-af4a-2c96e55e2bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141015776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3141015776
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.180643040
Short name T107
Test name
Test status
Simulation time 179973335 ps
CPU time 1.87 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 213360 kb
Host smart-46f11b9b-cdbe-49a8-8274-293ccc8929c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180643040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keym
gr_dpe_shadow_reg_errors.180643040
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2997656290
Short name T14
Test name
Test status
Simulation time 6103743814 ps
CPU time 95.33 seconds
Started Feb 01 01:39:04 PM PST 24
Finished Feb 01 01:40:57 PM PST 24
Peak memory 206632 kb
Host smart-9aeedb2b-2948-4b7f-8194-9733b5ac1e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997656290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2997656290
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.3929164915
Short name T27
Test name
Test status
Simulation time 144091722 ps
CPU time 2.87 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 221176 kb
Host smart-b0cb4e14-85ff-4a20-81fd-45918a213fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929164915 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
3929164915
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1739919765
Short name T44
Test name
Test status
Simulation time 57264064 ps
CPU time 2.56 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:34 PM PST 24
Peak memory 213336 kb
Host smart-aec94242-2e37-4ec9-a23d-53bb31124ddd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739919765 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1739919765
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2915528076
Short name T100
Test name
Test status
Simulation time 46549902 ps
CPU time 0.71 seconds
Started Feb 01 01:19:14 PM PST 24
Finished Feb 01 01:19:21 PM PST 24
Peak memory 204496 kb
Host smart-3987200b-b54f-4ef2-a775-74a83f6824f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915528076 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2
915528076
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.738761726
Short name T125
Test name
Test status
Simulation time 119617409 ps
CPU time 0.75 seconds
Started Feb 01 01:39:13 PM PST 24
Finished Feb 01 01:39:37 PM PST 24
Peak memory 204768 kb
Host smart-66fd7c9c-44b2-489c-8861-c921c4d35b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738761726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.738761726
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.3572167440
Short name T49
Test name
Test status
Simulation time 192828305 ps
CPU time 2.9 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 212984 kb
Host smart-77b8c35a-5453-4de5-835d-d8ca008de543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572167440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
3572167440
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.2956274919
Short name T74
Test name
Test status
Simulation time 5289686090 ps
CPU time 23.86 seconds
Started Feb 01 01:39:24 PM PST 24
Finished Feb 01 01:40:13 PM PST 24
Peak memory 207488 kb
Host smart-66a85029-541e-40e9-bcd5-bfb1bf02276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956274919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.2956274919
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.2295190349
Short name T52
Test name
Test status
Simulation time 611823539 ps
CPU time 5.15 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:47 PM PST 24
Peak memory 212796 kb
Host smart-890dc906-4db0-4bde-be09-36fff7b25c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295190349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.2295190349
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1140384736
Short name T61
Test name
Test status
Simulation time 122956271 ps
CPU time 2.8 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 213336 kb
Host smart-165c96cd-e690-4a1c-900c-633f1ecbb877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140384736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1140384736
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.167972533
Short name T4
Test name
Test status
Simulation time 20880868022 ps
CPU time 28.54 seconds
Started Feb 01 01:38:59 PM PST 24
Finished Feb 01 01:39:43 PM PST 24
Peak memory 207364 kb
Host smart-4bef0234-ac6f-4c57-a5da-81b1a72a2335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167972533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.167972533
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2168752763
Short name T66
Test name
Test status
Simulation time 296698183 ps
CPU time 1.26 seconds
Started Feb 01 01:18:58 PM PST 24
Finished Feb 01 01:19:05 PM PST 24
Peak memory 213388 kb
Host smart-cc591cdc-61e7-47c5-9a84-b0f99d0db418
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168752763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2168752763
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.656454927
Short name T56
Test name
Test status
Simulation time 987989630 ps
CPU time 5.58 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:40 PM PST 24
Peak memory 212988 kb
Host smart-a5158c51-3513-4713-9966-eb34876012eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656454927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe
_tl_intg_err.656454927
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.853421251
Short name T48
Test name
Test status
Simulation time 410153290 ps
CPU time 3.64 seconds
Started Feb 01 01:19:10 PM PST 24
Finished Feb 01 01:19:18 PM PST 24
Peak memory 212980 kb
Host smart-27f4990c-301d-4398-bcf4-9773dd6a9f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853421251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_
tl_intg_err.853421251
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.1478288415
Short name T13
Test name
Test status
Simulation time 3765409678 ps
CPU time 19.62 seconds
Started Feb 01 01:39:05 PM PST 24
Finished Feb 01 01:39:43 PM PST 24
Peak memory 206052 kb
Host smart-474c9a9a-036a-4052-8c11-d01a4a7eb0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478288415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.1478288415
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.4284411066
Short name T54
Test name
Test status
Simulation time 673922476 ps
CPU time 7.09 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:43 PM PST 24
Peak memory 213388 kb
Host smart-23b3b1a2-56b4-4cec-824b-fc82aaaf5ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284411066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.4284411066
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.1513997631
Short name T58
Test name
Test status
Simulation time 95881854 ps
CPU time 4.02 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:37 PM PST 24
Peak memory 213576 kb
Host smart-fd8c940c-b5aa-4034-a8ca-aa171eec3778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513997631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.1513997631
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.596748191
Short name T42
Test name
Test status
Simulation time 211203537 ps
CPU time 3.88 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:12 PM PST 24
Peak memory 213876 kb
Host smart-2775c8b3-5ef1-4322-b1b2-95f8863d8120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596748191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe
_tl_intg_err.596748191
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.492503170
Short name T60
Test name
Test status
Simulation time 448960532 ps
CPU time 3.07 seconds
Started Feb 01 01:19:57 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 205492 kb
Host smart-fadb024c-abf8-4861-9b12-c208ca624a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492503170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.492503170
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3917201355
Short name T59
Test name
Test status
Simulation time 707343563 ps
CPU time 4.84 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:20 PM PST 24
Peak memory 214012 kb
Host smart-7497f22e-8073-47d3-9bfb-a6c1d60bd106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917201355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.3917201355
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.2849088687
Short name T124
Test name
Test status
Simulation time 19768116 ps
CPU time 1.28 seconds
Started Feb 01 01:18:43 PM PST 24
Finished Feb 01 01:18:46 PM PST 24
Peak memory 212808 kb
Host smart-6c5b1a69-17f5-46b7-98db-afbb35649fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849088687 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.2849088687
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.565380181
Short name T178
Test name
Test status
Simulation time 15718166 ps
CPU time 0.94 seconds
Started Feb 01 01:18:41 PM PST 24
Finished Feb 01 01:18:44 PM PST 24
Peak memory 204564 kb
Host smart-cfa483dc-0801-448e-bf64-5a355e86540e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565380181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.565380181
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2707426717
Short name T121
Test name
Test status
Simulation time 2070310268 ps
CPU time 18.31 seconds
Started Feb 01 01:38:24 PM PST 24
Finished Feb 01 01:38:57 PM PST 24
Peak memory 207224 kb
Host smart-a52a3a20-1de3-47b3-9977-698069b5d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707426717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2707426717
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.1454304574
Short name T3
Test name
Test status
Simulation time 527870555 ps
CPU time 19.92 seconds
Started Feb 01 01:39:00 PM PST 24
Finished Feb 01 01:39:36 PM PST 24
Peak memory 207456 kb
Host smart-2cfc8330-bf4b-4f25-b5ea-04c2f8e1d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454304574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.1454304574
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.2545735501
Short name T12
Test name
Test status
Simulation time 4291945412 ps
CPU time 42.52 seconds
Started Feb 01 01:39:05 PM PST 24
Finished Feb 01 01:40:06 PM PST 24
Peak memory 216876 kb
Host smart-7f635ed7-b55e-4693-a59b-9bcdcef48ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545735501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.2545735501
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.3869332605
Short name T94
Test name
Test status
Simulation time 2185262462 ps
CPU time 12.46 seconds
Started Feb 01 01:39:14 PM PST 24
Finished Feb 01 01:39:51 PM PST 24
Peak memory 207532 kb
Host smart-bbb62109-e0dd-414d-8074-5b0d9f11949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869332605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3869332605
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.919033881
Short name T114
Test name
Test status
Simulation time 592809273 ps
CPU time 14.64 seconds
Started Feb 01 01:39:27 PM PST 24
Finished Feb 01 01:40:07 PM PST 24
Peak memory 206916 kb
Host smart-66c67fa7-37e4-414c-8b8e-ced3b38ab665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919033881 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.919033881
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.90816938
Short name T83
Test name
Test status
Simulation time 17991048679 ps
CPU time 131.69 seconds
Started Feb 01 01:39:19 PM PST 24
Finished Feb 01 01:41:56 PM PST 24
Peak memory 207396 kb
Host smart-96196dd7-7ad8-4e57-b7af-ad094aadbf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90816938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.90816938
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.964832654
Short name T95
Test name
Test status
Simulation time 918295888 ps
CPU time 25.36 seconds
Started Feb 01 01:39:13 PM PST 24
Finished Feb 01 01:40:02 PM PST 24
Peak memory 207040 kb
Host smart-d177a1df-c76d-4628-93e5-be8bf2fdd73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964832654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.964832654
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1128514149
Short name T76
Test name
Test status
Simulation time 860529440 ps
CPU time 18.67 seconds
Started Feb 01 01:39:16 PM PST 24
Finished Feb 01 01:40:00 PM PST 24
Peak memory 205904 kb
Host smart-928a972c-5a88-46e4-b6e0-fdf7f46bfda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128514149 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1128514149
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.747389711
Short name T113
Test name
Test status
Simulation time 4420195766 ps
CPU time 25 seconds
Started Feb 01 01:39:23 PM PST 24
Finished Feb 01 01:40:13 PM PST 24
Peak memory 207372 kb
Host smart-094d6958-392f-4fd0-af5a-c3e9bb22172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747389711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.747389711
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3564746217
Short name T82
Test name
Test status
Simulation time 753731755 ps
CPU time 10.91 seconds
Started Feb 01 01:48:20 PM PST 24
Finished Feb 01 01:48:45 PM PST 24
Peak memory 207124 kb
Host smart-66a7d0e2-71df-4cfe-9d7f-d6ad1cb17c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564746217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3564746217
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3163654143
Short name T116
Test name
Test status
Simulation time 1380549939 ps
CPU time 23.28 seconds
Started Feb 01 01:44:06 PM PST 24
Finished Feb 01 01:44:59 PM PST 24
Peak memory 205928 kb
Host smart-8377ebfe-b81f-488f-a587-7af2251faa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163654143 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3163654143
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.3111143782
Short name T115
Test name
Test status
Simulation time 2052294569 ps
CPU time 19.06 seconds
Started Feb 01 01:39:44 PM PST 24
Finished Feb 01 01:40:28 PM PST 24
Peak memory 207488 kb
Host smart-82096a88-7eb8-4bc3-badb-8545ab13c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111143782 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.3111143782
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.129499182
Short name T23
Test name
Test status
Simulation time 4632510348 ps
CPU time 21.44 seconds
Started Feb 01 01:38:43 PM PST 24
Finished Feb 01 01:39:20 PM PST 24
Peak memory 230284 kb
Host smart-509764fb-c2e8-4e40-b4ab-518897912621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129499182 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.129499182
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.1567119781
Short name T71
Test name
Test status
Simulation time 82758218 ps
CPU time 2.81 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:52 PM PST 24
Peak memory 204736 kb
Host smart-fa26b62f-542a-4d87-a9b3-45764af26f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567119781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.1567119781
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2349548457
Short name T213
Test name
Test status
Simulation time 1730339154 ps
CPU time 12.17 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:19:07 PM PST 24
Peak memory 204752 kb
Host smart-1090538f-8c47-405a-b6f1-2cd1c34e81da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349548457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2349548457
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2498049123
Short name T102
Test name
Test status
Simulation time 39015532 ps
CPU time 1.05 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 204596 kb
Host smart-fc0ac71a-25a6-4d1c-bb72-561beca2e4d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498049123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2498049123
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3125227685
Short name T212
Test name
Test status
Simulation time 101514367 ps
CPU time 0.97 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204556 kb
Host smart-a0262a71-6864-48c9-ab7a-b007668f39f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125227685 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3
125227685
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.115029457
Short name T287
Test name
Test status
Simulation time 70641797 ps
CPU time 2.79 seconds
Started Feb 01 01:18:45 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 204748 kb
Host smart-49f38a1b-5b4a-4943-bf59-a77b7d66ccc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115029457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_dpe_same_csr_outstanding.115029457
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.4248821651
Short name T106
Test name
Test status
Simulation time 136385389 ps
CPU time 2.38 seconds
Started Feb 01 01:18:35 PM PST 24
Finished Feb 01 01:18:41 PM PST 24
Peak memory 213340 kb
Host smart-397a5ef3-f5c7-4bff-8174-df14433585ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248821651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.4248821651
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2640991446
Short name T222
Test name
Test status
Simulation time 81046396 ps
CPU time 2.93 seconds
Started Feb 01 01:18:40 PM PST 24
Finished Feb 01 01:18:46 PM PST 24
Peak memory 219512 kb
Host smart-ce3a22ca-6be7-4b08-8421-b7c3ef8188ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640991446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2640991446
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.1386063147
Short name T263
Test name
Test status
Simulation time 420663037 ps
CPU time 3.87 seconds
Started Feb 01 01:18:32 PM PST 24
Finished Feb 01 01:18:37 PM PST 24
Peak memory 212924 kb
Host smart-5d72d358-63d5-431a-bb39-6e1277856eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386063147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.1
386063147
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.230211375
Short name T277
Test name
Test status
Simulation time 236742498 ps
CPU time 3.38 seconds
Started Feb 01 01:18:35 PM PST 24
Finished Feb 01 01:18:42 PM PST 24
Peak memory 213916 kb
Host smart-003bb1d9-9b91-435e-897c-22cdfce99592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230211375 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_
tl_intg_err.230211375
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1614826340
Short name T285
Test name
Test status
Simulation time 43074999 ps
CPU time 3.01 seconds
Started Feb 01 01:18:44 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204608 kb
Host smart-2fce79e1-b26c-4ba7-a3e3-5ed5b0ebde19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614826340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.1614826340
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1622668123
Short name T300
Test name
Test status
Simulation time 341714643 ps
CPU time 9.92 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:59 PM PST 24
Peak memory 204732 kb
Host smart-95208d3f-2578-4e3f-a261-11d296204c5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622668123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1622668123
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.670465229
Short name T284
Test name
Test status
Simulation time 143951098 ps
CPU time 0.9 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204528 kb
Host smart-dde20409-683c-46fc-9a63-1320c1f71c86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670465229 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_hw_reset.670465229
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1704114819
Short name T230
Test name
Test status
Simulation time 59755139 ps
CPU time 1.56 seconds
Started Feb 01 01:18:59 PM PST 24
Finished Feb 01 01:19:06 PM PST 24
Peak memory 213064 kb
Host smart-1a4c213d-635b-41dc-a014-89ea73729583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704114819 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.1704114819
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.1751988409
Short name T297
Test name
Test status
Simulation time 42954327 ps
CPU time 1.06 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204640 kb
Host smart-9f616791-d30a-4c93-8352-f9406a0a396b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751988409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.1
751988409
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1219601501
Short name T41
Test name
Test status
Simulation time 11940532 ps
CPU time 0.83 seconds
Started Feb 01 01:18:48 PM PST 24
Finished Feb 01 01:18:53 PM PST 24
Peak memory 204496 kb
Host smart-8ac673bc-5a3e-435d-b255-fed152972ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219601501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1
219601501
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.1544405764
Short name T31
Test name
Test status
Simulation time 113044967 ps
CPU time 1.85 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:18:57 PM PST 24
Peak memory 204720 kb
Host smart-c4af9504-1e2c-4577-aa7a-9f07d7d1d740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544405764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.1544405764
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2423765441
Short name T254
Test name
Test status
Simulation time 541488694 ps
CPU time 5.29 seconds
Started Feb 01 01:18:44 PM PST 24
Finished Feb 01 01:18:53 PM PST 24
Peak memory 213152 kb
Host smart-eacf34af-0809-45ff-91dd-6c2e402b6b53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423765441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2423765441
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.3494845539
Short name T46
Test name
Test status
Simulation time 67753021 ps
CPU time 1.77 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:52 PM PST 24
Peak memory 214356 kb
Host smart-d60c5c01-2832-4671-87e3-5059ba7aeb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494845539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.3
494845539
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2501266542
Short name T47
Test name
Test status
Simulation time 264683235 ps
CPU time 2.41 seconds
Started Feb 01 01:18:44 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 212912 kb
Host smart-f80e1df0-273f-4849-9819-af58fa112193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501266542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2501266542
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.151908044
Short name T283
Test name
Test status
Simulation time 29275197 ps
CPU time 1.34 seconds
Started Feb 01 01:19:33 PM PST 24
Finished Feb 01 01:19:45 PM PST 24
Peak memory 213048 kb
Host smart-c693de2a-1e52-4bf0-9a0a-b29c41c90711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151908044 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.151908044
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2550245603
Short name T85
Test name
Test status
Simulation time 11979186 ps
CPU time 0.96 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:31 PM PST 24
Peak memory 204544 kb
Host smart-3839bc3e-56ed-4cdb-897d-df4e7767df6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550245603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2550245603
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.3902099909
Short name T208
Test name
Test status
Simulation time 10214719 ps
CPU time 0.84 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:36 PM PST 24
Peak memory 204380 kb
Host smart-b5a2e03f-72df-4d47-8c62-f8784c1402c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902099909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
3902099909
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1359241925
Short name T86
Test name
Test status
Simulation time 393807501 ps
CPU time 3.14 seconds
Started Feb 01 01:19:30 PM PST 24
Finished Feb 01 01:19:36 PM PST 24
Peak memory 212924 kb
Host smart-5756cd4b-f964-443b-8f2d-c7a4a9247bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359241925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1359241925
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1128234979
Short name T204
Test name
Test status
Simulation time 84072120 ps
CPU time 1.73 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 213124 kb
Host smart-e0f4abc1-7980-4a3b-aa68-5f1b2aadd8c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128234979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1128234979
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3454004935
Short name T233
Test name
Test status
Simulation time 485635141 ps
CPU time 5.83 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:36 PM PST 24
Peak memory 213364 kb
Host smart-4d609192-383f-4783-9e04-afe829278c3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454004935 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3454004935
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2723398916
Short name T237
Test name
Test status
Simulation time 844550240 ps
CPU time 5.81 seconds
Started Feb 01 01:19:33 PM PST 24
Finished Feb 01 01:19:50 PM PST 24
Peak memory 216028 kb
Host smart-6617f4bf-ad19-4072-803a-9efe515ed807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723398916 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
2723398916
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.1086063564
Short name T221
Test name
Test status
Simulation time 33073439 ps
CPU time 1 seconds
Started Feb 01 01:19:33 PM PST 24
Finished Feb 01 01:19:44 PM PST 24
Peak memory 204648 kb
Host smart-ab5a5805-dc59-48f1-951e-e2f02c7acbef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086063564 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.1086063564
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3963852638
Short name T201
Test name
Test status
Simulation time 11756273 ps
CPU time 0.98 seconds
Started Feb 01 01:19:30 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 204652 kb
Host smart-2f9b35bc-f3f5-40b8-aa3c-1cbeea631a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963852638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
3963852638
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.3525904501
Short name T181
Test name
Test status
Simulation time 95830126 ps
CPU time 0.72 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:36 PM PST 24
Peak memory 204404 kb
Host smart-45753f96-0401-4beb-8591-f7a5d154c4bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525904501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
3525904501
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2697208415
Short name T228
Test name
Test status
Simulation time 131864632 ps
CPU time 1.4 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:35 PM PST 24
Peak memory 204716 kb
Host smart-5ecc89d2-1490-4478-b192-d950f8cbee42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697208415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2697208415
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.447744018
Short name T196
Test name
Test status
Simulation time 191468083 ps
CPU time 2.89 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:34 PM PST 24
Peak memory 213256 kb
Host smart-18f84048-1214-4f0e-a2e4-548826bd3f93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447744018 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keym
gr_dpe_shadow_reg_errors.447744018
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2200323886
Short name T226
Test name
Test status
Simulation time 218386209 ps
CPU time 3.1 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:38 PM PST 24
Peak memory 213288 kb
Host smart-943c83e7-37b7-4542-b3c3-0ea3454dfe80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200323886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2200323886
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.334859142
Short name T256
Test name
Test status
Simulation time 197596555 ps
CPU time 3.65 seconds
Started Feb 01 01:19:33 PM PST 24
Finished Feb 01 01:19:48 PM PST 24
Peak memory 221024 kb
Host smart-b4f33615-7e8e-4f61-8a3a-d1bb2242e53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334859142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.334859142
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2546183011
Short name T211
Test name
Test status
Simulation time 46031554 ps
CPU time 1.15 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:35 PM PST 24
Peak memory 212676 kb
Host smart-38f48e39-98a5-4d51-a220-ad127e74e543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546183011 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2546183011
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.14538498
Short name T32
Test name
Test status
Simulation time 84519965 ps
CPU time 1.28 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:41 PM PST 24
Peak memory 204640 kb
Host smart-4dc03218-6ff2-48fb-8e97-7c0386e7b67d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14538498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.14538498
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1753796494
Short name T225
Test name
Test status
Simulation time 24001146 ps
CPU time 0.84 seconds
Started Feb 01 01:19:30 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 204588 kb
Host smart-65d20bb5-1568-4eac-a77b-1c29e81db0e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753796494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
1753796494
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1940604307
Short name T87
Test name
Test status
Simulation time 31416284 ps
CPU time 2.06 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 204804 kb
Host smart-dffac687-2080-44aa-9040-a99d82f54afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940604307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1940604307
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.1144732698
Short name T64
Test name
Test status
Simulation time 126605535 ps
CPU time 2.42 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:35 PM PST 24
Peak memory 213312 kb
Host smart-6cd90db1-f19c-4ccf-8408-5fc6188ac375
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144732698 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.1144732698
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1808627659
Short name T197
Test name
Test status
Simulation time 2501717957 ps
CPU time 9.35 seconds
Started Feb 01 01:19:30 PM PST 24
Finished Feb 01 01:19:42 PM PST 24
Peak memory 219252 kb
Host smart-7c076c90-de71-4fa9-8aba-df455a587ddc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808627659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1808627659
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.2918717858
Short name T295
Test name
Test status
Simulation time 845303765 ps
CPU time 2.22 seconds
Started Feb 01 01:19:29 PM PST 24
Finished Feb 01 01:19:33 PM PST 24
Peak memory 213012 kb
Host smart-015608e3-5067-4945-9f1d-2f74f0d623ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918717858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
2918717858
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.637419288
Short name T262
Test name
Test status
Simulation time 66374341 ps
CPU time 1.21 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 212864 kb
Host smart-215be287-680a-4071-98c9-914e10b687f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637419288 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.637419288
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3378690699
Short name T266
Test name
Test status
Simulation time 96832939 ps
CPU time 1.21 seconds
Started Feb 01 01:19:32 PM PST 24
Finished Feb 01 01:19:43 PM PST 24
Peak memory 204704 kb
Host smart-84513e08-88a0-4615-8606-8b25bd3e599a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378690699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
3378690699
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.3504688849
Short name T103
Test name
Test status
Simulation time 20257676 ps
CPU time 0.7 seconds
Started Feb 01 01:19:33 PM PST 24
Finished Feb 01 01:19:44 PM PST 24
Peak memory 204452 kb
Host smart-2ac4aff9-380e-4fbb-baed-32cf2bdf4924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504688849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
3504688849
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.3391609021
Short name T243
Test name
Test status
Simulation time 157734531 ps
CPU time 1.23 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 204848 kb
Host smart-b4ebcb9e-dd11-4cd1-a86e-8fe371d836ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391609021 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.3391609021
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.4050369321
Short name T286
Test name
Test status
Simulation time 62633219 ps
CPU time 2.06 seconds
Started Feb 01 01:19:31 PM PST 24
Finished Feb 01 01:19:37 PM PST 24
Peak memory 213240 kb
Host smart-58a56e05-15bd-4f99-a7d1-55dece8cf035
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050369321 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.4050369321
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3777601862
Short name T259
Test name
Test status
Simulation time 80892612 ps
CPU time 1.67 seconds
Started Feb 01 01:19:45 PM PST 24
Finished Feb 01 01:19:58 PM PST 24
Peak memory 217212 kb
Host smart-b26cd532-0732-43ff-95d5-f68ed521415e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777601862 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3777601862
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2577228322
Short name T245
Test name
Test status
Simulation time 88125984 ps
CPU time 0.97 seconds
Started Feb 01 01:19:47 PM PST 24
Finished Feb 01 01:19:59 PM PST 24
Peak memory 204664 kb
Host smart-678ce189-e3bd-47e9-bf22-ef7fd7764285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577228322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2577228322
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2831599541
Short name T241
Test name
Test status
Simulation time 11357828 ps
CPU time 0.75 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:04 PM PST 24
Peak memory 204476 kb
Host smart-7345e48d-de0c-4091-be46-4eee81f5c347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831599541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2831599541
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.2376669302
Short name T198
Test name
Test status
Simulation time 471845190 ps
CPU time 2.35 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 204740 kb
Host smart-e91128c8-9f1b-4800-9204-2359d916cce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376669302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.2376669302
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.77802974
Short name T191
Test name
Test status
Simulation time 215473943 ps
CPU time 1.36 seconds
Started Feb 01 01:19:48 PM PST 24
Finished Feb 01 01:20:00 PM PST 24
Peak memory 213336 kb
Host smart-2f045d4b-4ccc-4b6c-bf97-4671d83d0928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77802974 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keym
gr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymg
r_dpe_shadow_reg_errors.77802974
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.37508611
Short name T68
Test name
Test status
Simulation time 566507822 ps
CPU time 3.48 seconds
Started Feb 01 01:19:48 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 213356 kb
Host smart-3b5535af-f8be-4fc8-9850-4d5284b93331
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37508611 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.37508611
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.87227202
Short name T252
Test name
Test status
Simulation time 62864067 ps
CPU time 1.46 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:05 PM PST 24
Peak memory 221008 kb
Host smart-e336aa8d-c796-45d0-a68c-d4656735376b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87227202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.87227202
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1616028214
Short name T62
Test name
Test status
Simulation time 91723482 ps
CPU time 2.46 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 214008 kb
Host smart-475845b3-255f-4ac0-8060-4f2b7c72c969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616028214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1616028214
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1620903914
Short name T303
Test name
Test status
Simulation time 61760875 ps
CPU time 1.17 seconds
Started Feb 01 01:19:49 PM PST 24
Finished Feb 01 01:20:01 PM PST 24
Peak memory 204720 kb
Host smart-36adeecc-7316-41be-8485-c6c8890047d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620903914 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1620903914
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1225142628
Short name T189
Test name
Test status
Simulation time 9893341 ps
CPU time 0.83 seconds
Started Feb 01 01:19:55 PM PST 24
Finished Feb 01 01:20:07 PM PST 24
Peak memory 204468 kb
Host smart-3c4bc4bb-a7d0-424c-903d-785a64789d89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225142628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
1225142628
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2530834738
Short name T190
Test name
Test status
Simulation time 10603459 ps
CPU time 0.8 seconds
Started Feb 01 01:19:44 PM PST 24
Finished Feb 01 01:19:55 PM PST 24
Peak memory 204576 kb
Host smart-20d4d175-a105-4bcf-9ca6-76f6b6ea06d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530834738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2530834738
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3523068656
Short name T224
Test name
Test status
Simulation time 36627484 ps
CPU time 1.4 seconds
Started Feb 01 01:19:48 PM PST 24
Finished Feb 01 01:20:00 PM PST 24
Peak memory 204680 kb
Host smart-c016a876-6048-4734-ab9d-e60b4002394f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523068656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3523068656
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2275028511
Short name T291
Test name
Test status
Simulation time 131557064 ps
CPU time 2.16 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 213184 kb
Host smart-987a226c-0005-4730-8b47-a72197c1eeab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275028511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2275028511
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3878521630
Short name T202
Test name
Test status
Simulation time 1210720035 ps
CPU time 4.49 seconds
Started Feb 01 01:19:54 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 213260 kb
Host smart-ca1953e8-b645-4df6-8a7b-f8bbb0c14104
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878521630 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3878521630
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.4251811120
Short name T21
Test name
Test status
Simulation time 62772397 ps
CPU time 1.1 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 204808 kb
Host smart-ba904815-c559-40d9-86ca-e6ab66b973b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251811120 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.4251811120
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.835529158
Short name T91
Test name
Test status
Simulation time 15636982 ps
CPU time 1.07 seconds
Started Feb 01 01:19:54 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 204544 kb
Host smart-41c7a697-f58f-46cb-9730-a5dbb9fb708b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835529158 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.835529158
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.759311423
Short name T105
Test name
Test status
Simulation time 39586958 ps
CPU time 0.7 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:05 PM PST 24
Peak memory 204432 kb
Host smart-3381e898-ca1a-46de-9180-6970b94ae202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759311423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.759311423
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.4033823125
Short name T185
Test name
Test status
Simulation time 28119254 ps
CPU time 1.9 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 204800 kb
Host smart-ff2d85ad-4679-4b32-bfa2-5fe6c34ecb4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033823125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.4033823125
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3246019432
Short name T288
Test name
Test status
Simulation time 201555743 ps
CPU time 7.57 seconds
Started Feb 01 01:19:51 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 213196 kb
Host smart-4f542bed-4ec4-4865-928f-2d478ab4a5a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246019432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3246019432
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.3328306456
Short name T306
Test name
Test status
Simulation time 82604954 ps
CPU time 2.89 seconds
Started Feb 01 01:19:52 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 212944 kb
Host smart-56c4c952-995b-49df-b77d-18d429f99f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328306456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
3328306456
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3454226016
Short name T50
Test name
Test status
Simulation time 80973732 ps
CPU time 3.09 seconds
Started Feb 01 01:19:55 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 213796 kb
Host smart-eea1626b-956b-4f9c-899e-e7fc987fa3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454226016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3454226016
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.3387936087
Short name T29
Test name
Test status
Simulation time 60754659 ps
CPU time 1.26 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:05 PM PST 24
Peak memory 204856 kb
Host smart-831054a2-0b2a-40cd-a338-b189fa4056d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387936087 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.3387936087
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1309087653
Short name T99
Test name
Test status
Simulation time 15013895 ps
CPU time 1.03 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:08 PM PST 24
Peak memory 204680 kb
Host smart-8b4b4a5f-066a-459a-a457-046c52012216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309087653 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1309087653
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.303638066
Short name T294
Test name
Test status
Simulation time 37184818 ps
CPU time 0.76 seconds
Started Feb 01 01:19:55 PM PST 24
Finished Feb 01 01:20:07 PM PST 24
Peak memory 204332 kb
Host smart-83f49f17-4e05-440f-b108-c9e9bbcaca6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303638066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.303638066
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1864976722
Short name T88
Test name
Test status
Simulation time 29474181 ps
CPU time 1.85 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 204708 kb
Host smart-1a402a41-2fc9-40f3-a722-3ae464843abc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864976722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.1864976722
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1595267661
Short name T276
Test name
Test status
Simulation time 138832519 ps
CPU time 1.41 seconds
Started Feb 01 01:19:47 PM PST 24
Finished Feb 01 01:19:59 PM PST 24
Peak memory 213384 kb
Host smart-7a6de00a-76f9-4e11-8231-b7ecdae7e680
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595267661 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1595267661
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.29746266
Short name T63
Test name
Test status
Simulation time 422554253 ps
CPU time 3.19 seconds
Started Feb 01 01:19:52 PM PST 24
Finished Feb 01 01:20:06 PM PST 24
Peak memory 218268 kb
Host smart-eaf43331-9d1c-470b-a6dd-86ade0e94292
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746266 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.29746266
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2578518628
Short name T280
Test name
Test status
Simulation time 137953569 ps
CPU time 2.97 seconds
Started Feb 01 01:19:46 PM PST 24
Finished Feb 01 01:20:00 PM PST 24
Peak memory 220720 kb
Host smart-1280e328-1a8e-4d25-9c0a-b28281531f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578518628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
2578518628
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.3361076772
Short name T55
Test name
Test status
Simulation time 644100414 ps
CPU time 5.08 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 213768 kb
Host smart-b52e82c4-e8fe-4730-9bf2-49b26323c1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361076772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.3361076772
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2018731802
Short name T258
Test name
Test status
Simulation time 492297919 ps
CPU time 1.7 seconds
Started Feb 01 01:19:59 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 213028 kb
Host smart-2b7fd8ca-5ced-4bb9-9024-17166ac749a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018731802 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2018731802
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2327810981
Short name T90
Test name
Test status
Simulation time 12794190 ps
CPU time 1.02 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 204648 kb
Host smart-621f7bab-f3fe-4130-908e-a9b38628bd08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327810981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2327810981
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.627518373
Short name T247
Test name
Test status
Simulation time 7845443 ps
CPU time 0.79 seconds
Started Feb 01 01:19:53 PM PST 24
Finished Feb 01 01:20:05 PM PST 24
Peak memory 204392 kb
Host smart-71cf0491-daa4-42d9-b609-b0d670b2f787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627518373 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.627518373
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1166667284
Short name T304
Test name
Test status
Simulation time 98940560 ps
CPU time 2.03 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 213000 kb
Host smart-51bbd211-71e9-4173-b31d-1ba6a6bce440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166667284 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1166667284
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1315339079
Short name T67
Test name
Test status
Simulation time 33750698 ps
CPU time 1.22 seconds
Started Feb 01 01:19:47 PM PST 24
Finished Feb 01 01:19:59 PM PST 24
Peak memory 213308 kb
Host smart-5bea9342-8c01-4878-9c45-6903c8e61e2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315339079 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1315339079
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.648015679
Short name T238
Test name
Test status
Simulation time 718794187 ps
CPU time 2.34 seconds
Started Feb 01 01:19:49 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 221108 kb
Host smart-302be982-dc9b-4418-bbb9-45be5b1ea7c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648015679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.648015679
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2649196288
Short name T270
Test name
Test status
Simulation time 26626111 ps
CPU time 1.83 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:02 PM PST 24
Peak memory 220836 kb
Host smart-a419bdc0-03d0-4eff-a433-8fe656828109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649196288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
2649196288
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.2318119574
Short name T236
Test name
Test status
Simulation time 132048960 ps
CPU time 1.27 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 212472 kb
Host smart-a15c5529-2821-45cb-8b6c-85c747e7d400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318119574 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.2318119574
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.3242475663
Short name T175
Test name
Test status
Simulation time 62871158 ps
CPU time 0.93 seconds
Started Feb 01 01:19:50 PM PST 24
Finished Feb 01 01:20:01 PM PST 24
Peak memory 204580 kb
Host smart-ea9d4e63-1741-4f21-92bd-eda6cc59d6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242475663 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
3242475663
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.4191774732
Short name T98
Test name
Test status
Simulation time 20516651 ps
CPU time 0.81 seconds
Started Feb 01 01:19:45 PM PST 24
Finished Feb 01 01:19:56 PM PST 24
Peak memory 204528 kb
Host smart-c39a882b-2436-4375-bd7e-214d31215a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191774732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
4191774732
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.2582167550
Short name T282
Test name
Test status
Simulation time 232962292 ps
CPU time 1.87 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 204312 kb
Host smart-3bff2efe-0209-461d-97bd-881a034cf0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582167550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.2582167550
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2927198585
Short name T193
Test name
Test status
Simulation time 133834518 ps
CPU time 1.36 seconds
Started Feb 01 01:19:52 PM PST 24
Finished Feb 01 01:20:04 PM PST 24
Peak memory 213320 kb
Host smart-897641ce-edc4-4a9f-8a68-2fe15cab5de9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927198585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2927198585
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.813622078
Short name T108
Test name
Test status
Simulation time 271886289 ps
CPU time 4.88 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:11 PM PST 24
Peak memory 218384 kb
Host smart-52b8f6d2-57e6-48ea-88c6-cdfbe32860b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813622078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.813622078
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2186600684
Short name T38
Test name
Test status
Simulation time 62255950 ps
CPU time 2.41 seconds
Started Feb 01 01:19:56 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 212988 kb
Host smart-a37c0004-efdc-450c-bd4c-3f62b8042953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186600684 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
2186600684
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.354392516
Short name T279
Test name
Test status
Simulation time 93644418 ps
CPU time 5.67 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:54 PM PST 24
Peak memory 204824 kb
Host smart-bd242532-30b6-48bc-b4df-eebadfce9523
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354392516 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.354392516
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.1805563587
Short name T217
Test name
Test status
Simulation time 577783829 ps
CPU time 6.16 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:56 PM PST 24
Peak memory 204744 kb
Host smart-71806b80-6392-42a2-9b90-d1a16ce48a55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805563587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.1805563587
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.973913635
Short name T210
Test name
Test status
Simulation time 27922558 ps
CPU time 1.35 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204696 kb
Host smart-27da5782-e528-4cc0-838d-660744281af0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973913635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.973913635
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2811096094
Short name T110
Test name
Test status
Simulation time 65270988 ps
CPU time 1.01 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:18:56 PM PST 24
Peak memory 204692 kb
Host smart-9bf364d6-90d3-4499-bb00-270310b38fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811096094 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2811096094
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1996196623
Short name T253
Test name
Test status
Simulation time 168665680 ps
CPU time 1.13 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:18:56 PM PST 24
Peak memory 204428 kb
Host smart-a2514971-e531-4d50-9b4f-bbc542fe9344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996196623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
996196623
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.217966763
Short name T272
Test name
Test status
Simulation time 72476422 ps
CPU time 0.75 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 204556 kb
Host smart-69f077af-3643-4e44-a431-92059a4b9128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217966763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.217966763
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3145988857
Short name T219
Test name
Test status
Simulation time 77116135 ps
CPU time 2.78 seconds
Started Feb 01 01:18:44 PM PST 24
Finished Feb 01 01:18:50 PM PST 24
Peak memory 204580 kb
Host smart-0690edb9-385a-4cfa-bb0a-d12d4993f936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145988857 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.3145988857
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.2580628447
Short name T109
Test name
Test status
Simulation time 154391305 ps
CPU time 2.1 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:52 PM PST 24
Peak memory 213308 kb
Host smart-150c6e14-13df-476a-9fae-16f2e9b3188c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580628447 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.2580628447
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1484623436
Short name T275
Test name
Test status
Simulation time 548818632 ps
CPU time 5.69 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:19:01 PM PST 24
Peak memory 213124 kb
Host smart-0c8ae58e-e118-45d0-abe2-542a098a352e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484623436 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1484623436
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.182576658
Short name T296
Test name
Test status
Simulation time 148081027 ps
CPU time 1.39 seconds
Started Feb 01 01:18:50 PM PST 24
Finished Feb 01 01:18:57 PM PST 24
Peak memory 212652 kb
Host smart-6e9e6cfd-c4b6-4f89-acdf-90f4af983e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182576658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.182576658
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.1358705490
Short name T28
Test name
Test status
Simulation time 276743475 ps
CPU time 6.08 seconds
Started Feb 01 01:18:43 PM PST 24
Finished Feb 01 01:18:52 PM PST 24
Peak memory 215264 kb
Host smart-0d0bdeef-37a1-4621-8326-f8681de2d7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358705490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.1358705490
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2177927548
Short name T239
Test name
Test status
Simulation time 9749956 ps
CPU time 0.72 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:08 PM PST 24
Peak memory 204524 kb
Host smart-a897e633-886c-449a-9427-d263e2733a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177927548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2177927548
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.1224919632
Short name T188
Test name
Test status
Simulation time 45161596 ps
CPU time 0.8 seconds
Started Feb 01 01:21:15 PM PST 24
Finished Feb 01 01:21:18 PM PST 24
Peak memory 204496 kb
Host smart-c406b343-cfb8-44ce-bf90-f570a0552dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224919632 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
1224919632
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.664356163
Short name T174
Test name
Test status
Simulation time 39588597 ps
CPU time 0.81 seconds
Started Feb 01 01:20:06 PM PST 24
Finished Feb 01 01:20:12 PM PST 24
Peak memory 204576 kb
Host smart-e2c722e5-184c-449b-801d-941488122511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664356163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.664356163
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.3595037632
Short name T251
Test name
Test status
Simulation time 10146045 ps
CPU time 0.68 seconds
Started Feb 01 01:19:59 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 204620 kb
Host smart-cb740d19-ceb4-4063-8474-f590eb693f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595037632 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
3595037632
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3173629615
Short name T199
Test name
Test status
Simulation time 46042010 ps
CPU time 0.89 seconds
Started Feb 01 01:19:58 PM PST 24
Finished Feb 01 01:20:09 PM PST 24
Peak memory 204516 kb
Host smart-a2509e47-146a-41ae-a8df-c1f0e647630f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173629615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3173629615
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.1408397232
Short name T101
Test name
Test status
Simulation time 38361440 ps
CPU time 0.69 seconds
Started Feb 01 01:20:00 PM PST 24
Finished Feb 01 01:20:10 PM PST 24
Peak memory 204540 kb
Host smart-5d75ecd1-22c0-46f2-af5e-006432598753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408397232 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
1408397232
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.1563641569
Short name T299
Test name
Test status
Simulation time 138027763 ps
CPU time 0.76 seconds
Started Feb 01 01:20:04 PM PST 24
Finished Feb 01 01:20:12 PM PST 24
Peak memory 204584 kb
Host smart-690b2ad8-3d9b-413e-bf2d-7f18e87c1b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563641569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
1563641569
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3167748628
Short name T240
Test name
Test status
Simulation time 28038603 ps
CPU time 0.71 seconds
Started Feb 01 01:20:04 PM PST 24
Finished Feb 01 01:20:12 PM PST 24
Peak memory 204548 kb
Host smart-6bfb0209-6695-4059-aee2-15015a63889f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167748628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
3167748628
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1670347113
Short name T290
Test name
Test status
Simulation time 28118863 ps
CPU time 0.73 seconds
Started Feb 01 01:23:44 PM PST 24
Finished Feb 01 01:24:09 PM PST 24
Peak memory 204600 kb
Host smart-48ef5ffe-0853-432b-992e-4396ae06d5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670347113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
1670347113
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.3654696434
Short name T242
Test name
Test status
Simulation time 12631602 ps
CPU time 0.84 seconds
Started Feb 01 01:22:20 PM PST 24
Finished Feb 01 01:22:22 PM PST 24
Peak memory 204424 kb
Host smart-cb7416b9-4e25-41f5-9bf2-6a7fb8627bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654696434 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
3654696434
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3007503114
Short name T179
Test name
Test status
Simulation time 638814085 ps
CPU time 4.88 seconds
Started Feb 01 01:18:50 PM PST 24
Finished Feb 01 01:19:00 PM PST 24
Peak memory 204440 kb
Host smart-0d6bab14-bf68-424d-aa59-696cf4985253
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007503114 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.3007503114
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.3366366465
Short name T264
Test name
Test status
Simulation time 666626441 ps
CPU time 10.27 seconds
Started Feb 01 01:18:45 PM PST 24
Finished Feb 01 01:18:59 PM PST 24
Peak memory 204712 kb
Host smart-38dbd35d-ce38-4246-9c5e-bcc69c28a2d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366366465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.3366366465
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.4084563812
Short name T209
Test name
Test status
Simulation time 34084674 ps
CPU time 1.1 seconds
Started Feb 01 01:18:47 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 204760 kb
Host smart-099b1e73-af63-4f3d-be2c-3374a23af406
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084563812 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.4084563812
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1526728500
Short name T216
Test name
Test status
Simulation time 19159272 ps
CPU time 1.34 seconds
Started Feb 01 01:18:48 PM PST 24
Finished Feb 01 01:18:54 PM PST 24
Peak memory 213032 kb
Host smart-7e37515d-f602-4cbf-89b5-99331f01df0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526728500 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1526728500
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3659634408
Short name T281
Test name
Test status
Simulation time 70577142 ps
CPU time 1.06 seconds
Started Feb 01 01:18:48 PM PST 24
Finished Feb 01 01:18:55 PM PST 24
Peak memory 204488 kb
Host smart-a3f805f0-e86c-4bbc-b77a-d305f0afc882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659634408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.3
659634408
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3769508561
Short name T73
Test name
Test status
Simulation time 42709922 ps
CPU time 0.7 seconds
Started Feb 01 01:18:44 PM PST 24
Finished Feb 01 01:18:48 PM PST 24
Peak memory 204408 kb
Host smart-520667ed-9b2c-41ad-9396-ff703b815023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769508561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
769508561
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2975483170
Short name T255
Test name
Test status
Simulation time 29977025 ps
CPU time 1.93 seconds
Started Feb 01 01:18:46 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 204876 kb
Host smart-19db7ed5-f723-4b37-b45f-c4fed956cc75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975483170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2975483170
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.2221715378
Short name T220
Test name
Test status
Simulation time 84035006 ps
CPU time 3.04 seconds
Started Feb 01 01:18:48 PM PST 24
Finished Feb 01 01:18:56 PM PST 24
Peak memory 213072 kb
Host smart-b56006a5-7167-40a8-a47c-891e16699c99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221715378 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.2221715378
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1669921011
Short name T177
Test name
Test status
Simulation time 107408613 ps
CPU time 2.61 seconds
Started Feb 01 01:18:45 PM PST 24
Finished Feb 01 01:18:51 PM PST 24
Peak memory 213232 kb
Host smart-62f781ae-ff0b-4c17-bc62-ef1a547a7539
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669921011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1669921011
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.2565625417
Short name T26
Test name
Test status
Simulation time 971982873 ps
CPU time 4.31 seconds
Started Feb 01 01:18:48 PM PST 24
Finished Feb 01 01:18:55 PM PST 24
Peak memory 216112 kb
Host smart-0c9d9633-2a42-46f5-bcc1-c636549663c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565625417 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.2
565625417
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3727917650
Short name T57
Test name
Test status
Simulation time 360575126 ps
CPU time 5.62 seconds
Started Feb 01 01:18:49 PM PST 24
Finished Feb 01 01:19:00 PM PST 24
Peak memory 212804 kb
Host smart-74ec6d82-22a3-490c-bc4c-edb0bc3075a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727917650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3727917650
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.737423429
Short name T89
Test name
Test status
Simulation time 32134333 ps
CPU time 0.7 seconds
Started Feb 01 01:22:50 PM PST 24
Finished Feb 01 01:22:52 PM PST 24
Peak memory 204540 kb
Host smart-76f90d51-8725-4c72-8868-83cd3aa91314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737423429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.737423429
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1522474140
Short name T39
Test name
Test status
Simulation time 14060028 ps
CPU time 0.85 seconds
Started Feb 01 01:23:10 PM PST 24
Finished Feb 01 01:23:22 PM PST 24
Peak memory 204656 kb
Host smart-c02147d3-f90a-4d0e-8517-1b4d386d24f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522474140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1522474140
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1983787343
Short name T176
Test name
Test status
Simulation time 7923282 ps
CPU time 0.69 seconds
Started Feb 01 01:21:01 PM PST 24
Finished Feb 01 01:21:04 PM PST 24
Peak memory 204436 kb
Host smart-89a58358-ea41-4cf9-a441-a66c21008d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983787343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1983787343
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.4133017001
Short name T187
Test name
Test status
Simulation time 42990099 ps
CPU time 0.76 seconds
Started Feb 01 01:22:53 PM PST 24
Finished Feb 01 01:23:00 PM PST 24
Peak memory 204624 kb
Host smart-b54b0f75-edcc-4c98-8084-12c329e466af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133017001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
4133017001
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3638705036
Short name T72
Test name
Test status
Simulation time 29959261 ps
CPU time 0.68 seconds
Started Feb 01 01:23:14 PM PST 24
Finished Feb 01 01:23:30 PM PST 24
Peak memory 204544 kb
Host smart-7266f176-a2b3-49f6-a444-8c76abdbc36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638705036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
3638705036
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3265860388
Short name T265
Test name
Test status
Simulation time 70841963 ps
CPU time 0.72 seconds
Started Feb 01 01:22:52 PM PST 24
Finished Feb 01 01:22:53 PM PST 24
Peak memory 204588 kb
Host smart-5ae75634-d63e-4fae-81d9-fe9ebe025fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265860388 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3265860388
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1433761243
Short name T200
Test name
Test status
Simulation time 42031355 ps
CPU time 0.69 seconds
Started Feb 01 01:23:02 PM PST 24
Finished Feb 01 01:23:09 PM PST 24
Peak memory 204604 kb
Host smart-f3c1f3cf-26ed-448e-aed2-549bf06a08ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433761243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1433761243
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.120659993
Short name T192
Test name
Test status
Simulation time 10265217 ps
CPU time 0.7 seconds
Started Feb 01 01:22:15 PM PST 24
Finished Feb 01 01:22:17 PM PST 24
Peak memory 204584 kb
Host smart-0ea5f0c5-0f1c-43eb-a3f3-9a5ecb39abd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120659993 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.120659993
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.4176626583
Short name T229
Test name
Test status
Simulation time 8945592 ps
CPU time 0.71 seconds
Started Feb 01 01:22:30 PM PST 24
Finished Feb 01 01:22:32 PM PST 24
Peak memory 204656 kb
Host smart-43703cf9-3284-45d5-bcda-f3d64bd3d508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176626583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
4176626583
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3354629672
Short name T292
Test name
Test status
Simulation time 13214567 ps
CPU time 0.71 seconds
Started Feb 01 01:23:13 PM PST 24
Finished Feb 01 01:23:29 PM PST 24
Peak memory 204440 kb
Host smart-8a44f226-5238-4f6f-85a4-ad71f74fbe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354629672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3354629672
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1683966772
Short name T309
Test name
Test status
Simulation time 452579382 ps
CPU time 2.92 seconds
Started Feb 01 01:19:08 PM PST 24
Finished Feb 01 01:19:12 PM PST 24
Peak memory 204744 kb
Host smart-b3455c9e-9599-486f-8d90-34c145755c2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683966772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1683966772
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3603159938
Short name T215
Test name
Test status
Simulation time 1193648712 ps
CPU time 5.91 seconds
Started Feb 01 01:19:02 PM PST 24
Finished Feb 01 01:19:12 PM PST 24
Peak memory 204780 kb
Host smart-766ef2c4-6e19-4fa2-8b3a-4824860d3c48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603159938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3603159938
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.2208712529
Short name T70
Test name
Test status
Simulation time 211457217 ps
CPU time 1.34 seconds
Started Feb 01 01:19:09 PM PST 24
Finished Feb 01 01:19:14 PM PST 24
Peak memory 204632 kb
Host smart-a7254712-0497-4b21-8609-bd58f2b19274
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208712529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.2208712529
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.2564367300
Short name T214
Test name
Test status
Simulation time 54228637 ps
CPU time 1.48 seconds
Started Feb 01 01:19:01 PM PST 24
Finished Feb 01 01:19:07 PM PST 24
Peak memory 213012 kb
Host smart-c4430536-b87d-4812-9e9e-ff5a1642d4c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564367300 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.2564367300
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1883256411
Short name T183
Test name
Test status
Simulation time 22930656 ps
CPU time 0.87 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:15 PM PST 24
Peak memory 204480 kb
Host smart-30ef90c6-7215-49d5-be90-6ae32f361387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883256411 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
883256411
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.2604202021
Short name T182
Test name
Test status
Simulation time 20629438 ps
CPU time 0.82 seconds
Started Feb 01 01:19:02 PM PST 24
Finished Feb 01 01:19:07 PM PST 24
Peak memory 204608 kb
Host smart-85059673-238a-4b3d-ae33-8c9be381576f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604202021 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.2
604202021
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1625169310
Short name T173
Test name
Test status
Simulation time 103107743 ps
CPU time 1.94 seconds
Started Feb 01 01:19:10 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 204728 kb
Host smart-58741906-6288-48e5-aa00-131becac24c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625169310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1625169310
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.451945872
Short name T180
Test name
Test status
Simulation time 189692985 ps
CPU time 1.84 seconds
Started Feb 01 01:19:03 PM PST 24
Finished Feb 01 01:19:08 PM PST 24
Peak memory 213280 kb
Host smart-87b56f7f-1bc1-467f-aa5d-c4a623ffa967
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451945872 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.451945872
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.909713585
Short name T195
Test name
Test status
Simulation time 129785382 ps
CPU time 4.93 seconds
Started Feb 01 01:19:10 PM PST 24
Finished Feb 01 01:19:19 PM PST 24
Peak memory 213356 kb
Host smart-1c80157b-d618-48b1-9b84-f4a0c0af0237
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909713585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.909713585
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.4012377126
Short name T30
Test name
Test status
Simulation time 33635502 ps
CPU time 1.83 seconds
Started Feb 01 01:19:08 PM PST 24
Finished Feb 01 01:19:12 PM PST 24
Peak memory 213088 kb
Host smart-6a4f0f09-1152-457a-9d86-6041f60a8e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012377126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.4
012377126
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.1658415344
Short name T231
Test name
Test status
Simulation time 12586914 ps
CPU time 0.74 seconds
Started Feb 01 01:21:05 PM PST 24
Finished Feb 01 01:21:10 PM PST 24
Peak memory 204584 kb
Host smart-503ba05e-7005-481b-9df5-4169a863a454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658415344 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
1658415344
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.919345342
Short name T104
Test name
Test status
Simulation time 25781907 ps
CPU time 0.75 seconds
Started Feb 01 01:23:36 PM PST 24
Finished Feb 01 01:23:59 PM PST 24
Peak memory 204460 kb
Host smart-3147085c-a89a-42f3-99f4-fddb8580251c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919345342 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.919345342
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2207003368
Short name T194
Test name
Test status
Simulation time 9314368 ps
CPU time 0.82 seconds
Started Feb 01 01:22:15 PM PST 24
Finished Feb 01 01:22:17 PM PST 24
Peak memory 204588 kb
Host smart-996eb15a-ef1c-4c25-9b45-d05a690d9362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207003368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2207003368
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2394424298
Short name T248
Test name
Test status
Simulation time 8505482 ps
CPU time 0.68 seconds
Started Feb 01 01:22:53 PM PST 24
Finished Feb 01 01:22:56 PM PST 24
Peak memory 204568 kb
Host smart-7f96dafb-f9ef-437f-bc3c-daa874e94874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394424298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2394424298
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3520775508
Short name T305
Test name
Test status
Simulation time 17204517 ps
CPU time 0.79 seconds
Started Feb 01 01:22:56 PM PST 24
Finished Feb 01 01:23:07 PM PST 24
Peak memory 204628 kb
Host smart-81be8565-fc89-4f91-8cae-04b5c58c939c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520775508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
3520775508
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.761551266
Short name T40
Test name
Test status
Simulation time 11916174 ps
CPU time 0.81 seconds
Started Feb 01 01:23:45 PM PST 24
Finished Feb 01 01:24:10 PM PST 24
Peak memory 204560 kb
Host smart-5756cc70-e33c-47ac-b237-6df4ec9df5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761551266 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.761551266
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.3989294614
Short name T278
Test name
Test status
Simulation time 27963654 ps
CPU time 0.7 seconds
Started Feb 01 01:22:43 PM PST 24
Finished Feb 01 01:22:44 PM PST 24
Peak memory 204472 kb
Host smart-a4f841c6-d137-4e9b-a110-5fe47bdafd09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989294614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
3989294614
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2392039974
Short name T186
Test name
Test status
Simulation time 14869071 ps
CPU time 0.69 seconds
Started Feb 01 01:23:09 PM PST 24
Finished Feb 01 01:23:18 PM PST 24
Peak memory 204480 kb
Host smart-cb4ca512-63f1-467e-a58b-f4a7b70ad54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392039974 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2392039974
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.2824275856
Short name T203
Test name
Test status
Simulation time 88965924 ps
CPU time 0.72 seconds
Started Feb 01 01:23:13 PM PST 24
Finished Feb 01 01:23:30 PM PST 24
Peak memory 204560 kb
Host smart-454ab6d9-51ed-44c5-bfc4-f10d40413934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824275856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
2824275856
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3863156983
Short name T206
Test name
Test status
Simulation time 39602650 ps
CPU time 0.8 seconds
Started Feb 01 01:22:01 PM PST 24
Finished Feb 01 01:22:03 PM PST 24
Peak memory 204572 kb
Host smart-c59e2912-e89e-4252-8163-c3481916a491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863156983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3863156983
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.893009021
Short name T65
Test name
Test status
Simulation time 28862560 ps
CPU time 1.04 seconds
Started Feb 01 01:19:08 PM PST 24
Finished Feb 01 01:19:11 PM PST 24
Peak memory 212992 kb
Host smart-2401df8a-6790-40fd-97e3-4a255600feb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893009021 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.893009021
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.809368810
Short name T260
Test name
Test status
Simulation time 121852319 ps
CPU time 1.07 seconds
Started Feb 01 01:19:09 PM PST 24
Finished Feb 01 01:19:14 PM PST 24
Peak memory 204552 kb
Host smart-bebc0bde-c253-4b57-ae88-6849ecc20ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809368810 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.809368810
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2493648130
Short name T301
Test name
Test status
Simulation time 21050273 ps
CPU time 0.82 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 204504 kb
Host smart-76554257-c528-473d-adb4-79b3acc85db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493648130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
493648130
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.1063801131
Short name T232
Test name
Test status
Simulation time 68272409 ps
CPU time 1.65 seconds
Started Feb 01 01:19:08 PM PST 24
Finished Feb 01 01:19:13 PM PST 24
Peak memory 204740 kb
Host smart-4ef64009-ad06-43ca-97b5-48c97c57bf10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063801131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.1063801131
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1301388813
Short name T274
Test name
Test status
Simulation time 52368616 ps
CPU time 1.94 seconds
Started Feb 01 01:19:07 PM PST 24
Finished Feb 01 01:19:11 PM PST 24
Peak memory 213380 kb
Host smart-4819e957-66e8-4f67-afa8-6f2d535c7f78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301388813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1301388813
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.808805867
Short name T249
Test name
Test status
Simulation time 309878269 ps
CPU time 5.7 seconds
Started Feb 01 01:19:10 PM PST 24
Finished Feb 01 01:19:19 PM PST 24
Peak memory 213384 kb
Host smart-d7802bec-3984-477d-9fbb-7446e77eef8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808805867 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.808805867
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2124474557
Short name T244
Test name
Test status
Simulation time 83713817 ps
CPU time 2.45 seconds
Started Feb 01 01:19:04 PM PST 24
Finished Feb 01 01:19:09 PM PST 24
Peak memory 212952 kb
Host smart-4fe073dd-3ed0-4dd1-a1e1-722a84a9b845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124474557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
124474557
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2875643609
Short name T308
Test name
Test status
Simulation time 201474322 ps
CPU time 0.85 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 204656 kb
Host smart-a08bc3d8-f8fd-4806-b379-fe3069f03aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875643609 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2875643609
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.4094857868
Short name T184
Test name
Test status
Simulation time 14296035 ps
CPU time 0.95 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 204504 kb
Host smart-a79f93e2-ef21-4bd1-a6fe-5f1d7ec7e166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094857868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.4
094857868
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.3946061915
Short name T207
Test name
Test status
Simulation time 47770826 ps
CPU time 0.71 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 204412 kb
Host smart-9d683c94-859b-4cc7-acb4-aae4391ca21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946061915 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.3
946061915
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.3012431275
Short name T302
Test name
Test status
Simulation time 18098594 ps
CPU time 1.4 seconds
Started Feb 01 01:19:15 PM PST 24
Finished Feb 01 01:19:23 PM PST 24
Peak memory 204644 kb
Host smart-6ae70ec2-5a4c-42a8-8192-04eca43918f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012431275 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.3012431275
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.418301462
Short name T218
Test name
Test status
Simulation time 435223728 ps
CPU time 2.23 seconds
Started Feb 01 01:19:09 PM PST 24
Finished Feb 01 01:19:14 PM PST 24
Peak memory 213192 kb
Host smart-77084b87-99e0-4251-9d22-612fb522e0c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418301462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymg
r_dpe_shadow_reg_errors.418301462
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1523249121
Short name T268
Test name
Test status
Simulation time 205862494 ps
CPU time 4.52 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:19 PM PST 24
Peak memory 213116 kb
Host smart-01a55f66-1d8e-4d36-8a01-90bc562bed74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523249121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.1523249121
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.715480616
Short name T261
Test name
Test status
Simulation time 1249289856 ps
CPU time 4.52 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:18 PM PST 24
Peak memory 215088 kb
Host smart-c9b9029b-31e3-4211-af5e-cc9fb25856d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715480616 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.715480616
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2518767224
Short name T51
Test name
Test status
Simulation time 179522585 ps
CPU time 2.65 seconds
Started Feb 01 01:19:14 PM PST 24
Finished Feb 01 01:19:23 PM PST 24
Peak memory 213196 kb
Host smart-67335241-a6f4-4a2e-b064-0bc48880ac4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518767224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2518767224
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1795891285
Short name T69
Test name
Test status
Simulation time 20221892 ps
CPU time 1.63 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:17 PM PST 24
Peak memory 221116 kb
Host smart-9b511b0e-bdff-4d95-b038-8e0d456cb2c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795891285 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1795891285
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.3723273626
Short name T235
Test name
Test status
Simulation time 22545168 ps
CPU time 0.87 seconds
Started Feb 01 01:19:14 PM PST 24
Finished Feb 01 01:19:22 PM PST 24
Peak memory 204520 kb
Host smart-f0d3598d-4e3a-4f53-b98c-760288ed57a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723273626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.3
723273626
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.3219641313
Short name T250
Test name
Test status
Simulation time 27758385 ps
CPU time 0.82 seconds
Started Feb 01 01:19:17 PM PST 24
Finished Feb 01 01:19:25 PM PST 24
Peak memory 204620 kb
Host smart-2481d229-d00d-4bff-8d7e-7b6bbfa100c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219641313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.3
219641313
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3226479265
Short name T223
Test name
Test status
Simulation time 88809867 ps
CPU time 2.23 seconds
Started Feb 01 01:19:15 PM PST 24
Finished Feb 01 01:19:24 PM PST 24
Peak memory 204632 kb
Host smart-bb5bf9a0-9c20-40ff-b25d-1f08c2ab4b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226479265 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.3226479265
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1645119796
Short name T257
Test name
Test status
Simulation time 214392663 ps
CPU time 1.65 seconds
Started Feb 01 01:19:16 PM PST 24
Finished Feb 01 01:19:25 PM PST 24
Peak memory 213612 kb
Host smart-e8bd29c4-96d3-4272-8222-be1902b50489
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645119796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1645119796
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1419005961
Short name T271
Test name
Test status
Simulation time 174026952 ps
CPU time 2.28 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:18 PM PST 24
Peak memory 213356 kb
Host smart-707d0c9f-2f5c-435d-bf3a-31e262c9a38a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419005961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1419005961
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.250674078
Short name T273
Test name
Test status
Simulation time 168068806 ps
CPU time 2.76 seconds
Started Feb 01 01:19:16 PM PST 24
Finished Feb 01 01:19:27 PM PST 24
Peak memory 212968 kb
Host smart-d0ad5b93-c981-4f8d-aa4e-ea3a405f44f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250674078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.250674078
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2501709367
Short name T246
Test name
Test status
Simulation time 112754643 ps
CPU time 1.33 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:16 PM PST 24
Peak memory 213008 kb
Host smart-61fcec94-121c-4d30-a7fe-230c3ad2f6d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501709367 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2501709367
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1424300945
Short name T234
Test name
Test status
Simulation time 63256303 ps
CPU time 0.86 seconds
Started Feb 01 01:19:16 PM PST 24
Finished Feb 01 01:19:24 PM PST 24
Peak memory 204608 kb
Host smart-ebabebc0-9dbe-49f4-aeac-7644b4f4c78f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424300945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
424300945
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.3729273043
Short name T227
Test name
Test status
Simulation time 73264738 ps
CPU time 2.71 seconds
Started Feb 01 01:19:15 PM PST 24
Finished Feb 01 01:19:25 PM PST 24
Peak memory 205044 kb
Host smart-3f614386-6b18-4901-a56a-02fbea82169a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729273043 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.3729273043
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.580738338
Short name T298
Test name
Test status
Simulation time 89463242 ps
CPU time 1.27 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:17 PM PST 24
Peak memory 213360 kb
Host smart-8ef7e5e1-783b-4be1-be52-ed8ef5139a59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580738338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.580738338
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2363755845
Short name T293
Test name
Test status
Simulation time 1816050556 ps
CPU time 6.56 seconds
Started Feb 01 01:19:12 PM PST 24
Finished Feb 01 01:19:22 PM PST 24
Peak memory 213308 kb
Host smart-e092da36-2943-44d3-8131-939f91eebc48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363755845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2363755845
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3362904969
Short name T307
Test name
Test status
Simulation time 296888206 ps
CPU time 3.71 seconds
Started Feb 01 01:19:16 PM PST 24
Finished Feb 01 01:19:27 PM PST 24
Peak memory 221176 kb
Host smart-5da7a0f2-c80f-4f54-8692-6f553e33c756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362904969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
362904969
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3335240320
Short name T19
Test name
Test status
Simulation time 213247516 ps
CPU time 2.5 seconds
Started Feb 01 01:19:13 PM PST 24
Finished Feb 01 01:19:19 PM PST 24
Peak memory 212756 kb
Host smart-f91f8a88-2f18-4fce-9749-0b50e4f61c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335240320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3335240320
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1052389449
Short name T269
Test name
Test status
Simulation time 28303261 ps
CPU time 1.38 seconds
Started Feb 01 01:19:17 PM PST 24
Finished Feb 01 01:19:26 PM PST 24
Peak memory 214616 kb
Host smart-24e0826a-2f28-4f5d-9d4b-e77bddfd6387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052389449 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1052389449
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.306091128
Short name T205
Test name
Test status
Simulation time 88923969 ps
CPU time 0.97 seconds
Started Feb 01 01:19:13 PM PST 24
Finished Feb 01 01:19:17 PM PST 24
Peak memory 204516 kb
Host smart-26c65f2c-cacd-4e63-ad0f-153f9ab981eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306091128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.306091128
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2016332358
Short name T122
Test name
Test status
Simulation time 14991277 ps
CPU time 0.7 seconds
Started Feb 01 01:19:15 PM PST 24
Finished Feb 01 01:19:23 PM PST 24
Peak memory 204524 kb
Host smart-5040e912-e45b-4e51-8d85-1ee5b4fcfdf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016332358 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
016332358
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2308441291
Short name T289
Test name
Test status
Simulation time 160620844 ps
CPU time 2 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:17 PM PST 24
Peak memory 204752 kb
Host smart-56a8f572-4d19-4ac3-ad54-a66adecb9b09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308441291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2308441291
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3789766095
Short name T43
Test name
Test status
Simulation time 103013222 ps
CPU time 1.81 seconds
Started Feb 01 01:19:13 PM PST 24
Finished Feb 01 01:19:18 PM PST 24
Peak memory 213300 kb
Host smart-d0522c15-cffa-453c-b1d6-d7f919a2f6bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789766095 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.3789766095
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.977624648
Short name T267
Test name
Test status
Simulation time 253510574 ps
CPU time 5.96 seconds
Started Feb 01 01:19:14 PM PST 24
Finished Feb 01 01:19:24 PM PST 24
Peak memory 213144 kb
Host smart-8eefa928-053d-44ca-a150-3b59d9f6ab1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977624648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.977624648
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3905845357
Short name T45
Test name
Test status
Simulation time 709099155 ps
CPU time 2.98 seconds
Started Feb 01 01:19:11 PM PST 24
Finished Feb 01 01:19:17 PM PST 24
Peak memory 212956 kb
Host smart-0efce728-2b61-4de7-9666-5f46c918b8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905845357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
905845357
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1096163554
Short name T53
Test name
Test status
Simulation time 703290521 ps
CPU time 4.47 seconds
Started Feb 01 01:19:14 PM PST 24
Finished Feb 01 01:19:25 PM PST 24
Peak memory 212964 kb
Host smart-e800bafe-2991-46bd-88a6-34a8381dd512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096163554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1096163554
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.747207049
Short name T133
Test name
Test status
Simulation time 86895490 ps
CPU time 0.72 seconds
Started Feb 01 01:38:27 PM PST 24
Finished Feb 01 01:38:44 PM PST 24
Peak memory 204708 kb
Host smart-fb86cbc8-339d-4ff1-be56-843ffd9de675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747207049 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.747207049
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.30561353
Short name T6
Test name
Test status
Simulation time 1022316934 ps
CPU time 14.69 seconds
Started Feb 01 01:38:30 PM PST 24
Finished Feb 01 01:39:03 PM PST 24
Peak memory 231048 kb
Host smart-0ce93d1a-dfe1-4745-b837-43c4855f7f3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30561353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.30561353
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.4138806326
Short name T153
Test name
Test status
Simulation time 12197991 ps
CPU time 0.93 seconds
Started Feb 01 01:38:28 PM PST 24
Finished Feb 01 01:38:45 PM PST 24
Peak memory 204836 kb
Host smart-9d0986c1-e36b-4a1a-936e-d61c73783905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138806326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.4
138806326
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.4186509579
Short name T132
Test name
Test status
Simulation time 70142688 ps
CPU time 0.81 seconds
Started Feb 01 01:39:00 PM PST 24
Finished Feb 01 01:39:16 PM PST 24
Peak memory 204612 kb
Host smart-4be3ff86-4712-4d1d-bc66-159d5f9fb5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186509579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
4186509579
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2202904714
Short name T16
Test name
Test status
Simulation time 18979410 ps
CPU time 0.81 seconds
Started Feb 01 01:38:59 PM PST 24
Finished Feb 01 01:39:16 PM PST 24
Peak memory 204736 kb
Host smart-871ad478-eab0-4627-9c1d-d84363850ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202904714 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2202904714
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.3689743132
Short name T84
Test name
Test status
Simulation time 1041134789 ps
CPU time 17.57 seconds
Started Feb 01 01:38:58 PM PST 24
Finished Feb 01 01:39:31 PM PST 24
Peak memory 207304 kb
Host smart-a1242d21-6b1f-4ec5-ae23-1441b58e814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689743132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.3689743132
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1506937921
Short name T127
Test name
Test status
Simulation time 136269391 ps
CPU time 0.78 seconds
Started Feb 01 01:39:04 PM PST 24
Finished Feb 01 01:39:23 PM PST 24
Peak memory 204732 kb
Host smart-5738eb41-27fa-45f7-841b-88bdb107a272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506937921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1506937921
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.3679716224
Short name T24
Test name
Test status
Simulation time 42521471 ps
CPU time 0.89 seconds
Started Feb 01 01:39:01 PM PST 24
Finished Feb 01 01:39:18 PM PST 24
Peak memory 204796 kb
Host smart-00daddaa-9c3f-46f2-bc5d-a9d26612350a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679716224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
3679716224
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3011262116
Short name T9
Test name
Test status
Simulation time 12668583655 ps
CPU time 55.46 seconds
Started Feb 01 01:39:03 PM PST 24
Finished Feb 01 01:40:15 PM PST 24
Peak memory 221424 kb
Host smart-22e6bc27-42f8-4fb4-af08-ce848163dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011262116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3011262116
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.354764525
Short name T144
Test name
Test status
Simulation time 17834274 ps
CPU time 0.82 seconds
Started Feb 01 01:39:02 PM PST 24
Finished Feb 01 01:39:19 PM PST 24
Peak memory 204784 kb
Host smart-31fbd1a8-72ec-466f-ad1e-17f61c0e18d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354764525 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.354764525
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.636779587
Short name T150
Test name
Test status
Simulation time 2058444570 ps
CPU time 38.4 seconds
Started Feb 01 01:39:06 PM PST 24
Finished Feb 01 01:40:04 PM PST 24
Peak memory 207760 kb
Host smart-b667b6b9-d30e-404c-b391-a3d1da0509ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636779587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.636779587
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.4198132422
Short name T129
Test name
Test status
Simulation time 17179328 ps
CPU time 0.71 seconds
Started Feb 01 01:39:04 PM PST 24
Finished Feb 01 01:39:23 PM PST 24
Peak memory 204720 kb
Host smart-9cef764f-457d-4592-b820-b9209ad02463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198132422 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
4198132422
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1825767175
Short name T128
Test name
Test status
Simulation time 45788216 ps
CPU time 0.96 seconds
Started Feb 01 01:39:08 PM PST 24
Finished Feb 01 01:39:30 PM PST 24
Peak memory 204952 kb
Host smart-4d66d341-74c7-45bd-a916-0ea29bceddcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825767175 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1825767175
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.4289501196
Short name T140
Test name
Test status
Simulation time 37909359 ps
CPU time 0.79 seconds
Started Feb 01 01:39:08 PM PST 24
Finished Feb 01 01:39:29 PM PST 24
Peak memory 204828 kb
Host smart-33a26849-dc40-4abb-b1c8-f6ebcd80cea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289501196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
4289501196
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3213076669
Short name T79
Test name
Test status
Simulation time 5781303122 ps
CPU time 94.96 seconds
Started Feb 01 01:39:06 PM PST 24
Finished Feb 01 01:41:00 PM PST 24
Peak memory 207012 kb
Host smart-64cfc267-4c9d-4640-9512-885f6fee83e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213076669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3213076669
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2728524873
Short name T166
Test name
Test status
Simulation time 35904064 ps
CPU time 0.81 seconds
Started Feb 01 01:39:10 PM PST 24
Finished Feb 01 01:39:33 PM PST 24
Peak memory 204648 kb
Host smart-b8666f24-e4d4-4667-8860-2fdc479847f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728524873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2728524873
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.1665894389
Short name T136
Test name
Test status
Simulation time 234229817 ps
CPU time 1.08 seconds
Started Feb 01 01:39:21 PM PST 24
Finished Feb 01 01:39:47 PM PST 24
Peak memory 204868 kb
Host smart-1fd49f19-0817-4a13-b710-9323bedd7c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665894389 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
1665894389
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.1391588374
Short name T165
Test name
Test status
Simulation time 5281309123 ps
CPU time 17.25 seconds
Started Feb 01 01:39:11 PM PST 24
Finished Feb 01 01:39:50 PM PST 24
Peak memory 205592 kb
Host smart-3c8f40c4-0326-4a8b-a6b8-d699ff7a1479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391588374 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.1391588374
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.898744908
Short name T145
Test name
Test status
Simulation time 47358118 ps
CPU time 0.79 seconds
Started Feb 01 01:38:42 PM PST 24
Finished Feb 01 01:38:59 PM PST 24
Peak memory 204624 kb
Host smart-6c811288-d009-4dfb-bf7e-4fa379270b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898744908 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.898744908
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.322401368
Short name T11
Test name
Test status
Simulation time 676385565 ps
CPU time 20.88 seconds
Started Feb 01 01:38:27 PM PST 24
Finished Feb 01 01:39:04 PM PST 24
Peak memory 206668 kb
Host smart-28e72832-49ce-4b24-89b4-4fec20cfd073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322401368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.322401368
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3109877858
Short name T137
Test name
Test status
Simulation time 40054465 ps
CPU time 0.81 seconds
Started Feb 01 01:39:12 PM PST 24
Finished Feb 01 01:39:36 PM PST 24
Peak memory 204736 kb
Host smart-5ae2f8a0-d43a-469c-8fee-f845619c1738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109877858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3109877858
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.560218845
Short name T170
Test name
Test status
Simulation time 13319479 ps
CPU time 0.76 seconds
Started Feb 01 01:39:14 PM PST 24
Finished Feb 01 01:39:38 PM PST 24
Peak memory 204724 kb
Host smart-7fbf0157-962d-4d69-b9ec-19911320cb73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560218845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.560218845
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.2585434298
Short name T80
Test name
Test status
Simulation time 1639427591 ps
CPU time 29.59 seconds
Started Feb 01 01:39:20 PM PST 24
Finished Feb 01 01:40:15 PM PST 24
Peak memory 206612 kb
Host smart-30bc27dd-9e6a-4f3b-b57c-4c59cfce2acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585434298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.2585434298
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.905526957
Short name T81
Test name
Test status
Simulation time 29446167 ps
CPU time 0.78 seconds
Started Feb 01 01:39:17 PM PST 24
Finished Feb 01 01:39:43 PM PST 24
Peak memory 204696 kb
Host smart-9576dc12-5112-4b7f-866e-d79b6540e77d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905526957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.905526957
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3037904515
Short name T25
Test name
Test status
Simulation time 93294644 ps
CPU time 0.73 seconds
Started Feb 01 01:39:22 PM PST 24
Finished Feb 01 01:39:48 PM PST 24
Peak memory 204720 kb
Host smart-a6484d4e-8a3f-4638-b720-e6fe40867bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037904515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3037904515
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.2927766483
Short name T172
Test name
Test status
Simulation time 57926750 ps
CPU time 0.77 seconds
Started Feb 01 01:39:22 PM PST 24
Finished Feb 01 01:39:48 PM PST 24
Peak memory 204816 kb
Host smart-b6dde71d-854d-4f84-bfb1-a924b34036d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927766483 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
2927766483
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1731274346
Short name T163
Test name
Test status
Simulation time 50154325 ps
CPU time 0.76 seconds
Started Feb 01 01:39:18 PM PST 24
Finished Feb 01 01:39:44 PM PST 24
Peak memory 204772 kb
Host smart-f3f523d1-cfbe-49d0-b875-26e51002ab89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731274346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1731274346
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2903346848
Short name T151
Test name
Test status
Simulation time 63646768 ps
CPU time 0.74 seconds
Started Feb 01 01:39:13 PM PST 24
Finished Feb 01 01:39:37 PM PST 24
Peak memory 204776 kb
Host smart-c7f1fba9-9ee7-43f5-ab98-d1968bae5ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903346848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2903346848
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.3444470951
Short name T119
Test name
Test status
Simulation time 469514661 ps
CPU time 15.81 seconds
Started Feb 01 01:39:19 PM PST 24
Finished Feb 01 01:40:00 PM PST 24
Peak memory 205624 kb
Host smart-cb976dcc-2ca9-4476-90d5-14e39f7dc5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444470951 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.3444470951
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.963799965
Short name T37
Test name
Test status
Simulation time 610471480 ps
CPU time 20.64 seconds
Started Feb 01 01:39:21 PM PST 24
Finished Feb 01 01:40:06 PM PST 24
Peak memory 213988 kb
Host smart-395dd8d7-7545-4cc8-a3c1-b92f4596c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963799965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.963799965
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.1183707160
Short name T147
Test name
Test status
Simulation time 44025029 ps
CPU time 1.05 seconds
Started Feb 01 01:39:17 PM PST 24
Finished Feb 01 01:39:44 PM PST 24
Peak memory 205004 kb
Host smart-0df7e0fa-24f0-49ec-9a61-5e3548aa5eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183707160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
1183707160
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.4033385568
Short name T171
Test name
Test status
Simulation time 887163845 ps
CPU time 18.45 seconds
Started Feb 01 01:39:21 PM PST 24
Finished Feb 01 01:40:04 PM PST 24
Peak memory 207808 kb
Host smart-66d30c43-8d5e-409c-8a06-4fea4924a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033385568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.4033385568
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.3996830626
Short name T34
Test name
Test status
Simulation time 64846420 ps
CPU time 0.77 seconds
Started Feb 01 01:39:13 PM PST 24
Finished Feb 01 01:39:38 PM PST 24
Peak memory 204672 kb
Host smart-ea2c6f53-c9ab-4b74-a8f4-56d6e7ac65c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996830626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
3996830626
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3894863445
Short name T112
Test name
Test status
Simulation time 1368100527 ps
CPU time 17.61 seconds
Started Feb 01 01:39:21 PM PST 24
Finished Feb 01 01:40:03 PM PST 24
Peak memory 205696 kb
Host smart-34d05c0a-22db-44f5-aae6-2e3e34425050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894863445 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3894863445
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.3239711405
Short name T169
Test name
Test status
Simulation time 21299307 ps
CPU time 0.78 seconds
Started Feb 01 01:38:55 PM PST 24
Finished Feb 01 01:39:09 PM PST 24
Peak memory 204720 kb
Host smart-2e5ff29a-acea-40f3-aa08-a01635544d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239711405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.3
239711405
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.1002364911
Short name T8
Test name
Test status
Simulation time 1768295836 ps
CPU time 17.41 seconds
Started Feb 01 01:38:45 PM PST 24
Finished Feb 01 01:39:17 PM PST 24
Peak memory 231452 kb
Host smart-554606ce-80cf-4b37-a96e-a202fe93f75f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002364911 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.1002364911
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1139729526
Short name T97
Test name
Test status
Simulation time 290644498 ps
CPU time 9.08 seconds
Started Feb 01 01:38:46 PM PST 24
Finished Feb 01 01:39:09 PM PST 24
Peak memory 207600 kb
Host smart-b1341719-d678-484e-96e0-e72d6b9acf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139729526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1139729526
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3480071144
Short name T35
Test name
Test status
Simulation time 68633312 ps
CPU time 0.92 seconds
Started Feb 01 01:39:23 PM PST 24
Finished Feb 01 01:39:49 PM PST 24
Peak memory 204872 kb
Host smart-5b7fdc77-e502-4ec1-ab93-0687aa53f27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480071144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3480071144
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.2877770949
Short name T77
Test name
Test status
Simulation time 12222921 ps
CPU time 0.9 seconds
Started Feb 01 01:39:19 PM PST 24
Finished Feb 01 01:39:45 PM PST 24
Peak memory 204704 kb
Host smart-f3247ef3-9318-4242-afc0-85a2c67f57d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877770949 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
2877770949
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.2881393179
Short name T111
Test name
Test status
Simulation time 893637526 ps
CPU time 25.4 seconds
Started Feb 01 01:39:21 PM PST 24
Finished Feb 01 01:40:11 PM PST 24
Peak memory 207188 kb
Host smart-a147bf39-5fbf-4f3d-a09e-c62737653dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881393179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.2881393179
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3190919140
Short name T143
Test name
Test status
Simulation time 61881905 ps
CPU time 0.82 seconds
Started Feb 01 01:39:22 PM PST 24
Finished Feb 01 01:39:48 PM PST 24
Peak memory 204788 kb
Host smart-bc86b1e1-fe31-4d8d-abcb-4f4dd27a08d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190919140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3190919140
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.2045252204
Short name T75
Test name
Test status
Simulation time 648695484 ps
CPU time 21.33 seconds
Started Feb 01 01:39:16 PM PST 24
Finished Feb 01 01:40:02 PM PST 24
Peak memory 207840 kb
Host smart-8d3af799-b48c-40bb-9d5c-217eb282c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045252204 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.2045252204
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.2232840366
Short name T156
Test name
Test status
Simulation time 32314627 ps
CPU time 0.75 seconds
Started Feb 01 01:39:24 PM PST 24
Finished Feb 01 01:39:50 PM PST 24
Peak memory 204816 kb
Host smart-28c8ab5d-8073-44e8-8264-cd555a51a6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232840366 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
2232840366
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.1513807288
Short name T15
Test name
Test status
Simulation time 11372989848 ps
CPU time 86.18 seconds
Started Feb 01 01:39:26 PM PST 24
Finished Feb 01 01:41:18 PM PST 24
Peak memory 207500 kb
Host smart-95d5eff3-765c-4ae2-b8ec-965140dfdfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513807288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.1513807288
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.1979583479
Short name T148
Test name
Test status
Simulation time 12446639 ps
CPU time 0.89 seconds
Started Feb 01 01:39:25 PM PST 24
Finished Feb 01 01:39:50 PM PST 24
Peak memory 204808 kb
Host smart-0bc97670-7578-469a-8103-63e232fd6b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979583479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
1979583479
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3572915536
Short name T154
Test name
Test status
Simulation time 10815440172 ps
CPU time 88.09 seconds
Started Feb 01 01:39:28 PM PST 24
Finished Feb 01 01:41:22 PM PST 24
Peak memory 221236 kb
Host smart-b1760504-bdd3-45e1-99ff-2561932dffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572915536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3572915536
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.3672129647
Short name T149
Test name
Test status
Simulation time 105400406 ps
CPU time 1.04 seconds
Started Feb 01 01:39:22 PM PST 24
Finished Feb 01 01:39:48 PM PST 24
Peak memory 204972 kb
Host smart-adfc1869-cf23-4b6a-af01-32074a01b0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672129647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
3672129647
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.1556145200
Short name T118
Test name
Test status
Simulation time 699827351 ps
CPU time 21.98 seconds
Started Feb 01 01:39:24 PM PST 24
Finished Feb 01 01:40:10 PM PST 24
Peak memory 207524 kb
Host smart-a0a860c5-be74-4db0-b006-944b2943fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556145200 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.1556145200
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.20318453
Short name T130
Test name
Test status
Simulation time 46934877 ps
CPU time 0.85 seconds
Started Feb 01 01:43:53 PM PST 24
Finished Feb 01 01:44:20 PM PST 24
Peak memory 204740 kb
Host smart-728b4951-c5df-4cee-ad03-1ea8341190dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.20318453
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.4133444338
Short name T93
Test name
Test status
Simulation time 458507838 ps
CPU time 15.99 seconds
Started Feb 01 01:39:24 PM PST 24
Finished Feb 01 01:40:05 PM PST 24
Peak memory 207076 kb
Host smart-72d65220-313e-4819-96b6-01a237406a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133444338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.4133444338
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.2505387863
Short name T134
Test name
Test status
Simulation time 18215156 ps
CPU time 0.81 seconds
Started Feb 01 01:39:22 PM PST 24
Finished Feb 01 01:39:48 PM PST 24
Peak memory 204768 kb
Host smart-34e29569-65c3-42df-afb4-368e0bbe03fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505387863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
2505387863
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2530675845
Short name T142
Test name
Test status
Simulation time 6067579375 ps
CPU time 90.96 seconds
Started Feb 01 02:20:06 PM PST 24
Finished Feb 01 02:21:55 PM PST 24
Peak memory 221440 kb
Host smart-e7780de1-537d-497d-9a22-7676ce7ba5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530675845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2530675845
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.4097939067
Short name T159
Test name
Test status
Simulation time 10196473 ps
CPU time 0.84 seconds
Started Feb 01 01:39:26 PM PST 24
Finished Feb 01 01:39:53 PM PST 24
Peak memory 204724 kb
Host smart-e465788e-6b67-4927-ac0d-86e1f4449b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097939067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
4097939067
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.207343477
Short name T126
Test name
Test status
Simulation time 32496749 ps
CPU time 0.74 seconds
Started Feb 01 01:39:24 PM PST 24
Finished Feb 01 01:39:49 PM PST 24
Peak memory 204648 kb
Host smart-7940c0b9-8c1f-4d1e-9da2-3c9fdb2d8e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207343477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.207343477
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.1762020847
Short name T168
Test name
Test status
Simulation time 2748338380 ps
CPU time 18.45 seconds
Started Feb 01 01:39:28 PM PST 24
Finished Feb 01 01:40:13 PM PST 24
Peak memory 207656 kb
Host smart-d0701f91-d2f5-46c7-abc5-c6b83954f43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762020847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.1762020847
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.3678032983
Short name T131
Test name
Test status
Simulation time 12363668 ps
CPU time 0.87 seconds
Started Feb 01 01:38:42 PM PST 24
Finished Feb 01 01:39:00 PM PST 24
Peak memory 204684 kb
Host smart-7706a4bf-51c1-41c8-9fe0-81d9eda178b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678032983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.3
678032983
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.2004457847
Short name T7
Test name
Test status
Simulation time 1595938237 ps
CPU time 9.7 seconds
Started Feb 01 01:38:44 PM PST 24
Finished Feb 01 01:39:09 PM PST 24
Peak memory 229752 kb
Host smart-2b4e2711-ca80-44a2-a990-b28090cf7101
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004457847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2004457847
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.2531998654
Short name T33
Test name
Test status
Simulation time 804429793 ps
CPU time 19.09 seconds
Started Feb 01 01:38:47 PM PST 24
Finished Feb 01 01:39:20 PM PST 24
Peak memory 207320 kb
Host smart-0fb6aa32-fae3-461f-848e-2a1bc6613683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531998654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.2531998654
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.3462005689
Short name T135
Test name
Test status
Simulation time 14188768 ps
CPU time 0.76 seconds
Started Feb 01 02:26:07 PM PST 24
Finished Feb 01 02:26:23 PM PST 24
Peak memory 204712 kb
Host smart-aeee22f7-95ed-4ba7-be01-55a47102d6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462005689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
3462005689
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.1083177298
Short name T146
Test name
Test status
Simulation time 16189787 ps
CPU time 0.8 seconds
Started Feb 01 01:55:07 PM PST 24
Finished Feb 01 01:55:29 PM PST 24
Peak memory 204740 kb
Host smart-634a5ad4-0aa7-4db3-b09e-8432cfc18095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083177298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
1083177298
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1908336889
Short name T78
Test name
Test status
Simulation time 11838311418 ps
CPU time 20.59 seconds
Started Feb 01 01:39:27 PM PST 24
Finished Feb 01 01:40:13 PM PST 24
Peak memory 205648 kb
Host smart-82b5ea19-e04c-452d-8e55-754ddd794218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908336889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1908336889
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.259054258
Short name T2
Test name
Test status
Simulation time 43944568 ps
CPU time 0.93 seconds
Started Feb 01 01:39:32 PM PST 24
Finished Feb 01 01:39:59 PM PST 24
Peak memory 204692 kb
Host smart-66347ef1-ecfa-44cc-ab77-06817592b3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259054258 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.259054258
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.494092479
Short name T123
Test name
Test status
Simulation time 45814333 ps
CPU time 0.88 seconds
Started Feb 01 01:39:33 PM PST 24
Finished Feb 01 01:39:59 PM PST 24
Peak memory 204780 kb
Host smart-4763cf95-07fd-4441-817f-f73c9bc58b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494092479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.494092479
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.3051639605
Short name T5
Test name
Test status
Simulation time 2893766127 ps
CPU time 17.96 seconds
Started Feb 01 01:39:32 PM PST 24
Finished Feb 01 01:40:16 PM PST 24
Peak memory 207156 kb
Host smart-b36aef89-4a9d-46a9-92e7-1bbffe00b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051639605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.3051639605
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2647161682
Short name T139
Test name
Test status
Simulation time 80000112 ps
CPU time 0.79 seconds
Started Feb 01 01:39:30 PM PST 24
Finished Feb 01 01:39:57 PM PST 24
Peak memory 204816 kb
Host smart-3743062a-2508-4339-8047-19e9c947abd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647161682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2647161682
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2809885804
Short name T92
Test name
Test status
Simulation time 439974043 ps
CPU time 12.11 seconds
Started Feb 01 01:39:34 PM PST 24
Finished Feb 01 01:40:12 PM PST 24
Peak memory 205820 kb
Host smart-5c03217a-7dda-4a32-8b61-f003b9fe60af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809885804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2809885804
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.198016382
Short name T158
Test name
Test status
Simulation time 45138976 ps
CPU time 0.75 seconds
Started Feb 01 01:39:33 PM PST 24
Finished Feb 01 01:39:59 PM PST 24
Peak memory 204792 kb
Host smart-378ba832-f1b3-46b3-8ae2-6fb40ddecce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198016382 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.198016382
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.293172758
Short name T157
Test name
Test status
Simulation time 1957545435 ps
CPU time 16.39 seconds
Started Feb 01 01:39:33 PM PST 24
Finished Feb 01 01:40:15 PM PST 24
Peak memory 207460 kb
Host smart-07203b5f-3034-4160-a550-fd5fe30f63ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293172758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.293172758
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3923386538
Short name T138
Test name
Test status
Simulation time 12970074 ps
CPU time 0.78 seconds
Started Feb 01 01:39:36 PM PST 24
Finished Feb 01 01:40:02 PM PST 24
Peak memory 204688 kb
Host smart-9c8d5bf0-d139-401b-a31b-bc22200821f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923386538 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3923386538
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.2691433231
Short name T162
Test name
Test status
Simulation time 642957027 ps
CPU time 10.72 seconds
Started Feb 01 01:39:39 PM PST 24
Finished Feb 01 01:40:13 PM PST 24
Peak memory 207732 kb
Host smart-f6be33d5-7a6c-4627-bb58-9e19aa32abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691433231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.2691433231
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.269460415
Short name T155
Test name
Test status
Simulation time 10745905 ps
CPU time 0.7 seconds
Started Feb 01 01:39:40 PM PST 24
Finished Feb 01 01:40:04 PM PST 24
Peak memory 204736 kb
Host smart-db0dc1f5-c5ab-44f4-bafe-74c5f1eb18ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269460415 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.269460415
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.1245329398
Short name T120
Test name
Test status
Simulation time 133247095 ps
CPU time 8.19 seconds
Started Feb 01 01:39:40 PM PST 24
Finished Feb 01 01:40:11 PM PST 24
Peak memory 207072 kb
Host smart-bd78b7e6-e1ba-467b-a3db-9c64509b2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245329398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.1245329398
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.4107417595
Short name T167
Test name
Test status
Simulation time 19887942 ps
CPU time 0.83 seconds
Started Feb 01 01:39:43 PM PST 24
Finished Feb 01 01:40:08 PM PST 24
Peak memory 204704 kb
Host smart-4c7a04ba-d88c-4e66-83ed-5d270f2ac889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107417595 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
4107417595
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.3884506187
Short name T160
Test name
Test status
Simulation time 2044222230 ps
CPU time 20.07 seconds
Started Feb 01 01:39:38 PM PST 24
Finished Feb 01 01:40:22 PM PST 24
Peak memory 205536 kb
Host smart-87c0aa3f-f0cd-4bca-9615-64daeaec09a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884506187 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.3884506187
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.3633395892
Short name T36
Test name
Test status
Simulation time 228971857 ps
CPU time 0.84 seconds
Started Feb 01 01:39:46 PM PST 24
Finished Feb 01 01:40:12 PM PST 24
Peak memory 204812 kb
Host smart-3d329e8b-2995-4712-96e5-6fec9bba5267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633395892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
3633395892
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.1371079892
Short name T18
Test name
Test status
Simulation time 161596726 ps
CPU time 0.74 seconds
Started Feb 01 01:38:46 PM PST 24
Finished Feb 01 01:39:01 PM PST 24
Peak memory 204776 kb
Host smart-6c30d12a-882a-4638-8b89-92561013757e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371079892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.1
371079892
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3605032514
Short name T152
Test name
Test status
Simulation time 2193041798 ps
CPU time 19.24 seconds
Started Feb 01 01:38:41 PM PST 24
Finished Feb 01 01:39:18 PM PST 24
Peak memory 205740 kb
Host smart-5a6e168d-9338-414b-8ba0-c85beccd14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605032514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3605032514
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3034265255
Short name T1
Test name
Test status
Simulation time 24175051 ps
CPU time 0.77 seconds
Started Feb 01 01:38:43 PM PST 24
Finished Feb 01 01:39:00 PM PST 24
Peak memory 204760 kb
Host smart-33af9799-bc4b-4f2c-8b11-f697253e428d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034265255 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
034265255
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.2475088296
Short name T117
Test name
Test status
Simulation time 6571417915 ps
CPU time 30.55 seconds
Started Feb 01 01:38:44 PM PST 24
Finished Feb 01 01:39:30 PM PST 24
Peak memory 206480 kb
Host smart-ea8cb6b3-4a58-4780-aa71-c427f81604f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475088296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.2475088296
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.2443369443
Short name T141
Test name
Test status
Simulation time 31132197 ps
CPU time 0.81 seconds
Started Feb 01 01:38:54 PM PST 24
Finished Feb 01 01:39:08 PM PST 24
Peak memory 204716 kb
Host smart-c180f6c5-31a5-4808-a8c1-e57ef118ac5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443369443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.2
443369443
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.912446137
Short name T96
Test name
Test status
Simulation time 4238790677 ps
CPU time 37.45 seconds
Started Feb 01 01:38:43 PM PST 24
Finished Feb 01 01:39:37 PM PST 24
Peak memory 207100 kb
Host smart-f543f4dc-56ce-4469-a776-b8e4f5e210a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912446137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.912446137
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.105562721
Short name T17
Test name
Test status
Simulation time 19080560 ps
CPU time 0.78 seconds
Started Feb 01 01:38:56 PM PST 24
Finished Feb 01 01:39:09 PM PST 24
Peak memory 204824 kb
Host smart-7225ca88-2128-47a6-aa4a-61d0454a40e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105562721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.105562721
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2589424670
Short name T164
Test name
Test status
Simulation time 392898749 ps
CPU time 14.54 seconds
Started Feb 01 01:38:56 PM PST 24
Finished Feb 01 01:39:23 PM PST 24
Peak memory 206972 kb
Host smart-12bb1a52-a05a-421e-aacd-ba4d01ddba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589424670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2589424670
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1553682287
Short name T161
Test name
Test status
Simulation time 19657814 ps
CPU time 1.01 seconds
Started Feb 01 01:39:01 PM PST 24
Finished Feb 01 01:39:18 PM PST 24
Peak memory 204952 kb
Host smart-90f2da1a-2476-4e6a-9946-5250f841d010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553682287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
553682287
Directory /workspace/9.keymgr_dpe_alert_test/latest
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