Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.70 90.62 57.52 76.92 94.94 98.34 17.75


Total test records in report: 307
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2362424940 Feb 05 03:25:03 PM PST 24 Feb 05 03:25:06 PM PST 24 20713731 ps
T258 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.699290169 Feb 05 03:25:05 PM PST 24 Feb 05 03:25:11 PM PST 24 43770553 ps
T259 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1840511542 Feb 05 03:24:25 PM PST 24 Feb 05 03:24:29 PM PST 24 139909263 ps
T260 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.1292207928 Feb 05 03:25:12 PM PST 24 Feb 05 03:25:22 PM PST 24 48864178 ps
T261 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1395572602 Feb 05 03:24:20 PM PST 24 Feb 05 03:24:29 PM PST 24 865856345 ps
T262 /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.178075067 Feb 05 03:24:52 PM PST 24 Feb 05 03:24:54 PM PST 24 31602550 ps
T65 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.2656299715 Feb 05 03:24:51 PM PST 24 Feb 05 03:24:55 PM PST 24 52226364 ps
T263 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1854892174 Feb 05 03:25:05 PM PST 24 Feb 05 03:25:17 PM PST 24 1067111121 ps
T264 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1903015771 Feb 05 03:25:11 PM PST 24 Feb 05 03:25:21 PM PST 24 249141750 ps
T265 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.40383846 Feb 05 03:24:19 PM PST 24 Feb 05 03:24:25 PM PST 24 908324602 ps
T266 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3366501562 Feb 05 03:25:12 PM PST 24 Feb 05 03:25:22 PM PST 24 775476316 ps
T267 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2934501709 Feb 05 03:24:13 PM PST 24 Feb 05 03:24:16 PM PST 24 106001275 ps
T268 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.4273932045 Feb 05 03:24:44 PM PST 24 Feb 05 03:24:51 PM PST 24 466686289 ps
T59 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3556148663 Feb 05 03:25:20 PM PST 24 Feb 05 03:25:28 PM PST 24 116952995 ps
T269 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2425383688 Feb 05 03:24:31 PM PST 24 Feb 05 03:24:38 PM PST 24 121506655 ps
T270 /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.989360722 Feb 05 03:25:28 PM PST 24 Feb 05 03:25:31 PM PST 24 13970652 ps
T271 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1027186715 Feb 05 03:24:47 PM PST 24 Feb 05 03:24:53 PM PST 24 199393866 ps
T272 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.953439504 Feb 05 03:24:17 PM PST 24 Feb 05 03:24:19 PM PST 24 37104990 ps
T273 /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2895029877 Feb 05 03:24:23 PM PST 24 Feb 05 03:24:26 PM PST 24 127959502 ps
T274 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1694799737 Feb 05 03:25:30 PM PST 24 Feb 05 03:25:33 PM PST 24 18582021 ps
T275 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1877745624 Feb 05 03:25:33 PM PST 24 Feb 05 03:25:37 PM PST 24 534792051 ps
T276 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.3203008529 Feb 05 03:24:56 PM PST 24 Feb 05 03:24:59 PM PST 24 92923696 ps
T277 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.3258956513 Feb 05 03:25:31 PM PST 24 Feb 05 03:25:34 PM PST 24 39683449 ps
T278 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.404065353 Feb 05 03:24:40 PM PST 24 Feb 05 03:24:44 PM PST 24 317904289 ps
T279 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4246264194 Feb 05 03:24:22 PM PST 24 Feb 05 03:24:31 PM PST 24 270684587 ps
T280 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.439759892 Feb 05 03:24:43 PM PST 24 Feb 05 03:24:47 PM PST 24 57833217 ps
T281 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.52799495 Feb 05 03:25:26 PM PST 24 Feb 05 03:25:30 PM PST 24 36332308 ps
T282 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.3078851512 Feb 05 03:25:00 PM PST 24 Feb 05 03:25:02 PM PST 24 15869328 ps
T283 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.1081315703 Feb 05 03:24:47 PM PST 24 Feb 05 03:24:51 PM PST 24 42199651 ps
T284 /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2027989982 Feb 05 03:25:15 PM PST 24 Feb 05 03:25:23 PM PST 24 92607191 ps
T285 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3368464659 Feb 05 03:25:23 PM PST 24 Feb 05 03:25:28 PM PST 24 144205902 ps
T63 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2931506337 Feb 05 03:24:56 PM PST 24 Feb 05 03:25:00 PM PST 24 368548106 ps
T286 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.2968617018 Feb 05 03:25:10 PM PST 24 Feb 05 03:25:14 PM PST 24 64739069 ps
T287 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.812911985 Feb 05 03:24:44 PM PST 24 Feb 05 03:24:50 PM PST 24 125528851 ps
T288 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3262858147 Feb 05 03:24:48 PM PST 24 Feb 05 03:25:07 PM PST 24 1331661469 ps
T61 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2821325367 Feb 05 03:24:39 PM PST 24 Feb 05 03:24:43 PM PST 24 101805766 ps
T66 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.4188127356 Feb 05 03:25:22 PM PST 24 Feb 05 03:25:34 PM PST 24 1341620947 ps
T289 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.176254406 Feb 05 03:25:27 PM PST 24 Feb 05 03:25:30 PM PST 24 28324887 ps
T290 /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3981743775 Feb 05 03:25:22 PM PST 24 Feb 05 03:25:26 PM PST 24 42550675 ps
T291 /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.1231235199 Feb 05 03:25:27 PM PST 24 Feb 05 03:25:30 PM PST 24 8266894 ps
T292 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.4153584911 Feb 05 03:25:10 PM PST 24 Feb 05 03:25:16 PM PST 24 920752620 ps
T54 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.2284054817 Feb 05 03:24:45 PM PST 24 Feb 05 03:24:53 PM PST 24 326339366 ps
T293 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4094774546 Feb 05 03:24:41 PM PST 24 Feb 05 03:24:43 PM PST 24 86966902 ps
T294 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.425832048 Feb 05 03:24:16 PM PST 24 Feb 05 03:24:20 PM PST 24 135254007 ps
T295 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.931850911 Feb 05 03:24:52 PM PST 24 Feb 05 03:24:54 PM PST 24 32317044 ps
T296 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2710348454 Feb 05 03:24:21 PM PST 24 Feb 05 03:24:22 PM PST 24 24411373 ps
T297 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2564252085 Feb 05 03:24:16 PM PST 24 Feb 05 03:24:18 PM PST 24 95667501 ps
T298 /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1062444066 Feb 05 03:25:31 PM PST 24 Feb 05 03:25:33 PM PST 24 20857482 ps
T299 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1105495521 Feb 05 03:25:09 PM PST 24 Feb 05 03:25:16 PM PST 24 118318965 ps
T300 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1523153714 Feb 05 03:24:42 PM PST 24 Feb 05 03:24:54 PM PST 24 3346668961 ps
T301 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1280587703 Feb 05 03:25:26 PM PST 24 Feb 05 03:25:29 PM PST 24 16230937 ps
T302 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1005149477 Feb 05 03:24:39 PM PST 24 Feb 05 03:24:40 PM PST 24 9378287 ps
T303 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.750270271 Feb 05 03:25:14 PM PST 24 Feb 05 03:25:23 PM PST 24 56407631 ps
T304 /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1794680305 Feb 05 03:25:32 PM PST 24 Feb 05 03:25:35 PM PST 24 14106702 ps
T305 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3554295228 Feb 05 03:24:24 PM PST 24 Feb 05 03:24:30 PM PST 24 283422309 ps
T306 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1043198320 Feb 05 03:24:39 PM PST 24 Feb 05 03:24:43 PM PST 24 75987333 ps
T307 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.500203161 Feb 05 03:25:23 PM PST 24 Feb 05 03:25:30 PM PST 24 420591678 ps

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2711771671
Short name T8
Test name
Test status
Simulation time 1985259449 ps
CPU time 20.71 seconds
Started Feb 05 12:35:06 PM PST 24
Finished Feb 05 12:35:46 PM PST 24
Peak memory 207192 kb
Host smart-6277fa6f-3075-4218-89fd-13f9109b6ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711771671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2711771671
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3706631743
Short name T18
Test name
Test status
Simulation time 937435528 ps
CPU time 7.56 seconds
Started Feb 05 03:24:55 PM PST 24
Finished Feb 05 03:25:03 PM PST 24
Peak memory 213680 kb
Host smart-4b6d0429-bed1-4ff8-9526-ccabae8dd853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706631743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.3706631743
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.1368443037
Short name T5
Test name
Test status
Simulation time 1858807565 ps
CPU time 7.22 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:35:08 PM PST 24
Peak memory 229756 kb
Host smart-4fbc54e9-86fa-487f-9267-55afd5ed9c82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368443037 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.1368443037
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2199777887
Short name T51
Test name
Test status
Simulation time 819844688 ps
CPU time 6.69 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:56 PM PST 24
Peak memory 213024 kb
Host smart-996ef406-b355-4ef1-a263-d4b5ab49c16d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199777887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2199777887
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2946036751
Short name T20
Test name
Test status
Simulation time 167551979 ps
CPU time 2.69 seconds
Started Feb 05 03:24:58 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 212592 kb
Host smart-56b8c6c2-3c29-413f-bf17-c42e1119b5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946036751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2946036751
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1169943688
Short name T27
Test name
Test status
Simulation time 1041020906 ps
CPU time 14.07 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:35:40 PM PST 24
Peak memory 207960 kb
Host smart-82805f58-8543-4e57-bdad-c9a13802a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169943688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1169943688
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.807072508
Short name T115
Test name
Test status
Simulation time 7954850 ps
CPU time 0.78 seconds
Started Feb 05 03:25:29 PM PST 24
Finished Feb 05 03:25:32 PM PST 24
Peak memory 204244 kb
Host smart-9abd50d4-26a5-4414-96b8-2559467e0333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807072508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.807072508
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.217906136
Short name T33
Test name
Test status
Simulation time 14483045 ps
CPU time 0.77 seconds
Started Feb 05 12:34:50 PM PST 24
Finished Feb 05 12:35:09 PM PST 24
Peak memory 205460 kb
Host smart-e021130a-ec59-4e73-aa89-30d70dc9dd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217906136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.217906136
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.387775019
Short name T44
Test name
Test status
Simulation time 51541435 ps
CPU time 3.42 seconds
Started Feb 05 03:24:22 PM PST 24
Finished Feb 05 03:24:27 PM PST 24
Peak memory 215736 kb
Host smart-4f55553d-5c4e-4014-8821-5e003833200b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387775019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.387775019
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.2403439780
Short name T68
Test name
Test status
Simulation time 50473345 ps
CPU time 1.31 seconds
Started Feb 05 03:25:02 PM PST 24
Finished Feb 05 03:25:06 PM PST 24
Peak memory 212992 kb
Host smart-de224aef-02ba-4b53-8c34-7d0c0cb00c06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403439780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.2403439780
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.807503864
Short name T31
Test name
Test status
Simulation time 1804048200 ps
CPU time 17.95 seconds
Started Feb 05 12:34:34 PM PST 24
Finished Feb 05 12:35:11 PM PST 24
Peak memory 206380 kb
Host smart-a19d97db-ff3d-4153-b819-0d03bf2e28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807503864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.807503864
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3111437644
Short name T48
Test name
Test status
Simulation time 93316240 ps
CPU time 3.54 seconds
Started Feb 05 03:25:02 PM PST 24
Finished Feb 05 03:25:07 PM PST 24
Peak memory 212660 kb
Host smart-d508bceb-b2ae-4451-ba42-b37e2deb2116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111437644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3111437644
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2346905695
Short name T53
Test name
Test status
Simulation time 177600896 ps
CPU time 6.35 seconds
Started Feb 05 03:25:25 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 213812 kb
Host smart-2ef16d09-1f72-42a2-b690-f74598d71838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346905695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2346905695
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.2116406088
Short name T96
Test name
Test status
Simulation time 332181924 ps
CPU time 2.83 seconds
Started Feb 05 03:24:10 PM PST 24
Finished Feb 05 03:24:14 PM PST 24
Peak memory 213068 kb
Host smart-351df4cf-f5fa-4ea0-881c-90615bad12db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116406088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.2116406088
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2007256521
Short name T58
Test name
Test status
Simulation time 138250717 ps
CPU time 4.16 seconds
Started Feb 05 03:24:22 PM PST 24
Finished Feb 05 03:24:29 PM PST 24
Peak memory 213632 kb
Host smart-3ebaaade-e706-40f8-83be-db8cefd30b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007256521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2007256521
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2821325367
Short name T61
Test name
Test status
Simulation time 101805766 ps
CPU time 2.55 seconds
Started Feb 05 03:24:39 PM PST 24
Finished Feb 05 03:24:43 PM PST 24
Peak memory 220784 kb
Host smart-fbde46ae-4ef7-46bc-86c7-8cb06d6aac1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821325367 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.2821325367
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2931506337
Short name T63
Test name
Test status
Simulation time 368548106 ps
CPU time 2.8 seconds
Started Feb 05 03:24:56 PM PST 24
Finished Feb 05 03:25:00 PM PST 24
Peak memory 212632 kb
Host smart-e5de0829-8aa3-453c-9811-48d6a2efafaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931506337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2931506337
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.1413567948
Short name T6
Test name
Test status
Simulation time 702406093 ps
CPU time 20.89 seconds
Started Feb 05 12:34:45 PM PST 24
Finished Feb 05 12:35:26 PM PST 24
Peak memory 231128 kb
Host smart-394bf7e0-83a3-48d6-a4be-009d5d629e54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413567948 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.1413567948
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.3586264271
Short name T57
Test name
Test status
Simulation time 330148152 ps
CPU time 4.74 seconds
Started Feb 05 03:25:05 PM PST 24
Finished Feb 05 03:25:13 PM PST 24
Peak memory 214216 kb
Host smart-e126d5d8-c8de-4567-ac91-3a323b6c0396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586264271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.3586264271
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.615364770
Short name T62
Test name
Test status
Simulation time 197854917 ps
CPU time 7.49 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:27 PM PST 24
Peak memory 213196 kb
Host smart-27cf3cef-656c-4571-ac69-e2657c8608a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615364770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe
_tl_intg_err.615364770
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3556148663
Short name T59
Test name
Test status
Simulation time 116952995 ps
CPU time 4.05 seconds
Started Feb 05 03:25:20 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 213624 kb
Host smart-ae5ece10-aab1-46f7-bde8-873022590204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556148663 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3556148663
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.2284054817
Short name T54
Test name
Test status
Simulation time 326339366 ps
CPU time 4.92 seconds
Started Feb 05 03:24:45 PM PST 24
Finished Feb 05 03:24:53 PM PST 24
Peak memory 204336 kb
Host smart-a9c0c3e5-0339-4b89-9458-d1e4e979f6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284054817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.2284054817
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.473856967
Short name T60
Test name
Test status
Simulation time 18281015 ps
CPU time 1.27 seconds
Started Feb 05 03:25:01 PM PST 24
Finished Feb 05 03:25:04 PM PST 24
Peak memory 212684 kb
Host smart-b7ac7de3-d6b9-41af-afc1-757c69d4c671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473856967 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.473856967
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3468065142
Short name T168
Test name
Test status
Simulation time 88072490 ps
CPU time 0.76 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:21 PM PST 24
Peak memory 204264 kb
Host smart-5893293a-272f-4b1e-892a-8a2653472892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468065142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3468065142
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.1796948468
Short name T111
Test name
Test status
Simulation time 671657258 ps
CPU time 13.07 seconds
Started Feb 05 12:34:36 PM PST 24
Finished Feb 05 12:35:07 PM PST 24
Peak memory 206376 kb
Host smart-6323fe75-1141-41e1-8f5c-80a554cfa279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796948468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.1796948468
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2608210404
Short name T11
Test name
Test status
Simulation time 139138662 ps
CPU time 8.82 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 207852 kb
Host smart-7b80eabb-e869-4624-96ae-dfaad4d3b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608210404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2608210404
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2213699427
Short name T109
Test name
Test status
Simulation time 10668366643 ps
CPU time 19.41 seconds
Started Feb 05 12:34:48 PM PST 24
Finished Feb 05 12:35:28 PM PST 24
Peak memory 206036 kb
Host smart-47bacf62-055e-41c7-b3b1-3ed6d849ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213699427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2213699427
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3031265596
Short name T77
Test name
Test status
Simulation time 869788315 ps
CPU time 19.47 seconds
Started Feb 05 12:34:48 PM PST 24
Finished Feb 05 12:35:28 PM PST 24
Peak memory 205972 kb
Host smart-f384cb83-8883-4903-986d-2394212f3317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031265596 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3031265596
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.367151806
Short name T2
Test name
Test status
Simulation time 225004822 ps
CPU time 12.02 seconds
Started Feb 05 12:34:46 PM PST 24
Finished Feb 05 12:35:18 PM PST 24
Peak memory 207968 kb
Host smart-2a54771b-7186-435b-88a5-a7fa45c827f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367151806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.367151806
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1216177522
Short name T105
Test name
Test status
Simulation time 16223479493 ps
CPU time 79.19 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:36:20 PM PST 24
Peak memory 207544 kb
Host smart-274a4dbe-3237-4d4f-85ee-ecf0e0d8ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216177522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1216177522
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3063507562
Short name T108
Test name
Test status
Simulation time 4903479779 ps
CPU time 25.25 seconds
Started Feb 05 12:35:01 PM PST 24
Finished Feb 05 12:35:45 PM PST 24
Peak memory 207348 kb
Host smart-aa0e7583-ad56-4740-8b5e-8dd3f47f031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063507562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3063507562
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1139065739
Short name T92
Test name
Test status
Simulation time 29224682188 ps
CPU time 183.97 seconds
Started Feb 05 12:34:55 PM PST 24
Finished Feb 05 12:38:16 PM PST 24
Peak memory 221768 kb
Host smart-43fd9d2a-0897-4899-bb0d-c2b1166f647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139065739 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1139065739
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.500419148
Short name T93
Test name
Test status
Simulation time 578209719 ps
CPU time 19.39 seconds
Started Feb 05 12:34:58 PM PST 24
Finished Feb 05 12:35:35 PM PST 24
Peak memory 207932 kb
Host smart-087c908e-4323-4b78-af72-f587b4f25109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500419148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.500419148
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.2585291763
Short name T106
Test name
Test status
Simulation time 10033086783 ps
CPU time 48.4 seconds
Started Feb 05 12:35:06 PM PST 24
Finished Feb 05 12:36:14 PM PST 24
Peak memory 208084 kb
Host smart-55c1960b-3311-4ffd-b071-8d225d5b3e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585291763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.2585291763
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.1105665107
Short name T78
Test name
Test status
Simulation time 56672426369 ps
CPU time 412.13 seconds
Started Feb 05 12:34:50 PM PST 24
Finished Feb 05 12:42:01 PM PST 24
Peak memory 208068 kb
Host smart-712dafe0-f8bc-4392-a831-a70606abd714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105665107 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.1105665107
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1552829995
Short name T107
Test name
Test status
Simulation time 2112921043 ps
CPU time 19.42 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:32 PM PST 24
Peak memory 206348 kb
Host smart-6c8e530c-bdb4-4834-8f2a-ef4f535bd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552829995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1552829995
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3792536549
Short name T3
Test name
Test status
Simulation time 223249750 ps
CPU time 12.08 seconds
Started Feb 05 12:34:33 PM PST 24
Finished Feb 05 12:35:05 PM PST 24
Peak memory 206104 kb
Host smart-30383f3f-46ec-4a38-8dc3-68221b43dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792536549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3792536549
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.425832048
Short name T294
Test name
Test status
Simulation time 135254007 ps
CPU time 3.1 seconds
Started Feb 05 03:24:16 PM PST 24
Finished Feb 05 03:24:20 PM PST 24
Peak memory 204692 kb
Host smart-5d0d1624-405f-4eae-9f3e-647aba759be0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425832048 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.425832048
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1510163464
Short name T226
Test name
Test status
Simulation time 734380512 ps
CPU time 20.11 seconds
Started Feb 05 03:24:09 PM PST 24
Finished Feb 05 03:24:31 PM PST 24
Peak memory 204396 kb
Host smart-668ca18f-bfb7-4315-8e42-c179367a9ba5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510163464 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1510163464
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.1734620665
Short name T164
Test name
Test status
Simulation time 110336820 ps
CPU time 1.23 seconds
Started Feb 05 03:24:11 PM PST 24
Finished Feb 05 03:24:13 PM PST 24
Peak memory 204368 kb
Host smart-3a12b009-eb07-4573-82a5-871960154eed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734620665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.1734620665
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3366813906
Short name T202
Test name
Test status
Simulation time 17422412 ps
CPU time 1.27 seconds
Started Feb 05 03:24:29 PM PST 24
Finished Feb 05 03:24:36 PM PST 24
Peak memory 212500 kb
Host smart-e73302dc-53a2-4102-b608-f1f6a866d6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366813906 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3366813906
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2564252085
Short name T297
Test name
Test status
Simulation time 95667501 ps
CPU time 1.24 seconds
Started Feb 05 03:24:16 PM PST 24
Finished Feb 05 03:24:18 PM PST 24
Peak memory 204552 kb
Host smart-d1c4f086-8eb2-4ee8-aff3-f7a221683bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564252085 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
564252085
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2910880367
Short name T165
Test name
Test status
Simulation time 10837345 ps
CPU time 0.85 seconds
Started Feb 05 03:24:10 PM PST 24
Finished Feb 05 03:24:12 PM PST 24
Peak memory 204232 kb
Host smart-c6245497-a490-4ff5-af5f-d795b86d239f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910880367 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
910880367
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2934501709
Short name T267
Test name
Test status
Simulation time 106001275 ps
CPU time 2.44 seconds
Started Feb 05 03:24:13 PM PST 24
Finished Feb 05 03:24:16 PM PST 24
Peak memory 212624 kb
Host smart-508967a8-4d87-4067-ab39-de23e9aaed86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934501709 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2934501709
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2073700125
Short name T69
Test name
Test status
Simulation time 530968669 ps
CPU time 4.79 seconds
Started Feb 05 03:24:16 PM PST 24
Finished Feb 05 03:24:22 PM PST 24
Peak memory 212980 kb
Host smart-78f40892-065f-477b-9ac2-19afd3ad8d00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073700125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2073700125
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.79287053
Short name T235
Test name
Test status
Simulation time 349971888 ps
CPU time 1.36 seconds
Started Feb 05 03:24:09 PM PST 24
Finished Feb 05 03:24:12 PM PST 24
Peak memory 212688 kb
Host smart-80d06b12-c914-4c59-80a0-69534b9543e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79287053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.79287053
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1946738866
Short name T232
Test name
Test status
Simulation time 627859455 ps
CPU time 2.19 seconds
Started Feb 05 03:24:13 PM PST 24
Finished Feb 05 03:24:16 PM PST 24
Peak memory 213664 kb
Host smart-a6beb908-1293-49d6-8c6a-7693b8fd8d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946738866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1946738866
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1395572602
Short name T261
Test name
Test status
Simulation time 865856345 ps
CPU time 8.78 seconds
Started Feb 05 03:24:20 PM PST 24
Finished Feb 05 03:24:29 PM PST 24
Peak memory 204404 kb
Host smart-2dbfa505-cd5c-47c3-9980-294767ca71f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395572602 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.1395572602
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.821294585
Short name T252
Test name
Test status
Simulation time 1214231522 ps
CPU time 5.98 seconds
Started Feb 05 03:24:20 PM PST 24
Finished Feb 05 03:24:27 PM PST 24
Peak memory 204436 kb
Host smart-5e4b017a-8be4-4cff-8192-fa8eb84a5e36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821294585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.821294585
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1154216225
Short name T200
Test name
Test status
Simulation time 21780071 ps
CPU time 1.1 seconds
Started Feb 05 03:24:20 PM PST 24
Finished Feb 05 03:24:21 PM PST 24
Peak memory 204444 kb
Host smart-aff79d1b-fa1e-4790-a352-ceee3d9b125a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154216225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1154216225
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3262397785
Short name T55
Test name
Test status
Simulation time 23383049 ps
CPU time 1.63 seconds
Started Feb 05 03:24:17 PM PST 24
Finished Feb 05 03:24:19 PM PST 24
Peak memory 212716 kb
Host smart-93e9b713-3def-4761-9d59-894fe98a1048
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262397785 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3262397785
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2937527581
Short name T163
Test name
Test status
Simulation time 53575089 ps
CPU time 1.06 seconds
Started Feb 05 03:24:20 PM PST 24
Finished Feb 05 03:24:22 PM PST 24
Peak memory 204372 kb
Host smart-76c3d201-c8f2-4344-a426-d0126de45647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937527581 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
937527581
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.2710348454
Short name T296
Test name
Test status
Simulation time 24411373 ps
CPU time 0.74 seconds
Started Feb 05 03:24:21 PM PST 24
Finished Feb 05 03:24:22 PM PST 24
Peak memory 204236 kb
Host smart-98f37a1f-f7f4-45d4-ae05-817fb978a533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710348454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.2
710348454
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.953439504
Short name T272
Test name
Test status
Simulation time 37104990 ps
CPU time 1.39 seconds
Started Feb 05 03:24:17 PM PST 24
Finished Feb 05 03:24:19 PM PST 24
Peak memory 204412 kb
Host smart-109b593c-79bd-4dee-8ba1-723980790556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953439504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.953439504
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.183062010
Short name T244
Test name
Test status
Simulation time 233443829 ps
CPU time 1.81 seconds
Started Feb 05 03:24:17 PM PST 24
Finished Feb 05 03:24:20 PM PST 24
Peak memory 212908 kb
Host smart-9310f043-5d85-4fd0-9144-271bbb9d2370
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183062010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymg
r_dpe_shadow_reg_errors.183062010
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.40383846
Short name T265
Test name
Test status
Simulation time 908324602 ps
CPU time 4.82 seconds
Started Feb 05 03:24:19 PM PST 24
Finished Feb 05 03:24:25 PM PST 24
Peak memory 213020 kb
Host smart-a78a120e-e095-43d1-ad14-4af715ba8c3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40383846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.40383846
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.1003817788
Short name T42
Test name
Test status
Simulation time 280343570 ps
CPU time 2.85 seconds
Started Feb 05 03:24:22 PM PST 24
Finished Feb 05 03:24:26 PM PST 24
Peak memory 212716 kb
Host smart-691f4dd0-a0de-4615-92f8-1b120b9df5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003817788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.1
003817788
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.3078851512
Short name T282
Test name
Test status
Simulation time 15869328 ps
CPU time 0.85 seconds
Started Feb 05 03:25:00 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 204272 kb
Host smart-6e8f67bd-e3a8-4a83-a423-7a4b88ee7956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078851512 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
3078851512
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.800659289
Short name T239
Test name
Test status
Simulation time 24430789 ps
CPU time 0.69 seconds
Started Feb 05 03:25:01 PM PST 24
Finished Feb 05 03:25:04 PM PST 24
Peak memory 204296 kb
Host smart-88c06859-64e5-484a-a2ce-028c491a4907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800659289 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.800659289
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1859788137
Short name T187
Test name
Test status
Simulation time 527121362 ps
CPU time 2.67 seconds
Started Feb 05 03:25:03 PM PST 24
Finished Feb 05 03:25:08 PM PST 24
Peak memory 204440 kb
Host smart-3ac9f24c-68bf-4eaa-9cfe-69647df12a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859788137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1859788137
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1261514612
Short name T71
Test name
Test status
Simulation time 72681893 ps
CPU time 2.11 seconds
Started Feb 05 03:24:55 PM PST 24
Finished Feb 05 03:24:58 PM PST 24
Peak memory 212996 kb
Host smart-612af600-f29b-4ca9-902a-d761c35dc398
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261514612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1261514612
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1508129989
Short name T196
Test name
Test status
Simulation time 797972152 ps
CPU time 5.64 seconds
Started Feb 05 03:25:00 PM PST 24
Finished Feb 05 03:25:07 PM PST 24
Peak memory 213060 kb
Host smart-8ed028a9-138b-4d85-bf28-8757ab15997b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508129989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1508129989
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.1172876046
Short name T56
Test name
Test status
Simulation time 121181124 ps
CPU time 2.83 seconds
Started Feb 05 03:24:56 PM PST 24
Finished Feb 05 03:24:59 PM PST 24
Peak memory 212668 kb
Host smart-89e67a43-73df-467f-9d3f-da57acd29211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172876046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
1172876046
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2163555399
Short name T19
Test name
Test status
Simulation time 670636722 ps
CPU time 3.49 seconds
Started Feb 05 03:25:03 PM PST 24
Finished Feb 05 03:25:08 PM PST 24
Peak memory 212716 kb
Host smart-6027d32c-d11c-47b3-9927-362fe4981c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163555399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.2163555399
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.1978501759
Short name T37
Test name
Test status
Simulation time 35206783 ps
CPU time 1.88 seconds
Started Feb 05 03:25:02 PM PST 24
Finished Feb 05 03:25:06 PM PST 24
Peak memory 212900 kb
Host smart-aacd6607-8cf3-450f-9a35-8e86b4617319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978501759 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.1978501759
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1015820547
Short name T216
Test name
Test status
Simulation time 32597539 ps
CPU time 0.89 seconds
Started Feb 05 03:25:01 PM PST 24
Finished Feb 05 03:25:03 PM PST 24
Peak memory 204204 kb
Host smart-a2416e56-5982-489f-abe6-a1b13caacac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015820547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1015820547
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1408185641
Short name T179
Test name
Test status
Simulation time 22198182 ps
CPU time 0.73 seconds
Started Feb 05 03:25:05 PM PST 24
Finished Feb 05 03:25:09 PM PST 24
Peak memory 204244 kb
Host smart-b39d2125-97d4-448b-b07e-ec0b0f1ff5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408185641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1408185641
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.531915622
Short name T90
Test name
Test status
Simulation time 96804576 ps
CPU time 3.26 seconds
Started Feb 05 03:25:05 PM PST 24
Finished Feb 05 03:25:11 PM PST 24
Peak memory 204308 kb
Host smart-0cdafdde-7e25-4ea6-9ed2-5e14b37bee63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531915622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_dpe_same_csr_outstanding.531915622
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1133480569
Short name T100
Test name
Test status
Simulation time 491499117 ps
CPU time 1.43 seconds
Started Feb 05 03:25:00 PM PST 24
Finished Feb 05 03:25:03 PM PST 24
Peak memory 213004 kb
Host smart-01f4a81d-3cd5-4504-b51f-9bfd9cdbbadf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133480569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1133480569
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1176009150
Short name T241
Test name
Test status
Simulation time 108858167 ps
CPU time 5.26 seconds
Started Feb 05 03:24:55 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 220872 kb
Host smart-7cd20647-520f-4317-8891-b36fef843fd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176009150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1176009150
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2362424940
Short name T257
Test name
Test status
Simulation time 20713731 ps
CPU time 1.16 seconds
Started Feb 05 03:25:03 PM PST 24
Finished Feb 05 03:25:06 PM PST 24
Peak memory 204432 kb
Host smart-5581862c-abcc-47c4-a183-326c84f1a3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362424940 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2362424940
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2179622183
Short name T83
Test name
Test status
Simulation time 16836793 ps
CPU time 1.1 seconds
Started Feb 05 03:25:02 PM PST 24
Finished Feb 05 03:25:06 PM PST 24
Peak memory 204444 kb
Host smart-4d789b66-8a9e-40cd-a9bd-c4e0dedd477d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179622183 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2179622183
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.354885965
Short name T205
Test name
Test status
Simulation time 33043332 ps
CPU time 0.7 seconds
Started Feb 05 03:25:01 PM PST 24
Finished Feb 05 03:25:03 PM PST 24
Peak memory 204268 kb
Host smart-bc972b46-5364-4416-86f0-9f5e12fccbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354885965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.354885965
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.668865154
Short name T101
Test name
Test status
Simulation time 195044199 ps
CPU time 1.38 seconds
Started Feb 05 03:25:06 PM PST 24
Finished Feb 05 03:25:11 PM PST 24
Peak memory 204396 kb
Host smart-f6d50fb6-95b3-4aa3-8494-ccff35f7ed9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668865154 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_dpe_same_csr_outstanding.668865154
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1854892174
Short name T263
Test name
Test status
Simulation time 1067111121 ps
CPU time 9.34 seconds
Started Feb 05 03:25:05 PM PST 24
Finished Feb 05 03:25:17 PM PST 24
Peak memory 213000 kb
Host smart-4e8b3a0c-db9d-4fb5-8641-95596c81e62e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854892174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1854892174
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.699290169
Short name T258
Test name
Test status
Simulation time 43770553 ps
CPU time 2.63 seconds
Started Feb 05 03:25:05 PM PST 24
Finished Feb 05 03:25:11 PM PST 24
Peak memory 212648 kb
Host smart-f35a8c04-385e-4fcc-b105-7ec41474548f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699290169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.699290169
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.2968617018
Short name T286
Test name
Test status
Simulation time 64739069 ps
CPU time 1.73 seconds
Started Feb 05 03:25:10 PM PST 24
Finished Feb 05 03:25:14 PM PST 24
Peak memory 216428 kb
Host smart-b0806d2a-67ba-4524-b981-83f6fabc9490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968617018 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.2968617018
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1068222008
Short name T234
Test name
Test status
Simulation time 48120652 ps
CPU time 1.13 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 204404 kb
Host smart-1317a308-1b08-4e8f-a129-72606c2026e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068222008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1068222008
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1936622253
Short name T248
Test name
Test status
Simulation time 10248632 ps
CPU time 0.85 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:21 PM PST 24
Peak memory 204308 kb
Host smart-d979c53f-3bc5-466d-9425-418debb31146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936622253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1936622253
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1957927447
Short name T85
Test name
Test status
Simulation time 61759945 ps
CPU time 1.75 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:21 PM PST 24
Peak memory 204500 kb
Host smart-559df18d-d892-4faf-a0d2-6f7b03bfbb3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957927447 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1957927447
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1549711549
Short name T217
Test name
Test status
Simulation time 212576159 ps
CPU time 4.6 seconds
Started Feb 05 03:25:02 PM PST 24
Finished Feb 05 03:25:09 PM PST 24
Peak memory 217664 kb
Host smart-71b076b0-65f3-4b7b-85bb-b989086f8a2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549711549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1549711549
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3967223719
Short name T194
Test name
Test status
Simulation time 229248367 ps
CPU time 2.59 seconds
Started Feb 05 03:25:15 PM PST 24
Finished Feb 05 03:25:23 PM PST 24
Peak memory 213108 kb
Host smart-7963928c-c179-48a5-a280-effbbb16b9d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967223719 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3967223719
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.4153584911
Short name T292
Test name
Test status
Simulation time 920752620 ps
CPU time 3.15 seconds
Started Feb 05 03:25:10 PM PST 24
Finished Feb 05 03:25:16 PM PST 24
Peak memory 212692 kb
Host smart-44f57b89-0d73-4115-b7b1-f07c06abe92b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153584911 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
4153584911
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1218585257
Short name T94
Test name
Test status
Simulation time 32852431 ps
CPU time 1.35 seconds
Started Feb 05 03:25:10 PM PST 24
Finished Feb 05 03:25:13 PM PST 24
Peak memory 212588 kb
Host smart-619ff8de-beba-4c0c-8bde-b59b20dd74ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218585257 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1218585257
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2911967720
Short name T186
Test name
Test status
Simulation time 18632471 ps
CPU time 1.09 seconds
Started Feb 05 03:25:11 PM PST 24
Finished Feb 05 03:25:19 PM PST 24
Peak memory 204452 kb
Host smart-6c4c186f-9da8-4192-a9bc-616888394272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911967720 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2911967720
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.665532514
Short name T224
Test name
Test status
Simulation time 105459573 ps
CPU time 2.37 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 204500 kb
Host smart-4ce29fd4-775e-47ca-9023-1f44d2623cf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665532514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.665532514
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1903015771
Short name T264
Test name
Test status
Simulation time 249141750 ps
CPU time 2.75 seconds
Started Feb 05 03:25:11 PM PST 24
Finished Feb 05 03:25:21 PM PST 24
Peak memory 213252 kb
Host smart-dc237ec2-c41c-459e-9ee0-4ccf56c75e05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903015771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.1903015771
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3366501562
Short name T266
Test name
Test status
Simulation time 775476316 ps
CPU time 2.62 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 212992 kb
Host smart-35c3c4c6-ad8d-4663-b2e5-2068eb79207b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366501562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3366501562
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.344508007
Short name T190
Test name
Test status
Simulation time 89690399 ps
CPU time 2.05 seconds
Started Feb 05 03:25:10 PM PST 24
Finished Feb 05 03:25:14 PM PST 24
Peak memory 212648 kb
Host smart-941aae10-cc55-4239-89e9-6887c84c671e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344508007 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.344508007
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.750270271
Short name T303
Test name
Test status
Simulation time 56407631 ps
CPU time 2.34 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:23 PM PST 24
Peak memory 212604 kb
Host smart-87ebb7af-acb9-44f1-ac0a-c7064e1c1bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750270271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.750270271
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2125471354
Short name T236
Test name
Test status
Simulation time 28294190 ps
CPU time 2.08 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:23 PM PST 24
Peak memory 217400 kb
Host smart-232c07dc-597b-4f04-b044-3aec452e47bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125471354 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2125471354
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1820933686
Short name T38
Test name
Test status
Simulation time 166883855 ps
CPU time 0.94 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 204312 kb
Host smart-820e83c7-29cc-44d4-ae97-0cf0f0c14d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820933686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
1820933686
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3789315038
Short name T97
Test name
Test status
Simulation time 54611597 ps
CPU time 0.88 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:21 PM PST 24
Peak memory 204232 kb
Host smart-512064ec-f47a-43af-981d-6eff43afa475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789315038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3789315038
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2027989982
Short name T284
Test name
Test status
Simulation time 92607191 ps
CPU time 2.17 seconds
Started Feb 05 03:25:15 PM PST 24
Finished Feb 05 03:25:23 PM PST 24
Peak memory 204412 kb
Host smart-7ca96364-c7bb-4245-947a-e5ec3d0908bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027989982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2027989982
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.657346103
Short name T203
Test name
Test status
Simulation time 63399501 ps
CPU time 1.53 seconds
Started Feb 05 03:25:10 PM PST 24
Finished Feb 05 03:25:14 PM PST 24
Peak memory 213032 kb
Host smart-0f973ad5-aca0-4f62-a1f1-2bdf683515f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657346103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.657346103
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.2194215213
Short name T198
Test name
Test status
Simulation time 57176375 ps
CPU time 3.42 seconds
Started Feb 05 03:25:11 PM PST 24
Finished Feb 05 03:25:17 PM PST 24
Peak memory 213184 kb
Host smart-869f8064-8461-4ddc-9865-dac5a9ebe131
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194215213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.2194215213
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1105495521
Short name T299
Test name
Test status
Simulation time 118318965 ps
CPU time 3.75 seconds
Started Feb 05 03:25:09 PM PST 24
Finished Feb 05 03:25:16 PM PST 24
Peak memory 220184 kb
Host smart-37852801-face-4955-8d8d-a8ad19ecc446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105495521 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1105495521
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.1292207928
Short name T260
Test name
Test status
Simulation time 48864178 ps
CPU time 2.59 seconds
Started Feb 05 03:25:12 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 213692 kb
Host smart-dbed7204-f408-4ae0-b0fa-6348c3b2cc15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292207928 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.1292207928
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.1583828337
Short name T247
Test name
Test status
Simulation time 124279591 ps
CPU time 1.22 seconds
Started Feb 05 03:25:23 PM PST 24
Finished Feb 05 03:25:27 PM PST 24
Peak memory 212740 kb
Host smart-02ef228a-5307-4af7-a502-3c7cb4a78fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583828337 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.1583828337
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1220776334
Short name T242
Test name
Test status
Simulation time 10048918 ps
CPU time 0.95 seconds
Started Feb 05 03:25:21 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 204312 kb
Host smart-4cc6632c-72a2-42e8-884c-385ad9449279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220776334 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1220776334
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.31196188
Short name T176
Test name
Test status
Simulation time 44047482 ps
CPU time 0.83 seconds
Started Feb 05 03:25:21 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 204224 kb
Host smart-9c0e161f-89c3-48a7-b010-8aa10e4ffd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196188 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.31196188
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.637741361
Short name T221
Test name
Test status
Simulation time 91490115 ps
CPU time 2.2 seconds
Started Feb 05 03:25:26 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204416 kb
Host smart-19ace02b-9648-47db-abd1-e662ba661695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637741361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_dpe_same_csr_outstanding.637741361
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1169005761
Short name T173
Test name
Test status
Simulation time 109679532 ps
CPU time 1.35 seconds
Started Feb 05 03:25:14 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 204820 kb
Host smart-feb8c3d0-ec48-4c2d-8f5b-4b6743826481
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169005761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1169005761
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1148076782
Short name T70
Test name
Test status
Simulation time 207399152 ps
CPU time 3.02 seconds
Started Feb 05 03:25:15 PM PST 24
Finished Feb 05 03:25:24 PM PST 24
Peak memory 212944 kb
Host smart-680cc056-747c-431e-b357-00a381e10da9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148076782 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1148076782
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.241872480
Short name T191
Test name
Test status
Simulation time 59068139 ps
CPU time 1.59 seconds
Started Feb 05 03:25:11 PM PST 24
Finished Feb 05 03:25:19 PM PST 24
Peak memory 212716 kb
Host smart-17093636-b136-440c-8386-46af4a4df158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241872480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.241872480
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3193106184
Short name T35
Test name
Test status
Simulation time 51827104 ps
CPU time 2.32 seconds
Started Feb 05 03:25:20 PM PST 24
Finished Feb 05 03:25:24 PM PST 24
Peak memory 213708 kb
Host smart-82616cec-c97e-4961-a3c0-1140a76b2558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193106184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3193106184
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.494269547
Short name T98
Test name
Test status
Simulation time 40670083 ps
CPU time 1.26 seconds
Started Feb 05 03:25:16 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 212676 kb
Host smart-341309e0-dd70-497b-ba64-38fff98fd939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494269547 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.494269547
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2695006494
Short name T91
Test name
Test status
Simulation time 11202257 ps
CPU time 0.81 seconds
Started Feb 05 03:25:24 PM PST 24
Finished Feb 05 03:25:27 PM PST 24
Peak memory 204244 kb
Host smart-4f62ca7d-ba8f-4b36-a558-1d44f919f7b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695006494 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2695006494
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3981743775
Short name T290
Test name
Test status
Simulation time 42550675 ps
CPU time 0.77 seconds
Started Feb 05 03:25:22 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 204268 kb
Host smart-7f9530e6-e74c-4f56-b27c-93676bc316bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981743775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3981743775
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.4273946744
Short name T209
Test name
Test status
Simulation time 68696448 ps
CPU time 1.21 seconds
Started Feb 05 03:25:17 PM PST 24
Finished Feb 05 03:25:22 PM PST 24
Peak memory 204492 kb
Host smart-960840cd-af9d-43b9-bb81-09e841d32d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273946744 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.4273946744
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.183211631
Short name T52
Test name
Test status
Simulation time 827519601 ps
CPU time 2.27 seconds
Started Feb 05 03:25:25 PM PST 24
Finished Feb 05 03:25:29 PM PST 24
Peak memory 213016 kb
Host smart-8a6fc108-1613-4964-9b97-a24a8094bb07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183211631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym
gr_dpe_shadow_reg_errors.183211631
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.500203161
Short name T307
Test name
Test status
Simulation time 420591678 ps
CPU time 4.38 seconds
Started Feb 05 03:25:23 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 212976 kb
Host smart-eb24ae42-540b-4e9b-a780-28a71e51a2f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500203161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.500203161
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.403882513
Short name T180
Test name
Test status
Simulation time 182437303 ps
CPU time 2.2 seconds
Started Feb 05 03:25:22 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 212732 kb
Host smart-a5321d3c-b9a4-4303-a4bd-f0f25de8b446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403882513 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.403882513
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2304640817
Short name T223
Test name
Test status
Simulation time 176272596 ps
CPU time 1.32 seconds
Started Feb 05 03:25:23 PM PST 24
Finished Feb 05 03:25:27 PM PST 24
Peak memory 212704 kb
Host smart-bd9b0834-5537-46ef-91a2-33331c1153e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304640817 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2304640817
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3139495504
Short name T197
Test name
Test status
Simulation time 81678900 ps
CPU time 0.98 seconds
Started Feb 05 03:25:22 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 204268 kb
Host smart-3a61b5cd-1865-445c-856a-67d3f5e17c8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139495504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3139495504
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1890979338
Short name T207
Test name
Test status
Simulation time 12146053 ps
CPU time 0.83 seconds
Started Feb 05 03:25:21 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 204216 kb
Host smart-b4581964-3c7f-4df2-817d-58ecd5e2cbd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890979338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1890979338
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3368464659
Short name T285
Test name
Test status
Simulation time 144205902 ps
CPU time 2.07 seconds
Started Feb 05 03:25:23 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 204372 kb
Host smart-0150a1ea-99c4-41c6-b06c-b8472ced3939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368464659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.3368464659
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3851024010
Short name T233
Test name
Test status
Simulation time 144715867 ps
CPU time 1.84 seconds
Started Feb 05 03:25:20 PM PST 24
Finished Feb 05 03:25:26 PM PST 24
Peak memory 212988 kb
Host smart-99d8b53f-5889-4376-be77-3ad91e22cc73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851024010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3851024010
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.52799495
Short name T281
Test name
Test status
Simulation time 36332308 ps
CPU time 2.13 seconds
Started Feb 05 03:25:26 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 213088 kb
Host smart-87d6cd07-c5ea-45cf-965c-7bdcd17ba2ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52799495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.52799495
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2154414035
Short name T41
Test name
Test status
Simulation time 310316910 ps
CPU time 2.3 seconds
Started Feb 05 03:25:24 PM PST 24
Finished Feb 05 03:25:29 PM PST 24
Peak memory 212688 kb
Host smart-fe7070e5-0038-4431-9a58-d2531837b159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154414035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
2154414035
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1034394585
Short name T253
Test name
Test status
Simulation time 17092241 ps
CPU time 1.21 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 220444 kb
Host smart-8c311f94-8bac-45d6-adc9-ee6f49a546cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034394585 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1034394585
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1280587703
Short name T301
Test name
Test status
Simulation time 16230937 ps
CPU time 1.18 seconds
Started Feb 05 03:25:26 PM PST 24
Finished Feb 05 03:25:29 PM PST 24
Peak memory 204336 kb
Host smart-8ec07947-2a35-47e1-8ba1-13e46b861585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280587703 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
1280587703
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1849495873
Short name T169
Test name
Test status
Simulation time 26175858 ps
CPU time 0.72 seconds
Started Feb 05 03:25:25 PM PST 24
Finished Feb 05 03:25:27 PM PST 24
Peak memory 204252 kb
Host smart-eb22bba1-0297-40df-81cd-b304dbc3e017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849495873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
1849495873
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1877745624
Short name T275
Test name
Test status
Simulation time 534792051 ps
CPU time 2.12 seconds
Started Feb 05 03:25:33 PM PST 24
Finished Feb 05 03:25:37 PM PST 24
Peak memory 204424 kb
Host smart-05aa50f0-c11c-4ce6-8198-896821386b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877745624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.1877745624
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2267411012
Short name T72
Test name
Test status
Simulation time 163757503 ps
CPU time 1.79 seconds
Started Feb 05 03:25:23 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 212928 kb
Host smart-7f92ca85-282d-4b2c-96fb-9571df14577c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267411012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2267411012
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1549334024
Short name T222
Test name
Test status
Simulation time 99313157 ps
CPU time 4.3 seconds
Started Feb 05 03:25:19 PM PST 24
Finished Feb 05 03:25:25 PM PST 24
Peak memory 212928 kb
Host smart-67b49763-39e0-43e7-9b57-2977559e29af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549334024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1549334024
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3296029891
Short name T219
Test name
Test status
Simulation time 24543391 ps
CPU time 1.55 seconds
Started Feb 05 03:25:20 PM PST 24
Finished Feb 05 03:25:23 PM PST 24
Peak memory 213924 kb
Host smart-c0ba9b55-38ef-4acb-a2d9-1ebc091ce0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296029891 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3296029891
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.4188127356
Short name T66
Test name
Test status
Simulation time 1341620947 ps
CPU time 8.2 seconds
Started Feb 05 03:25:22 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 214444 kb
Host smart-43906fb4-08e9-4192-b090-fb9ad09177cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188127356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.4188127356
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1103546208
Short name T184
Test name
Test status
Simulation time 274408097 ps
CPU time 5.44 seconds
Started Feb 05 03:24:23 PM PST 24
Finished Feb 05 03:24:32 PM PST 24
Peak memory 204368 kb
Host smart-9c08a665-49ab-4f30-a089-510906d74407
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103546208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.1103546208
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.2859121568
Short name T256
Test name
Test status
Simulation time 866820518 ps
CPU time 11.6 seconds
Started Feb 05 03:24:20 PM PST 24
Finished Feb 05 03:24:32 PM PST 24
Peak memory 204428 kb
Host smart-efe68f6d-4154-4586-a7d1-d2b834037d61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859121568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.2859121568
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2940659443
Short name T188
Test name
Test status
Simulation time 14640185 ps
CPU time 0.89 seconds
Started Feb 05 03:24:32 PM PST 24
Finished Feb 05 03:24:36 PM PST 24
Peak memory 204152 kb
Host smart-7fce208c-737d-4d32-ae11-77e5e95cfbc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940659443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2940659443
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3853419794
Short name T218
Test name
Test status
Simulation time 39184035 ps
CPU time 1.56 seconds
Started Feb 05 03:24:25 PM PST 24
Finished Feb 05 03:24:29 PM PST 24
Peak memory 212636 kb
Host smart-db2e8c93-9f7f-40b1-b24e-30613182143b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853419794 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.3853419794
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2811625629
Short name T251
Test name
Test status
Simulation time 201527696 ps
CPU time 0.94 seconds
Started Feb 05 03:24:32 PM PST 24
Finished Feb 05 03:24:36 PM PST 24
Peak memory 204324 kb
Host smart-c71ea565-c9f2-4686-95df-f3e3bc04b5f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811625629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
811625629
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2895029877
Short name T273
Test name
Test status
Simulation time 127959502 ps
CPU time 0.9 seconds
Started Feb 05 03:24:23 PM PST 24
Finished Feb 05 03:24:26 PM PST 24
Peak memory 204308 kb
Host smart-39ff8818-bb92-402a-80a3-a2ef79d427cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895029877 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
895029877
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1840511542
Short name T259
Test name
Test status
Simulation time 139909263 ps
CPU time 1.21 seconds
Started Feb 05 03:24:25 PM PST 24
Finished Feb 05 03:24:29 PM PST 24
Peak memory 204436 kb
Host smart-48c633c3-cb36-43a8-93b2-b0b3f36e06c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840511542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1840511542
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3311746595
Short name T246
Test name
Test status
Simulation time 115596705 ps
CPU time 2.55 seconds
Started Feb 05 03:24:18 PM PST 24
Finished Feb 05 03:24:21 PM PST 24
Peak memory 213008 kb
Host smart-89bd164b-9786-485d-a57c-207a12fa49c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311746595 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3311746595
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4246264194
Short name T279
Test name
Test status
Simulation time 270684587 ps
CPU time 6.09 seconds
Started Feb 05 03:24:22 PM PST 24
Finished Feb 05 03:24:31 PM PST 24
Peak memory 212912 kb
Host smart-72ded808-c37f-4271-9035-48953d880211
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246264194 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4246264194
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3217533452
Short name T67
Test name
Test status
Simulation time 206692893 ps
CPU time 4.73 seconds
Started Feb 05 03:24:18 PM PST 24
Finished Feb 05 03:24:23 PM PST 24
Peak memory 213776 kb
Host smart-9f38fc2d-4133-464f-9324-01bbafaa6c61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217533452 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3217533452
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.548541445
Short name T170
Test name
Test status
Simulation time 31201466 ps
CPU time 0.8 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 204268 kb
Host smart-667113ab-21eb-4a85-9f6e-ede1128cb553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548541445 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.548541445
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2288113723
Short name T45
Test name
Test status
Simulation time 14205956 ps
CPU time 0.89 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 204452 kb
Host smart-4c7c3205-6088-4175-a172-e839a2a03d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288113723 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2288113723
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.1622765867
Short name T240
Test name
Test status
Simulation time 17694581 ps
CPU time 0.78 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 204272 kb
Host smart-3a4d5a36-dc42-4877-9b56-76483239bdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622765867 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
1622765867
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.821267854
Short name T174
Test name
Test status
Simulation time 38391021 ps
CPU time 0.69 seconds
Started Feb 05 03:25:29 PM PST 24
Finished Feb 05 03:25:32 PM PST 24
Peak memory 204200 kb
Host smart-2efccf55-9954-4945-9889-f511ce0e045c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821267854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.821267854
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2322371601
Short name T46
Test name
Test status
Simulation time 26704905 ps
CPU time 0.67 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:29 PM PST 24
Peak memory 204236 kb
Host smart-129b7cd0-0709-4978-a09a-36f9bb8ba9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322371601 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2322371601
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.176254406
Short name T289
Test name
Test status
Simulation time 28324887 ps
CPU time 0.76 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204252 kb
Host smart-87c2a76b-0316-4bd0-ac53-e6a80da1c65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176254406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.176254406
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.2290606802
Short name T229
Test name
Test status
Simulation time 43912206 ps
CPU time 0.78 seconds
Started Feb 05 03:25:29 PM PST 24
Finished Feb 05 03:25:32 PM PST 24
Peak memory 204240 kb
Host smart-d700d2b4-af26-4a1d-99bf-67950729c10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290606802 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
2290606802
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2273184341
Short name T212
Test name
Test status
Simulation time 13290972 ps
CPU time 0.72 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 204444 kb
Host smart-bd2c7a98-542d-4bbe-a2cf-b71a638cacde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273184341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2273184341
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.1516948652
Short name T249
Test name
Test status
Simulation time 10386079 ps
CPU time 0.79 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204284 kb
Host smart-fca6ca10-951f-4597-a4b7-9dcbb5299c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516948652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
1516948652
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.165582650
Short name T225
Test name
Test status
Simulation time 229153739 ps
CPU time 8.72 seconds
Started Feb 05 03:24:48 PM PST 24
Finished Feb 05 03:24:59 PM PST 24
Peak memory 204392 kb
Host smart-74ec2847-d881-4f2e-8ea9-d5a53bec0914
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165582650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_aliasing.165582650
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1523153714
Short name T300
Test name
Test status
Simulation time 3346668961 ps
CPU time 8.96 seconds
Started Feb 05 03:24:42 PM PST 24
Finished Feb 05 03:24:54 PM PST 24
Peak memory 204484 kb
Host smart-67f724c1-606d-437d-b3a0-5e9c7c8a3857
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523153714 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1523153714
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.439759892
Short name T280
Test name
Test status
Simulation time 57833217 ps
CPU time 1.33 seconds
Started Feb 05 03:24:43 PM PST 24
Finished Feb 05 03:24:47 PM PST 24
Peak memory 204448 kb
Host smart-a59ddf8e-ca4f-4252-b65d-52e70dddd9fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439759892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_hw_reset.439759892
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4094774546
Short name T293
Test name
Test status
Simulation time 86966902 ps
CPU time 1.3 seconds
Started Feb 05 03:24:41 PM PST 24
Finished Feb 05 03:24:43 PM PST 24
Peak memory 212736 kb
Host smart-ecef2fbd-eb95-46f3-897c-a6d95b5aa9fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094774546 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.4094774546
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1337380096
Short name T193
Test name
Test status
Simulation time 27930762 ps
CPU time 0.85 seconds
Started Feb 05 03:24:40 PM PST 24
Finished Feb 05 03:24:42 PM PST 24
Peak memory 204240 kb
Host smart-afc87325-bea1-4444-bc32-62d35487a467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337380096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
337380096
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2851118973
Short name T102
Test name
Test status
Simulation time 18146844 ps
CPU time 0.8 seconds
Started Feb 05 03:24:42 PM PST 24
Finished Feb 05 03:24:46 PM PST 24
Peak memory 204220 kb
Host smart-e694c0b8-cf56-4f0f-a89f-15b9ae5186eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851118973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.2
851118973
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.4120979095
Short name T88
Test name
Test status
Simulation time 22672100 ps
CPU time 1.47 seconds
Started Feb 05 03:24:43 PM PST 24
Finished Feb 05 03:24:48 PM PST 24
Peak memory 204388 kb
Host smart-ac540b5f-0b31-4025-a288-dc4ea06cc3f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120979095 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.4120979095
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3554295228
Short name T305
Test name
Test status
Simulation time 283422309 ps
CPU time 2.52 seconds
Started Feb 05 03:24:24 PM PST 24
Finished Feb 05 03:24:30 PM PST 24
Peak memory 212964 kb
Host smart-2e253dde-0537-4d6e-a44e-2ab22f0d7fea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554295228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3554295228
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2425383688
Short name T269
Test name
Test status
Simulation time 121506655 ps
CPU time 3.12 seconds
Started Feb 05 03:24:31 PM PST 24
Finished Feb 05 03:24:38 PM PST 24
Peak memory 213060 kb
Host smart-7307717a-fb38-4bf9-b275-dcdf1b805358
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425383688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2425383688
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.4063152062
Short name T228
Test name
Test status
Simulation time 166049896 ps
CPU time 6.21 seconds
Started Feb 05 03:24:32 PM PST 24
Finished Feb 05 03:24:41 PM PST 24
Peak memory 212700 kb
Host smart-6f09615a-b5eb-4837-b700-8ab86fa90d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063152062 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.4
063152062
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1794680305
Short name T304
Test name
Test status
Simulation time 14106702 ps
CPU time 0.72 seconds
Started Feb 05 03:25:32 PM PST 24
Finished Feb 05 03:25:35 PM PST 24
Peak memory 204244 kb
Host smart-fb21dc2d-0c54-4b19-9442-a02c75f17faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794680305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
1794680305
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1062444066
Short name T298
Test name
Test status
Simulation time 20857482 ps
CPU time 0.7 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:33 PM PST 24
Peak memory 204236 kb
Host smart-2102288b-920e-4193-b019-073244fb670b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062444066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1062444066
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.2346934060
Short name T73
Test name
Test status
Simulation time 12630005 ps
CPU time 0.82 seconds
Started Feb 05 03:25:29 PM PST 24
Finished Feb 05 03:25:32 PM PST 24
Peak memory 204232 kb
Host smart-0fb150d1-0ab5-4338-b4dc-b3e3f2a71545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346934060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
2346934060
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.1231235199
Short name T291
Test name
Test status
Simulation time 8266894 ps
CPU time 0.69 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204212 kb
Host smart-bbff2d3f-5328-4690-af03-801a41d6e412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231235199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
1231235199
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.989360722
Short name T270
Test name
Test status
Simulation time 13970652 ps
CPU time 0.72 seconds
Started Feb 05 03:25:28 PM PST 24
Finished Feb 05 03:25:31 PM PST 24
Peak memory 204280 kb
Host smart-00e9a607-80e3-43a9-bfe9-2c14f7f2aa0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989360722 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.989360722
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1693557125
Short name T172
Test name
Test status
Simulation time 10670327 ps
CPU time 0.74 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 204260 kb
Host smart-1cc63e8d-df5c-426c-9ff8-b70d295140ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693557125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1693557125
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.2377409080
Short name T175
Test name
Test status
Simulation time 21229740 ps
CPU time 0.78 seconds
Started Feb 05 03:25:33 PM PST 24
Finished Feb 05 03:25:36 PM PST 24
Peak memory 204308 kb
Host smart-92efca6d-e9e8-4d99-9149-afd61946ebf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377409080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
2377409080
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.2637502863
Short name T189
Test name
Test status
Simulation time 14023369 ps
CPU time 0.7 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:29 PM PST 24
Peak memory 204212 kb
Host smart-77b9b717-4580-408c-a815-d9ad140dc940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637502863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
2637502863
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3938263766
Short name T166
Test name
Test status
Simulation time 17422941 ps
CPU time 0.78 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204252 kb
Host smart-f839b6af-26b7-4e92-ac2a-9466546502b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938263766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3938263766
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2954060660
Short name T201
Test name
Test status
Simulation time 23064133 ps
CPU time 0.86 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 204280 kb
Host smart-170862f1-d0c9-4eb8-b8c5-7549fc3ecf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954060660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2954060660
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.3754335347
Short name T254
Test name
Test status
Simulation time 308650352 ps
CPU time 5.23 seconds
Started Feb 05 03:24:46 PM PST 24
Finished Feb 05 03:24:53 PM PST 24
Peak memory 204364 kb
Host smart-c49cfc19-dece-4a10-9087-6b29770e64ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754335347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.3754335347
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3262858147
Short name T288
Test name
Test status
Simulation time 1331661469 ps
CPU time 17.47 seconds
Started Feb 05 03:24:48 PM PST 24
Finished Feb 05 03:25:07 PM PST 24
Peak memory 204468 kb
Host smart-720a6ee7-5a94-4fba-bd1b-fea6d44d4c35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262858147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3262858147
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3267154635
Short name T167
Test name
Test status
Simulation time 18729153 ps
CPU time 1 seconds
Started Feb 05 03:24:52 PM PST 24
Finished Feb 05 03:24:54 PM PST 24
Peak memory 204428 kb
Host smart-e68643af-0b1f-46a5-b3bc-95207d79debe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267154635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3267154635
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1318516512
Short name T182
Test name
Test status
Simulation time 17212290 ps
CPU time 0.98 seconds
Started Feb 05 03:24:57 PM PST 24
Finished Feb 05 03:24:59 PM PST 24
Peak memory 204356 kb
Host smart-01ef1624-bce5-4fa3-bc44-dd5363982272
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318516512 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1318516512
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.931850911
Short name T295
Test name
Test status
Simulation time 32317044 ps
CPU time 0.84 seconds
Started Feb 05 03:24:52 PM PST 24
Finished Feb 05 03:24:54 PM PST 24
Peak memory 204512 kb
Host smart-92084f63-5cd5-43c3-98eb-24d14ff7d2b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931850911 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.931850911
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1008397634
Short name T215
Test name
Test status
Simulation time 38067382 ps
CPU time 0.75 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:50 PM PST 24
Peak memory 204288 kb
Host smart-b9125239-d525-445a-87ce-6fed48ef5bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008397634 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
008397634
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3174170940
Short name T99
Test name
Test status
Simulation time 149953534 ps
CPU time 1.78 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:51 PM PST 24
Peak memory 204380 kb
Host smart-a541ac2e-d6aa-4472-b656-a178f428ca9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174170940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.3174170940
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.3779873422
Short name T185
Test name
Test status
Simulation time 100536554 ps
CPU time 3.37 seconds
Started Feb 05 03:24:43 PM PST 24
Finished Feb 05 03:24:48 PM PST 24
Peak memory 212932 kb
Host smart-e9c29cc5-2a34-44c3-9d5e-43f9f3b32549
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779873422 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.3779873422
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.4273932045
Short name T268
Test name
Test status
Simulation time 466686289 ps
CPU time 4.23 seconds
Started Feb 05 03:24:44 PM PST 24
Finished Feb 05 03:24:51 PM PST 24
Peak memory 213248 kb
Host smart-9520f82f-e7e6-4fb0-a59a-c408f0b45111
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273932045 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.4273932045
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2967327051
Short name T34
Test name
Test status
Simulation time 222253254 ps
CPU time 2.22 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:52 PM PST 24
Peak memory 213192 kb
Host smart-5451db28-26a4-4bbc-91c6-f1734fef01a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967327051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
967327051
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.1776219777
Short name T181
Test name
Test status
Simulation time 12221813 ps
CPU time 0.74 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 204264 kb
Host smart-a1385428-dd6a-46b9-a3f5-b9c837720514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776219777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
1776219777
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1694799737
Short name T274
Test name
Test status
Simulation time 18582021 ps
CPU time 0.75 seconds
Started Feb 05 03:25:30 PM PST 24
Finished Feb 05 03:25:33 PM PST 24
Peak memory 204272 kb
Host smart-15fa07cc-fe50-4d11-a35d-6b674e7b3db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694799737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1694799737
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.2314284251
Short name T208
Test name
Test status
Simulation time 32623312 ps
CPU time 0.77 seconds
Started Feb 05 03:25:33 PM PST 24
Finished Feb 05 03:25:36 PM PST 24
Peak memory 204232 kb
Host smart-2f29dde3-b210-4354-ba78-8c0b45c1128e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314284251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
2314284251
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.3258956513
Short name T277
Test name
Test status
Simulation time 39683449 ps
CPU time 0.82 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:34 PM PST 24
Peak memory 204236 kb
Host smart-04cf2e48-0494-4f5e-91f7-6d8fdfe18be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258956513 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
3258956513
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.2370387442
Short name T47
Test name
Test status
Simulation time 42791064 ps
CPU time 0.83 seconds
Started Feb 05 03:25:25 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 204188 kb
Host smart-03ff5b21-ae92-4871-9ef6-c9f23ccff618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370387442 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
2370387442
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.4123139369
Short name T243
Test name
Test status
Simulation time 30383074 ps
CPU time 0.7 seconds
Started Feb 05 03:25:26 PM PST 24
Finished Feb 05 03:25:28 PM PST 24
Peak memory 204228 kb
Host smart-655010d4-d434-4732-9e27-ab79cc935fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123139369 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
4123139369
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.60400697
Short name T230
Test name
Test status
Simulation time 11036005 ps
CPU time 0.73 seconds
Started Feb 05 03:25:31 PM PST 24
Finished Feb 05 03:25:33 PM PST 24
Peak memory 204304 kb
Host smart-8e6e5f01-9808-467e-9808-3aefe450b799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60400697 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.60400697
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3264897653
Short name T95
Test name
Test status
Simulation time 139545630 ps
CPU time 0.7 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204220 kb
Host smart-1265ca91-4dfa-444d-9480-f7a01be0a0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264897653 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3264897653
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.2706179813
Short name T171
Test name
Test status
Simulation time 15224671 ps
CPU time 0.68 seconds
Started Feb 05 03:25:27 PM PST 24
Finished Feb 05 03:25:30 PM PST 24
Peak memory 204264 kb
Host smart-2a06e2fe-234e-4cdb-beff-d0afd25c62c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706179813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
2706179813
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.4186539135
Short name T220
Test name
Test status
Simulation time 42860346 ps
CPU time 0.72 seconds
Started Feb 05 03:25:36 PM PST 24
Finished Feb 05 03:25:39 PM PST 24
Peak memory 204264 kb
Host smart-b9802ea6-b18b-408e-aaa4-30108a539d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186539135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
4186539135
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3742209438
Short name T210
Test name
Test status
Simulation time 20641792 ps
CPU time 1.47 seconds
Started Feb 05 03:24:39 PM PST 24
Finished Feb 05 03:24:41 PM PST 24
Peak memory 212764 kb
Host smart-85874485-e55c-4e72-bc90-bd29c084d68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742209438 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.3742209438
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.2471316578
Short name T211
Test name
Test status
Simulation time 13111357 ps
CPU time 1.13 seconds
Started Feb 05 03:24:41 PM PST 24
Finished Feb 05 03:24:43 PM PST 24
Peak memory 204404 kb
Host smart-d109de2c-2ef4-498a-880a-61c8e9ce85ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471316578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.2
471316578
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.606951290
Short name T183
Test name
Test status
Simulation time 14390697 ps
CPU time 0.88 seconds
Started Feb 05 03:24:40 PM PST 24
Finished Feb 05 03:24:42 PM PST 24
Peak memory 204416 kb
Host smart-611a7e24-720e-42dc-a137-bc038205604e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606951290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.606951290
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.404065353
Short name T278
Test name
Test status
Simulation time 317904289 ps
CPU time 2.06 seconds
Started Feb 05 03:24:40 PM PST 24
Finished Feb 05 03:24:44 PM PST 24
Peak memory 204484 kb
Host smart-6c010b5d-b756-49dc-b792-2677e9fb7221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404065353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_dpe_same_csr_outstanding.404065353
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3854023766
Short name T213
Test name
Test status
Simulation time 150911682 ps
CPU time 3.19 seconds
Started Feb 05 03:24:44 PM PST 24
Finished Feb 05 03:24:50 PM PST 24
Peak memory 212932 kb
Host smart-baa0b6b7-8b2f-4960-ae0f-ca2535a5ca30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854023766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3854023766
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.143440758
Short name T195
Test name
Test status
Simulation time 171746898 ps
CPU time 3.61 seconds
Started Feb 05 03:24:46 PM PST 24
Finished Feb 05 03:24:52 PM PST 24
Peak memory 213052 kb
Host smart-c7151d74-b045-4f42-8b1b-69f4a7b167f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143440758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.143440758
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2899623810
Short name T227
Test name
Test status
Simulation time 69082504 ps
CPU time 1.99 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:52 PM PST 24
Peak memory 212564 kb
Host smart-da05dce7-6f0b-45d7-921d-663fd2216f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899623810 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
899623810
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.2656299715
Short name T65
Test name
Test status
Simulation time 52226364 ps
CPU time 2.44 seconds
Started Feb 05 03:24:51 PM PST 24
Finished Feb 05 03:24:55 PM PST 24
Peak memory 212580 kb
Host smart-52b06bae-43f2-4b4d-96f5-aebb21542508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656299715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.2656299715
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.1081315703
Short name T283
Test name
Test status
Simulation time 42199651 ps
CPU time 1.02 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:51 PM PST 24
Peak memory 204316 kb
Host smart-2502754c-b75e-470a-a633-2e526bda057f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081315703 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.1081315703
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2763931552
Short name T238
Test name
Test status
Simulation time 14591890 ps
CPU time 1.06 seconds
Started Feb 05 03:24:42 PM PST 24
Finished Feb 05 03:24:46 PM PST 24
Peak memory 204368 kb
Host smart-4d574b7b-b8f9-412c-88b7-c4144b34e784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763931552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
763931552
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1005149477
Short name T302
Test name
Test status
Simulation time 9378287 ps
CPU time 0.81 seconds
Started Feb 05 03:24:39 PM PST 24
Finished Feb 05 03:24:40 PM PST 24
Peak memory 204276 kb
Host smart-589aba4e-6620-48f2-8577-d562d9629b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005149477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
005149477
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1043198320
Short name T306
Test name
Test status
Simulation time 75987333 ps
CPU time 3.1 seconds
Started Feb 05 03:24:39 PM PST 24
Finished Feb 05 03:24:43 PM PST 24
Peak memory 204320 kb
Host smart-6a0b8b6d-eee2-4d64-a394-6dc9eb486780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043198320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1043198320
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1530807848
Short name T245
Test name
Test status
Simulation time 69838977 ps
CPU time 1.49 seconds
Started Feb 05 03:24:45 PM PST 24
Finished Feb 05 03:24:49 PM PST 24
Peak memory 213004 kb
Host smart-f32632e5-b01d-4511-b22f-b470c638af08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530807848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1530807848
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3789929733
Short name T199
Test name
Test status
Simulation time 98327283 ps
CPU time 2.53 seconds
Started Feb 05 03:24:40 PM PST 24
Finished Feb 05 03:24:43 PM PST 24
Peak memory 212996 kb
Host smart-d478141c-07ce-427b-b839-9733b1667f31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789929733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3789929733
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.4144364563
Short name T231
Test name
Test status
Simulation time 65650641 ps
CPU time 2.15 seconds
Started Feb 05 03:24:42 PM PST 24
Finished Feb 05 03:24:47 PM PST 24
Peak memory 212724 kb
Host smart-9ccab3ae-0011-47b5-95c4-1a145b88f832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144364563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.4
144364563
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4119557119
Short name T64
Test name
Test status
Simulation time 111097391 ps
CPU time 2.71 seconds
Started Feb 05 03:24:43 PM PST 24
Finished Feb 05 03:24:48 PM PST 24
Peak memory 212596 kb
Host smart-e884da2d-9c48-4d8a-a126-163dfb1e8068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119557119 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.4119557119
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1333704963
Short name T36
Test name
Test status
Simulation time 136666590 ps
CPU time 1.48 seconds
Started Feb 05 03:24:48 PM PST 24
Finished Feb 05 03:24:51 PM PST 24
Peak memory 212704 kb
Host smart-e977abeb-0d6e-41d6-861a-905a72c7c065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333704963 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1333704963
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.3818160658
Short name T206
Test name
Test status
Simulation time 97861962 ps
CPU time 1.34 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:51 PM PST 24
Peak memory 204352 kb
Host smart-a7a54a53-96e2-4c39-8afd-a24fd0de5bad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818160658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.3
818160658
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.454102035
Short name T177
Test name
Test status
Simulation time 39651940 ps
CPU time 0.8 seconds
Started Feb 05 03:24:45 PM PST 24
Finished Feb 05 03:24:49 PM PST 24
Peak memory 204236 kb
Host smart-4baef5a5-67e4-4881-b1af-e1c337be8976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454102035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.454102035
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3477527106
Short name T204
Test name
Test status
Simulation time 71623212 ps
CPU time 1.89 seconds
Started Feb 05 03:24:52 PM PST 24
Finished Feb 05 03:24:55 PM PST 24
Peak memory 204556 kb
Host smart-19ac4988-847b-4c8e-915c-6225500b760d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477527106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.3477527106
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.894204804
Short name T50
Test name
Test status
Simulation time 126971580 ps
CPU time 1.33 seconds
Started Feb 05 03:24:56 PM PST 24
Finished Feb 05 03:24:58 PM PST 24
Peak memory 213000 kb
Host smart-aad19a22-af7b-4959-923a-2ec5d25842db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894204804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymg
r_dpe_shadow_reg_errors.894204804
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1027186715
Short name T271
Test name
Test status
Simulation time 199393866 ps
CPU time 3.03 seconds
Started Feb 05 03:24:47 PM PST 24
Finished Feb 05 03:24:53 PM PST 24
Peak memory 212960 kb
Host smart-71c6b793-70c4-4721-85eb-7271ac3d0d2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027186715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1027186715
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.812911985
Short name T287
Test name
Test status
Simulation time 125528851 ps
CPU time 2.44 seconds
Started Feb 05 03:24:44 PM PST 24
Finished Feb 05 03:24:50 PM PST 24
Peak memory 212660 kb
Host smart-0e0de2cd-adcb-4f44-9f3e-0311e3b76342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812911985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.812911985
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.2987716846
Short name T49
Test name
Test status
Simulation time 365435711 ps
CPU time 4.9 seconds
Started Feb 05 03:24:40 PM PST 24
Finished Feb 05 03:24:46 PM PST 24
Peak memory 213884 kb
Host smart-d852f4cc-8134-47e7-9082-3843c4e59fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987716846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.2987716846
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.641077273
Short name T43
Test name
Test status
Simulation time 114710919 ps
CPU time 1.91 seconds
Started Feb 05 03:24:53 PM PST 24
Finished Feb 05 03:24:57 PM PST 24
Peak memory 212756 kb
Host smart-6c259e9c-5b88-43c3-b186-b7637938f154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641077273 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.641077273
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1780008623
Short name T86
Test name
Test status
Simulation time 13963483 ps
CPU time 0.86 seconds
Started Feb 05 03:25:00 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 204224 kb
Host smart-9a9352a7-dd53-41bb-b2b5-fb524a1248d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780008623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
780008623
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.1491877130
Short name T87
Test name
Test status
Simulation time 42405197 ps
CPU time 0.8 seconds
Started Feb 05 03:24:54 PM PST 24
Finished Feb 05 03:24:56 PM PST 24
Peak memory 204268 kb
Host smart-01c95e56-0675-4f84-b532-938519f00c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491877130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.1
491877130
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.178075067
Short name T262
Test name
Test status
Simulation time 31602550 ps
CPU time 1.67 seconds
Started Feb 05 03:24:52 PM PST 24
Finished Feb 05 03:24:54 PM PST 24
Peak memory 204460 kb
Host smart-b455afdd-7144-4f14-a7ec-23e78c8c0762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178075067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.178075067
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.3203008529
Short name T276
Test name
Test status
Simulation time 92923696 ps
CPU time 1.69 seconds
Started Feb 05 03:24:56 PM PST 24
Finished Feb 05 03:24:59 PM PST 24
Peak memory 213116 kb
Host smart-514f7c37-38e8-44c1-8c7e-d1fa7ad6cf3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203008529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.3203008529
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3737155598
Short name T250
Test name
Test status
Simulation time 61204112 ps
CPU time 2.36 seconds
Started Feb 05 03:24:48 PM PST 24
Finished Feb 05 03:24:52 PM PST 24
Peak memory 215296 kb
Host smart-d8157311-e9ff-4c27-937e-71a0f105bed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737155598 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
737155598
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3237460040
Short name T214
Test name
Test status
Simulation time 23499966 ps
CPU time 1.08 seconds
Started Feb 05 03:24:59 PM PST 24
Finished Feb 05 03:25:01 PM PST 24
Peak memory 212568 kb
Host smart-345222d8-23a1-475e-9eff-16d832e37b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237460040 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.3237460040
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.4027324453
Short name T84
Test name
Test status
Simulation time 48627004 ps
CPU time 1.33 seconds
Started Feb 05 03:24:58 PM PST 24
Finished Feb 05 03:25:00 PM PST 24
Peak memory 204372 kb
Host smart-ca784187-05b2-430a-8abe-77a2022b38e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027324453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.4
027324453
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.3091751352
Short name T237
Test name
Test status
Simulation time 49355099 ps
CPU time 0.76 seconds
Started Feb 05 03:25:01 PM PST 24
Finished Feb 05 03:25:04 PM PST 24
Peak memory 204224 kb
Host smart-9308cc0b-d931-485a-b9cd-5f2492f771c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091751352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.3
091751352
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.1165090437
Short name T89
Test name
Test status
Simulation time 213053991 ps
CPU time 1.7 seconds
Started Feb 05 03:24:59 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 204408 kb
Host smart-8ac578dc-4526-4b0a-ae41-af6f11fe502b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165090437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.1165090437
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.1740427816
Short name T255
Test name
Test status
Simulation time 90952765 ps
CPU time 2.12 seconds
Started Feb 05 03:24:59 PM PST 24
Finished Feb 05 03:25:02 PM PST 24
Peak memory 213012 kb
Host smart-e43451b3-480f-46f7-972b-26af33325e82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740427816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.1740427816
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2679970054
Short name T178
Test name
Test status
Simulation time 134355007 ps
CPU time 4.35 seconds
Started Feb 05 03:24:54 PM PST 24
Finished Feb 05 03:25:00 PM PST 24
Peak memory 212968 kb
Host smart-52901efe-8970-4ce9-a2ba-24d2bd94335e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679970054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2679970054
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.2306127368
Short name T192
Test name
Test status
Simulation time 191284853 ps
CPU time 2.78 seconds
Started Feb 05 03:24:55 PM PST 24
Finished Feb 05 03:24:59 PM PST 24
Peak memory 212712 kb
Host smart-f754d0ed-9d3f-4c76-9ad4-2f98eb84ba4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306127368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.2
306127368
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2581998238
Short name T130
Test name
Test status
Simulation time 32072501 ps
CPU time 0.82 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:35:01 PM PST 24
Peak memory 204960 kb
Host smart-ed7a2555-1cf3-4226-bee6-537dbeff030a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581998238 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
581998238
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2068983769
Short name T159
Test name
Test status
Simulation time 52168529 ps
CPU time 0.9 seconds
Started Feb 05 12:34:49 PM PST 24
Finished Feb 05 12:35:09 PM PST 24
Peak memory 205164 kb
Host smart-a5c7f6c6-4f74-459b-980c-9493e8cff2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068983769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
068983769
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1870375118
Short name T21
Test name
Test status
Simulation time 913761877 ps
CPU time 5.62 seconds
Started Feb 05 12:34:52 PM PST 24
Finished Feb 05 12:35:15 PM PST 24
Peak memory 228336 kb
Host smart-0c50b4db-854e-401b-a63b-22924bf30c8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870375118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1870375118
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.300817801
Short name T160
Test name
Test status
Simulation time 41290320 ps
CPU time 0.91 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205512 kb
Host smart-b79200b0-0e50-4164-838d-6c641015a5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300817801 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.300817801
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.3879291810
Short name T134
Test name
Test status
Simulation time 15676815721 ps
CPU time 64.43 seconds
Started Feb 05 12:34:49 PM PST 24
Finished Feb 05 12:36:13 PM PST 24
Peak memory 208076 kb
Host smart-eead11f6-49a6-4c3d-a6db-d6b47fa6692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879291810 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.3879291810
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2974202453
Short name T123
Test name
Test status
Simulation time 13040050 ps
CPU time 0.79 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:12 PM PST 24
Peak memory 205208 kb
Host smart-d3d1ab2d-34b3-47d0-9cb3-48d8173e4bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974202453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2974202453
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.3468602043
Short name T82
Test name
Test status
Simulation time 2955259125 ps
CPU time 29.92 seconds
Started Feb 05 12:34:59 PM PST 24
Finished Feb 05 12:35:47 PM PST 24
Peak memory 206244 kb
Host smart-c0c8bc2e-993e-4462-b860-97eb4765e28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468602043 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.3468602043
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.3001754204
Short name T162
Test name
Test status
Simulation time 52112478 ps
CPU time 0.8 seconds
Started Feb 05 12:34:57 PM PST 24
Finished Feb 05 12:35:14 PM PST 24
Peak memory 205184 kb
Host smart-2299e532-befc-40f6-840e-508957efd9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001754204 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
3001754204
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.3192579638
Short name T145
Test name
Test status
Simulation time 40796094 ps
CPU time 0.81 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205220 kb
Host smart-f22520c2-466f-40dc-9d58-1d274fbd9941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192579638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
3192579638
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3978267622
Short name T10
Test name
Test status
Simulation time 491617929 ps
CPU time 15.22 seconds
Started Feb 05 12:34:49 PM PST 24
Finished Feb 05 12:35:23 PM PST 24
Peak memory 206192 kb
Host smart-b8758f0a-5422-4873-8624-1d24395e5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978267622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3978267622
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3521059287
Short name T141
Test name
Test status
Simulation time 24024455 ps
CPU time 0.74 seconds
Started Feb 05 12:34:51 PM PST 24
Finished Feb 05 12:35:10 PM PST 24
Peak memory 205536 kb
Host smart-ab66dbce-097e-4662-855e-2e2f9e3915e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521059287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3521059287
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.229983677
Short name T117
Test name
Test status
Simulation time 779325517 ps
CPU time 22.75 seconds
Started Feb 05 12:34:51 PM PST 24
Finished Feb 05 12:35:32 PM PST 24
Peak memory 207324 kb
Host smart-bd9648b7-75cd-4588-9a51-8a32d2fd5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229983677 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.229983677
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1173595038
Short name T156
Test name
Test status
Simulation time 53777071 ps
CPU time 0.93 seconds
Started Feb 05 12:34:51 PM PST 24
Finished Feb 05 12:35:10 PM PST 24
Peak memory 205536 kb
Host smart-5208665f-ad13-4d6a-bea3-0f15407ebf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173595038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1173595038
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3669721379
Short name T9
Test name
Test status
Simulation time 1160629514 ps
CPU time 20.08 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:32 PM PST 24
Peak memory 207792 kb
Host smart-1441c92a-11d8-4d7f-b066-e46806b35a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669721379 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3669721379
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.2146935886
Short name T137
Test name
Test status
Simulation time 12192206 ps
CPU time 0.89 seconds
Started Feb 05 12:34:49 PM PST 24
Finished Feb 05 12:35:09 PM PST 24
Peak memory 205300 kb
Host smart-de403308-8000-4edf-a952-51d98883d05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146935886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
2146935886
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2935117115
Short name T74
Test name
Test status
Simulation time 13065494 ps
CPU time 0.78 seconds
Started Feb 05 12:34:50 PM PST 24
Finished Feb 05 12:35:09 PM PST 24
Peak memory 205168 kb
Host smart-64bc4c4d-83d1-4332-9c79-1f618698c31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935117115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2935117115
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2625611420
Short name T157
Test name
Test status
Simulation time 9722514 ps
CPU time 0.84 seconds
Started Feb 05 12:34:57 PM PST 24
Finished Feb 05 12:35:14 PM PST 24
Peak memory 205244 kb
Host smart-59ca4264-18cc-47ed-82ab-f46d63c329aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625611420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2625611420
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.1506012217
Short name T75
Test name
Test status
Simulation time 8932438 ps
CPU time 0.81 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:35:01 PM PST 24
Peak memory 205224 kb
Host smart-9cb3daf9-de9e-4429-b681-a9b087e91646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506012217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
1506012217
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3476254159
Short name T139
Test name
Test status
Simulation time 373174735 ps
CPU time 13.4 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:25 PM PST 24
Peak memory 205992 kb
Host smart-63fe2eb6-f0dc-498d-9a48-36cddb1aa9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476254159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3476254159
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.2424290465
Short name T23
Test name
Test status
Simulation time 40712034 ps
CPU time 0.86 seconds
Started Feb 05 12:34:33 PM PST 24
Finished Feb 05 12:34:53 PM PST 24
Peak memory 205300 kb
Host smart-11edd4d0-de67-4115-a157-de704d306db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424290465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.2
424290465
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3398554582
Short name T7
Test name
Test status
Simulation time 2113241727 ps
CPU time 16.66 seconds
Started Feb 05 12:34:50 PM PST 24
Finished Feb 05 12:35:25 PM PST 24
Peak memory 234324 kb
Host smart-fcdc798e-99b6-4055-aa01-7374c700887b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398554582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3398554582
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.4254323093
Short name T32
Test name
Test status
Simulation time 1367131762 ps
CPU time 12.65 seconds
Started Feb 05 12:34:45 PM PST 24
Finished Feb 05 12:35:18 PM PST 24
Peak memory 206684 kb
Host smart-54a83e75-7b23-41ac-ae16-a5939e5371ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254323093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.4254323093
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.1508011578
Short name T28
Test name
Test status
Simulation time 1467901824 ps
CPU time 23.33 seconds
Started Feb 05 12:35:04 PM PST 24
Finished Feb 05 12:35:47 PM PST 24
Peak memory 208008 kb
Host smart-16388b3f-a9c7-4f7f-9950-626065d33949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508011578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.1508011578
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2177979241
Short name T161
Test name
Test status
Simulation time 13443973 ps
CPU time 0.99 seconds
Started Feb 05 12:34:55 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205168 kb
Host smart-c9658094-3a70-4c27-ae4c-ba42f8c25faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177979241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2177979241
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2914557795
Short name T24
Test name
Test status
Simulation time 19524076 ps
CPU time 0.84 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:35:01 PM PST 24
Peak memory 205244 kb
Host smart-ad276223-67ca-43bd-942b-e35cee85085d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914557795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2914557795
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.1726787106
Short name T140
Test name
Test status
Simulation time 14987127 ps
CPU time 0.93 seconds
Started Feb 05 12:34:46 PM PST 24
Finished Feb 05 12:35:07 PM PST 24
Peak memory 205336 kb
Host smart-1ee524de-af26-4dd9-8d48-c633f4b5b16d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726787106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
1726787106
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.211173813
Short name T80
Test name
Test status
Simulation time 2238236294 ps
CPU time 21.63 seconds
Started Feb 05 12:34:59 PM PST 24
Finished Feb 05 12:35:38 PM PST 24
Peak memory 207120 kb
Host smart-d4c911c6-d05a-4586-8cec-b0f9692dee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211173813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.211173813
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1659240312
Short name T124
Test name
Test status
Simulation time 65909940 ps
CPU time 0.83 seconds
Started Feb 05 12:34:59 PM PST 24
Finished Feb 05 12:35:17 PM PST 24
Peak memory 205112 kb
Host smart-35ccd5b9-ee3c-4430-96a6-5c9d5c78bac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659240312 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1659240312
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.3411696222
Short name T129
Test name
Test status
Simulation time 586491169 ps
CPU time 9.83 seconds
Started Feb 05 12:35:00 PM PST 24
Finished Feb 05 12:35:27 PM PST 24
Peak memory 206636 kb
Host smart-61ac1e7b-b7b7-4ab6-a157-6a72978f4681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411696222 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.3411696222
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.155422223
Short name T146
Test name
Test status
Simulation time 19923066 ps
CPU time 0.8 seconds
Started Feb 05 12:34:45 PM PST 24
Finished Feb 05 12:35:06 PM PST 24
Peak memory 205152 kb
Host smart-03ca12c6-01a2-4108-96d1-80f921c99f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155422223 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.155422223
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.1032110848
Short name T120
Test name
Test status
Simulation time 22015300 ps
CPU time 0.86 seconds
Started Feb 05 12:34:55 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205156 kb
Host smart-c66961b8-9116-46d7-bb87-f672d6f1027e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032110848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
1032110848
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1546446316
Short name T126
Test name
Test status
Simulation time 10633420 ps
CPU time 0.81 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:14 PM PST 24
Peak memory 205196 kb
Host smart-39c37624-8986-4f17-a153-ffec0cbde400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546446316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1546446316
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.471232345
Short name T136
Test name
Test status
Simulation time 11235029 ps
CPU time 0.7 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205224 kb
Host smart-fec7b512-600c-4826-a155-ac0a5e41e528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471232345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.471232345
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.3061537457
Short name T12
Test name
Test status
Simulation time 4275332700 ps
CPU time 39.97 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:36:00 PM PST 24
Peak memory 207720 kb
Host smart-74aca779-dd93-4445-a537-2677abaeea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061537457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.3061537457
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.4098595186
Short name T25
Test name
Test status
Simulation time 20687138 ps
CPU time 1.03 seconds
Started Feb 05 12:35:13 PM PST 24
Finished Feb 05 12:35:39 PM PST 24
Peak memory 205336 kb
Host smart-4580ec83-71a0-4e5f-bcc5-e0f1168423f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098595186 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
4098595186
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3088073995
Short name T40
Test name
Test status
Simulation time 1622886640 ps
CPU time 15.22 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:35:41 PM PST 24
Peak memory 206680 kb
Host smart-d2616878-c60b-451c-a87c-19631e3ed2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088073995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3088073995
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1042833802
Short name T26
Test name
Test status
Simulation time 67984380 ps
CPU time 0.86 seconds
Started Feb 05 12:34:58 PM PST 24
Finished Feb 05 12:35:16 PM PST 24
Peak memory 205436 kb
Host smart-527005ba-956e-461c-a54d-e267b015d8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042833802 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
042833802
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.1387616626
Short name T22
Test name
Test status
Simulation time 1043598213 ps
CPU time 15.18 seconds
Started Feb 05 12:34:45 PM PST 24
Finished Feb 05 12:35:20 PM PST 24
Peak memory 232504 kb
Host smart-db0ef0b6-7ef1-42c8-acea-fe85c268735b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387616626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.1387616626
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2106688504
Short name T112
Test name
Test status
Simulation time 4358175868 ps
CPU time 23.61 seconds
Started Feb 05 12:34:35 PM PST 24
Finished Feb 05 12:35:17 PM PST 24
Peak memory 207156 kb
Host smart-2174a1d8-d782-44a7-b6da-0fd2963c3a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106688504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2106688504
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3553028065
Short name T148
Test name
Test status
Simulation time 44456508 ps
CPU time 0.77 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:35:26 PM PST 24
Peak memory 205236 kb
Host smart-b4c47c10-273b-4e0b-a231-e5e725c93b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553028065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3553028065
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.798779558
Short name T103
Test name
Test status
Simulation time 3305597144 ps
CPU time 18.73 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:35:39 PM PST 24
Peak memory 206060 kb
Host smart-92741846-d775-4bb9-ab3b-2beade9df33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798779558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.798779558
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.170945543
Short name T1
Test name
Test status
Simulation time 26785439 ps
CPU time 0.78 seconds
Started Feb 05 12:34:50 PM PST 24
Finished Feb 05 12:35:09 PM PST 24
Peak memory 205232 kb
Host smart-d6c4d617-b5bc-4a0e-aacc-9494f4bd553a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170945543 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.170945543
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.416911212
Short name T116
Test name
Test status
Simulation time 36487389 ps
CPU time 0.83 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:12 PM PST 24
Peak memory 205240 kb
Host smart-f1cb0dc8-845e-4594-82ad-b107f129d7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416911212 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.416911212
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.3271918178
Short name T143
Test name
Test status
Simulation time 1104153056 ps
CPU time 16.76 seconds
Started Feb 05 12:35:09 PM PST 24
Finished Feb 05 12:35:47 PM PST 24
Peak memory 205980 kb
Host smart-4264d4ff-04cb-4c37-898a-e6f887074be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271918178 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.3271918178
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.744132316
Short name T128
Test name
Test status
Simulation time 97786528 ps
CPU time 0.77 seconds
Started Feb 05 12:34:59 PM PST 24
Finished Feb 05 12:35:17 PM PST 24
Peak memory 205120 kb
Host smart-9f9f83b4-440c-479e-92e3-47490a3a58c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744132316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.744132316
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.2936676803
Short name T13
Test name
Test status
Simulation time 4467300787 ps
CPU time 23.52 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:35:45 PM PST 24
Peak memory 207540 kb
Host smart-187f9dca-af1d-4c27-986d-7bb438fbcf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936676803 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2936676803
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.3365512028
Short name T16
Test name
Test status
Simulation time 14827225 ps
CPU time 0.83 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:35:22 PM PST 24
Peak memory 205208 kb
Host smart-460ff6f0-4d7b-4621-9ab6-d5aab3ca5927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365512028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
3365512028
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.4103919709
Short name T79
Test name
Test status
Simulation time 2901973526 ps
CPU time 23.99 seconds
Started Feb 05 12:35:01 PM PST 24
Finished Feb 05 12:35:44 PM PST 24
Peak memory 206232 kb
Host smart-5a5b5538-6b9c-4b7d-b225-c8471a61a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103919709 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.4103919709
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.883237019
Short name T121
Test name
Test status
Simulation time 18934936 ps
CPU time 0.79 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:35:26 PM PST 24
Peak memory 205116 kb
Host smart-11234331-fdfb-4f04-b3b1-d11ab9544daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883237019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.883237019
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.1948866807
Short name T15
Test name
Test status
Simulation time 11007162 ps
CPU time 0.71 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 205116 kb
Host smart-10fcc98c-987b-4bb6-9e14-cb4be481b3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948866807 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
1948866807
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1228697373
Short name T113
Test name
Test status
Simulation time 8762984836 ps
CPU time 27.81 seconds
Started Feb 05 12:34:58 PM PST 24
Finished Feb 05 12:35:43 PM PST 24
Peak memory 207128 kb
Host smart-e99649e3-52a6-40ad-a822-5fda0da8b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228697373 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1228697373
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.3168406702
Short name T127
Test name
Test status
Simulation time 90706778 ps
CPU time 0.85 seconds
Started Feb 05 12:35:04 PM PST 24
Finished Feb 05 12:35:23 PM PST 24
Peak memory 205160 kb
Host smart-585404fa-4d5e-4bd8-acfe-2d6991694132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168406702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
3168406702
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.3984297347
Short name T150
Test name
Test status
Simulation time 411806662 ps
CPU time 14.8 seconds
Started Feb 05 12:34:54 PM PST 24
Finished Feb 05 12:35:27 PM PST 24
Peak memory 207636 kb
Host smart-b97fa1e4-9630-420e-88c1-bc530dd61cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984297347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.3984297347
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.72316759
Short name T151
Test name
Test status
Simulation time 13827665 ps
CPU time 0.9 seconds
Started Feb 05 12:34:58 PM PST 24
Finished Feb 05 12:35:16 PM PST 24
Peak memory 205300 kb
Host smart-0f02b55a-7304-4b8d-b180-462894e319b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72316759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.72316759
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.3632631649
Short name T4
Test name
Test status
Simulation time 3181562563 ps
CPU time 28.54 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:35:49 PM PST 24
Peak memory 207824 kb
Host smart-b80a7970-4c02-411d-90e3-8321a8bde811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632631649 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.3632631649
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1575654191
Short name T149
Test name
Test status
Simulation time 17352114 ps
CPU time 0.8 seconds
Started Feb 05 12:34:55 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205272 kb
Host smart-5f49932e-ca1f-4b6e-a2cc-d5ab07dba4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575654191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1575654191
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.2424414908
Short name T132
Test name
Test status
Simulation time 424716564 ps
CPU time 10.97 seconds
Started Feb 05 12:34:49 PM PST 24
Finished Feb 05 12:35:19 PM PST 24
Peak memory 205924 kb
Host smart-f1fdfd20-7188-47e5-b6c1-6bba52aca3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424414908 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.2424414908
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.771728253
Short name T29
Test name
Test status
Simulation time 15659695 ps
CPU time 0.78 seconds
Started Feb 05 12:34:31 PM PST 24
Finished Feb 05 12:34:52 PM PST 24
Peak memory 205072 kb
Host smart-f734aaa1-b0f0-4686-8749-6213dada6faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771728253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.771728253
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3489961983
Short name T133
Test name
Test status
Simulation time 286437150 ps
CPU time 12.6 seconds
Started Feb 05 12:34:51 PM PST 24
Finished Feb 05 12:35:22 PM PST 24
Peak memory 208224 kb
Host smart-5569094c-0efe-45ba-b091-f64fcc7fefdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489961983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3489961983
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.3133775780
Short name T122
Test name
Test status
Simulation time 13286281 ps
CPU time 0.9 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 205148 kb
Host smart-4f95fcd6-d001-4e70-a39b-facf96826365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133775780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
3133775780
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2564473975
Short name T153
Test name
Test status
Simulation time 685372513 ps
CPU time 22.98 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:35:44 PM PST 24
Peak memory 207576 kb
Host smart-f2bd3d06-f75b-4c9d-912d-88cfaa3f4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564473975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2564473975
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3154958383
Short name T125
Test name
Test status
Simulation time 17400520 ps
CPU time 0.94 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 205380 kb
Host smart-a5b00060-1eea-4165-bacc-a25a2df1f08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154958383 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3154958383
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.3946754121
Short name T104
Test name
Test status
Simulation time 602342551 ps
CPU time 21 seconds
Started Feb 05 12:35:01 PM PST 24
Finished Feb 05 12:35:41 PM PST 24
Peak memory 207344 kb
Host smart-c32dcc22-a678-4f2e-8f64-82410156d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946754121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.3946754121
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.2204006402
Short name T119
Test name
Test status
Simulation time 41912009 ps
CPU time 0.82 seconds
Started Feb 05 12:35:00 PM PST 24
Finished Feb 05 12:35:18 PM PST 24
Peak memory 205076 kb
Host smart-02d84356-ca32-4414-adfa-118c9b9973a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204006402 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
2204006402
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1562060190
Short name T76
Test name
Test status
Simulation time 5745240921 ps
CPU time 91.77 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:36:57 PM PST 24
Peak memory 207332 kb
Host smart-57715d1f-4acf-4ccd-9543-1d9499f46a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562060190 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1562060190
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2023149044
Short name T138
Test name
Test status
Simulation time 12533922 ps
CPU time 0.78 seconds
Started Feb 05 12:34:57 PM PST 24
Finished Feb 05 12:35:15 PM PST 24
Peak memory 205148 kb
Host smart-78cb9ef6-c9dc-41fa-9cb6-df0ea2b94f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023149044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2023149044
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2598872548
Short name T39
Test name
Test status
Simulation time 70010566 ps
CPU time 0.74 seconds
Started Feb 05 12:35:06 PM PST 24
Finished Feb 05 12:35:28 PM PST 24
Peak memory 205180 kb
Host smart-c0fe0c33-a5df-4694-a8b1-1f0d8e58f84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598872548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2598872548
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2986201905
Short name T81
Test name
Test status
Simulation time 384852680 ps
CPU time 14.89 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:35:36 PM PST 24
Peak memory 208248 kb
Host smart-47d533a9-b587-4667-88e9-5caf131b2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986201905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2986201905
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.2478509902
Short name T154
Test name
Test status
Simulation time 11903766 ps
CPU time 0.73 seconds
Started Feb 05 12:35:06 PM PST 24
Finished Feb 05 12:35:27 PM PST 24
Peak memory 205160 kb
Host smart-0795a907-c6fb-4496-9fb9-e51f9153bd6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478509902 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
2478509902
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3150198187
Short name T131
Test name
Test status
Simulation time 20448227 ps
CPU time 0.75 seconds
Started Feb 05 12:35:02 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 205112 kb
Host smart-d4342814-3e0b-4071-bef9-ca86f3b8a47c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150198187 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3150198187
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.955441698
Short name T14
Test name
Test status
Simulation time 1002802355 ps
CPU time 25.64 seconds
Started Feb 05 12:35:06 PM PST 24
Finished Feb 05 12:35:52 PM PST 24
Peak memory 207828 kb
Host smart-f4e25b0f-8ccb-4868-82ff-37185be3364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955441698 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.955441698
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1030426824
Short name T142
Test name
Test status
Simulation time 18741860 ps
CPU time 0.84 seconds
Started Feb 05 12:35:01 PM PST 24
Finished Feb 05 12:35:21 PM PST 24
Peak memory 205208 kb
Host smart-e75baaaa-a76e-4a96-8096-68030a6fe5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030426824 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1030426824
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.2294565498
Short name T114
Test name
Test status
Simulation time 18355066271 ps
CPU time 131.5 seconds
Started Feb 05 12:35:03 PM PST 24
Finished Feb 05 12:37:32 PM PST 24
Peak memory 208268 kb
Host smart-ff9277a8-910f-4234-9ef3-7cb2dc0acd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294565498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.2294565498
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2014554310
Short name T147
Test name
Test status
Simulation time 77960231 ps
CPU time 0.89 seconds
Started Feb 05 12:35:05 PM PST 24
Finished Feb 05 12:35:26 PM PST 24
Peak memory 205132 kb
Host smart-7ea01675-2c2c-499a-a762-a8bc66691dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014554310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2014554310
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.1654963352
Short name T155
Test name
Test status
Simulation time 14370310698 ps
CPU time 125.44 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:37:18 PM PST 24
Peak memory 221788 kb
Host smart-5bc6715f-41d9-44d6-aebc-b7ee990a75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654963352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.1654963352
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.2085319297
Short name T152
Test name
Test status
Simulation time 25146419 ps
CPU time 0.89 seconds
Started Feb 05 12:35:11 PM PST 24
Finished Feb 05 12:35:35 PM PST 24
Peak memory 205184 kb
Host smart-c4111245-ce26-4b05-bcf0-992648f6637d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085319297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
2085319297
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.4019541889
Short name T118
Test name
Test status
Simulation time 13368259 ps
CPU time 0.8 seconds
Started Feb 05 12:34:53 PM PST 24
Finished Feb 05 12:35:11 PM PST 24
Peak memory 205168 kb
Host smart-778cfd4e-266c-42bf-97c5-64559ebd2f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019541889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.4
019541889
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1925182973
Short name T144
Test name
Test status
Simulation time 41225230 ps
CPU time 0.88 seconds
Started Feb 05 12:34:38 PM PST 24
Finished Feb 05 12:34:58 PM PST 24
Peak memory 205148 kb
Host smart-0eb55f51-7043-4fbc-9b4c-d11191e09d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925182973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
925182973
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.3373175103
Short name T158
Test name
Test status
Simulation time 12663839 ps
CPU time 0.75 seconds
Started Feb 05 12:34:45 PM PST 24
Finished Feb 05 12:35:06 PM PST 24
Peak memory 205164 kb
Host smart-eea0c57d-d71e-49fa-a5dd-517728fe88fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373175103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.3
373175103
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.411158522
Short name T17
Test name
Test status
Simulation time 10726059 ps
CPU time 0.81 seconds
Started Feb 05 12:34:52 PM PST 24
Finished Feb 05 12:35:10 PM PST 24
Peak memory 205216 kb
Host smart-fbe8301b-fb67-46b5-ac9d-bcc84e6fe4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411158522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.411158522
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3383464177
Short name T110
Test name
Test status
Simulation time 2182306423 ps
CPU time 18.24 seconds
Started Feb 05 12:34:58 PM PST 24
Finished Feb 05 12:35:34 PM PST 24
Peak memory 207176 kb
Host smart-f321851d-dd36-478b-ac78-1747c85631a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383464177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3383464177
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.3664167387
Short name T30
Test name
Test status
Simulation time 11496779 ps
CPU time 0.82 seconds
Started Feb 05 12:34:56 PM PST 24
Finished Feb 05 12:35:13 PM PST 24
Peak memory 205404 kb
Host smart-ab228b21-d686-4697-bdc9-e04d5d73a016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664167387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.3
664167387
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.2682782499
Short name T135
Test name
Test status
Simulation time 12968105017 ps
CPU time 172.03 seconds
Started Feb 05 12:34:41 PM PST 24
Finished Feb 05 12:37:54 PM PST 24
Peak memory 207960 kb
Host smart-3c8f0b66-5e8f-4a58-a8b3-0eb2d0bea832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682782499 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.2682782499
Directory /workspace/9.keymgr_dpe_smoke/latest
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