Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.27 97.70 90.62 57.52 76.92 94.94 98.34 17.85


Total test records in report: 308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3630384929 Feb 08 12:32:29 PM PST 24 Feb 08 12:32:51 PM PST 24 312561550 ps
T256 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2986798511 Feb 08 12:32:27 PM PST 24 Feb 08 12:32:58 PM PST 24 3542305975 ps
T257 /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3746477987 Feb 08 12:32:37 PM PST 24 Feb 08 12:33:00 PM PST 24 12276994 ps
T258 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2452600552 Feb 08 12:32:42 PM PST 24 Feb 08 12:33:09 PM PST 24 37258117 ps
T259 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.279055308 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:02 PM PST 24 556605193 ps
T260 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1249196891 Feb 08 12:32:23 PM PST 24 Feb 08 12:33:00 PM PST 24 3156373771 ps
T261 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.4248524141 Feb 08 12:32:25 PM PST 24 Feb 08 12:32:45 PM PST 24 27521891 ps
T262 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1152915563 Feb 08 12:32:28 PM PST 24 Feb 08 12:32:47 PM PST 24 18012668 ps
T263 /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.1725923072 Feb 08 12:31:58 PM PST 24 Feb 08 12:32:31 PM PST 24 10209619 ps
T264 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3608237866 Feb 08 12:32:29 PM PST 24 Feb 08 12:33:07 PM PST 24 9160322827 ps
T265 /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1051886335 Feb 08 12:32:39 PM PST 24 Feb 08 12:33:06 PM PST 24 25113492 ps
T266 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.570127935 Feb 08 12:32:31 PM PST 24 Feb 08 12:32:55 PM PST 24 89813589 ps
T267 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2845642532 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:02 PM PST 24 89737564 ps
T268 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1662246567 Feb 08 12:32:26 PM PST 24 Feb 08 12:32:48 PM PST 24 336854292 ps
T269 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1695492089 Feb 08 12:32:45 PM PST 24 Feb 08 12:33:11 PM PST 24 28621397 ps
T270 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2327066496 Feb 08 12:32:42 PM PST 24 Feb 08 12:33:08 PM PST 24 11049359 ps
T271 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.3422823196 Feb 08 12:32:45 PM PST 24 Feb 08 12:33:11 PM PST 24 36921687 ps
T272 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2407573499 Feb 08 12:32:30 PM PST 24 Feb 08 12:32:50 PM PST 24 40428068 ps
T42 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.1162706054 Feb 08 12:32:37 PM PST 24 Feb 08 12:33:02 PM PST 24 323502936 ps
T273 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2127204184 Feb 08 12:32:24 PM PST 24 Feb 08 12:32:46 PM PST 24 160489247 ps
T274 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3164746224 Feb 08 12:32:26 PM PST 24 Feb 08 12:32:46 PM PST 24 38379011 ps
T53 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2620051080 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:04 PM PST 24 122594809 ps
T275 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.778416355 Feb 08 12:32:28 PM PST 24 Feb 08 12:32:47 PM PST 24 86265803 ps
T276 /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.2386366318 Feb 08 12:32:37 PM PST 24 Feb 08 12:32:59 PM PST 24 12174388 ps
T277 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.2177739327 Feb 08 12:32:34 PM PST 24 Feb 08 12:32:56 PM PST 24 39096576 ps
T278 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1609803014 Feb 08 12:32:27 PM PST 24 Feb 08 12:32:48 PM PST 24 21817094 ps
T279 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.3209480365 Feb 08 12:32:35 PM PST 24 Feb 08 12:32:58 PM PST 24 344073607 ps
T54 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.1324672939 Feb 08 12:32:25 PM PST 24 Feb 08 12:32:49 PM PST 24 338894523 ps
T280 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3498875719 Feb 08 12:32:26 PM PST 24 Feb 08 12:32:54 PM PST 24 1815858675 ps
T281 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1795991742 Feb 08 12:32:39 PM PST 24 Feb 08 12:33:05 PM PST 24 42831590 ps
T282 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.352783822 Feb 08 12:32:30 PM PST 24 Feb 08 12:32:50 PM PST 24 71198076 ps
T283 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.2629501032 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:04 PM PST 24 84247523 ps
T50 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.707490030 Feb 08 12:32:28 PM PST 24 Feb 08 12:32:53 PM PST 24 537438941 ps
T284 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2781206454 Feb 08 12:32:30 PM PST 24 Feb 08 12:32:51 PM PST 24 92344445 ps
T285 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3366947394 Feb 08 12:32:21 PM PST 24 Feb 08 12:32:45 PM PST 24 165609293 ps
T286 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3156628195 Feb 08 12:32:26 PM PST 24 Feb 08 12:32:52 PM PST 24 83032224 ps
T287 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2342257955 Feb 08 12:32:36 PM PST 24 Feb 08 12:32:58 PM PST 24 54913424 ps
T288 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3769595271 Feb 08 12:32:35 PM PST 24 Feb 08 12:32:58 PM PST 24 120585051 ps
T289 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.74448851 Feb 08 12:32:35 PM PST 24 Feb 08 12:32:57 PM PST 24 216320411 ps
T290 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1798289130 Feb 08 12:32:29 PM PST 24 Feb 08 12:32:49 PM PST 24 36492508 ps
T291 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1040100009 Feb 08 12:32:37 PM PST 24 Feb 08 12:33:01 PM PST 24 41439943 ps
T292 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.821627421 Feb 08 12:32:30 PM PST 24 Feb 08 12:32:51 PM PST 24 25946715 ps
T293 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3755798315 Feb 08 12:32:51 PM PST 24 Feb 08 12:33:16 PM PST 24 15537799 ps
T294 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1958568776 Feb 08 12:32:43 PM PST 24 Feb 08 12:33:08 PM PST 24 31942109 ps
T295 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2635065298 Feb 08 12:32:43 PM PST 24 Feb 08 12:33:10 PM PST 24 53536797 ps
T296 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2054841443 Feb 08 12:32:30 PM PST 24 Feb 08 12:32:50 PM PST 24 43853730 ps
T297 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.1375149254 Feb 08 12:36:10 PM PST 24 Feb 08 12:36:24 PM PST 24 37493435 ps
T298 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.717028319 Feb 08 12:32:35 PM PST 24 Feb 08 12:32:57 PM PST 24 39079033 ps
T299 /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.883580752 Feb 08 12:32:32 PM PST 24 Feb 08 12:32:52 PM PST 24 59658452 ps
T300 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3775447509 Feb 08 12:32:42 PM PST 24 Feb 08 12:33:08 PM PST 24 44353476 ps
T301 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.833332750 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:07 PM PST 24 246642001 ps
T302 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.144697447 Feb 08 12:32:28 PM PST 24 Feb 08 12:32:47 PM PST 24 20794647 ps
T303 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.3441751568 Feb 08 12:32:26 PM PST 24 Feb 08 12:32:47 PM PST 24 190577512 ps
T304 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.310982474 Feb 08 12:32:28 PM PST 24 Feb 08 12:32:49 PM PST 24 141226349 ps
T305 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.893683906 Feb 08 12:32:42 PM PST 24 Feb 08 12:33:09 PM PST 24 45994710 ps
T306 /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.1868031070 Feb 08 12:32:43 PM PST 24 Feb 08 12:33:10 PM PST 24 597482176 ps
T307 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.3003749916 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:05 PM PST 24 192388508 ps
T308 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2339556543 Feb 08 12:32:38 PM PST 24 Feb 08 12:33:02 PM PST 24 598304719 ps

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.2473968798
Short name T5
Test name
Test status
Simulation time 1576732525 ps
CPU time 16.33 seconds
Started Feb 08 12:31:00 PM PST 24
Finished Feb 08 12:32:06 PM PST 24
Peak memory 206364 kb
Host smart-7c5b8e68-e128-45fb-b804-37a5bf8454f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473968798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.2473968798
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.153211307
Short name T8
Test name
Test status
Simulation time 360911307 ps
CPU time 10.19 seconds
Started Feb 08 12:31:02 PM PST 24
Finished Feb 08 12:32:01 PM PST 24
Peak memory 230340 kb
Host smart-abacbd0b-c293-41f5-a35e-53c785fff451
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153211307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.153211307
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.822354335
Short name T37
Test name
Test status
Simulation time 148638165 ps
CPU time 4.76 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212916 kb
Host smart-594e064d-e76c-485e-a09e-d57a0672d44b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822354335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.822354335
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.701733171
Short name T32
Test name
Test status
Simulation time 1216241372 ps
CPU time 3.59 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 220568 kb
Host smart-de745e41-b5cf-485b-817f-49068f7de6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701733171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.701733171
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.1239452837
Short name T16
Test name
Test status
Simulation time 4778755421 ps
CPU time 22.35 seconds
Started Feb 08 12:31:49 PM PST 24
Finished Feb 08 12:32:44 PM PST 24
Peak memory 208196 kb
Host smart-5b373f3e-f165-49f5-b6d7-00fdd1a69a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239452837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1239452837
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3479307343
Short name T95
Test name
Test status
Simulation time 822599958 ps
CPU time 8.2 seconds
Started Feb 08 12:32:23 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 212808 kb
Host smart-dcaf5861-f8e1-44b8-b882-ceb9bd8f5e8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479307343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.3479307343
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.3571843263
Short name T36
Test name
Test status
Simulation time 864143316 ps
CPU time 6.22 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 212520 kb
Host smart-fb04cf37-4100-468b-9a70-7a195fccfdd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571843263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.3571843263
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.1391690160
Short name T76
Test name
Test status
Simulation time 20066550 ps
CPU time 0.77 seconds
Started Feb 08 12:30:58 PM PST 24
Finished Feb 08 12:31:49 PM PST 24
Peak memory 205552 kb
Host smart-6d1d371e-3bb3-419b-bad0-6b87cf7b4621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391690160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.1
391690160
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3666691015
Short name T44
Test name
Test status
Simulation time 12879206 ps
CPU time 0.71 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204180 kb
Host smart-09cdb82c-5d84-4459-bb7c-dd10d38b29fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666691015 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3666691015
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.2840861725
Short name T180
Test name
Test status
Simulation time 31201779 ps
CPU time 1.99 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 214788 kb
Host smart-50422c36-acc0-4523-a528-bb5db7fbca86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840861725 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
2840861725
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3759190509
Short name T81
Test name
Test status
Simulation time 506869022 ps
CPU time 13.77 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:15 PM PST 24
Peak memory 207960 kb
Host smart-b483ccb3-0aac-4202-8cac-c63b2c567e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759190509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3759190509
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.1804910799
Short name T4
Test name
Test status
Simulation time 224501072 ps
CPU time 11.14 seconds
Started Feb 08 12:31:48 PM PST 24
Finished Feb 08 12:32:32 PM PST 24
Peak memory 207744 kb
Host smart-7f0cca8d-aaf4-42ba-ba2c-1db711850624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804910799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.1804910799
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.184134385
Short name T52
Test name
Test status
Simulation time 287989184 ps
CPU time 6.01 seconds
Started Feb 08 12:32:18 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 213872 kb
Host smart-f0e7b584-949f-4aa4-adae-b01ced118e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184134385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_
tl_intg_err.184134385
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.646599104
Short name T59
Test name
Test status
Simulation time 221307671 ps
CPU time 6.75 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 213772 kb
Host smart-f5455777-b1ac-477a-a875-d512fa81c547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646599104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.646599104
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3894346268
Short name T48
Test name
Test status
Simulation time 187150662 ps
CPU time 4.29 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:05 PM PST 24
Peak memory 213804 kb
Host smart-f7f4da3d-679d-43a1-b37c-6dc9c09b26b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894346268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.3894346268
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3432328941
Short name T63
Test name
Test status
Simulation time 246953444 ps
CPU time 3.77 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:54 PM PST 24
Peak memory 213460 kb
Host smart-16ae0be1-cc97-4434-8995-7aae9f5deab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432328941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3432328941
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.3165659290
Short name T7
Test name
Test status
Simulation time 659533286 ps
CPU time 8.18 seconds
Started Feb 08 12:31:08 PM PST 24
Finished Feb 08 12:32:02 PM PST 24
Peak memory 230296 kb
Host smart-fb89565a-170b-4816-b5f3-9b4122c6da45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165659290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.3165659290
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.702684396
Short name T34
Test name
Test status
Simulation time 123644107 ps
CPU time 2.87 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:12 PM PST 24
Peak memory 213068 kb
Host smart-32ab8a03-d045-4838-be0a-18ab19062017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702684396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.702684396
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.4157894096
Short name T41
Test name
Test status
Simulation time 180226214 ps
CPU time 2.73 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 212480 kb
Host smart-551c3d87-f667-44ed-ab1a-056f38109f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157894096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.4157894096
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.707490030
Short name T50
Test name
Test status
Simulation time 537438941 ps
CPU time 6.97 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 212552 kb
Host smart-f4ffffd5-b53e-4a18-9898-be73b50b6d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707490030 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.707490030
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.1324672939
Short name T54
Test name
Test status
Simulation time 338894523 ps
CPU time 4.84 seconds
Started Feb 08 12:32:25 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 213572 kb
Host smart-50491c5e-55da-44e5-89aa-a329aa2e4765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324672939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.1324672939
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1385129026
Short name T113
Test name
Test status
Simulation time 1122723714 ps
CPU time 3.83 seconds
Started Feb 08 12:31:53 PM PST 24
Finished Feb 08 12:32:29 PM PST 24
Peak memory 213552 kb
Host smart-d2cddea0-6595-49f3-91b8-f01bcaeb5038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385129026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1385129026
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2342257955
Short name T287
Test name
Test status
Simulation time 54913424 ps
CPU time 1.47 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 212488 kb
Host smart-ca0a84e2-3d5a-4f47-96e6-65f9fc7743a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342257955 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2342257955
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.1952100102
Short name T13
Test name
Test status
Simulation time 271674004 ps
CPU time 8.37 seconds
Started Feb 08 12:30:54 PM PST 24
Finished Feb 08 12:31:52 PM PST 24
Peak memory 205884 kb
Host smart-7ff7e0f9-8141-49f3-b0ef-9dbd11e85668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952100102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.1952100102
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.2715211941
Short name T80
Test name
Test status
Simulation time 4093421247 ps
CPU time 35.22 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:37 PM PST 24
Peak memory 208520 kb
Host smart-ac2dbe48-698e-461d-85b3-6417968c9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715211941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.2715211941
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3499860851
Short name T111
Test name
Test status
Simulation time 3526639069 ps
CPU time 81.33 seconds
Started Feb 08 12:31:41 PM PST 24
Finished Feb 08 12:33:37 PM PST 24
Peak memory 207364 kb
Host smart-74dac873-eed7-48e4-a00b-9f7f0170d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499860851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3499860851
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.246730533
Short name T24
Test name
Test status
Simulation time 692063317 ps
CPU time 20.69 seconds
Started Feb 08 12:31:44 PM PST 24
Finished Feb 08 12:32:39 PM PST 24
Peak memory 206908 kb
Host smart-224a5cba-ec9e-44e5-9967-13fe194a72d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246730533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.246730533
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.406750888
Short name T107
Test name
Test status
Simulation time 4525447001 ps
CPU time 25.21 seconds
Started Feb 08 12:31:28 PM PST 24
Finished Feb 08 12:32:30 PM PST 24
Peak memory 207660 kb
Host smart-29204ed2-3e06-434b-b9e5-44ac33d6b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406750888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.406750888
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.2989150197
Short name T82
Test name
Test status
Simulation time 2694627083 ps
CPU time 21.8 seconds
Started Feb 08 12:31:25 PM PST 24
Finished Feb 08 12:32:25 PM PST 24
Peak memory 206080 kb
Host smart-6c66df38-2650-4eb7-b4d1-1d279665655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989150197 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.2989150197
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1634343503
Short name T84
Test name
Test status
Simulation time 798884590 ps
CPU time 11.95 seconds
Started Feb 08 12:31:32 PM PST 24
Finished Feb 08 12:32:21 PM PST 24
Peak memory 207912 kb
Host smart-0cda5367-7b28-4fa2-9017-bd71e29da8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634343503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1634343503
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.46951257
Short name T101
Test name
Test status
Simulation time 403647889 ps
CPU time 16.23 seconds
Started Feb 08 12:31:30 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 206192 kb
Host smart-1e97c6ed-dd75-4b2c-90f9-34bf3471a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46951257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.46951257
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1905475087
Short name T100
Test name
Test status
Simulation time 973579915 ps
CPU time 17 seconds
Started Feb 08 12:30:59 PM PST 24
Finished Feb 08 12:32:06 PM PST 24
Peak memory 206100 kb
Host smart-8dcda94a-c1a4-4979-b99d-25b7fd394e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905475087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1905475087
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.300373176
Short name T97
Test name
Test status
Simulation time 1176740911 ps
CPU time 18.47 seconds
Started Feb 08 12:31:59 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 207184 kb
Host smart-e7329f2b-c090-4332-afa3-4c01d0ce69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300373176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.300373176
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.2193488678
Short name T99
Test name
Test status
Simulation time 3925773698 ps
CPU time 33.53 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 207472 kb
Host smart-a9212508-a7d8-4c89-916e-12bd08d75383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193488678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.2193488678
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.1559442692
Short name T102
Test name
Test status
Simulation time 148113892 ps
CPU time 9.29 seconds
Started Feb 08 12:31:46 PM PST 24
Finished Feb 08 12:32:28 PM PST 24
Peak memory 206612 kb
Host smart-daf23651-a05f-4bca-a3af-9230b47c2a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559442692 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1559442692
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.2099053965
Short name T103
Test name
Test status
Simulation time 3146271853 ps
CPU time 24.27 seconds
Started Feb 08 12:31:56 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 206036 kb
Host smart-e9cd8c37-434e-479e-947e-6ffa891c4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099053965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.2099053965
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.509289247
Short name T105
Test name
Test status
Simulation time 6193138472 ps
CPU time 35.25 seconds
Started Feb 08 12:31:21 PM PST 24
Finished Feb 08 12:32:37 PM PST 24
Peak memory 207860 kb
Host smart-eff91bc3-244b-4382-8388-6389ff6b66db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509289247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.509289247
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.600879035
Short name T222
Test name
Test status
Simulation time 277834340 ps
CPU time 5.03 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 204324 kb
Host smart-f2e47d9c-2d21-4173-9d38-f88965ddad08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600879035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.600879035
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1249196891
Short name T260
Test name
Test status
Simulation time 3156373771 ps
CPU time 17.02 seconds
Started Feb 08 12:32:23 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 204376 kb
Host smart-9f1b6ece-2565-4980-9dba-2aac479e113d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249196891 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1249196891
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2599492135
Short name T235
Test name
Test status
Simulation time 49703358 ps
CPU time 1.02 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:26 PM PST 24
Peak memory 204216 kb
Host smart-c4bb7f37-9c5a-41f4-84df-d7babe25718a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599492135 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2599492135
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1063537551
Short name T182
Test name
Test status
Simulation time 26170359 ps
CPU time 0.88 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 204216 kb
Host smart-c69e3031-6aa6-41de-9e9c-075dc5f4a324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063537551 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1063537551
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3069634401
Short name T178
Test name
Test status
Simulation time 20249641 ps
CPU time 1.25 seconds
Started Feb 08 12:32:24 PM PST 24
Finished Feb 08 12:32:45 PM PST 24
Peak memory 204312 kb
Host smart-c005a8a7-ecdc-4403-90df-25d0b017aa7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069634401 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3
069634401
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.1725923072
Short name T263
Test name
Test status
Simulation time 10209619 ps
CPU time 0.72 seconds
Started Feb 08 12:31:58 PM PST 24
Finished Feb 08 12:32:31 PM PST 24
Peak memory 204176 kb
Host smart-ca044e6c-da0f-4c29-b97c-7880ba06a84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725923072 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.1
725923072
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3366947394
Short name T285
Test name
Test status
Simulation time 165609293 ps
CPU time 2.22 seconds
Started Feb 08 12:32:21 PM PST 24
Finished Feb 08 12:32:45 PM PST 24
Peak memory 204408 kb
Host smart-84797225-e7f2-4168-8e91-e8d3921c44ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366947394 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3366947394
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.1532220953
Short name T68
Test name
Test status
Simulation time 95183679 ps
CPU time 2.8 seconds
Started Feb 08 12:31:53 PM PST 24
Finished Feb 08 12:32:28 PM PST 24
Peak memory 212848 kb
Host smart-5d5357a2-d763-4969-91b3-5536cb3a149f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532220953 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.1532220953
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.4036216864
Short name T249
Test name
Test status
Simulation time 1201919882 ps
CPU time 4.25 seconds
Started Feb 08 12:31:58 PM PST 24
Finished Feb 08 12:32:34 PM PST 24
Peak memory 212864 kb
Host smart-c3de6523-8e34-4a3e-be1f-838ffe16e301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036216864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.4036216864
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2658966412
Short name T206
Test name
Test status
Simulation time 214133027 ps
CPU time 2.56 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 212548 kb
Host smart-10a93611-e1fe-4f89-8429-96181ff40808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658966412 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
658966412
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3156628195
Short name T286
Test name
Test status
Simulation time 83032224 ps
CPU time 6.06 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 204340 kb
Host smart-efa4e656-3388-4614-a963-188da382aba8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156628195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.3156628195
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2986798511
Short name T256
Test name
Test status
Simulation time 3542305975 ps
CPU time 12.25 seconds
Started Feb 08 12:32:27 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 204384 kb
Host smart-dc0294d0-eb98-431a-963c-50bd9accb8b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986798511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.2986798511
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.38596498
Short name T188
Test name
Test status
Simulation time 25508059 ps
CPU time 0.87 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204212 kb
Host smart-b0baf176-c98d-4b70-a900-403a819f902d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_
hw_reset.38596498
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2054841443
Short name T296
Test name
Test status
Simulation time 43853730 ps
CPU time 1 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 212404 kb
Host smart-4666aa26-9fbd-441d-ba13-19efb90f5a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054841443 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.2054841443
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.1257052326
Short name T242
Test name
Test status
Simulation time 39436128 ps
CPU time 1.24 seconds
Started Feb 08 12:32:25 PM PST 24
Finished Feb 08 12:32:46 PM PST 24
Peak memory 204416 kb
Host smart-43813992-af98-4335-9463-531cf5acb102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257052326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.1
257052326
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.778416355
Short name T275
Test name
Test status
Simulation time 86265803 ps
CPU time 0.71 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204176 kb
Host smart-095a515e-3ede-4cc1-a84c-56cd1d5f8506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778416355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.778416355
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2555631583
Short name T191
Test name
Test status
Simulation time 133231262 ps
CPU time 2.76 seconds
Started Feb 08 12:32:19 PM PST 24
Finished Feb 08 12:32:45 PM PST 24
Peak memory 204436 kb
Host smart-95236fc0-9644-4b0d-9202-32a80ca4dd0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555631583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.2555631583
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.509210558
Short name T218
Test name
Test status
Simulation time 99257983 ps
CPU time 1.33 seconds
Started Feb 08 12:32:24 PM PST 24
Finished Feb 08 12:32:45 PM PST 24
Peak memory 212908 kb
Host smart-b72ee42a-ab92-437c-9a1b-6183b943a79d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509210558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymg
r_dpe_shadow_reg_errors.509210558
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2781206454
Short name T284
Test name
Test status
Simulation time 92344445 ps
CPU time 2.53 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 212580 kb
Host smart-cfdc10ca-8414-4ba5-9f6c-ffb1df6fa0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781206454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.2
781206454
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3983069537
Short name T91
Test name
Test status
Simulation time 55594784 ps
CPU time 1.22 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 220308 kb
Host smart-0860e944-e003-475f-aeff-52bf05a4bd24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983069537 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3983069537
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.1177102566
Short name T88
Test name
Test status
Simulation time 27374715 ps
CPU time 0.84 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 204092 kb
Host smart-f718ebab-d90d-4f72-bd6d-ff389063fc1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177102566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
1177102566
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.4066178834
Short name T71
Test name
Test status
Simulation time 17015448 ps
CPU time 0.69 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 204088 kb
Host smart-ea6e073c-3444-4c56-bda8-60fe2462760b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066178834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
4066178834
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1806362775
Short name T223
Test name
Test status
Simulation time 29874221 ps
CPU time 1.95 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:03 PM PST 24
Peak memory 204444 kb
Host smart-014d16d2-52a8-4cd6-9df7-ae7a1220e641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806362775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1806362775
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2635065298
Short name T295
Test name
Test status
Simulation time 53536797 ps
CPU time 1.17 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 212952 kb
Host smart-7ef45ab3-b78f-4d02-ab9f-be1aaf91bfbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635065298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2635065298
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4108878620
Short name T66
Test name
Test status
Simulation time 198460268 ps
CPU time 7.39 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 212928 kb
Host smart-838e1fc3-6d07-4f48-872c-86371486c17f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108878620 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.4108878620
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.893683906
Short name T305
Test name
Test status
Simulation time 45994710 ps
CPU time 1.54 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:09 PM PST 24
Peak memory 212492 kb
Host smart-bc4dba3c-b2c4-4259-b3bd-61c10839af1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893683906 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.893683906
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1097304829
Short name T179
Test name
Test status
Simulation time 188441899 ps
CPU time 1.05 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 204152 kb
Host smart-93576f15-b5c9-402b-93b1-3243493ecbc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097304829 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1097304829
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.3697026683
Short name T192
Test name
Test status
Simulation time 13192991 ps
CPU time 0.73 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 204104 kb
Host smart-361dc878-fd68-465d-a583-67a53f3bb4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697026683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
3697026683
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.4288301391
Short name T237
Test name
Test status
Simulation time 226623792 ps
CPU time 2.84 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 204252 kb
Host smart-0a2797b9-7bdd-4147-916e-ad1191bd51ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288301391 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.4288301391
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.489058290
Short name T65
Test name
Test status
Simulation time 39815057 ps
CPU time 1.52 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 212872 kb
Host smart-0b3d7f91-c84d-4997-84f6-ac002a4525da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489058290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keym
gr_dpe_shadow_reg_errors.489058290
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.3632976088
Short name T239
Test name
Test status
Simulation time 112304577 ps
CPU time 2.6 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212960 kb
Host smart-f1193374-591e-40e9-8bbb-c4510a73a5b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632976088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.3632976088
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2403477820
Short name T19
Test name
Test status
Simulation time 41666268 ps
CPU time 1.44 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212832 kb
Host smart-8bd3db79-bf89-4058-8ed8-8c43aabb32a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403477820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2403477820
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.1711874502
Short name T51
Test name
Test status
Simulation time 770636425 ps
CPU time 7.35 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:15 PM PST 24
Peak memory 213616 kb
Host smart-29be9ea0-955c-4770-80af-9bc17d36d6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711874502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.1711874502
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2345764217
Short name T232
Test name
Test status
Simulation time 17609310 ps
CPU time 1.11 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 204288 kb
Host smart-76972b9a-322a-43fb-a35e-aeedbd37fcc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345764217 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2345764217
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.341285396
Short name T244
Test name
Test status
Simulation time 14807492 ps
CPU time 0.88 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 204124 kb
Host smart-7bf0c8ca-922c-4ce7-85c6-7b3e4af65af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341285396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.341285396
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.135872740
Short name T224
Test name
Test status
Simulation time 144279585 ps
CPU time 0.8 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 204048 kb
Host smart-9b98066a-a16b-44e3-a178-c39dcb8428d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135872740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.135872740
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.3630701696
Short name T203
Test name
Test status
Simulation time 43856628 ps
CPU time 1.91 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204308 kb
Host smart-f1db2c97-a30b-47a5-a6e2-69936c0dd187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630701696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.3630701696
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.208472508
Short name T234
Test name
Test status
Simulation time 567389447 ps
CPU time 2.6 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 212696 kb
Host smart-2bf18605-c7d5-4b67-8262-c07e513875f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208472508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym
gr_dpe_shadow_reg_errors.208472508
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2135021530
Short name T248
Test name
Test status
Simulation time 132911370 ps
CPU time 4.73 seconds
Started Feb 08 12:32:27 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 212912 kb
Host smart-390b3574-cd72-46be-b876-8aa9097a27d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135021530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2135021530
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.261587184
Short name T40
Test name
Test status
Simulation time 453801999 ps
CPU time 2.1 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 212560 kb
Host smart-7f74746b-2ef6-48ed-b648-72e4e0628ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261587184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.261587184
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.1379598785
Short name T47
Test name
Test status
Simulation time 447289890 ps
CPU time 2.83 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 212528 kb
Host smart-6fcfd6f9-a522-4012-80c1-f2d6abd36681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379598785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.1379598785
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1714643391
Short name T92
Test name
Test status
Simulation time 26938566 ps
CPU time 1.14 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 220656 kb
Host smart-7782f08a-9c56-407a-b87e-8a3c7f172a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714643391 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1714643391
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1152915563
Short name T262
Test name
Test status
Simulation time 18012668 ps
CPU time 0.95 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204200 kb
Host smart-6755f93f-0bff-47e9-8df7-9da4e2d85a25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152915563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1152915563
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.470852240
Short name T197
Test name
Test status
Simulation time 40834143 ps
CPU time 0.81 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204092 kb
Host smart-59faae5d-16f6-40a0-a7b9-49507178d432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470852240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.470852240
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1798289130
Short name T290
Test name
Test status
Simulation time 36492508 ps
CPU time 1.39 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 204416 kb
Host smart-cda5416c-b955-4cc1-9455-9fe664a6100d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798289130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1798289130
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3769595271
Short name T288
Test name
Test status
Simulation time 120585051 ps
CPU time 2.12 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 212892 kb
Host smart-f5cc25e2-24e3-4004-bf34-12af2f8a452a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769595271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.3769595271
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1906663421
Short name T184
Test name
Test status
Simulation time 102251167 ps
CPU time 1.08 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 211796 kb
Host smart-c07c71e6-481f-4b4a-8aba-4cb2324599a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906663421 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1906663421
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.1737544910
Short name T247
Test name
Test status
Simulation time 82951784 ps
CPU time 1.32 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 204324 kb
Host smart-e034fe70-b1d8-4abd-b07e-bb3a8b651012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737544910 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
1737544910
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.1375149254
Short name T297
Test name
Test status
Simulation time 37493435 ps
CPU time 0.72 seconds
Started Feb 08 12:36:10 PM PST 24
Finished Feb 08 12:36:24 PM PST 24
Peak memory 203360 kb
Host smart-e5efe8a4-12d7-4057-9464-1eaf39da5171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375149254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
1375149254
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.1868031070
Short name T306
Test name
Test status
Simulation time 597482176 ps
CPU time 1.57 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 204352 kb
Host smart-8d21b82d-8bc3-4988-8f1f-30b534e72d1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868031070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.1868031070
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.3633638000
Short name T238
Test name
Test status
Simulation time 83313411 ps
CPU time 1.37 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212960 kb
Host smart-9e254377-a753-451b-b4e9-c178ba6756d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633638000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.3633638000
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2309688531
Short name T245
Test name
Test status
Simulation time 955958074 ps
CPU time 8.13 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:09 PM PST 24
Peak memory 212888 kb
Host smart-e5d85376-0602-49d0-98d0-e057b1a373f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309688531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2309688531
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1040100009
Short name T291
Test name
Test status
Simulation time 41439943 ps
CPU time 1.56 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:01 PM PST 24
Peak memory 211900 kb
Host smart-d260df4f-fb6b-4902-8d53-b22ee5a2a701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040100009 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1040100009
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1609803014
Short name T278
Test name
Test status
Simulation time 21817094 ps
CPU time 1.76 seconds
Started Feb 08 12:32:27 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212600 kb
Host smart-19430c0b-2c30-4e47-811f-bf7d1fd5b2c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609803014 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1609803014
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2032509878
Short name T39
Test name
Test status
Simulation time 15171736 ps
CPU time 1.05 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 204052 kb
Host smart-a2705975-6c35-410e-948c-e26cc277f1e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032509878 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2032509878
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.3059853047
Short name T253
Test name
Test status
Simulation time 19989151 ps
CPU time 0.68 seconds
Started Feb 08 12:32:41 PM PST 24
Finished Feb 08 12:33:06 PM PST 24
Peak memory 204148 kb
Host smart-de32e6de-a2a8-4cb3-a175-fcf641fb6cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059853047 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
3059853047
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.883580752
Short name T299
Test name
Test status
Simulation time 59658452 ps
CPU time 1.39 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 204340 kb
Host smart-b9c5701d-09b6-41b6-bc07-7c204ada00d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883580752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_dpe_same_csr_outstanding.883580752
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.425239540
Short name T169
Test name
Test status
Simulation time 198709126 ps
CPU time 1.51 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 212696 kb
Host smart-4085b5bf-1f4b-46a8-b047-115ad5051eb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425239540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.425239540
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4115669689
Short name T183
Test name
Test status
Simulation time 547183034 ps
CPU time 3.21 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 212812 kb
Host smart-4c38bc42-fc14-495a-ba54-a3245f69543b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115669689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.4115669689
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.3209480365
Short name T279
Test name
Test status
Simulation time 344073607 ps
CPU time 2.19 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 213016 kb
Host smart-dac71cef-7b67-4e84-878b-b21344e3fb17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209480365 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
3209480365
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.306949594
Short name T60
Test name
Test status
Simulation time 301022189 ps
CPU time 3.63 seconds
Started Feb 08 12:32:34 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 213872 kb
Host smart-d9804484-29ae-4c51-a3d2-09b3e373893d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306949594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe
_tl_intg_err.306949594
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.1501467958
Short name T210
Test name
Test status
Simulation time 32875794 ps
CPU time 1.82 seconds
Started Feb 08 12:32:33 PM PST 24
Finished Feb 08 12:32:54 PM PST 24
Peak memory 212912 kb
Host smart-e22aa060-71be-4777-b503-917405c21d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501467958 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.1501467958
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.717028319
Short name T298
Test name
Test status
Simulation time 39079033 ps
CPU time 0.91 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 204228 kb
Host smart-9c6e3eed-4b68-4b61-a51a-aee9d8527f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717028319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.717028319
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.144697447
Short name T302
Test name
Test status
Simulation time 20794647 ps
CPU time 0.84 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204256 kb
Host smart-a6dc5cb7-b1eb-42a8-9282-d142857613e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144697447 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.144697447
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2339556543
Short name T308
Test name
Test status
Simulation time 598304719 ps
CPU time 1.47 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 204364 kb
Host smart-3342faf9-11d2-4193-9650-ac6ba834aa87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339556543 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.2339556543
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.3144895247
Short name T233
Test name
Test status
Simulation time 182976586 ps
CPU time 1.79 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 212856 kb
Host smart-977edfda-be70-4807-82a6-c2bcfac65032
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144895247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.3144895247
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2507434367
Short name T96
Test name
Test status
Simulation time 311183603 ps
CPU time 8.6 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:33:06 PM PST 24
Peak memory 212896 kb
Host smart-06c34f11-0b31-40f4-a837-877b2c16528b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507434367 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2507434367
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.4135856533
Short name T43
Test name
Test status
Simulation time 82360958 ps
CPU time 2.27 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 213780 kb
Host smart-a1c0b503-2b65-4426-8721-1f3262ec9b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135856533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
4135856533
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.2620051080
Short name T53
Test name
Test status
Simulation time 122594809 ps
CPU time 2.22 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:04 PM PST 24
Peak memory 204316 kb
Host smart-0d3bb2e9-9833-43da-a392-36d56c9aaa45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620051080 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.2620051080
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2845642532
Short name T267
Test name
Test status
Simulation time 89737564 ps
CPU time 1.16 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212588 kb
Host smart-89780a43-81c9-4a14-81ef-2db5eca34bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845642532 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2845642532
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1187278308
Short name T215
Test name
Test status
Simulation time 54463164 ps
CPU time 0.86 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 204192 kb
Host smart-e4332586-2229-44a4-b2b7-8a3f0e453f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187278308 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1187278308
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2687051540
Short name T176
Test name
Test status
Simulation time 78792164 ps
CPU time 0.79 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 204136 kb
Host smart-4bca0ae4-1e1b-48c7-acab-379f43d8b2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687051540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2687051540
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.199714929
Short name T211
Test name
Test status
Simulation time 50337524 ps
CPU time 2.09 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:01 PM PST 24
Peak memory 212584 kb
Host smart-e06b24f0-631f-404c-bf0f-adec50c816ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199714929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_dpe_same_csr_outstanding.199714929
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.310982474
Short name T304
Test name
Test status
Simulation time 141226349 ps
CPU time 2.26 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 212884 kb
Host smart-19c2d62e-8116-4156-9688-a92c3efd2bcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310982474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keym
gr_dpe_shadow_reg_errors.310982474
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.852317079
Short name T67
Test name
Test status
Simulation time 134282686 ps
CPU time 5.13 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:33:03 PM PST 24
Peak memory 212864 kb
Host smart-f14d6a3c-0201-4749-8237-1aa7f72e03b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852317079 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.852317079
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.3782162360
Short name T220
Test name
Test status
Simulation time 32184210 ps
CPU time 2.01 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 220384 kb
Host smart-31750f6b-aea9-4ce8-abda-f531680410f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782162360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
3782162360
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.229700012
Short name T61
Test name
Test status
Simulation time 262932275 ps
CPU time 5.31 seconds
Started Feb 08 12:32:22 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 214368 kb
Host smart-f8fbcf19-9384-4a60-a998-db88c3ed7915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229700012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe
_tl_intg_err.229700012
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3513986667
Short name T58
Test name
Test status
Simulation time 111743480 ps
CPU time 1.76 seconds
Started Feb 08 12:32:51 PM PST 24
Finished Feb 08 12:33:17 PM PST 24
Peak memory 212532 kb
Host smart-cfa60fa6-ddfe-40c3-b9fe-6f691f59c08a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513986667 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3513986667
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2452600552
Short name T258
Test name
Test status
Simulation time 37258117 ps
CPU time 1.21 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:09 PM PST 24
Peak memory 204256 kb
Host smart-88dbe531-6027-4207-ad68-13a673a1298e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452600552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2452600552
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1691097100
Short name T193
Test name
Test status
Simulation time 13497828 ps
CPU time 0.77 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 204132 kb
Host smart-f83ca97d-59f2-4d93-b932-0ce333a7bbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691097100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1691097100
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.2629501032
Short name T283
Test name
Test status
Simulation time 84247523 ps
CPU time 1.44 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:04 PM PST 24
Peak memory 204692 kb
Host smart-c53b59f9-dc1f-49e2-a9f5-cead188eb44f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629501032 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.2629501032
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.448840702
Short name T214
Test name
Test status
Simulation time 63962998 ps
CPU time 2.03 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:04 PM PST 24
Peak memory 212948 kb
Host smart-8182f3be-4a0d-4d76-8bb3-70131a7c1850
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448840702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keym
gr_dpe_shadow_reg_errors.448840702
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2266415757
Short name T212
Test name
Test status
Simulation time 219164191 ps
CPU time 7.65 seconds
Started Feb 08 12:32:40 PM PST 24
Finished Feb 08 12:33:13 PM PST 24
Peak memory 212828 kb
Host smart-3c2a55a0-166a-4088-8cd1-97897f8b6bb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266415757 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2266415757
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1051886335
Short name T265
Test name
Test status
Simulation time 25113492 ps
CPU time 1.95 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:06 PM PST 24
Peak memory 214992 kb
Host smart-a4206ac0-d108-4c2c-8f46-339a1a64b7de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051886335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1051886335
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3897056900
Short name T230
Test name
Test status
Simulation time 75499263 ps
CPU time 3.04 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 212520 kb
Host smart-0b90bd95-6c59-4ee4-9c46-0b3a09ccf70e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897056900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3897056900
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.4265809713
Short name T204
Test name
Test status
Simulation time 79484872 ps
CPU time 1.45 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 212844 kb
Host smart-c4c03329-af0e-4d24-ba5b-532cd35c8fa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265809713 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.4265809713
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.1795991742
Short name T281
Test name
Test status
Simulation time 42831590 ps
CPU time 1.08 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:05 PM PST 24
Peak memory 204268 kb
Host smart-1fb3496c-3354-4d66-a8c4-291109ffdbf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795991742 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
1795991742
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3746477987
Short name T257
Test name
Test status
Simulation time 12276994 ps
CPU time 0.83 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 204252 kb
Host smart-04052a8e-cc81-4e3b-b95a-40d362bc95c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746477987 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
3746477987
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.185022174
Short name T185
Test name
Test status
Simulation time 280930334 ps
CPU time 2.14 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 204308 kb
Host smart-2ecb288f-fccf-4cf2-87fb-94429b6d752a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185022174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.185022174
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.1564389853
Short name T94
Test name
Test status
Simulation time 120699278 ps
CPU time 1.64 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:04 PM PST 24
Peak memory 212776 kb
Host smart-e73ecc82-dad4-4bf8-bef4-1e52f4ab4b4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564389853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.1564389853
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.755596754
Short name T172
Test name
Test status
Simulation time 784547302 ps
CPU time 2.28 seconds
Started Feb 08 12:32:46 PM PST 24
Finished Feb 08 12:33:13 PM PST 24
Peak memory 212796 kb
Host smart-082ebc75-b7b9-4667-a805-590e8279c1f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755596754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.755596754
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2241731612
Short name T56
Test name
Test status
Simulation time 25809729 ps
CPU time 1.72 seconds
Started Feb 08 12:32:40 PM PST 24
Finished Feb 08 12:33:06 PM PST 24
Peak memory 214648 kb
Host smart-9587cb2b-bf82-4749-8d7f-6d493d8172a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241731612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
2241731612
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.570127935
Short name T266
Test name
Test status
Simulation time 89813589 ps
CPU time 4.69 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:55 PM PST 24
Peak memory 204264 kb
Host smart-9146f69b-003d-445a-a2ef-8e4816681a1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570127935 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.570127935
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3608237866
Short name T264
Test name
Test status
Simulation time 9160322827 ps
CPU time 19.55 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:33:07 PM PST 24
Peak memory 204412 kb
Host smart-6acfcb8e-ed1a-4ed2-86d1-859adc3809e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608237866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3608237866
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.352783822
Short name T282
Test name
Test status
Simulation time 71198076 ps
CPU time 1.07 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204184 kb
Host smart-253ce5f1-a347-4911-8f38-74d9bc8aaa4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352783822 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.352783822
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.985374120
Short name T75
Test name
Test status
Simulation time 67726442 ps
CPU time 1.24 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212640 kb
Host smart-8e4cfa7a-f2f0-415a-8e3a-3290d1380dee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985374120 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.985374120
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1245524056
Short name T175
Test name
Test status
Simulation time 16741319 ps
CPU time 0.81 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204124 kb
Host smart-6eec66bc-d408-49d2-a7e6-2b28bc003a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245524056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
245524056
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3005629877
Short name T217
Test name
Test status
Simulation time 31296076 ps
CPU time 0.76 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 204156 kb
Host smart-2940a114-8e99-4732-a642-b72b08eea57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005629877 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3
005629877
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3939395922
Short name T194
Test name
Test status
Simulation time 247497663 ps
CPU time 2.35 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 204264 kb
Host smart-1e41944a-375e-4dc7-84a3-41643095c7b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939395922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.3939395922
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3932777189
Short name T229
Test name
Test status
Simulation time 62280524 ps
CPU time 1.48 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 212884 kb
Host smart-7b78fe49-3323-447f-a469-58d53fa363cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932777189 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3932777189
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2127204184
Short name T273
Test name
Test status
Simulation time 160489247 ps
CPU time 2.12 seconds
Started Feb 08 12:32:24 PM PST 24
Finished Feb 08 12:32:46 PM PST 24
Peak memory 213128 kb
Host smart-330bf437-6e71-49e3-a9ed-cb8b5a3a420c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127204184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2127204184
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1915158409
Short name T33
Test name
Test status
Simulation time 88936478 ps
CPU time 2.83 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 212504 kb
Host smart-c24fa402-1007-4805-8255-6553da868ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915158409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.1
915158409
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.1516706356
Short name T55
Test name
Test status
Simulation time 266775375 ps
CPU time 8.47 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:55 PM PST 24
Peak memory 213844 kb
Host smart-b05c6ae9-a2b5-4307-9aa9-b668ed00eba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516706356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.1516706356
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.997070851
Short name T225
Test name
Test status
Simulation time 7933104 ps
CPU time 0.75 seconds
Started Feb 08 12:32:47 PM PST 24
Finished Feb 08 12:33:12 PM PST 24
Peak memory 204168 kb
Host smart-b32c8dcf-af9b-4b4e-b690-bb0af8da0f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997070851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.997070851
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2665625549
Short name T164
Test name
Test status
Simulation time 43481509 ps
CPU time 0.73 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 204272 kb
Host smart-f0a3d446-56a8-4b1d-b44c-cf854c838e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665625549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2665625549
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.1388379489
Short name T187
Test name
Test status
Simulation time 11294277 ps
CPU time 0.75 seconds
Started Feb 08 12:32:51 PM PST 24
Finished Feb 08 12:33:16 PM PST 24
Peak memory 204128 kb
Host smart-7dacf2a4-bace-49bb-8c9a-06311d0cd198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388379489 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
1388379489
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.2386366318
Short name T276
Test name
Test status
Simulation time 12174388 ps
CPU time 0.85 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 204176 kb
Host smart-1b0963cb-1e3a-4c22-bac3-8bc702f06b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386366318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
2386366318
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.1740423948
Short name T177
Test name
Test status
Simulation time 15822617 ps
CPU time 0.75 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204188 kb
Host smart-02980b94-0571-4cd7-9fde-5c6acd3e8086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740423948 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
1740423948
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.3691033214
Short name T174
Test name
Test status
Simulation time 20131395 ps
CPU time 0.74 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204188 kb
Host smart-af32d5ef-046b-4686-b86c-0beb151a3880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691033214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
3691033214
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2327066496
Short name T270
Test name
Test status
Simulation time 11049359 ps
CPU time 0.83 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 204148 kb
Host smart-f643ea39-fce6-4d6a-b896-cd167c8e7c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327066496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
2327066496
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.129919523
Short name T246
Test name
Test status
Simulation time 10610870 ps
CPU time 0.88 seconds
Started Feb 08 12:32:39 PM PST 24
Finished Feb 08 12:33:04 PM PST 24
Peak memory 204144 kb
Host smart-16f93fc9-684f-4337-b00d-ba3311933cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129919523 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.129919523
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1958568776
Short name T294
Test name
Test status
Simulation time 31942109 ps
CPU time 0.7 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 204116 kb
Host smart-25f1374a-49a4-4eef-a104-e9212c2cd2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958568776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
1958568776
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2525060223
Short name T254
Test name
Test status
Simulation time 8082479 ps
CPU time 0.73 seconds
Started Feb 08 12:32:44 PM PST 24
Finished Feb 08 12:33:10 PM PST 24
Peak memory 204164 kb
Host smart-ed5c2c45-4b37-410b-8956-49b489d5ac27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525060223 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
2525060223
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.920247011
Short name T202
Test name
Test status
Simulation time 275684010 ps
CPU time 2.62 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 204392 kb
Host smart-1067ff57-47a4-4e58-ad91-0a1c16df4ce2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920247011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_aliasing.920247011
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1785032666
Short name T252
Test name
Test status
Simulation time 747798673 ps
CPU time 6.27 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:07 PM PST 24
Peak memory 204336 kb
Host smart-26f05bd1-a5f9-42e3-959d-04b37e636bc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785032666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1785032666
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.2603827496
Short name T163
Test name
Test status
Simulation time 50290913 ps
CPU time 1.4 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 204328 kb
Host smart-911efcc1-38bd-4970-b51c-c69d5a61ac76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603827496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.2603827496
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.2108741588
Short name T198
Test name
Test status
Simulation time 38571267 ps
CPU time 1.26 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:01 PM PST 24
Peak memory 212616 kb
Host smart-f7598b61-eec8-4efb-aa04-d2b7c06abc7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108741588 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.2108741588
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2006557176
Short name T208
Test name
Test status
Simulation time 60261735 ps
CPU time 0.89 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204196 kb
Host smart-9a1804e7-113d-4af7-a62e-9075ec3c64ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006557176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.2
006557176
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.558904813
Short name T167
Test name
Test status
Simulation time 19485475 ps
CPU time 0.72 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 203988 kb
Host smart-5f0dd42c-51f3-45cf-91fa-8a222bf49856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558904813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.558904813
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.1376981658
Short name T221
Test name
Test status
Simulation time 99751510 ps
CPU time 1.38 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:03 PM PST 24
Peak memory 204168 kb
Host smart-9ab8d149-a525-465a-8565-1c31903f3859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376981658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.1376981658
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.4216441940
Short name T216
Test name
Test status
Simulation time 151218285 ps
CPU time 2.65 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:32:59 PM PST 24
Peak memory 212860 kb
Host smart-8a40ca91-b143-4a9f-8208-214921baa6e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216441940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.4216441940
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3711926028
Short name T69
Test name
Test status
Simulation time 693873578 ps
CPU time 3.01 seconds
Started Feb 08 12:32:36 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 212900 kb
Host smart-34b7caa0-2f7b-456d-823d-927a1f19bab2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711926028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3711926028
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.74448851
Short name T289
Test name
Test status
Simulation time 216320411 ps
CPU time 1.63 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 212576 kb
Host smart-b403cd70-47e3-4d44-bed2-ccaa21d6bb68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74448851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.74448851
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2093332435
Short name T35
Test name
Test status
Simulation time 603467414 ps
CPU time 6.9 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 213616 kb
Host smart-13516572-c132-4424-8402-cc264eeb86b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093332435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.2093332435
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.670924073
Short name T251
Test name
Test status
Simulation time 7795024 ps
CPU time 0.74 seconds
Started Feb 08 12:32:43 PM PST 24
Finished Feb 08 12:33:09 PM PST 24
Peak memory 204176 kb
Host smart-88436887-6423-4cea-a59b-c7ab80b6b83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670924073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.670924073
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.2305754738
Short name T168
Test name
Test status
Simulation time 11119077 ps
CPU time 0.7 seconds
Started Feb 08 12:32:44 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204188 kb
Host smart-5e1b011a-ea5c-4a68-8064-458dd843a34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305754738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
2305754738
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.4246971950
Short name T171
Test name
Test status
Simulation time 22378472 ps
CPU time 0.85 seconds
Started Feb 08 12:32:51 PM PST 24
Finished Feb 08 12:33:16 PM PST 24
Peak memory 204156 kb
Host smart-7e5b64df-c776-489c-b01e-b7ad3cfff19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246971950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
4246971950
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.771676460
Short name T72
Test name
Test status
Simulation time 9125008 ps
CPU time 0.8 seconds
Started Feb 08 12:32:52 PM PST 24
Finished Feb 08 12:33:16 PM PST 24
Peak memory 204160 kb
Host smart-bfb086b6-3751-43ba-8cff-d771dfb3d287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771676460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.771676460
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.1175756346
Short name T45
Test name
Test status
Simulation time 18387672 ps
CPU time 0.74 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204132 kb
Host smart-32a5383b-ad67-41c7-b80f-e75c6e1ef3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175756346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
1175756346
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3755798315
Short name T293
Test name
Test status
Simulation time 15537799 ps
CPU time 0.73 seconds
Started Feb 08 12:32:51 PM PST 24
Finished Feb 08 12:33:16 PM PST 24
Peak memory 204112 kb
Host smart-2ae03fe8-24c6-4f90-9de9-63907f387268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755798315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3755798315
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.92330703
Short name T190
Test name
Test status
Simulation time 14515455 ps
CPU time 0.74 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 204144 kb
Host smart-b510128e-6225-4c97-8ba3-0d68a43e7cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92330703 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.92330703
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.1364858470
Short name T241
Test name
Test status
Simulation time 64866987 ps
CPU time 0.76 seconds
Started Feb 08 12:32:44 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204144 kb
Host smart-646357e4-326f-45c0-921e-a0f271e54889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364858470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
1364858470
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.1723840844
Short name T201
Test name
Test status
Simulation time 9297644 ps
CPU time 0.72 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 204176 kb
Host smart-2b88b061-31a2-4e69-8509-60749eaa1230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723840844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
1723840844
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.833332750
Short name T301
Test name
Test status
Simulation time 246642001 ps
CPU time 6.1 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:07 PM PST 24
Peak memory 204336 kb
Host smart-cf03561b-1d0d-43b6-861a-1ab6483a112d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833332750 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_aliasing.833332750
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.1579137231
Short name T70
Test name
Test status
Simulation time 206778636 ps
CPU time 8.27 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:55 PM PST 24
Peak memory 204316 kb
Host smart-f840b10d-4c34-41d3-b44b-e371a6909ce0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579137231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.1579137231
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.1650409424
Short name T205
Test name
Test status
Simulation time 51910499 ps
CPU time 1.08 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 204320 kb
Host smart-338efe2d-e1c6-4e21-9eb6-18740e1fc77b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650409424 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.1650409424
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.2177739327
Short name T277
Test name
Test status
Simulation time 39096576 ps
CPU time 1.62 seconds
Started Feb 08 12:32:34 PM PST 24
Finished Feb 08 12:32:56 PM PST 24
Peak memory 220776 kb
Host smart-1696d0ae-e115-4021-beaf-471243d0ff38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177739327 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.2177739327
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.317102361
Short name T200
Test name
Test status
Simulation time 60598538 ps
CPU time 0.92 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 204120 kb
Host smart-27b10ed1-aa6e-4d7e-bf07-6730fe6aa492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317102361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.317102361
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3597636023
Short name T213
Test name
Test status
Simulation time 9469789 ps
CPU time 0.75 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:01 PM PST 24
Peak memory 204244 kb
Host smart-cdb6baf2-a2b4-4ee2-806c-c7b8f37410e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597636023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.3
597636023
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1668553554
Short name T240
Test name
Test status
Simulation time 175374748 ps
CPU time 1.97 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:32:58 PM PST 24
Peak memory 204340 kb
Host smart-9689090c-5946-4a0a-8663-604bd0fe0c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668553554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1668553554
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.3003749916
Short name T307
Test name
Test status
Simulation time 192388508 ps
CPU time 4.37 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:05 PM PST 24
Peak memory 212808 kb
Host smart-466e7e30-107c-41a9-977e-bce7f6617a6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003749916 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.3003749916
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2054620169
Short name T227
Test name
Test status
Simulation time 1069136351 ps
CPU time 6.96 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 213128 kb
Host smart-4f331b43-31fd-40f9-a8d9-d4a7708be989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054620169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2054620169
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2194223342
Short name T57
Test name
Test status
Simulation time 84976906 ps
CPU time 2.33 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 212512 kb
Host smart-fffdd2ed-3b08-4c83-bd58-1b7fbb29dea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194223342 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
194223342
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3775447509
Short name T300
Test name
Test status
Simulation time 44353476 ps
CPU time 0.85 seconds
Started Feb 08 12:32:42 PM PST 24
Finished Feb 08 12:33:08 PM PST 24
Peak memory 204052 kb
Host smart-4cbb066e-ae11-4f88-a1fd-4221cc85c50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775447509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3775447509
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1695492089
Short name T269
Test name
Test status
Simulation time 28621397 ps
CPU time 0.68 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204136 kb
Host smart-af63260a-961a-4459-a211-b3184b7cb781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695492089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1695492089
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.992470960
Short name T46
Test name
Test status
Simulation time 202101619 ps
CPU time 0.86 seconds
Started Feb 08 12:32:54 PM PST 24
Finished Feb 08 12:33:18 PM PST 24
Peak memory 204132 kb
Host smart-567a57dd-fdc2-4cb7-aca6-002258872027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992470960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.992470960
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.3422823196
Short name T271
Test name
Test status
Simulation time 36921687 ps
CPU time 0.79 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204148 kb
Host smart-32528171-0080-4d55-b442-5be5de8e4f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422823196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
3422823196
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.248464903
Short name T165
Test name
Test status
Simulation time 93880192 ps
CPU time 0.72 seconds
Started Feb 08 12:32:54 PM PST 24
Finished Feb 08 12:33:18 PM PST 24
Peak memory 204152 kb
Host smart-c997336a-8b3b-4b38-af68-6df4f1c900a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248464903 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.248464903
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.400880893
Short name T170
Test name
Test status
Simulation time 107640333 ps
CPU time 0.76 seconds
Started Feb 08 12:32:54 PM PST 24
Finished Feb 08 12:33:18 PM PST 24
Peak memory 204184 kb
Host smart-20bc9f9e-ed13-41c7-b41f-42d6b2fb9d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400880893 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.400880893
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.872702793
Short name T166
Test name
Test status
Simulation time 28650763 ps
CPU time 0.7 seconds
Started Feb 08 12:32:49 PM PST 24
Finished Feb 08 12:33:14 PM PST 24
Peak memory 204176 kb
Host smart-8e7f394a-c615-4b67-b02b-a3465789b9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872702793 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.872702793
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.1704582642
Short name T114
Test name
Test status
Simulation time 58344859 ps
CPU time 0.82 seconds
Started Feb 08 12:32:45 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 204180 kb
Host smart-19064785-df7a-4be5-8bfc-e8b9518c3566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704582642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
1704582642
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.4171383872
Short name T195
Test name
Test status
Simulation time 41451452 ps
CPU time 0.73 seconds
Started Feb 08 12:33:04 PM PST 24
Finished Feb 08 12:33:24 PM PST 24
Peak memory 204168 kb
Host smart-70abb774-200b-4f71-8617-856681cb5ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171383872 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
4171383872
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.897558971
Short name T243
Test name
Test status
Simulation time 37879957 ps
CPU time 0.82 seconds
Started Feb 08 12:32:49 PM PST 24
Finished Feb 08 12:33:15 PM PST 24
Peak memory 204208 kb
Host smart-6cea8637-6855-43b8-87cc-964a7d0eaeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897558971 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.897558971
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.4248524141
Short name T261
Test name
Test status
Simulation time 27521891 ps
CPU time 1.13 seconds
Started Feb 08 12:32:25 PM PST 24
Finished Feb 08 12:32:45 PM PST 24
Peak memory 212596 kb
Host smart-aa15c5d5-1cc1-45bb-8ec4-d61eef7dc172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248524141 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.4248524141
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.3029332648
Short name T173
Test name
Test status
Simulation time 17756748 ps
CPU time 1.13 seconds
Started Feb 08 12:32:19 PM PST 24
Finished Feb 08 12:32:43 PM PST 24
Peak memory 204648 kb
Host smart-951581c4-2843-4d87-b3df-dc8d8ddd9824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029332648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.3
029332648
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3164746224
Short name T274
Test name
Test status
Simulation time 38379011 ps
CPU time 0.71 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:46 PM PST 24
Peak memory 204104 kb
Host smart-873255e2-b1e0-45ce-a661-11d46f99a37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164746224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
164746224
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.545905785
Short name T219
Test name
Test status
Simulation time 425550051 ps
CPU time 1.15 seconds
Started Feb 08 12:32:25 PM PST 24
Finished Feb 08 12:32:46 PM PST 24
Peak memory 204300 kb
Host smart-2eb397aa-d5aa-4c78-8059-9aff3e85e220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545905785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_dpe_same_csr_outstanding.545905785
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.279055308
Short name T259
Test name
Test status
Simulation time 556605193 ps
CPU time 1.66 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212860 kb
Host smart-4756a82b-e514-48b5-ad16-b0b179817359
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279055308 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymg
r_dpe_shadow_reg_errors.279055308
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.4056004337
Short name T231
Test name
Test status
Simulation time 137120739 ps
CPU time 3.98 seconds
Started Feb 08 12:32:35 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 220712 kb
Host smart-8b9482b3-fe10-4552-8874-0778ed8280a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056004337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.4056004337
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.49231512
Short name T21
Test name
Test status
Simulation time 41661815 ps
CPU time 1.32 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212612 kb
Host smart-5b57cda3-670e-4e54-abc2-f397671de4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49231512 -assert nopostproc +UVM_TESTNAME=k
eymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.49231512
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.3441751568
Short name T303
Test name
Test status
Simulation time 190577512 ps
CPU time 0.91 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 204140 kb
Host smart-164df37c-ff47-4f41-9427-270226b6b676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441751568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.3
441751568
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1755463026
Short name T228
Test name
Test status
Simulation time 40410037 ps
CPU time 0.75 seconds
Started Feb 08 12:32:23 PM PST 24
Finished Feb 08 12:32:44 PM PST 24
Peak memory 204156 kb
Host smart-8fd80c07-7e1e-4cb7-9d76-e412787bab02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755463026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
755463026
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1817238093
Short name T38
Test name
Test status
Simulation time 565861167 ps
CPU time 1.45 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204372 kb
Host smart-1e9aa466-25cf-40cb-8130-5d0c5f2df6b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817238093 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1817238093
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.924133766
Short name T49
Test name
Test status
Simulation time 102804083 ps
CPU time 1.94 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212924 kb
Host smart-50aaca29-4d04-451b-a758-c1cf8a4e2bd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924133766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymg
r_dpe_shadow_reg_errors.924133766
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3745021321
Short name T73
Test name
Test status
Simulation time 106496674 ps
CPU time 4.27 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 212856 kb
Host smart-889df2e4-9f1f-4cc7-8633-0f9cb5d07f9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745021321 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3745021321
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.4087386436
Short name T20
Test name
Test status
Simulation time 86005645 ps
CPU time 2.72 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 212556 kb
Host smart-2aa6c653-0979-4ee8-b5f3-37b9486fa486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087386436 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.4
087386436
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.977832579
Short name T93
Test name
Test status
Simulation time 23489859 ps
CPU time 1.32 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204336 kb
Host smart-0bb5bb14-021c-4e1d-9434-af3a6ffc0284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977832579 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.977832579
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.3247641749
Short name T87
Test name
Test status
Simulation time 11594878 ps
CPU time 0.85 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 204172 kb
Host smart-ff835828-6bf9-4fdd-9af6-cbf8c314fdce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247641749 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.3
247641749
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2201035311
Short name T226
Test name
Test status
Simulation time 21066416 ps
CPU time 0.83 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 204208 kb
Host smart-7e80f5aa-1fe3-4153-b063-1a01f2dc8a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201035311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.2
201035311
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.821627421
Short name T292
Test name
Test status
Simulation time 25946715 ps
CPU time 1.62 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 204416 kb
Host smart-aab481b1-7495-4546-8afc-73c896836f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821627421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_dpe_same_csr_outstanding.821627421
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1541035018
Short name T199
Test name
Test status
Simulation time 335491312 ps
CPU time 3.09 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212960 kb
Host smart-548fcfbc-0413-400f-9d6f-0d3fe6e77f36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541035018 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1541035018
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3498875719
Short name T280
Test name
Test status
Simulation time 1815858675 ps
CPU time 8.22 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:54 PM PST 24
Peak memory 212988 kb
Host smart-2284d3ad-6229-4448-b656-4806d0d4291c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498875719 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3498875719
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2284322814
Short name T196
Test name
Test status
Simulation time 75728717 ps
CPU time 2.7 seconds
Started Feb 08 12:32:25 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 220804 kb
Host smart-e587b45a-c009-448c-8660-df476aa7659a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284322814 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
284322814
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3822296543
Short name T62
Test name
Test status
Simulation time 99625740 ps
CPU time 2.3 seconds
Started Feb 08 12:32:28 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 212560 kb
Host smart-277e8859-46b7-42fc-a166-e3925ecdde17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822296543 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.3822296543
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.313190964
Short name T236
Test name
Test status
Simulation time 257675109 ps
CPU time 1.55 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 220340 kb
Host smart-a3524c98-cc32-4ad1-a6b4-41dcf0dcd074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313190964 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.313190964
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.2976612724
Short name T86
Test name
Test status
Simulation time 73389970 ps
CPU time 0.98 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:49 PM PST 24
Peak memory 204140 kb
Host smart-84393490-3387-42bc-9d89-9e8d38e213d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976612724 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.2
976612724
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.4131367156
Short name T209
Test name
Test status
Simulation time 29075214 ps
CPU time 0.71 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 204088 kb
Host smart-56ca32df-5d51-4a4b-8a08-9c039f5ad799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131367156 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.4
131367156
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.3652147978
Short name T250
Test name
Test status
Simulation time 221452263 ps
CPU time 1.55 seconds
Started Feb 08 12:32:32 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 204344 kb
Host smart-c8c7390c-6520-4eb4-a7a4-f70e91492ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652147978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.3652147978
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1662246567
Short name T268
Test name
Test status
Simulation time 336854292 ps
CPU time 2.4 seconds
Started Feb 08 12:32:26 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 212908 kb
Host smart-cddc15ad-cd5d-4ac2-896b-b21e7feaffbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662246567 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1662246567
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3341686345
Short name T207
Test name
Test status
Simulation time 102117856 ps
CPU time 4.08 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 212924 kb
Host smart-c588102b-31e3-4665-b74e-a6944cf9b678
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341686345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3341686345
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.1162706054
Short name T42
Test name
Test status
Simulation time 323502936 ps
CPU time 3.98 seconds
Started Feb 08 12:32:37 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 220112 kb
Host smart-04416de0-03f3-42ec-9acd-cd440c7de9bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162706054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.1
162706054
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2540354761
Short name T189
Test name
Test status
Simulation time 371183203 ps
CPU time 3.9 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 212496 kb
Host smart-1263ba96-d921-4c96-b921-0dc1f2342a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540354761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2540354761
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2485110954
Short name T186
Test name
Test status
Simulation time 114403354 ps
CPU time 1.4 seconds
Started Feb 08 12:32:38 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 212552 kb
Host smart-19f416c8-4c5b-4db6-9f23-dd90948d7a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485110954 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2485110954
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2407573499
Short name T272
Test name
Test status
Simulation time 40428068 ps
CPU time 1.25 seconds
Started Feb 08 12:32:30 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204328 kb
Host smart-4915443f-0667-48cd-8ed8-0d69dc89e55a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407573499 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.2
407573499
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2656661061
Short name T74
Test name
Test status
Simulation time 76762155 ps
CPU time 0.85 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:50 PM PST 24
Peak memory 204080 kb
Host smart-5fde1d9a-9522-4168-8567-1205163288d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656661061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
656661061
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.892031399
Short name T64
Test name
Test status
Simulation time 147525489 ps
CPU time 2.45 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:52 PM PST 24
Peak memory 212772 kb
Host smart-6c388eb3-ab41-45f2-bbfd-7fad5e95b5d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892031399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymg
r_dpe_shadow_reg_errors.892031399
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3877552466
Short name T181
Test name
Test status
Simulation time 156212524 ps
CPU time 3.19 seconds
Started Feb 08 12:32:31 PM PST 24
Finished Feb 08 12:32:53 PM PST 24
Peak memory 212868 kb
Host smart-b13309f5-d931-4e19-9161-44c311cdfd00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877552466 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3877552466
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3630384929
Short name T255
Test name
Test status
Simulation time 312561550 ps
CPU time 3.07 seconds
Started Feb 08 12:32:29 PM PST 24
Finished Feb 08 12:32:51 PM PST 24
Peak memory 212588 kb
Host smart-e805e23d-9662-4cff-b971-20bd14076b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630384929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
630384929
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.177228192
Short name T23
Test name
Test status
Simulation time 1654845728 ps
CPU time 9.17 seconds
Started Feb 08 12:30:58 PM PST 24
Finished Feb 08 12:31:58 PM PST 24
Peak memory 233156 kb
Host smart-85d29e12-4a2d-4d5b-8023-902810e107a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177228192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.177228192
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.4196419500
Short name T78
Test name
Test status
Simulation time 1675238528 ps
CPU time 28.25 seconds
Started Feb 08 12:30:57 PM PST 24
Finished Feb 08 12:32:16 PM PST 24
Peak memory 207564 kb
Host smart-7dd15d53-1806-4a85-ad0b-21680bab9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196419500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.4196419500
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.3466779601
Short name T116
Test name
Test status
Simulation time 32310484 ps
CPU time 0.82 seconds
Started Feb 08 12:30:56 PM PST 24
Finished Feb 08 12:31:48 PM PST 24
Peak memory 205308 kb
Host smart-aa0d072b-70f8-4d3d-828d-a359c02d0c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466779601 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.3
466779601
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2383895579
Short name T140
Test name
Test status
Simulation time 25481331 ps
CPU time 0.81 seconds
Started Feb 08 12:31:41 PM PST 24
Finished Feb 08 12:32:16 PM PST 24
Peak memory 205236 kb
Host smart-3c32519e-6f34-4af2-bc52-e29c627b0eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383895579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2383895579
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.3682048623
Short name T136
Test name
Test status
Simulation time 12749922 ps
CPU time 0.84 seconds
Started Feb 08 12:31:25 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205252 kb
Host smart-21506ebd-b9fb-483e-90d5-fb70bcd7a755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682048623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
3682048623
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.3159795497
Short name T150
Test name
Test status
Simulation time 15519621578 ps
CPU time 117.57 seconds
Started Feb 08 12:31:40 PM PST 24
Finished Feb 08 12:34:13 PM PST 24
Peak memory 207224 kb
Host smart-53c03a0f-b48c-462c-b130-c3a048714c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159795497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.3159795497
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.3397135959
Short name T3
Test name
Test status
Simulation time 12837236 ps
CPU time 0.74 seconds
Started Feb 08 12:31:26 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205192 kb
Host smart-8380f3b9-906d-487e-b79c-eabdbd478387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397135959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
3397135959
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.3245603801
Short name T79
Test name
Test status
Simulation time 51187391 ps
CPU time 0.79 seconds
Started Feb 08 12:31:41 PM PST 24
Finished Feb 08 12:32:16 PM PST 24
Peak memory 205200 kb
Host smart-5407caa4-9223-45b1-8220-b5d80d349491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245603801 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
3245603801
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.4066770603
Short name T122
Test name
Test status
Simulation time 20852039 ps
CPU time 0.86 seconds
Started Feb 08 12:31:35 PM PST 24
Finished Feb 08 12:32:12 PM PST 24
Peak memory 205260 kb
Host smart-f9cc18b6-fb55-4ea3-a925-523893f23343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066770603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
4066770603
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1200504313
Short name T159
Test name
Test status
Simulation time 24304116 ps
CPU time 0.73 seconds
Started Feb 08 12:31:31 PM PST 24
Finished Feb 08 12:32:08 PM PST 24
Peak memory 205136 kb
Host smart-ac8d28d2-fc3e-4a11-a696-b661a0e3b305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200504313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1200504313
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.757848933
Short name T98
Test name
Test status
Simulation time 5897717701 ps
CPU time 38.72 seconds
Started Feb 08 12:31:44 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 207780 kb
Host smart-75497635-5be0-45b3-94b0-aa6905c9add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757848933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.757848933
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.2751968262
Short name T158
Test name
Test status
Simulation time 103735060 ps
CPU time 0.85 seconds
Started Feb 08 12:31:49 PM PST 24
Finished Feb 08 12:32:22 PM PST 24
Peak memory 204984 kb
Host smart-b24716d9-f9bc-4523-b555-5087b9890870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751968262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
2751968262
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1081832505
Short name T12
Test name
Test status
Simulation time 703894704 ps
CPU time 16.01 seconds
Started Feb 08 12:31:30 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 206236 kb
Host smart-11cb1556-06ae-4cea-a43e-1131795691c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081832505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1081832505
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3150663949
Short name T130
Test name
Test status
Simulation time 16870134 ps
CPU time 0.71 seconds
Started Feb 08 12:31:33 PM PST 24
Finished Feb 08 12:32:10 PM PST 24
Peak memory 205212 kb
Host smart-cd394b23-e144-47e2-987d-239e9475cf69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150663949 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3150663949
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.386640974
Short name T120
Test name
Test status
Simulation time 1512344519 ps
CPU time 25.46 seconds
Started Feb 08 12:31:30 PM PST 24
Finished Feb 08 12:32:32 PM PST 24
Peak memory 207916 kb
Host smart-22f8f271-1ca2-414b-9961-cbb49e140fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386640974 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.386640974
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.1185467432
Short name T137
Test name
Test status
Simulation time 29046575 ps
CPU time 0.73 seconds
Started Feb 08 12:31:28 PM PST 24
Finished Feb 08 12:32:06 PM PST 24
Peak memory 205204 kb
Host smart-8c0df969-ffb5-405b-bd09-75263cc17fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185467432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
1185467432
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.2823527931
Short name T157
Test name
Test status
Simulation time 3452559410 ps
CPU time 32.44 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:34 PM PST 24
Peak memory 208172 kb
Host smart-3027a2c1-4e12-48ca-bd85-799534c8e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823527931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.2823527931
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.717067144
Short name T145
Test name
Test status
Simulation time 37270935 ps
CPU time 0.8 seconds
Started Feb 08 12:31:28 PM PST 24
Finished Feb 08 12:32:06 PM PST 24
Peak memory 205156 kb
Host smart-43e43345-df59-4e55-8d4b-7fb028781814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717067144 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.717067144
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2494550405
Short name T125
Test name
Test status
Simulation time 1408856617 ps
CPU time 26.99 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:29 PM PST 24
Peak memory 207956 kb
Host smart-571a01b2-40f9-4574-9359-d7ac56ed1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494550405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2494550405
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1068091890
Short name T138
Test name
Test status
Simulation time 67325001 ps
CPU time 0.74 seconds
Started Feb 08 12:31:03 PM PST 24
Finished Feb 08 12:31:52 PM PST 24
Peak memory 205136 kb
Host smart-ac948c00-c360-41eb-ae65-82cef689a612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068091890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
068091890
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.1801644429
Short name T143
Test name
Test status
Simulation time 5609124234 ps
CPU time 29.21 seconds
Started Feb 08 12:30:58 PM PST 24
Finished Feb 08 12:32:18 PM PST 24
Peak memory 207464 kb
Host smart-436be389-5f90-491d-bfd3-40e3eefd9d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801644429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.1801644429
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.2465374672
Short name T117
Test name
Test status
Simulation time 78255727 ps
CPU time 0.87 seconds
Started Feb 08 12:31:25 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205144 kb
Host smart-6ca9d358-fae6-4d7d-a9d5-cac8eb98539b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465374672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
2465374672
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.3327931428
Short name T90
Test name
Test status
Simulation time 1652944256 ps
CPU time 17.73 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:19 PM PST 24
Peak memory 207764 kb
Host smart-84ec0481-f3c9-43c9-aecd-078831e1499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327931428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3327931428
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.141663699
Short name T118
Test name
Test status
Simulation time 16620258 ps
CPU time 0.83 seconds
Started Feb 08 12:31:29 PM PST 24
Finished Feb 08 12:32:07 PM PST 24
Peak memory 205468 kb
Host smart-f1e69e53-f189-4ddc-8a57-ac66590018c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141663699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.141663699
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.2591048548
Short name T160
Test name
Test status
Simulation time 43593864 ps
CPU time 0.73 seconds
Started Feb 08 12:31:40 PM PST 24
Finished Feb 08 12:32:16 PM PST 24
Peak memory 205112 kb
Host smart-9ee0fa01-e632-4501-bc66-706c04f27872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591048548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
2591048548
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.2177038470
Short name T10
Test name
Test status
Simulation time 227052422 ps
CPU time 11.36 seconds
Started Feb 08 12:31:35 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 207784 kb
Host smart-ebd19330-4fa9-414e-bb3b-46972813285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177038470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.2177038470
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3472270768
Short name T142
Test name
Test status
Simulation time 12126619 ps
CPU time 0.77 seconds
Started Feb 08 12:31:33 PM PST 24
Finished Feb 08 12:32:10 PM PST 24
Peak memory 205196 kb
Host smart-e7c9dcdf-06f8-464d-91ee-dbd93e48107a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472270768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3472270768
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3801442179
Short name T154
Test name
Test status
Simulation time 1252628704 ps
CPU time 25.49 seconds
Started Feb 08 12:31:23 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 208192 kb
Host smart-be73aa9a-8270-452d-9eff-cf4536c9d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801442179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3801442179
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1408973136
Short name T29
Test name
Test status
Simulation time 10712363 ps
CPU time 0.83 seconds
Started Feb 08 12:31:24 PM PST 24
Finished Feb 08 12:32:03 PM PST 24
Peak memory 205248 kb
Host smart-4fca9dee-05a3-4493-bf7d-44dc89e5473a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408973136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1408973136
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.3189072004
Short name T1
Test name
Test status
Simulation time 72145616 ps
CPU time 0.68 seconds
Started Feb 08 12:31:27 PM PST 24
Finished Feb 08 12:32:05 PM PST 24
Peak memory 205264 kb
Host smart-b9df25ba-d301-4c4b-ab8d-2f51c59645fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189072004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
3189072004
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.3557492792
Short name T146
Test name
Test status
Simulation time 1838317026 ps
CPU time 32.51 seconds
Started Feb 08 12:31:32 PM PST 24
Finished Feb 08 12:32:41 PM PST 24
Peak memory 208308 kb
Host smart-ba9fad18-6fa1-49fb-a09b-3c16d2baeb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557492792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.3557492792
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.4201275431
Short name T128
Test name
Test status
Simulation time 17820777 ps
CPU time 0.85 seconds
Started Feb 08 12:31:26 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205172 kb
Host smart-44571393-7f5a-4efa-b560-d4d558ac781e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201275431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
4201275431
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.3875150594
Short name T108
Test name
Test status
Simulation time 3171354457 ps
CPU time 25.63 seconds
Started Feb 08 12:31:27 PM PST 24
Finished Feb 08 12:32:29 PM PST 24
Peak memory 207972 kb
Host smart-172f4e9d-e962-4209-afa2-b02211ba19bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875150594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.3875150594
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.3515056539
Short name T121
Test name
Test status
Simulation time 59589947 ps
CPU time 0.76 seconds
Started Feb 08 12:31:26 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205248 kb
Host smart-d234b958-631f-41a6-89a5-fe3db113e250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515056539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
3515056539
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.205868496
Short name T11
Test name
Test status
Simulation time 651339262 ps
CPU time 22.21 seconds
Started Feb 08 12:31:28 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 207820 kb
Host smart-5ba161e2-cfd8-4244-83d8-0febdf4ec1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205868496 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.205868496
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.3819672887
Short name T133
Test name
Test status
Simulation time 48208831 ps
CPU time 0.85 seconds
Started Feb 08 12:31:35 PM PST 24
Finished Feb 08 12:32:13 PM PST 24
Peak memory 205148 kb
Host smart-1f0e7b3a-fe92-4731-bc5b-16b56b3135e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819672887 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
3819672887
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.780054503
Short name T144
Test name
Test status
Simulation time 10123369 ps
CPU time 0.72 seconds
Started Feb 08 12:31:47 PM PST 24
Finished Feb 08 12:32:20 PM PST 24
Peak memory 205276 kb
Host smart-b9e302fc-379d-450c-8aeb-3a849622f1d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780054503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.780054503
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1673649330
Short name T123
Test name
Test status
Simulation time 10529890 ps
CPU time 0.83 seconds
Started Feb 08 12:31:00 PM PST 24
Finished Feb 08 12:31:51 PM PST 24
Peak memory 205096 kb
Host smart-f22d66a5-cacb-44d1-adde-a2420bd5cdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673649330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
673649330
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.539404412
Short name T22
Test name
Test status
Simulation time 842368629 ps
CPU time 19.79 seconds
Started Feb 08 12:31:08 PM PST 24
Finished Feb 08 12:32:14 PM PST 24
Peak memory 229960 kb
Host smart-200b66ab-37dd-43a6-985f-2fe4b00204ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539404412 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.539404412
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3475957814
Short name T25
Test name
Test status
Simulation time 36097045 ps
CPU time 0.77 seconds
Started Feb 08 12:31:49 PM PST 24
Finished Feb 08 12:32:22 PM PST 24
Peak memory 205260 kb
Host smart-44dc1763-f103-4ab0-8eed-701892e131b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475957814 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3475957814
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.2833605153
Short name T110
Test name
Test status
Simulation time 1682606627 ps
CPU time 16.65 seconds
Started Feb 08 12:31:47 PM PST 24
Finished Feb 08 12:32:36 PM PST 24
Peak memory 206364 kb
Host smart-02f0060e-760b-4010-aac1-707bee7d5465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833605153 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.2833605153
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.895124446
Short name T149
Test name
Test status
Simulation time 15330980 ps
CPU time 0.74 seconds
Started Feb 08 12:31:45 PM PST 24
Finished Feb 08 12:32:19 PM PST 24
Peak memory 205264 kb
Host smart-15c6880e-164c-46ab-a9e9-83f75254f6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895124446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.895124446
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.3347951104
Short name T26
Test name
Test status
Simulation time 2075754558 ps
CPU time 19.86 seconds
Started Feb 08 12:31:48 PM PST 24
Finished Feb 08 12:32:40 PM PST 24
Peak memory 207816 kb
Host smart-ba34423d-00b2-4e72-a4cc-19485de11efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347951104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.3347951104
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2933063580
Short name T132
Test name
Test status
Simulation time 15936170 ps
CPU time 0.95 seconds
Started Feb 08 12:31:45 PM PST 24
Finished Feb 08 12:32:19 PM PST 24
Peak memory 205444 kb
Host smart-6255e016-de40-4643-b025-7b3140d01d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933063580 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2933063580
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.2960729703
Short name T129
Test name
Test status
Simulation time 1798430916 ps
CPU time 18.79 seconds
Started Feb 08 12:31:45 PM PST 24
Finished Feb 08 12:32:37 PM PST 24
Peak memory 207916 kb
Host smart-03efecad-039c-4e96-9ad3-2828270924a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960729703 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.2960729703
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.4285946575
Short name T30
Test name
Test status
Simulation time 45237699 ps
CPU time 0.94 seconds
Started Feb 08 12:31:44 PM PST 24
Finished Feb 08 12:32:19 PM PST 24
Peak memory 205248 kb
Host smart-0fd74e39-92a9-4a15-876d-ebc5dee34743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285946575 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
4285946575
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.2730652213
Short name T28
Test name
Test status
Simulation time 6250335680 ps
CPU time 26.09 seconds
Started Feb 08 12:31:50 PM PST 24
Finished Feb 08 12:32:48 PM PST 24
Peak memory 207324 kb
Host smart-7ef0d1ae-c2eb-42ee-9725-0a3cc1ea4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730652213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2730652213
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.1482664486
Short name T139
Test name
Test status
Simulation time 171129835 ps
CPU time 0.83 seconds
Started Feb 08 12:31:45 PM PST 24
Finished Feb 08 12:32:20 PM PST 24
Peak memory 205264 kb
Host smart-06f7524b-0810-474e-ad29-054858ae8f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482664486 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
1482664486
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.601105319
Short name T77
Test name
Test status
Simulation time 158689320 ps
CPU time 8.51 seconds
Started Feb 08 12:31:45 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 207256 kb
Host smart-c3bb64e6-d7a1-4583-b198-8197aa6bb590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601105319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.601105319
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.901547668
Short name T156
Test name
Test status
Simulation time 33709284 ps
CPU time 0.83 seconds
Started Feb 08 12:31:50 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 205304 kb
Host smart-88e3cba8-9e4d-41bd-aee0-72d87939d7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901547668 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.901547668
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3928092089
Short name T112
Test name
Test status
Simulation time 1068800004 ps
CPU time 16.72 seconds
Started Feb 08 12:31:57 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 207572 kb
Host smart-f099ea40-229d-45d7-a7cb-9af04bc22e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928092089 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3928092089
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.3814291866
Short name T31
Test name
Test status
Simulation time 31031882 ps
CPU time 0.84 seconds
Started Feb 08 12:31:43 PM PST 24
Finished Feb 08 12:32:18 PM PST 24
Peak memory 205244 kb
Host smart-d6b1af20-4ec8-4e30-b097-9ba0ea072891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814291866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
3814291866
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.4064004768
Short name T119
Test name
Test status
Simulation time 2975889847 ps
CPU time 43.15 seconds
Started Feb 08 12:31:59 PM PST 24
Finished Feb 08 12:33:14 PM PST 24
Peak memory 207644 kb
Host smart-1e4238c2-810e-4319-9798-b131c9347335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064004768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.4064004768
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.473818165
Short name T152
Test name
Test status
Simulation time 51632548 ps
CPU time 0.76 seconds
Started Feb 08 12:31:57 PM PST 24
Finished Feb 08 12:32:31 PM PST 24
Peak memory 205136 kb
Host smart-53baa8f2-028a-4de7-bbb4-d6120dd85f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473818165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.473818165
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.597652453
Short name T27
Test name
Test status
Simulation time 149854076 ps
CPU time 0.82 seconds
Started Feb 08 12:31:53 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 205260 kb
Host smart-03330590-a49b-4f8f-a573-db66bc0f7ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597652453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.597652453
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1792928762
Short name T148
Test name
Test status
Simulation time 52543656 ps
CPU time 0.73 seconds
Started Feb 08 12:31:51 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 205260 kb
Host smart-bb2d540a-e390-4eec-910a-23b092a01cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792928762 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1792928762
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2444346913
Short name T161
Test name
Test status
Simulation time 9694418 ps
CPU time 0.78 seconds
Started Feb 08 12:30:59 PM PST 24
Finished Feb 08 12:31:51 PM PST 24
Peak memory 205156 kb
Host smart-25409a1a-6bbc-4993-9cca-22bf0c1ec3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444346913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
444346913
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.4038830332
Short name T9
Test name
Test status
Simulation time 2513113740 ps
CPU time 14.26 seconds
Started Feb 08 12:30:59 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 233896 kb
Host smart-8d97e428-43e6-4f7f-925c-786bbab13bb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038830332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.4038830332
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1247891515
Short name T141
Test name
Test status
Simulation time 13509736 ps
CPU time 0.74 seconds
Started Feb 08 12:31:57 PM PST 24
Finished Feb 08 12:32:31 PM PST 24
Peak memory 205212 kb
Host smart-c012c890-bfc7-4460-b69c-31a4cbbb1a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247891515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1247891515
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2139996712
Short name T109
Test name
Test status
Simulation time 183663128 ps
CPU time 10.85 seconds
Started Feb 08 12:32:01 PM PST 24
Finished Feb 08 12:32:43 PM PST 24
Peak memory 208212 kb
Host smart-1050930f-5ec7-46ec-8218-aeb594d194fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139996712 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2139996712
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3887018210
Short name T135
Test name
Test status
Simulation time 20320282 ps
CPU time 0.95 seconds
Started Feb 08 12:31:48 PM PST 24
Finished Feb 08 12:32:21 PM PST 24
Peak memory 205432 kb
Host smart-33e4f3c8-4159-422f-ae1c-315b77386bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887018210 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3887018210
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.3467505257
Short name T89
Test name
Test status
Simulation time 5979997634 ps
CPU time 45.12 seconds
Started Feb 08 12:31:54 PM PST 24
Finished Feb 08 12:33:11 PM PST 24
Peak memory 207640 kb
Host smart-56a4c899-70d8-41e2-a2f9-e5c14a0e96e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467505257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.3467505257
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.4084776495
Short name T18
Test name
Test status
Simulation time 16649031 ps
CPU time 0.76 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:26 PM PST 24
Peak memory 205216 kb
Host smart-125bad75-da3f-412a-93f2-50df20c9ff36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084776495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
4084776495
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3415153041
Short name T14
Test name
Test status
Simulation time 908997260 ps
CPU time 24.15 seconds
Started Feb 08 12:32:01 PM PST 24
Finished Feb 08 12:32:57 PM PST 24
Peak memory 207444 kb
Host smart-6aee05c9-9a85-494b-b173-94a0ca0074e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415153041 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3415153041
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.4105535647
Short name T2
Test name
Test status
Simulation time 19937415 ps
CPU time 0.81 seconds
Started Feb 08 12:32:02 PM PST 24
Finished Feb 08 12:32:33 PM PST 24
Peak memory 205232 kb
Host smart-0b3b9f56-96c8-4b07-833d-0c30b7a23f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105535647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
4105535647
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.337694767
Short name T126
Test name
Test status
Simulation time 53417298 ps
CPU time 0.9 seconds
Started Feb 08 12:31:57 PM PST 24
Finished Feb 08 12:32:31 PM PST 24
Peak memory 205316 kb
Host smart-f0818362-561d-4877-981b-4b8a0f2715ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337694767 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.337694767
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.690932054
Short name T104
Test name
Test status
Simulation time 15204831686 ps
CPU time 34.32 seconds
Started Feb 08 12:31:53 PM PST 24
Finished Feb 08 12:33:00 PM PST 24
Peak memory 207324 kb
Host smart-ab6e7053-4015-4426-86aa-0eb9fed6f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690932054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.690932054
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1163751112
Short name T124
Test name
Test status
Simulation time 20260699 ps
CPU time 0.83 seconds
Started Feb 08 12:31:50 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 205320 kb
Host smart-2e1cae0f-4271-4a9a-8c76-3c7ce83a0213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163751112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1163751112
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.2185297629
Short name T85
Test name
Test status
Simulation time 3748147193 ps
CPU time 33.27 seconds
Started Feb 08 12:31:56 PM PST 24
Finished Feb 08 12:33:02 PM PST 24
Peak memory 207476 kb
Host smart-afd48bb0-447f-4c21-8f19-cf50082bbffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185297629 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.2185297629
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.733373920
Short name T153
Test name
Test status
Simulation time 14226231 ps
CPU time 0.87 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:25 PM PST 24
Peak memory 205244 kb
Host smart-97db99b2-7cc7-4b66-b820-92892aa5ab53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733373920 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.733373920
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3785303300
Short name T83
Test name
Test status
Simulation time 4246604729 ps
CPU time 21.14 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:46 PM PST 24
Peak memory 208088 kb
Host smart-077738d4-327f-4565-9f15-459880a872a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785303300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3785303300
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.45752924
Short name T127
Test name
Test status
Simulation time 7692289 ps
CPU time 0.81 seconds
Started Feb 08 12:31:52 PM PST 24
Finished Feb 08 12:32:26 PM PST 24
Peak memory 205140 kb
Host smart-761b1376-58f8-4b95-8367-ff77b4c9334b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45752924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.45752924
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2824511822
Short name T151
Test name
Test status
Simulation time 68088234 ps
CPU time 0.82 seconds
Started Feb 08 12:31:50 PM PST 24
Finished Feb 08 12:32:23 PM PST 24
Peak memory 205260 kb
Host smart-27f5cb58-55ad-4205-ad0f-9739f4f26834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824511822 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2824511822
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.602041120
Short name T106
Test name
Test status
Simulation time 789387995 ps
CPU time 16.47 seconds
Started Feb 08 12:31:50 PM PST 24
Finished Feb 08 12:32:38 PM PST 24
Peak memory 208160 kb
Host smart-cffecd9c-9a19-4795-9c7b-cc6224e0e26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602041120 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.602041120
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.3021441540
Short name T115
Test name
Test status
Simulation time 199638806 ps
CPU time 0.91 seconds
Started Feb 08 12:31:54 PM PST 24
Finished Feb 08 12:32:27 PM PST 24
Peak memory 205184 kb
Host smart-2625f846-9809-453c-af32-141b6047f58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021441540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
3021441540
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.1890684548
Short name T15
Test name
Test status
Simulation time 2153275947 ps
CPU time 17.3 seconds
Started Feb 08 12:31:58 PM PST 24
Finished Feb 08 12:32:47 PM PST 24
Peak memory 207348 kb
Host smart-e4c722d4-cae9-4384-a96e-deded1ffd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890684548 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.1890684548
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.3559474804
Short name T17
Test name
Test status
Simulation time 25425064 ps
CPU time 0.84 seconds
Started Feb 08 12:31:23 PM PST 24
Finished Feb 08 12:32:03 PM PST 24
Peak memory 205156 kb
Host smart-2d6adb87-1172-4af3-8f6c-5745376ea45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559474804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.3
559474804
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3083630116
Short name T155
Test name
Test status
Simulation time 45331733 ps
CPU time 0.78 seconds
Started Feb 08 12:31:24 PM PST 24
Finished Feb 08 12:32:04 PM PST 24
Peak memory 205552 kb
Host smart-b239c491-1564-468a-869e-0b70c9df65b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083630116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
083630116
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.421269487
Short name T147
Test name
Test status
Simulation time 1113991740 ps
CPU time 21.99 seconds
Started Feb 08 12:31:23 PM PST 24
Finished Feb 08 12:32:24 PM PST 24
Peak memory 207996 kb
Host smart-e9b025c6-b790-46f6-a5a9-9fd548f3b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421269487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.421269487
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.2952658340
Short name T134
Test name
Test status
Simulation time 11542397 ps
CPU time 0.77 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:02 PM PST 24
Peak memory 205288 kb
Host smart-fa592edd-b524-43fa-bd18-ab9ec268743f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952658340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.2
952658340
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.4195062846
Short name T6
Test name
Test status
Simulation time 594235775 ps
CPU time 22.22 seconds
Started Feb 08 12:31:24 PM PST 24
Finished Feb 08 12:32:25 PM PST 24
Peak memory 207528 kb
Host smart-6d4445b8-1eac-49ec-9674-3207c2f034fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195062846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.4195062846
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2317750036
Short name T162
Test name
Test status
Simulation time 65337939 ps
CPU time 0.77 seconds
Started Feb 08 12:31:22 PM PST 24
Finished Feb 08 12:32:02 PM PST 24
Peak memory 205220 kb
Host smart-bc137ad5-6bd8-4c41-8823-a54de2e39c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317750036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
317750036
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.659491642
Short name T131
Test name
Test status
Simulation time 21845583 ps
CPU time 0.8 seconds
Started Feb 08 12:31:41 PM PST 24
Finished Feb 08 12:32:16 PM PST 24
Peak memory 205204 kb
Host smart-12ce60ac-a656-4699-8634-75f968059fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659491642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.659491642
Directory /workspace/9.keymgr_dpe_alert_test/latest
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