Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.25 97.70 90.49 57.52 76.92 94.94 98.34 17.82


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T253 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3248156717 Feb 19 01:28:24 PM PST 24 Feb 19 01:28:27 PM PST 24 312113036 ps
T254 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.3983925253 Feb 19 01:28:12 PM PST 24 Feb 19 01:28:15 PM PST 24 43520145 ps
T255 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3105675240 Feb 19 01:28:51 PM PST 24 Feb 19 01:28:54 PM PST 24 232330355 ps
T256 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3836827387 Feb 19 01:28:08 PM PST 24 Feb 19 01:28:11 PM PST 24 334617351 ps
T257 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3646762721 Feb 19 01:28:19 PM PST 24 Feb 19 01:28:21 PM PST 24 64975158 ps
T258 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.249668825 Feb 19 01:28:59 PM PST 24 Feb 19 01:29:02 PM PST 24 32533131 ps
T259 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2238933551 Feb 19 01:29:21 PM PST 24 Feb 19 01:29:23 PM PST 24 22847038 ps
T260 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2643645915 Feb 19 01:28:20 PM PST 24 Feb 19 01:28:22 PM PST 24 17367034 ps
T261 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2912504392 Feb 19 01:28:23 PM PST 24 Feb 19 01:28:29 PM PST 24 1246184836 ps
T262 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1637356511 Feb 19 01:28:58 PM PST 24 Feb 19 01:29:02 PM PST 24 106674466 ps
T263 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.961412804 Feb 19 01:28:32 PM PST 24 Feb 19 01:28:36 PM PST 24 50370800 ps
T264 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.235584229 Feb 19 01:28:19 PM PST 24 Feb 19 01:28:20 PM PST 24 35899319 ps
T265 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3524728369 Feb 19 01:28:57 PM PST 24 Feb 19 01:29:00 PM PST 24 112499050 ps
T266 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.106679023 Feb 19 01:29:07 PM PST 24 Feb 19 01:29:15 PM PST 24 257197111 ps
T267 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2858686136 Feb 19 01:28:15 PM PST 24 Feb 19 01:28:18 PM PST 24 71903312 ps
T268 /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3522542794 Feb 19 01:29:10 PM PST 24 Feb 19 01:29:14 PM PST 24 25189480 ps
T269 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3241242860 Feb 19 01:28:24 PM PST 24 Feb 19 01:28:27 PM PST 24 51318722 ps
T270 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.93806776 Feb 19 01:29:15 PM PST 24 Feb 19 01:29:19 PM PST 24 11917349 ps
T271 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.4041521132 Feb 19 01:28:30 PM PST 24 Feb 19 01:28:32 PM PST 24 22277278 ps
T272 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1657441933 Feb 19 01:28:25 PM PST 24 Feb 19 01:28:27 PM PST 24 29480945 ps
T273 /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.1132774289 Feb 19 01:28:13 PM PST 24 Feb 19 01:28:15 PM PST 24 10613591 ps
T274 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.6790456 Feb 19 01:29:08 PM PST 24 Feb 19 01:29:12 PM PST 24 149133117 ps
T275 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.3967047269 Feb 19 01:28:52 PM PST 24 Feb 19 01:28:54 PM PST 24 23027829 ps
T276 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.1814024614 Feb 19 01:28:13 PM PST 24 Feb 19 01:28:15 PM PST 24 51214370 ps
T277 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1335414317 Feb 19 01:29:03 PM PST 24 Feb 19 01:29:10 PM PST 24 137300710 ps
T278 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.856980284 Feb 19 01:28:54 PM PST 24 Feb 19 01:28:56 PM PST 24 68883930 ps
T279 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1855588098 Feb 19 01:28:30 PM PST 24 Feb 19 01:28:33 PM PST 24 117531714 ps
T280 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2255914890 Feb 19 01:28:08 PM PST 24 Feb 19 01:28:10 PM PST 24 666635700 ps
T54 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.682167500 Feb 19 01:28:27 PM PST 24 Feb 19 01:28:32 PM PST 24 190133887 ps
T281 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2946637036 Feb 19 01:28:44 PM PST 24 Feb 19 01:28:46 PM PST 24 33510378 ps
T282 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4214506904 Feb 19 01:28:26 PM PST 24 Feb 19 01:28:28 PM PST 24 70552698 ps
T283 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3011693754 Feb 19 01:29:14 PM PST 24 Feb 19 01:29:18 PM PST 24 43540511 ps
T284 /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1667377776 Feb 19 01:28:56 PM PST 24 Feb 19 01:29:01 PM PST 24 240243062 ps
T285 /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1700381507 Feb 19 01:29:24 PM PST 24 Feb 19 01:29:26 PM PST 24 40437076 ps
T286 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.80761220 Feb 19 01:28:08 PM PST 24 Feb 19 01:28:11 PM PST 24 80562304 ps
T287 /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1779023852 Feb 19 01:29:00 PM PST 24 Feb 19 01:29:03 PM PST 24 50245285 ps
T288 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2096600222 Feb 19 01:28:13 PM PST 24 Feb 19 01:28:15 PM PST 24 32836962 ps
T289 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3772287242 Feb 19 01:29:08 PM PST 24 Feb 19 01:29:16 PM PST 24 244318548 ps
T290 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1749223420 Feb 19 01:28:26 PM PST 24 Feb 19 01:28:28 PM PST 24 41045820 ps
T291 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.529651970 Feb 19 01:28:58 PM PST 24 Feb 19 01:29:03 PM PST 24 63160187 ps
T292 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2206026013 Feb 19 01:28:31 PM PST 24 Feb 19 01:28:33 PM PST 24 15748836 ps
T293 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2631159475 Feb 19 01:28:47 PM PST 24 Feb 19 01:28:50 PM PST 24 26261274 ps
T294 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.2615778643 Feb 19 01:28:23 PM PST 24 Feb 19 01:28:29 PM PST 24 397754500 ps
T53 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.204995699 Feb 19 01:28:24 PM PST 24 Feb 19 01:28:29 PM PST 24 94819347 ps
T295 /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.798232565 Feb 19 01:29:14 PM PST 24 Feb 19 01:29:18 PM PST 24 11312129 ps
T296 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.301927058 Feb 19 01:28:12 PM PST 24 Feb 19 01:28:19 PM PST 24 739523802 ps
T297 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.85544170 Feb 19 01:28:58 PM PST 24 Feb 19 01:29:04 PM PST 24 82274702 ps
T298 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.3559873195 Feb 19 01:28:20 PM PST 24 Feb 19 01:28:24 PM PST 24 241196621 ps
T299 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1167259338 Feb 19 01:28:59 PM PST 24 Feb 19 01:29:08 PM PST 24 277573623 ps
T300 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.30356711 Feb 19 01:28:59 PM PST 24 Feb 19 01:29:03 PM PST 24 206938155 ps
T301 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.102868213 Feb 19 01:28:21 PM PST 24 Feb 19 01:28:24 PM PST 24 58608922 ps
T302 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3454364612 Feb 19 01:28:10 PM PST 24 Feb 19 01:28:12 PM PST 24 14030134 ps
T303 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1338038785 Feb 19 01:29:06 PM PST 24 Feb 19 01:29:09 PM PST 24 269823633 ps
T304 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.2708768372 Feb 19 01:28:47 PM PST 24 Feb 19 01:28:51 PM PST 24 132256370 ps
T305 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.206267327 Feb 19 01:29:10 PM PST 24 Feb 19 01:29:14 PM PST 24 41622327 ps
T306 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.4237292680 Feb 19 01:29:11 PM PST 24 Feb 19 01:29:15 PM PST 24 72259753 ps
T307 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.3317094690 Feb 19 01:28:22 PM PST 24 Feb 19 01:28:24 PM PST 24 11598734 ps
T308 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2115952337 Feb 19 01:29:00 PM PST 24 Feb 19 01:29:05 PM PST 24 224721354 ps
T309 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3923336037 Feb 19 01:29:18 PM PST 24 Feb 19 01:29:19 PM PST 24 11525682 ps

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.3063268671
Short name T1
Test name
Test status
Simulation time 2141532929 ps
CPU time 36.05 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:05:34 PM PST 24
Peak memory 207944 kb
Host smart-286d9525-31de-4ac1-b4f2-c4f9c27ee620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063268671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.3063268671
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.1426458162
Short name T4
Test name
Test status
Simulation time 1229563058 ps
CPU time 13.98 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:05:01 PM PST 24
Peak memory 233248 kb
Host smart-e6caba49-1799-4516-9fe0-ecab89f2fab0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426458162 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.1426458162
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2435272214
Short name T29
Test name
Test status
Simulation time 1026742918 ps
CPU time 6.03 seconds
Started Feb 19 01:28:21 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 213188 kb
Host smart-a29aebd6-7aa9-4695-8eb6-086ea330cef3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435272214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2435272214
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1684285140
Short name T19
Test name
Test status
Simulation time 225301952 ps
CPU time 2.92 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:27 PM PST 24
Peak memory 214996 kb
Host smart-963c5331-7c30-49f5-aebf-5a67aaa69039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684285140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.1
684285140
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.1583346143
Short name T14
Test name
Test status
Simulation time 871677706 ps
CPU time 13.85 seconds
Started Feb 19 01:05:12 PM PST 24
Finished Feb 19 01:05:27 PM PST 24
Peak memory 206168 kb
Host smart-1c492065-4fde-44f9-ac8c-d595e937b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583346143 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1583346143
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.840773674
Short name T44
Test name
Test status
Simulation time 176731835 ps
CPU time 3.99 seconds
Started Feb 19 01:29:02 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 212532 kb
Host smart-1261675a-024b-4293-9591-a675aa5ff87b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840773674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.840773674
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.3046252941
Short name T18
Test name
Test status
Simulation time 21737175 ps
CPU time 0.75 seconds
Started Feb 19 01:04:49 PM PST 24
Finished Feb 19 01:04:50 PM PST 24
Peak memory 205320 kb
Host smart-78736935-c6aa-49af-b4b5-6d90c9b6414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046252941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.3
046252941
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.4208534950
Short name T42
Test name
Test status
Simulation time 50235792 ps
CPU time 0.74 seconds
Started Feb 19 01:28:07 PM PST 24
Finished Feb 19 01:28:09 PM PST 24
Peak memory 204208 kb
Host smart-01118bef-5542-4454-8348-c9ebd0fcdf5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208534950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.4
208534950
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.4089311482
Short name T85
Test name
Test status
Simulation time 1796271831 ps
CPU time 20.67 seconds
Started Feb 19 01:04:45 PM PST 24
Finished Feb 19 01:05:07 PM PST 24
Peak memory 207968 kb
Host smart-b3a5c1bc-9b8c-40c4-b332-4dc5e13d2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089311482 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.4089311482
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1493139666
Short name T39
Test name
Test status
Simulation time 26380922 ps
CPU time 1.63 seconds
Started Feb 19 01:28:56 PM PST 24
Finished Feb 19 01:29:00 PM PST 24
Peak memory 220784 kb
Host smart-961409b6-85be-40cd-a4a6-bb70e7ac9bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493139666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1493139666
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2069611457
Short name T21
Test name
Test status
Simulation time 90335149 ps
CPU time 3.15 seconds
Started Feb 19 01:28:48 PM PST 24
Finished Feb 19 01:28:52 PM PST 24
Peak memory 204436 kb
Host smart-164fe5c9-fb61-41b7-a090-2bcd09939843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069611457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.2069611457
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.549630612
Short name T50
Test name
Test status
Simulation time 164024875 ps
CPU time 2.13 seconds
Started Feb 19 01:28:54 PM PST 24
Finished Feb 19 01:28:57 PM PST 24
Peak memory 204516 kb
Host smart-7f6e8e7a-a275-4bb0-99fb-8e2239be48f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549630612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe
_tl_intg_err.549630612
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1677571123
Short name T30
Test name
Test status
Simulation time 413266437 ps
CPU time 3.36 seconds
Started Feb 19 01:28:08 PM PST 24
Finished Feb 19 01:28:13 PM PST 24
Peak memory 213028 kb
Host smart-e97b9371-39bc-41ff-aaf9-f0d545704eb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677571123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1677571123
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.1170352124
Short name T57
Test name
Test status
Simulation time 372085403 ps
CPU time 3.83 seconds
Started Feb 19 01:28:18 PM PST 24
Finished Feb 19 01:28:23 PM PST 24
Peak memory 213584 kb
Host smart-6fc7f984-601d-43d7-ac2c-24a3526ef7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170352124 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.1170352124
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3744259961
Short name T46
Test name
Test status
Simulation time 74728437 ps
CPU time 2.26 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:16 PM PST 24
Peak memory 212880 kb
Host smart-69c3d840-544c-49f7-9fc2-22aa333db1f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744259961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3744259961
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2574184762
Short name T5
Test name
Test status
Simulation time 2785928030 ps
CPU time 10.51 seconds
Started Feb 19 01:04:43 PM PST 24
Finished Feb 19 01:04:55 PM PST 24
Peak memory 231140 kb
Host smart-5ad65e30-b608-4a23-9da3-35536f60f295
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574184762 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2574184762
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.795539199
Short name T40
Test name
Test status
Simulation time 12555171 ps
CPU time 0.72 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:01 PM PST 24
Peak memory 204268 kb
Host smart-cfd4921e-9520-41eb-89c0-c9b57fdd0ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795539199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.795539199
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3064835274
Short name T51
Test name
Test status
Simulation time 90887427 ps
CPU time 4.71 seconds
Started Feb 19 01:28:18 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 212468 kb
Host smart-e0543832-168c-45a0-8ac0-3e0ccd9bb3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064835274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3064835274
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3416617057
Short name T26
Test name
Test status
Simulation time 220276439 ps
CPU time 5.28 seconds
Started Feb 19 01:28:37 PM PST 24
Finished Feb 19 01:28:43 PM PST 24
Peak memory 214084 kb
Host smart-057f2074-1eba-40b4-824d-20c3d97d8c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416617057 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3416617057
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3524728369
Short name T265
Test name
Test status
Simulation time 112499050 ps
CPU time 1.32 seconds
Started Feb 19 01:28:57 PM PST 24
Finished Feb 19 01:29:00 PM PST 24
Peak memory 212728 kb
Host smart-ce09247f-4f58-462b-b046-9f786840948c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524728369 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3524728369
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.1366833209
Short name T87
Test name
Test status
Simulation time 9531837146 ps
CPU time 30.38 seconds
Started Feb 19 01:04:45 PM PST 24
Finished Feb 19 01:05:17 PM PST 24
Peak memory 207276 kb
Host smart-d2f89e25-bb03-4aab-ae2e-6e11af66cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366833209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.1366833209
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.2288166184
Short name T92
Test name
Test status
Simulation time 4599555791 ps
CPU time 42.84 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:42 PM PST 24
Peak memory 207620 kb
Host smart-816006ca-f7d0-4c88-b603-7bd198307218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288166184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.2288166184
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.225492137
Short name T94
Test name
Test status
Simulation time 2413743685 ps
CPU time 19.17 seconds
Started Feb 19 01:05:03 PM PST 24
Finished Feb 19 01:05:24 PM PST 24
Peak memory 208208 kb
Host smart-2f094bf9-61b5-4aca-ad39-3d257de3b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225492137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.225492137
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2488072816
Short name T2
Test name
Test status
Simulation time 5996465213 ps
CPU time 30.98 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:05:28 PM PST 24
Peak memory 207188 kb
Host smart-971a9ee0-b02d-4481-87fa-71627421392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488072816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2488072816
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.1176694918
Short name T77
Test name
Test status
Simulation time 772016412 ps
CPU time 19.22 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:05:17 PM PST 24
Peak memory 206052 kb
Host smart-93eedef4-9c2b-4bf2-8004-9631719abbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176694918 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.1176694918
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.4142682350
Short name T89
Test name
Test status
Simulation time 4243568839 ps
CPU time 32.11 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:32 PM PST 24
Peak memory 207772 kb
Host smart-5be9787b-93d3-43c8-9d3c-892abc24d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142682350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.4142682350
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.560487063
Short name T9
Test name
Test status
Simulation time 4467887825 ps
CPU time 68.95 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:06:06 PM PST 24
Peak memory 209372 kb
Host smart-2e5bffea-d0d2-47cb-ad2f-a39614a34894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560487063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.560487063
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.129404928
Short name T95
Test name
Test status
Simulation time 962638821 ps
CPU time 15.45 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:17 PM PST 24
Peak memory 207848 kb
Host smart-2af6a0f5-1eb2-4e42-a23c-559c60255969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129404928 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.129404928
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.929951333
Short name T81
Test name
Test status
Simulation time 2817178645 ps
CPU time 25.93 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:27 PM PST 24
Peak memory 207180 kb
Host smart-b4b094a5-77a1-48da-b1b1-1a2b37f84c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929951333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.929951333
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3516369256
Short name T70
Test name
Test status
Simulation time 1523699534 ps
CPU time 26.84 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:26 PM PST 24
Peak memory 207324 kb
Host smart-e6742552-66a9-4797-ae83-be480f4fc56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516369256 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3516369256
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1583562741
Short name T90
Test name
Test status
Simulation time 268258729 ps
CPU time 12.76 seconds
Started Feb 19 01:05:07 PM PST 24
Finished Feb 19 01:05:22 PM PST 24
Peak memory 207340 kb
Host smart-925abf99-df8b-4986-94db-34740e970f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583562741 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1583562741
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1763525368
Short name T76
Test name
Test status
Simulation time 498020479 ps
CPU time 16.87 seconds
Started Feb 19 01:05:07 PM PST 24
Finished Feb 19 01:05:26 PM PST 24
Peak memory 207492 kb
Host smart-b3046d7d-1b17-488e-91c6-57368ba0ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763525368 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1763525368
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.4146674652
Short name T91
Test name
Test status
Simulation time 787517666 ps
CPU time 21.97 seconds
Started Feb 19 01:05:02 PM PST 24
Finished Feb 19 01:05:25 PM PST 24
Peak memory 207140 kb
Host smart-016e4f37-430f-447f-adcd-1aa69c5471cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146674652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.4146674652
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.148714563
Short name T88
Test name
Test status
Simulation time 908439300 ps
CPU time 24.41 seconds
Started Feb 19 01:04:43 PM PST 24
Finished Feb 19 01:05:09 PM PST 24
Peak memory 207772 kb
Host smart-4a2640f1-5331-4155-ade2-2a906b860f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148714563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.148714563
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.3983925253
Short name T254
Test name
Test status
Simulation time 43520145 ps
CPU time 2.55 seconds
Started Feb 19 01:28:12 PM PST 24
Finished Feb 19 01:28:15 PM PST 24
Peak memory 204468 kb
Host smart-2b1e0d96-6bb2-402a-a4b9-774a8fa09b32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983925253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.3983925253
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2904305457
Short name T163
Test name
Test status
Simulation time 1162227403 ps
CPU time 17.76 seconds
Started Feb 19 01:28:14 PM PST 24
Finished Feb 19 01:28:32 PM PST 24
Peak memory 204432 kb
Host smart-d80ec1e8-1b11-4996-9611-cd1365d139cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904305457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2904305457
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.1243678242
Short name T169
Test name
Test status
Simulation time 55754427 ps
CPU time 1.06 seconds
Started Feb 19 01:28:05 PM PST 24
Finished Feb 19 01:28:07 PM PST 24
Peak memory 204420 kb
Host smart-a89e51f1-3d78-4e0a-bab1-0d465e98e4d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243678242 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.1243678242
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3646762721
Short name T257
Test name
Test status
Simulation time 64975158 ps
CPU time 1.23 seconds
Started Feb 19 01:28:19 PM PST 24
Finished Feb 19 01:28:21 PM PST 24
Peak memory 204504 kb
Host smart-1baef755-deff-4c5d-bb49-ec128519a4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646762721 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3646762721
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.424144787
Short name T241
Test name
Test status
Simulation time 42878989 ps
CPU time 0.95 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:14 PM PST 24
Peak memory 204236 kb
Host smart-d7b24800-7cdb-4b5c-8175-3a21857bf962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424144787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.424144787
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.1190985131
Short name T71
Test name
Test status
Simulation time 37962749 ps
CPU time 1.52 seconds
Started Feb 19 01:28:15 PM PST 24
Finished Feb 19 01:28:17 PM PST 24
Peak memory 204392 kb
Host smart-ef0a0cc4-3380-4505-8da8-63d648a5fd91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190985131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.1190985131
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.4240912775
Short name T235
Test name
Test status
Simulation time 274642544 ps
CPU time 4.85 seconds
Started Feb 19 01:28:10 PM PST 24
Finished Feb 19 01:28:16 PM PST 24
Peak memory 212984 kb
Host smart-9ad12996-d223-4740-b483-e3106204145c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240912775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.4240912775
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2484587755
Short name T245
Test name
Test status
Simulation time 47416063 ps
CPU time 1.68 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:23 PM PST 24
Peak memory 220216 kb
Host smart-2e7636cc-7a41-45c8-9bf9-559adfa28621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484587755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
484587755
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.843822988
Short name T67
Test name
Test status
Simulation time 239908811 ps
CPU time 3.22 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:17 PM PST 24
Peak memory 204276 kb
Host smart-bdc548e2-91bd-4c66-9e12-b45fea8bbff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843822988 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_
tl_intg_err.843822988
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.2873710176
Short name T73
Test name
Test status
Simulation time 224763583 ps
CPU time 4.46 seconds
Started Feb 19 01:28:12 PM PST 24
Finished Feb 19 01:28:17 PM PST 24
Peak memory 204368 kb
Host smart-379b94bf-ba72-4cc8-af6a-e8d93387af85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873710176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.2873710176
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.301927058
Short name T296
Test name
Test status
Simulation time 739523802 ps
CPU time 6.16 seconds
Started Feb 19 01:28:12 PM PST 24
Finished Feb 19 01:28:19 PM PST 24
Peak memory 204412 kb
Host smart-6dd601eb-7552-4807-9ec7-0e45c9cf3b5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301927058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.301927058
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1201982443
Short name T164
Test name
Test status
Simulation time 40970626 ps
CPU time 1.43 seconds
Started Feb 19 01:28:10 PM PST 24
Finished Feb 19 01:28:12 PM PST 24
Peak memory 204444 kb
Host smart-162d0ad8-422c-4ced-9a9f-851e3779188a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201982443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1201982443
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.2369607502
Short name T250
Test name
Test status
Simulation time 17539655 ps
CPU time 0.96 seconds
Started Feb 19 01:28:10 PM PST 24
Finished Feb 19 01:28:11 PM PST 24
Peak memory 204356 kb
Host smart-62674234-6e8a-4f08-b1dd-ec18479154c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369607502 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.2369607502
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3454364612
Short name T302
Test name
Test status
Simulation time 14030134 ps
CPU time 0.97 seconds
Started Feb 19 01:28:10 PM PST 24
Finished Feb 19 01:28:12 PM PST 24
Peak memory 204424 kb
Host smart-20f731fb-ff67-4899-bcda-34df4dce821f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454364612 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.3
454364612
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.555092606
Short name T204
Test name
Test status
Simulation time 9348085 ps
CPU time 0.72 seconds
Started Feb 19 01:28:10 PM PST 24
Finished Feb 19 01:28:11 PM PST 24
Peak memory 204144 kb
Host smart-092ff730-f805-4b4f-9938-0be777112e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555092606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.555092606
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.3836827387
Short name T256
Test name
Test status
Simulation time 334617351 ps
CPU time 2.28 seconds
Started Feb 19 01:28:08 PM PST 24
Finished Feb 19 01:28:11 PM PST 24
Peak memory 204612 kb
Host smart-30441bb3-4f19-4826-8a3c-5d9d9cfa77ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836827387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.3836827387
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.1525267539
Short name T189
Test name
Test status
Simulation time 326305077 ps
CPU time 2.98 seconds
Started Feb 19 01:28:09 PM PST 24
Finished Feb 19 01:28:13 PM PST 24
Peak memory 212984 kb
Host smart-b9d1bd24-be1d-412c-890b-837d26d0a299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525267539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.1525267539
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.610360454
Short name T59
Test name
Test status
Simulation time 1032069663 ps
CPU time 8.35 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:22 PM PST 24
Peak memory 218060 kb
Host smart-cb3ee304-41c2-4bfe-b89c-280186d7aa30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610360454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.610360454
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.80761220
Short name T286
Test name
Test status
Simulation time 80562304 ps
CPU time 3.08 seconds
Started Feb 19 01:28:08 PM PST 24
Finished Feb 19 01:28:11 PM PST 24
Peak memory 215044 kb
Host smart-94d554a4-99ee-488a-a212-55dbf92c32d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80761220 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.80761220
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.856980284
Short name T278
Test name
Test status
Simulation time 68883930 ps
CPU time 1.07 seconds
Started Feb 19 01:28:54 PM PST 24
Finished Feb 19 01:28:56 PM PST 24
Peak memory 204340 kb
Host smart-d999a5b4-971a-4553-ae58-775a84b58113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856980284 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.856980284
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1667377776
Short name T284
Test name
Test status
Simulation time 240243062 ps
CPU time 2.02 seconds
Started Feb 19 01:28:56 PM PST 24
Finished Feb 19 01:29:01 PM PST 24
Peak memory 204496 kb
Host smart-c605042d-c3b2-4fec-bf59-2571d6019610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667377776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1667377776
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.3622317286
Short name T60
Test name
Test status
Simulation time 66300765 ps
CPU time 2.14 seconds
Started Feb 19 01:28:52 PM PST 24
Finished Feb 19 01:28:55 PM PST 24
Peak memory 212992 kb
Host smart-0691c0ec-2ec9-4f3d-8378-8df399d6e862
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622317286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.3622317286
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1335414317
Short name T277
Test name
Test status
Simulation time 137300710 ps
CPU time 5 seconds
Started Feb 19 01:29:03 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 212936 kb
Host smart-81ace841-a98f-47e2-beb2-3eeecd9f9710
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335414317 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1335414317
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.3378532113
Short name T25
Test name
Test status
Simulation time 90395677 ps
CPU time 2.39 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 212668 kb
Host smart-37b17d8d-995f-4062-9392-86d7034b6bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378532113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
3378532113
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2631159475
Short name T293
Test name
Test status
Simulation time 26261274 ps
CPU time 1.94 seconds
Started Feb 19 01:28:47 PM PST 24
Finished Feb 19 01:28:50 PM PST 24
Peak memory 212676 kb
Host smart-e5727b6a-bfb2-4f17-8da4-243fdcbe24d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631159475 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2631159475
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1457188594
Short name T181
Test name
Test status
Simulation time 13111250 ps
CPU time 1.07 seconds
Started Feb 19 01:28:57 PM PST 24
Finished Feb 19 01:29:00 PM PST 24
Peak memory 204444 kb
Host smart-bcf73643-6c8b-42ba-af42-30927c224d68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457188594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1457188594
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1262346973
Short name T190
Test name
Test status
Simulation time 124903107 ps
CPU time 0.87 seconds
Started Feb 19 01:28:47 PM PST 24
Finished Feb 19 01:28:48 PM PST 24
Peak memory 204268 kb
Host smart-d5d27dcc-2b31-40f9-b538-db3c77f39f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262346973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1262346973
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1481953354
Short name T168
Test name
Test status
Simulation time 272718696 ps
CPU time 3.12 seconds
Started Feb 19 01:28:51 PM PST 24
Finished Feb 19 01:28:55 PM PST 24
Peak memory 204424 kb
Host smart-daeb9162-6216-4e2f-a61d-c961f8672b4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481953354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1481953354
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.2708768372
Short name T304
Test name
Test status
Simulation time 132256370 ps
CPU time 2.25 seconds
Started Feb 19 01:28:47 PM PST 24
Finished Feb 19 01:28:51 PM PST 24
Peak memory 213108 kb
Host smart-77a6a7f4-52f6-4f05-a7e8-2a348f52204d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708768372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.2708768372
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.719366247
Short name T63
Test name
Test status
Simulation time 367759811 ps
CPU time 4.33 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:05 PM PST 24
Peak memory 213280 kb
Host smart-85b1d9ad-ecb8-4d2c-9827-f55b62fd4b7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719366247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.719366247
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.812941547
Short name T38
Test name
Test status
Simulation time 392517525 ps
CPU time 4.16 seconds
Started Feb 19 01:28:48 PM PST 24
Finished Feb 19 01:28:53 PM PST 24
Peak memory 215684 kb
Host smart-57c804f4-735d-461a-ab91-df9ba0b2b7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812941547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.812941547
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3494778125
Short name T55
Test name
Test status
Simulation time 118129382 ps
CPU time 4.32 seconds
Started Feb 19 01:28:56 PM PST 24
Finished Feb 19 01:29:02 PM PST 24
Peak memory 213120 kb
Host smart-d7abbd16-0d92-46e9-accd-ed0b5e4f2b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494778125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3494778125
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.4151415748
Short name T36
Test name
Test status
Simulation time 109035898 ps
CPU time 1.94 seconds
Started Feb 19 01:29:00 PM PST 24
Finished Feb 19 01:29:04 PM PST 24
Peak memory 212688 kb
Host smart-5029132c-d480-4f28-b1b1-44feeff8627e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151415748 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.4151415748
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.3967047269
Short name T275
Test name
Test status
Simulation time 23027829 ps
CPU time 0.86 seconds
Started Feb 19 01:28:52 PM PST 24
Finished Feb 19 01:28:54 PM PST 24
Peak memory 204212 kb
Host smart-5a6732d8-6245-4e79-8a1e-1dc140f805cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967047269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
3967047269
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.711808094
Short name T161
Test name
Test status
Simulation time 11925164 ps
CPU time 0.85 seconds
Started Feb 19 01:28:47 PM PST 24
Finished Feb 19 01:28:49 PM PST 24
Peak memory 204212 kb
Host smart-00c355d6-961a-4459-8e21-c7abd8c08ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711808094 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.711808094
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1388602626
Short name T228
Test name
Test status
Simulation time 40680997 ps
CPU time 1.31 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:02 PM PST 24
Peak memory 204472 kb
Host smart-57eb322e-1006-4bb9-99e5-00cbf950cfa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388602626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1388602626
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.2702407370
Short name T188
Test name
Test status
Simulation time 122200308 ps
CPU time 3.91 seconds
Started Feb 19 01:28:59 PM PST 24
Finished Feb 19 01:29:05 PM PST 24
Peak memory 213012 kb
Host smart-8771f15b-4f1c-4306-9201-fed6c56b931d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702407370 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.2702407370
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.182300002
Short name T236
Test name
Test status
Simulation time 873695668 ps
CPU time 5.19 seconds
Started Feb 19 01:28:55 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 213004 kb
Host smart-f7bd2bd6-ab2b-4218-a041-2780150c1383
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182300002 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.182300002
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3472156248
Short name T248
Test name
Test status
Simulation time 105162016 ps
CPU time 4.09 seconds
Started Feb 19 01:28:56 PM PST 24
Finished Feb 19 01:29:02 PM PST 24
Peak memory 212636 kb
Host smart-a157e6a9-f698-4c0c-b75e-abd84d4613d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472156248 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3472156248
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.1356292473
Short name T102
Test name
Test status
Simulation time 56015843 ps
CPU time 0.99 seconds
Started Feb 19 01:29:01 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 204296 kb
Host smart-df492e74-a7cd-4f08-a2fb-b5cf05807feb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356292473 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.1356292473
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.249668825
Short name T258
Test name
Test status
Simulation time 32533131 ps
CPU time 1.08 seconds
Started Feb 19 01:28:59 PM PST 24
Finished Feb 19 01:29:02 PM PST 24
Peak memory 204408 kb
Host smart-f246e204-24e5-4a67-a74b-eb1971b50afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249668825 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.249668825
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1779023852
Short name T287
Test name
Test status
Simulation time 50245285 ps
CPU time 0.74 seconds
Started Feb 19 01:29:00 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 204272 kb
Host smart-a670cddf-dd42-4e26-a50e-30a9323dca0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779023852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1779023852
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.30356711
Short name T300
Test name
Test status
Simulation time 206938155 ps
CPU time 1.67 seconds
Started Feb 19 01:28:59 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 204356 kb
Host smart-8a66ba7d-2324-4a22-aabd-fd165d79ba19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ke
ymgr_dpe_same_csr_outstanding.30356711
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1637356511
Short name T262
Test name
Test status
Simulation time 106674466 ps
CPU time 2.28 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:02 PM PST 24
Peak memory 213008 kb
Host smart-58e2e85a-2136-4ca0-ab41-0159abfa7358
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637356511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1637356511
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2115952337
Short name T308
Test name
Test status
Simulation time 224721354 ps
CPU time 3.18 seconds
Started Feb 19 01:29:00 PM PST 24
Finished Feb 19 01:29:05 PM PST 24
Peak memory 217592 kb
Host smart-4f4e0e04-9276-4ffd-9e36-0e0d1b2f62fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115952337 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2115952337
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2809612637
Short name T49
Test name
Test status
Simulation time 467819277 ps
CPU time 3.81 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:05 PM PST 24
Peak memory 212528 kb
Host smart-ae3f4d36-25dd-4ae3-9aac-f88b7885073f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809612637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2809612637
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1524616974
Short name T58
Test name
Test status
Simulation time 56245549 ps
CPU time 1.95 seconds
Started Feb 19 01:29:12 PM PST 24
Finished Feb 19 01:29:17 PM PST 24
Peak memory 212612 kb
Host smart-41929d9e-7664-46d6-854a-d7201dff959d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524616974 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1524616974
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.4237292680
Short name T306
Test name
Test status
Simulation time 72259753 ps
CPU time 0.95 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 204308 kb
Host smart-78992bb2-f3f4-4d8a-8989-862e17ada636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237292680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
4237292680
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3963787109
Short name T192
Test name
Test status
Simulation time 43157265 ps
CPU time 0.82 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204296 kb
Host smart-fb7489de-a715-4db4-8bb8-a60a25279b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963787109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3963787109
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.3216881599
Short name T28
Test name
Test status
Simulation time 52845547 ps
CPU time 1.61 seconds
Started Feb 19 01:29:12 PM PST 24
Finished Feb 19 01:29:17 PM PST 24
Peak memory 204456 kb
Host smart-d796735c-0c0f-4521-b1d6-3286ea7d61cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216881599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.3216881599
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.529651970
Short name T291
Test name
Test status
Simulation time 63160187 ps
CPU time 2.25 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 212984 kb
Host smart-b49ab124-59e3-41a8-b9d9-4ec805c39281
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529651970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keym
gr_dpe_shadow_reg_errors.529651970
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1167259338
Short name T299
Test name
Test status
Simulation time 277573623 ps
CPU time 5.88 seconds
Started Feb 19 01:28:59 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 212944 kb
Host smart-5f2be76d-7ad3-4bff-985c-62b14e37217d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167259338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1167259338
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.85544170
Short name T297
Test name
Test status
Simulation time 82274702 ps
CPU time 2.92 seconds
Started Feb 19 01:28:58 PM PST 24
Finished Feb 19 01:29:04 PM PST 24
Peak memory 212720 kb
Host smart-957971e5-5808-41e0-be8f-25779ab84646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85544170 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.85544170
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2976782843
Short name T247
Test name
Test status
Simulation time 47266230 ps
CPU time 1.14 seconds
Started Feb 19 01:28:59 PM PST 24
Finished Feb 19 01:29:03 PM PST 24
Peak memory 212596 kb
Host smart-0dd0255f-cd7a-49e6-ba9a-e184a3b0c4f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976782843 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2976782843
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2340615909
Short name T206
Test name
Test status
Simulation time 30771946 ps
CPU time 1.09 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:09 PM PST 24
Peak memory 204356 kb
Host smart-64c1bc7a-f36b-4f24-a15f-2aa3d5be52ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340615909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2340615909
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2761243738
Short name T238
Test name
Test status
Simulation time 27938634 ps
CPU time 0.95 seconds
Started Feb 19 01:29:02 PM PST 24
Finished Feb 19 01:29:05 PM PST 24
Peak memory 204344 kb
Host smart-f7f78caa-5c9e-4721-b0a7-8ebd6aa0e55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761243738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2761243738
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3374358426
Short name T203
Test name
Test status
Simulation time 75902732 ps
CPU time 1.57 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 204428 kb
Host smart-1ddbfd77-c70b-4007-84d6-5705daaacaa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374358426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3374358426
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.106679023
Short name T266
Test name
Test status
Simulation time 257197111 ps
CPU time 5.47 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 213000 kb
Host smart-4c07b75d-ffe0-434f-a6b2-168ea28fcd5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106679023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.106679023
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.19874675
Short name T239
Test name
Test status
Simulation time 118477018 ps
CPU time 3.19 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:12 PM PST 24
Peak memory 213000 kb
Host smart-6cfeb23b-1fcf-469a-bcbc-56e3ec3a6270
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19874675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.19874675
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1135506671
Short name T37
Test name
Test status
Simulation time 35522237 ps
CPU time 2.58 seconds
Started Feb 19 01:29:04 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 214816 kb
Host smart-88c7bca1-225f-4053-a09c-56bd0097c873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135506671 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1135506671
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.3747156638
Short name T47
Test name
Test status
Simulation time 53101384 ps
CPU time 2.77 seconds
Started Feb 19 01:29:04 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204428 kb
Host smart-cd115e39-838c-4dc7-926e-b386c534f4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747156638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.3747156638
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.2160214116
Short name T246
Test name
Test status
Simulation time 318777702 ps
CPU time 1.61 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 212712 kb
Host smart-894f2975-3903-4244-b7b0-4a6b13f14dc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160214116 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.2160214116
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.3409148826
Short name T200
Test name
Test status
Simulation time 24123344 ps
CPU time 1.05 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204340 kb
Host smart-a06271b8-6eab-4bd1-ab21-9b8b7c9d7a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409148826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
3409148826
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3499138118
Short name T218
Test name
Test status
Simulation time 16935843 ps
CPU time 0.7 seconds
Started Feb 19 01:29:02 PM PST 24
Finished Feb 19 01:29:04 PM PST 24
Peak memory 204264 kb
Host smart-41b73b17-8ff1-439b-88f1-83e4043f918f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499138118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
3499138118
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.12699943
Short name T222
Test name
Test status
Simulation time 45868560 ps
CPU time 1.46 seconds
Started Feb 19 01:29:05 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204396 kb
Host smart-99d97499-84b5-4f2f-bf79-3aea248b66ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699943 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ke
ymgr_dpe_same_csr_outstanding.12699943
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1489056247
Short name T61
Test name
Test status
Simulation time 195305916 ps
CPU time 2.6 seconds
Started Feb 19 01:29:02 PM PST 24
Finished Feb 19 01:29:06 PM PST 24
Peak memory 212972 kb
Host smart-897a4c67-7545-4de4-8c9d-bee0de38a108
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489056247 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1489056247
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1471660869
Short name T211
Test name
Test status
Simulation time 58022037 ps
CPU time 3.33 seconds
Started Feb 19 01:29:05 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 212976 kb
Host smart-d2aec8d6-20a0-413d-b0dc-0ae7bfcc9350
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471660869 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1471660869
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2350688775
Short name T212
Test name
Test status
Simulation time 97784137 ps
CPU time 2.33 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 220820 kb
Host smart-9d8585d6-a502-4b7d-a3cd-60d97b035259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350688775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2350688775
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3772287242
Short name T289
Test name
Test status
Simulation time 244318548 ps
CPU time 6.32 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:16 PM PST 24
Peak memory 213828 kb
Host smart-e8b853ba-68bd-4c5f-a2ab-e63c54ce3fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772287242 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3772287242
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2578060181
Short name T196
Test name
Test status
Simulation time 55052924 ps
CPU time 1.2 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:12 PM PST 24
Peak memory 212692 kb
Host smart-7f12ee21-8694-4d5a-9682-9c29b42757bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578060181 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2578060181
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1031121855
Short name T172
Test name
Test status
Simulation time 13839646 ps
CPU time 0.98 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204432 kb
Host smart-87f83b7a-eb0d-415f-b25c-3e6bcd08ad3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031121855 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1031121855
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3152966713
Short name T82
Test name
Test status
Simulation time 16001693 ps
CPU time 0.77 seconds
Started Feb 19 01:29:04 PM PST 24
Finished Feb 19 01:29:06 PM PST 24
Peak memory 204276 kb
Host smart-301ac62c-bc0b-4921-a546-a4de3ede6a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152966713 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3152966713
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1071841116
Short name T197
Test name
Test status
Simulation time 104281299 ps
CPU time 1.76 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:09 PM PST 24
Peak memory 204432 kb
Host smart-8219519f-5592-4500-98ee-bc1265176f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071841116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.1071841116
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2734578468
Short name T62
Test name
Test status
Simulation time 66611326 ps
CPU time 2.36 seconds
Started Feb 19 01:29:05 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 213016 kb
Host smart-de8c9d8c-553a-4ad9-ac89-1664512456e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734578468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.2734578468
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.102857760
Short name T210
Test name
Test status
Simulation time 195499907 ps
CPU time 4.03 seconds
Started Feb 19 01:29:05 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 221176 kb
Host smart-c7b0af39-0c4c-416c-82fe-220475d00ddd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102857760 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.102857760
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.3669482543
Short name T237
Test name
Test status
Simulation time 661098550 ps
CPU time 5.79 seconds
Started Feb 19 01:29:03 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 212664 kb
Host smart-5b3c3d86-a586-43cd-b2f6-5a60f9b8dccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669482543 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
3669482543
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1023142597
Short name T56
Test name
Test status
Simulation time 178645007 ps
CPU time 2.65 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 213016 kb
Host smart-e470a635-0441-41c0-b0f5-6beb9e277307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023142597 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1023142597
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2381760225
Short name T65
Test name
Test status
Simulation time 95356223 ps
CPU time 1.39 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204472 kb
Host smart-917b9d1e-1849-42c2-b717-fcdc8c79b9b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381760225 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2381760225
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1338038785
Short name T303
Test name
Test status
Simulation time 269823633 ps
CPU time 1.12 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:09 PM PST 24
Peak memory 204312 kb
Host smart-4394d72c-c3b9-4e7a-932d-27f7a767212e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338038785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
1338038785
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.3994533053
Short name T174
Test name
Test status
Simulation time 10265621 ps
CPU time 0.71 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 204300 kb
Host smart-dc744609-dfc8-49c8-bcc3-d52d3a1ccf02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994533053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
3994533053
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.6790456
Short name T274
Test name
Test status
Simulation time 149133117 ps
CPU time 2.09 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:12 PM PST 24
Peak memory 204460 kb
Host smart-5eece478-6fd1-4bbe-8c7e-6a1f7fbe9f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6790456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_same_csr_outstanding.6790456
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.2995886844
Short name T193
Test name
Test status
Simulation time 95084031 ps
CPU time 3.33 seconds
Started Feb 19 01:29:12 PM PST 24
Finished Feb 19 01:29:19 PM PST 24
Peak memory 212952 kb
Host smart-c609254a-8c04-49df-a98d-7f5c11542832
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995886844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.2995886844
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3871458691
Short name T84
Test name
Test status
Simulation time 989736654 ps
CPU time 5.76 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 212984 kb
Host smart-776bda56-a9c7-4355-9214-d46206359eb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871458691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.3871458691
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1125673546
Short name T229
Test name
Test status
Simulation time 397542834 ps
CPU time 2.93 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:10 PM PST 24
Peak memory 212696 kb
Host smart-adcb033b-f51d-46e8-9255-ee171d62c3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125673546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1125673546
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3899891052
Short name T252
Test name
Test status
Simulation time 190779090 ps
CPU time 4.69 seconds
Started Feb 19 01:29:06 PM PST 24
Finished Feb 19 01:29:12 PM PST 24
Peak memory 212604 kb
Host smart-c6d5a317-95a5-4dfa-a971-2c2b81a2d721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899891052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3899891052
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.346097910
Short name T178
Test name
Test status
Simulation time 21240384 ps
CPU time 1.38 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:16 PM PST 24
Peak memory 212648 kb
Host smart-4ed09c5c-3386-44a5-affe-8c292e1fbfe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346097910 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.346097910
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.206267327
Short name T305
Test name
Test status
Simulation time 41622327 ps
CPU time 0.96 seconds
Started Feb 19 01:29:10 PM PST 24
Finished Feb 19 01:29:14 PM PST 24
Peak memory 204280 kb
Host smart-b9412914-bef0-44b0-a544-2c2412f27a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206267327 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.206267327
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3522542794
Short name T268
Test name
Test status
Simulation time 25189480 ps
CPU time 0.82 seconds
Started Feb 19 01:29:10 PM PST 24
Finished Feb 19 01:29:14 PM PST 24
Peak memory 204228 kb
Host smart-29f4f063-9987-4b39-b12a-c8c4d6010565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522542794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
3522542794
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.3423934108
Short name T195
Test name
Test status
Simulation time 260747011 ps
CPU time 3.47 seconds
Started Feb 19 01:29:09 PM PST 24
Finished Feb 19 01:29:16 PM PST 24
Peak memory 212656 kb
Host smart-9f794eb4-e121-4448-8725-3420f364e568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423934108 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.3423934108
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.401296243
Short name T243
Test name
Test status
Simulation time 191182123 ps
CPU time 1.66 seconds
Started Feb 19 01:29:05 PM PST 24
Finished Feb 19 01:29:08 PM PST 24
Peak memory 204800 kb
Host smart-73fd9b44-74b5-4d89-b039-0fef5385214b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401296243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keym
gr_dpe_shadow_reg_errors.401296243
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1916923571
Short name T167
Test name
Test status
Simulation time 368218974 ps
CPU time 3.86 seconds
Started Feb 19 01:29:07 PM PST 24
Finished Feb 19 01:29:12 PM PST 24
Peak memory 213044 kb
Host smart-29bca293-eeff-4bb7-bedb-62c57a47b3a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916923571 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1916923571
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.1348978820
Short name T45
Test name
Test status
Simulation time 259783459 ps
CPU time 1.53 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 212720 kb
Host smart-d7afe55b-0599-4173-a87e-d11c39aa9919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348978820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
1348978820
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.704368219
Short name T20
Test name
Test status
Simulation time 307203406 ps
CPU time 5.42 seconds
Started Feb 19 01:29:10 PM PST 24
Finished Feb 19 01:29:18 PM PST 24
Peak memory 213628 kb
Host smart-f6c6824e-9b84-40d7-b742-4c48066ecb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704368219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.704368219
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.2371797309
Short name T214
Test name
Test status
Simulation time 47786985 ps
CPU time 2.83 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:17 PM PST 24
Peak memory 204092 kb
Host smart-e619995c-deb4-418d-ab8f-8868b08ea87b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371797309 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.2371797309
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.332841903
Short name T205
Test name
Test status
Simulation time 986599295 ps
CPU time 11.29 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:26 PM PST 24
Peak memory 204432 kb
Host smart-c15e1934-4a4b-4240-89f7-d94b5ac60c79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332841903 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.332841903
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.1915269236
Short name T83
Test name
Test status
Simulation time 88039338 ps
CPU time 0.92 seconds
Started Feb 19 01:28:07 PM PST 24
Finished Feb 19 01:28:09 PM PST 24
Peak memory 204308 kb
Host smart-142937e1-2d50-4744-bb35-156f27643114
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915269236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.1915269236
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2096600222
Short name T288
Test name
Test status
Simulation time 32836962 ps
CPU time 1.52 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:15 PM PST 24
Peak memory 212624 kb
Host smart-f0fa02c0-cab6-4ce7-9f03-c935406e9963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096600222 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2096600222
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2643645915
Short name T260
Test name
Test status
Simulation time 17367034 ps
CPU time 0.9 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:22 PM PST 24
Peak memory 204280 kb
Host smart-fecc7aec-f846-4c14-bb8c-98331e14fca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643645915 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
643645915
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1277725598
Short name T165
Test name
Test status
Simulation time 27241933 ps
CPU time 0.7 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:22 PM PST 24
Peak memory 204240 kb
Host smart-b0794bd1-b469-43b5-92e1-fd0ba61311c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277725598 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.1
277725598
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2255914890
Short name T280
Test name
Test status
Simulation time 666635700 ps
CPU time 2.07 seconds
Started Feb 19 01:28:08 PM PST 24
Finished Feb 19 01:28:10 PM PST 24
Peak memory 204408 kb
Host smart-360b7511-2577-442c-bde5-27d72cdb277f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255914890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.2255914890
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.2958014084
Short name T226
Test name
Test status
Simulation time 142986100 ps
CPU time 2.07 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:16 PM PST 24
Peak memory 212664 kb
Host smart-b07b63f9-d1d7-47d6-a038-878993111fbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958014084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.2958014084
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3396302594
Short name T74
Test name
Test status
Simulation time 140356159 ps
CPU time 5.17 seconds
Started Feb 19 01:28:14 PM PST 24
Finished Feb 19 01:28:20 PM PST 24
Peak memory 212932 kb
Host smart-b0b4d2e8-1cce-4f0c-9c78-b23f6c170dbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396302594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3396302594
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.2541342386
Short name T27
Test name
Test status
Simulation time 201328609 ps
CPU time 2.62 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 220820 kb
Host smart-711fe64a-38b8-4062-9b0e-147968b17669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541342386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.2
541342386
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2872468128
Short name T166
Test name
Test status
Simulation time 17674986 ps
CPU time 0.81 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204208 kb
Host smart-8b68610d-f125-49ea-935f-23c0bac3ad69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872468128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2872468128
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.3940175109
Short name T186
Test name
Test status
Simulation time 10482377 ps
CPU time 0.7 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204248 kb
Host smart-e31b9dba-84c8-460e-81c0-3df5c3d3883f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940175109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
3940175109
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.1325461969
Short name T219
Test name
Test status
Simulation time 12640839 ps
CPU time 0.94 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204264 kb
Host smart-af02b5cc-abd0-48c4-a73a-697a51c81be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325461969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
1325461969
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.330613961
Short name T208
Test name
Test status
Simulation time 19388394 ps
CPU time 0.74 seconds
Started Feb 19 01:29:08 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204188 kb
Host smart-e58ad665-0b74-4eca-8c6d-f920b346b752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330613961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.330613961
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3771321556
Short name T176
Test name
Test status
Simulation time 27769563 ps
CPU time 0.7 seconds
Started Feb 19 01:29:10 PM PST 24
Finished Feb 19 01:29:14 PM PST 24
Peak memory 204240 kb
Host smart-8d90faf7-51eb-43e3-9554-3c4fced1f2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771321556 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3771321556
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.4219017991
Short name T221
Test name
Test status
Simulation time 12968189 ps
CPU time 0.7 seconds
Started Feb 19 01:29:09 PM PST 24
Finished Feb 19 01:29:11 PM PST 24
Peak memory 204200 kb
Host smart-9430d455-ca45-4747-87a0-804b5315cd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219017991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
4219017991
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3719223717
Short name T101
Test name
Test status
Simulation time 10185699 ps
CPU time 0.85 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 204240 kb
Host smart-93217b9e-50ea-405a-8814-3c578fd10ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719223717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3719223717
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1170154333
Short name T99
Test name
Test status
Simulation time 12905230 ps
CPU time 0.74 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 204192 kb
Host smart-36bfb63f-8d90-4460-a32e-0952aed5ce45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170154333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1170154333
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3011693754
Short name T283
Test name
Test status
Simulation time 43540511 ps
CPU time 0.74 seconds
Started Feb 19 01:29:14 PM PST 24
Finished Feb 19 01:29:18 PM PST 24
Peak memory 204248 kb
Host smart-90cb3cff-b846-4f1d-9dcf-5256f1342240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011693754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
3011693754
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.799544375
Short name T216
Test name
Test status
Simulation time 45497057 ps
CPU time 0.86 seconds
Started Feb 19 01:29:15 PM PST 24
Finished Feb 19 01:29:18 PM PST 24
Peak memory 204272 kb
Host smart-264143bd-e823-4e7c-86d7-cd9096033b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799544375 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.799544375
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.590300997
Short name T202
Test name
Test status
Simulation time 324813914 ps
CPU time 4.89 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:35 PM PST 24
Peak memory 204436 kb
Host smart-441d82dd-9f44-4616-bb05-54bad9c3715f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590300997 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_aliasing.590300997
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1793808390
Short name T215
Test name
Test status
Simulation time 1856617007 ps
CPU time 11.75 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 204216 kb
Host smart-5331d9e1-49e9-4ba0-ad4a-468ebc381845
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793808390 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1793808390
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.1565118199
Short name T232
Test name
Test status
Simulation time 29271141 ps
CPU time 1.04 seconds
Started Feb 19 01:28:18 PM PST 24
Finished Feb 19 01:28:19 PM PST 24
Peak memory 204332 kb
Host smart-4a56cbb9-083b-43e4-a75c-889e3044e347
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565118199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.1565118199
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4214506904
Short name T282
Test name
Test status
Simulation time 70552698 ps
CPU time 1.63 seconds
Started Feb 19 01:28:26 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 212748 kb
Host smart-aede6e8a-ccde-4753-9605-d64e1ac856c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214506904 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.4214506904
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1910881039
Short name T171
Test name
Test status
Simulation time 20520982 ps
CPU time 0.85 seconds
Started Feb 19 01:28:21 PM PST 24
Finished Feb 19 01:28:22 PM PST 24
Peak memory 204228 kb
Host smart-61b64b3d-718d-4138-b2fc-a460e7bac2bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910881039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
910881039
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.1132774289
Short name T273
Test name
Test status
Simulation time 10613591 ps
CPU time 0.7 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:15 PM PST 24
Peak memory 204268 kb
Host smart-fe4b1788-5da1-4721-87b8-f2f05ff6abd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132774289 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.1
132774289
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2858686136
Short name T267
Test name
Test status
Simulation time 71903312 ps
CPU time 2.16 seconds
Started Feb 19 01:28:15 PM PST 24
Finished Feb 19 01:28:18 PM PST 24
Peak memory 204412 kb
Host smart-044c5f3c-141c-4981-9b24-36c55691ec85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858686136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2858686136
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.1814024614
Short name T276
Test name
Test status
Simulation time 51214370 ps
CPU time 1.37 seconds
Started Feb 19 01:28:13 PM PST 24
Finished Feb 19 01:28:15 PM PST 24
Peak memory 212848 kb
Host smart-1fd0cfa8-f6df-4b9c-b005-81b985e44b2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814024614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.1814024614
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3677808285
Short name T184
Test name
Test status
Simulation time 229752038 ps
CPU time 5.53 seconds
Started Feb 19 01:28:14 PM PST 24
Finished Feb 19 01:28:20 PM PST 24
Peak memory 212932 kb
Host smart-c2ceceee-7e00-4262-8fc1-9963fbaf5f44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677808285 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3677808285
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.3559873195
Short name T298
Test name
Test status
Simulation time 241196621 ps
CPU time 2.79 seconds
Started Feb 19 01:28:20 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 212600 kb
Host smart-e78aea2b-0d57-47fc-8abe-575625d05976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559873195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.3
559873195
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.545112454
Short name T66
Test name
Test status
Simulation time 61482755 ps
CPU time 0.86 seconds
Started Feb 19 01:29:13 PM PST 24
Finished Feb 19 01:29:17 PM PST 24
Peak memory 204228 kb
Host smart-6376660f-24b5-4387-b877-bf33f7d288c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545112454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.545112454
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.3262727305
Short name T173
Test name
Test status
Simulation time 19700702 ps
CPU time 0.75 seconds
Started Feb 19 01:29:12 PM PST 24
Finished Feb 19 01:29:16 PM PST 24
Peak memory 204148 kb
Host smart-cc896abb-e08c-4384-8ab0-66b09b6b2888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262727305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
3262727305
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.542572423
Short name T201
Test name
Test status
Simulation time 19427839 ps
CPU time 0.74 seconds
Started Feb 19 01:29:11 PM PST 24
Finished Feb 19 01:29:15 PM PST 24
Peak memory 204276 kb
Host smart-165ef33d-6b74-4a84-9407-e6ad8cb606bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542572423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.542572423
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.798232565
Short name T295
Test name
Test status
Simulation time 11312129 ps
CPU time 0.73 seconds
Started Feb 19 01:29:14 PM PST 24
Finished Feb 19 01:29:18 PM PST 24
Peak memory 204248 kb
Host smart-734b6a86-dc75-44cb-8810-47a3d16df647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798232565 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.798232565
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3849971996
Short name T100
Test name
Test status
Simulation time 23287238 ps
CPU time 0.89 seconds
Started Feb 19 01:29:20 PM PST 24
Finished Feb 19 01:29:21 PM PST 24
Peak memory 204208 kb
Host smart-4c5cafd4-c527-4e21-b44a-beabb5f7a66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849971996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
3849971996
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.1155809294
Short name T223
Test name
Test status
Simulation time 44528464 ps
CPU time 0.86 seconds
Started Feb 19 01:29:16 PM PST 24
Finished Feb 19 01:29:19 PM PST 24
Peak memory 204188 kb
Host smart-aba72c38-00b9-4bad-b72e-223cfecdcc6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155809294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
1155809294
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.2864780269
Short name T249
Test name
Test status
Simulation time 11452163 ps
CPU time 0.83 seconds
Started Feb 19 01:29:21 PM PST 24
Finished Feb 19 01:29:23 PM PST 24
Peak memory 204224 kb
Host smart-37d4b09f-1c8b-436d-8c4a-cb0d791b8af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864780269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
2864780269
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3313165912
Short name T177
Test name
Test status
Simulation time 11935371 ps
CPU time 0.81 seconds
Started Feb 19 01:29:18 PM PST 24
Finished Feb 19 01:29:20 PM PST 24
Peak memory 204260 kb
Host smart-31176eec-97f7-4592-ae5a-c73a276db8cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313165912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3313165912
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.4281928184
Short name T183
Test name
Test status
Simulation time 12095670 ps
CPU time 0.74 seconds
Started Feb 19 01:29:18 PM PST 24
Finished Feb 19 01:29:20 PM PST 24
Peak memory 204232 kb
Host smart-a7ac2111-0bc9-4902-8594-00a560b46556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281928184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
4281928184
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3923336037
Short name T309
Test name
Test status
Simulation time 11525682 ps
CPU time 0.75 seconds
Started Feb 19 01:29:18 PM PST 24
Finished Feb 19 01:29:19 PM PST 24
Peak memory 204192 kb
Host smart-8423cd19-5546-45e7-a1a9-5f261a04b4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923336037 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3923336037
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2912504392
Short name T261
Test name
Test status
Simulation time 1246184836 ps
CPU time 4.35 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 204432 kb
Host smart-6295baad-e076-474d-8f7d-bc9b4663d32d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912504392 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2912504392
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.2615778643
Short name T294
Test name
Test status
Simulation time 397754500 ps
CPU time 5.48 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 204496 kb
Host smart-1398d993-565a-4dab-80d4-655cd4985a14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615778643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.2615778643
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3279703182
Short name T158
Test name
Test status
Simulation time 47003522 ps
CPU time 1.09 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:32 PM PST 24
Peak memory 204420 kb
Host smart-a4492b5a-d78e-4024-81b3-1cb1086b6b57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279703182 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3279703182
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.102868213
Short name T301
Test name
Test status
Simulation time 58608922 ps
CPU time 1.55 seconds
Started Feb 19 01:28:21 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 212684 kb
Host smart-50da2595-98ab-40c6-82c5-68028a3fb861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102868213 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.102868213
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1749223420
Short name T290
Test name
Test status
Simulation time 41045820 ps
CPU time 1.03 seconds
Started Feb 19 01:28:26 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 204200 kb
Host smart-37ea55aa-22f1-4c93-90e1-27bdbf75c787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749223420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
749223420
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1639394751
Short name T231
Test name
Test status
Simulation time 8712737 ps
CPU time 0.77 seconds
Started Feb 19 01:28:25 PM PST 24
Finished Feb 19 01:28:27 PM PST 24
Peak memory 204308 kb
Host smart-55927de9-73f7-4b28-9286-e1bcd759ab17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639394751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
639394751
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.4254453516
Short name T213
Test name
Test status
Simulation time 277662864 ps
CPU time 2.24 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 204380 kb
Host smart-30ccf58d-5910-44ed-9ab5-530d6596e6b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254453516 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.4254453516
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.859355711
Short name T191
Test name
Test status
Simulation time 65740423 ps
CPU time 1.61 seconds
Started Feb 19 01:28:26 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 212952 kb
Host smart-c644033f-3b59-42bb-84a5-377a0714a4b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859355711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.859355711
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.2545639815
Short name T251
Test name
Test status
Simulation time 153831559 ps
CPU time 5.22 seconds
Started Feb 19 01:28:18 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 212712 kb
Host smart-51bed452-68f8-4bdf-a1a6-c0ade32ef66f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545639815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.2
545639815
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3241242860
Short name T269
Test name
Test status
Simulation time 51318722 ps
CPU time 2.65 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:27 PM PST 24
Peak memory 212692 kb
Host smart-0a9e3a97-9310-49b0-baf4-117ed89c6b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241242860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.3241242860
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2966423765
Short name T242
Test name
Test status
Simulation time 13389552 ps
CPU time 0.83 seconds
Started Feb 19 01:29:18 PM PST 24
Finished Feb 19 01:29:20 PM PST 24
Peak memory 204276 kb
Host smart-675f2a34-2ff9-42e8-b356-58595df76b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966423765 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
2966423765
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.93806776
Short name T270
Test name
Test status
Simulation time 11917349 ps
CPU time 0.88 seconds
Started Feb 19 01:29:15 PM PST 24
Finished Feb 19 01:29:19 PM PST 24
Peak memory 204232 kb
Host smart-ba710173-32ae-4860-8260-8015106149d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93806776 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.93806776
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.3147193868
Short name T160
Test name
Test status
Simulation time 11032025 ps
CPU time 0.77 seconds
Started Feb 19 01:29:18 PM PST 24
Finished Feb 19 01:29:20 PM PST 24
Peak memory 204272 kb
Host smart-8434961b-e5c7-4806-8a1e-74b7d481e7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147193868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
3147193868
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2238933551
Short name T259
Test name
Test status
Simulation time 22847038 ps
CPU time 0.75 seconds
Started Feb 19 01:29:21 PM PST 24
Finished Feb 19 01:29:23 PM PST 24
Peak memory 204268 kb
Host smart-d0ae635b-2721-4cbc-ba87-3f56186b816c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238933551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2238933551
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1700381507
Short name T285
Test name
Test status
Simulation time 40437076 ps
CPU time 0.89 seconds
Started Feb 19 01:29:24 PM PST 24
Finished Feb 19 01:29:26 PM PST 24
Peak memory 204268 kb
Host smart-2c71918a-dba2-4229-8188-71b59b0cc6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700381507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1700381507
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1313837298
Short name T170
Test name
Test status
Simulation time 32819040 ps
CPU time 0.81 seconds
Started Feb 19 01:29:23 PM PST 24
Finished Feb 19 01:29:26 PM PST 24
Peak memory 204240 kb
Host smart-87b91e0c-2e28-4f76-9b2c-21ed364523b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313837298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1313837298
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.1723693301
Short name T209
Test name
Test status
Simulation time 31899948 ps
CPU time 0.71 seconds
Started Feb 19 01:29:25 PM PST 24
Finished Feb 19 01:29:27 PM PST 24
Peak memory 204236 kb
Host smart-eb8f5b7e-19f1-4ffb-8514-edd78a1d396c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723693301 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
1723693301
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.548078805
Short name T217
Test name
Test status
Simulation time 11010368 ps
CPU time 0.83 seconds
Started Feb 19 01:29:26 PM PST 24
Finished Feb 19 01:29:29 PM PST 24
Peak memory 204204 kb
Host smart-52df59ec-d6e8-4fb1-b082-e0eb7a3238db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548078805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.548078805
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3791576682
Short name T199
Test name
Test status
Simulation time 10744532 ps
CPU time 0.83 seconds
Started Feb 19 01:29:21 PM PST 24
Finished Feb 19 01:29:24 PM PST 24
Peak memory 204536 kb
Host smart-9cb4f7d1-068f-40a7-af9e-f09eee8d1c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791576682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
3791576682
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3626034986
Short name T162
Test name
Test status
Simulation time 10756618 ps
CPU time 0.85 seconds
Started Feb 19 01:29:22 PM PST 24
Finished Feb 19 01:29:24 PM PST 24
Peak memory 204308 kb
Host smart-e0674045-fb8f-4835-9761-47c6b6bf840c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626034986 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3626034986
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2853883749
Short name T194
Test name
Test status
Simulation time 13064301 ps
CPU time 1.15 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:26 PM PST 24
Peak memory 204492 kb
Host smart-6e1e0dd0-4db1-4132-8149-04316d989c4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853883749 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2853883749
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1657441933
Short name T272
Test name
Test status
Simulation time 29480945 ps
CPU time 1.42 seconds
Started Feb 19 01:28:25 PM PST 24
Finished Feb 19 01:28:27 PM PST 24
Peak memory 204484 kb
Host smart-30474285-684f-4123-bb11-009c13a59706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657441933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.1
657441933
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.235584229
Short name T264
Test name
Test status
Simulation time 35899319 ps
CPU time 0.74 seconds
Started Feb 19 01:28:19 PM PST 24
Finished Feb 19 01:28:20 PM PST 24
Peak memory 204264 kb
Host smart-19eb0c35-7591-4663-b29e-8c514c41c65d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235584229 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.235584229
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.4041521132
Short name T271
Test name
Test status
Simulation time 22277278 ps
CPU time 1.22 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:32 PM PST 24
Peak memory 204436 kb
Host smart-b37450ce-94e0-46a9-83c8-2266ce4b9515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041521132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.4041521132
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3248156717
Short name T253
Test name
Test status
Simulation time 312113036 ps
CPU time 2.63 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:27 PM PST 24
Peak memory 213080 kb
Host smart-b57c109d-9994-42c6-baa6-41579f8f6bb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248156717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3248156717
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.340441853
Short name T233
Test name
Test status
Simulation time 538306978 ps
CPU time 5.36 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 217964 kb
Host smart-bffcb6b7-c21f-4924-96db-693ddfc1fc78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340441853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.340441853
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.1727690193
Short name T43
Test name
Test status
Simulation time 433908223 ps
CPU time 5.05 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 213780 kb
Host smart-c633c708-d76d-483f-bfbf-a9093a74095c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727690193 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.1727690193
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.4255576353
Short name T220
Test name
Test status
Simulation time 137372571 ps
CPU time 1.39 seconds
Started Feb 19 01:28:40 PM PST 24
Finished Feb 19 01:28:42 PM PST 24
Peak memory 204436 kb
Host smart-1839994b-f0f9-402d-9ad7-1754adedcb25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255576353 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.4255576353
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2341144594
Short name T159
Test name
Test status
Simulation time 12448614 ps
CPU time 1.03 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:32 PM PST 24
Peak memory 204388 kb
Host smart-ebdfab50-727e-460d-9409-bc83c4299c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341144594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
341144594
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.3317094690
Short name T307
Test name
Test status
Simulation time 11598734 ps
CPU time 0.77 seconds
Started Feb 19 01:28:22 PM PST 24
Finished Feb 19 01:28:24 PM PST 24
Peak memory 204244 kb
Host smart-99d99b27-ce11-409b-8065-533d97b9e4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317094690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.3
317094690
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1794420829
Short name T179
Test name
Test status
Simulation time 21569773 ps
CPU time 1.5 seconds
Started Feb 19 01:28:26 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 204372 kb
Host smart-2733eaa8-5c53-41cb-94a7-f1d6c65e16a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794420829 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1794420829
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.2225308973
Short name T227
Test name
Test status
Simulation time 519600810 ps
CPU time 1.74 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 213008 kb
Host smart-3f138d81-ffd6-4e4f-9c8c-4456279bb64c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225308973 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.2225308973
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3628933212
Short name T187
Test name
Test status
Simulation time 478325423 ps
CPU time 4.26 seconds
Started Feb 19 01:28:23 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 212976 kb
Host smart-2de21881-b0e8-4ead-8838-42e776333433
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628933212 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3628933212
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.4273501249
Short name T230
Test name
Test status
Simulation time 435113852 ps
CPU time 3.25 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:28 PM PST 24
Peak memory 212616 kb
Host smart-ff31893a-790c-487d-aa60-1839919cd5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273501249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.4
273501249
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.204995699
Short name T53
Test name
Test status
Simulation time 94819347 ps
CPU time 3.89 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 212632 kb
Host smart-fc67995e-9b85-443e-b5c6-ad863d06fa33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204995699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_
tl_intg_err.204995699
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1855588098
Short name T279
Test name
Test status
Simulation time 117531714 ps
CPU time 2.01 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 212720 kb
Host smart-357abeb3-1848-4192-bc2f-f40b55d5edcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855588098 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1855588098
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2206026013
Short name T292
Test name
Test status
Simulation time 15748836 ps
CPU time 0.85 seconds
Started Feb 19 01:28:31 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 204284 kb
Host smart-af433641-5f30-4f22-9823-2365ee508ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206026013 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
206026013
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1196526587
Short name T244
Test name
Test status
Simulation time 30039233 ps
CPU time 0.71 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:31 PM PST 24
Peak memory 204276 kb
Host smart-6299f582-5ee6-489f-9641-5c36d9678e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196526587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.1
196526587
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.558649242
Short name T72
Test name
Test status
Simulation time 54254587 ps
CPU time 1.49 seconds
Started Feb 19 01:28:35 PM PST 24
Finished Feb 19 01:28:37 PM PST 24
Peak memory 204456 kb
Host smart-09b5513e-bf69-435f-bd34-ff1703060752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558649242 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_dpe_same_csr_outstanding.558649242
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.4061584399
Short name T180
Test name
Test status
Simulation time 137583669 ps
CPU time 1.2 seconds
Started Feb 19 01:28:27 PM PST 24
Finished Feb 19 01:28:29 PM PST 24
Peak memory 212620 kb
Host smart-d21a0142-9edf-45ea-8ad9-b07b6617f274
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061584399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.4061584399
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.4088136393
Short name T224
Test name
Test status
Simulation time 282508085 ps
CPU time 9.64 seconds
Started Feb 19 01:28:24 PM PST 24
Finished Feb 19 01:28:35 PM PST 24
Peak memory 213004 kb
Host smart-0476aaf8-cf5f-4dac-b50d-c6f295fb1455
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088136393 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.4088136393
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2926089552
Short name T225
Test name
Test status
Simulation time 558247768 ps
CPU time 3.3 seconds
Started Feb 19 01:28:30 PM PST 24
Finished Feb 19 01:28:34 PM PST 24
Peak memory 214928 kb
Host smart-1e8fa650-be76-4ae2-a710-ae054077fdec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926089552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
926089552
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.682167500
Short name T54
Test name
Test status
Simulation time 190133887 ps
CPU time 4.13 seconds
Started Feb 19 01:28:27 PM PST 24
Finished Feb 19 01:28:32 PM PST 24
Peak memory 212484 kb
Host smart-21e9bb72-844e-4466-a229-f6d141238ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682167500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_
tl_intg_err.682167500
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2946637036
Short name T281
Test name
Test status
Simulation time 33510378 ps
CPU time 0.91 seconds
Started Feb 19 01:28:44 PM PST 24
Finished Feb 19 01:28:46 PM PST 24
Peak memory 204324 kb
Host smart-07132a5d-5abb-4245-9c3d-4a36adcf3b85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946637036 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2946637036
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1164610904
Short name T207
Test name
Test status
Simulation time 31903578 ps
CPU time 0.91 seconds
Started Feb 19 01:28:45 PM PST 24
Finished Feb 19 01:28:46 PM PST 24
Peak memory 204276 kb
Host smart-3a51c68b-8580-46f5-a75e-1eab741420a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164610904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
164610904
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2844827254
Short name T41
Test name
Test status
Simulation time 15591695 ps
CPU time 0.75 seconds
Started Feb 19 01:28:44 PM PST 24
Finished Feb 19 01:28:46 PM PST 24
Peak memory 204252 kb
Host smart-50ad7df1-4a71-4dd6-80c7-d98b9f87d174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844827254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2
844827254
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1502728680
Short name T234
Test name
Test status
Simulation time 28958902 ps
CPU time 2.04 seconds
Started Feb 19 01:28:50 PM PST 24
Finished Feb 19 01:28:54 PM PST 24
Peak memory 204432 kb
Host smart-aba1bf0f-30ba-4e99-8a93-eea6d53f3927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502728680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.1502728680
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.3094688551
Short name T182
Test name
Test status
Simulation time 59699334 ps
CPU time 1.58 seconds
Started Feb 19 01:28:31 PM PST 24
Finished Feb 19 01:28:33 PM PST 24
Peak memory 212940 kb
Host smart-afbbd8e3-9660-4064-8e09-6b44db5a67b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094688551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.3094688551
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4053945763
Short name T175
Test name
Test status
Simulation time 400184376 ps
CPU time 2.49 seconds
Started Feb 19 01:28:38 PM PST 24
Finished Feb 19 01:28:41 PM PST 24
Peak memory 212976 kb
Host smart-093f545c-10cc-4d17-9dee-cba8399f63b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053945763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4053945763
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.961412804
Short name T263
Test name
Test status
Simulation time 50370800 ps
CPU time 3.76 seconds
Started Feb 19 01:28:32 PM PST 24
Finished Feb 19 01:28:36 PM PST 24
Peak memory 212668 kb
Host smart-31803798-01f1-498d-b990-677a2a2bf9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961412804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.961412804
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.1152271455
Short name T103
Test name
Test status
Simulation time 40045089 ps
CPU time 1.31 seconds
Started Feb 19 01:28:50 PM PST 24
Finished Feb 19 01:28:53 PM PST 24
Peak memory 212720 kb
Host smart-23d964c5-08c0-45ee-8983-27ee17aa3206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152271455 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.1152271455
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.185615439
Short name T185
Test name
Test status
Simulation time 13880418 ps
CPU time 0.96 seconds
Started Feb 19 01:28:42 PM PST 24
Finished Feb 19 01:28:44 PM PST 24
Peak memory 204404 kb
Host smart-bba77cae-61f9-4c0a-a131-b2d2f41f74ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185615439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.185615439
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.3007567758
Short name T198
Test name
Test status
Simulation time 95206092 ps
CPU time 0.84 seconds
Started Feb 19 01:28:45 PM PST 24
Finished Feb 19 01:28:47 PM PST 24
Peak memory 204248 kb
Host smart-ba2a47d4-d77c-4e85-b70f-2a5035cfffb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007567758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.3
007567758
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.881149529
Short name T240
Test name
Test status
Simulation time 32770559 ps
CPU time 1.32 seconds
Started Feb 19 01:28:49 PM PST 24
Finished Feb 19 01:28:51 PM PST 24
Peak memory 204408 kb
Host smart-dd4615dc-6a1c-411d-9c49-8daf1e64ad3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881149529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_dpe_same_csr_outstanding.881149529
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3105675240
Short name T255
Test name
Test status
Simulation time 232330355 ps
CPU time 2.21 seconds
Started Feb 19 01:28:51 PM PST 24
Finished Feb 19 01:28:54 PM PST 24
Peak memory 212940 kb
Host smart-6d63613b-b0cd-416b-b2d4-ce734cfef8c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105675240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.3105675240
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1344317473
Short name T64
Test name
Test status
Simulation time 137745162 ps
CPU time 4.47 seconds
Started Feb 19 01:28:49 PM PST 24
Finished Feb 19 01:28:54 PM PST 24
Peak memory 213076 kb
Host smart-54edb182-d84e-43b6-a689-9cbc1aadd4e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344317473 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1344317473
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3084655074
Short name T48
Test name
Test status
Simulation time 26844143 ps
CPU time 2.12 seconds
Started Feb 19 01:28:44 PM PST 24
Finished Feb 19 01:28:46 PM PST 24
Peak memory 212724 kb
Host smart-01c93d21-6636-476a-999e-c67ea0f7c632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084655074 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
084655074
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.2808514393
Short name T52
Test name
Test status
Simulation time 156175719 ps
CPU time 2.94 seconds
Started Feb 19 01:28:51 PM PST 24
Finished Feb 19 01:28:55 PM PST 24
Peak memory 213056 kb
Host smart-94896155-c420-4070-b034-68448680e0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808514393 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.2808514393
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.1490003767
Short name T113
Test name
Test status
Simulation time 12324191 ps
CPU time 0.9 seconds
Started Feb 19 01:04:44 PM PST 24
Finished Feb 19 01:04:47 PM PST 24
Peak memory 205272 kb
Host smart-3367c978-5ee7-4e32-ab17-ec51bcfe479e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490003767 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.1
490003767
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.353974602
Short name T16
Test name
Test status
Simulation time 158603064 ps
CPU time 0.88 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:04:59 PM PST 24
Peak memory 205240 kb
Host smart-a30c16a0-f97e-4b8d-bade-ebb5ed8f5426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353974602 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.353974602
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2172951122
Short name T120
Test name
Test status
Simulation time 12389363 ps
CPU time 0.75 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205336 kb
Host smart-8aa5a74b-552b-42eb-a7d1-29b2950412eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172951122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2172951122
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.1826616667
Short name T150
Test name
Test status
Simulation time 6231281358 ps
CPU time 21.76 seconds
Started Feb 19 01:05:01 PM PST 24
Finished Feb 19 01:05:24 PM PST 24
Peak memory 208152 kb
Host smart-0663e2e5-09e2-4ad7-a613-8d9e2f8f2cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826616667 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1826616667
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1502728219
Short name T111
Test name
Test status
Simulation time 32594413 ps
CPU time 0.76 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205296 kb
Host smart-5f05cd28-2536-4255-a7a1-6cfacc15feba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502728219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1502728219
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.2202822325
Short name T144
Test name
Test status
Simulation time 38335664 ps
CPU time 0.79 seconds
Started Feb 19 01:04:55 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205244 kb
Host smart-6c53e657-aa8c-489b-92a5-6f6c2c185bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202822325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
2202822325
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.795612555
Short name T146
Test name
Test status
Simulation time 4038726712 ps
CPU time 34.52 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:05:32 PM PST 24
Peak memory 207716 kb
Host smart-30e0df13-a2f2-4af7-a430-874547aac530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795612555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.795612555
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.1847922290
Short name T112
Test name
Test status
Simulation time 66188750 ps
CPU time 0.78 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205304 kb
Host smart-8098a49b-3e63-4e4b-a3f4-e0bbc5e1d791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847922290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
1847922290
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.1204862403
Short name T11
Test name
Test status
Simulation time 10614889127 ps
CPU time 182.43 seconds
Started Feb 19 01:05:02 PM PST 24
Finished Feb 19 01:08:06 PM PST 24
Peak memory 215776 kb
Host smart-8a323b0d-2fe1-45e3-b3d3-8f6dae09bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204862403 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.1204862403
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.3744185203
Short name T15
Test name
Test status
Simulation time 60123198 ps
CPU time 0.94 seconds
Started Feb 19 01:04:54 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205512 kb
Host smart-e7a53670-d49b-4c54-83f6-09b841707d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744185203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
3744185203
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.4250970573
Short name T12
Test name
Test status
Simulation time 6370226909 ps
CPU time 105.64 seconds
Started Feb 19 01:05:08 PM PST 24
Finished Feb 19 01:06:55 PM PST 24
Peak memory 207164 kb
Host smart-cca739fc-474a-4121-b0ff-4961dedd9a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250970573 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.4250970573
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1687752726
Short name T127
Test name
Test status
Simulation time 16987796 ps
CPU time 0.74 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205344 kb
Host smart-dcbffe71-eb34-428b-be45-3283e50100b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687752726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1687752726
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2342706967
Short name T3
Test name
Test status
Simulation time 51810191 ps
CPU time 0.77 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205224 kb
Host smart-9eb95268-7754-4963-bbcf-ddae958bac1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342706967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2342706967
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.2479382826
Short name T33
Test name
Test status
Simulation time 7599973 ps
CPU time 0.76 seconds
Started Feb 19 01:05:08 PM PST 24
Finished Feb 19 01:05:10 PM PST 24
Peak memory 205240 kb
Host smart-45317c61-ac04-4963-9d36-66d567908e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479382826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
2479382826
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.3787673783
Short name T151
Test name
Test status
Simulation time 742835479 ps
CPU time 23.46 seconds
Started Feb 19 01:04:55 PM PST 24
Finished Feb 19 01:05:21 PM PST 24
Peak memory 206076 kb
Host smart-30145bea-e38d-42fc-80ce-04f7dbc09d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787673783 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.3787673783
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.339156185
Short name T110
Test name
Test status
Simulation time 13848093 ps
CPU time 0.77 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205364 kb
Host smart-eae51fb9-96d2-4d53-a49b-557413714ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339156185 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.339156185
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.3623243826
Short name T148
Test name
Test status
Simulation time 9416507 ps
CPU time 0.72 seconds
Started Feb 19 01:04:44 PM PST 24
Finished Feb 19 01:04:47 PM PST 24
Peak memory 205316 kb
Host smart-fbdf542c-f66d-491b-a538-c550cc3102a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623243826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.3
623243826
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.157066024
Short name T22
Test name
Test status
Simulation time 2177660802 ps
CPU time 19.91 seconds
Started Feb 19 01:04:43 PM PST 24
Finished Feb 19 01:05:05 PM PST 24
Peak memory 232976 kb
Host smart-dfb15daa-98d0-40a7-bf4c-d7c7f42e0493
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157066024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.157066024
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.1670041582
Short name T138
Test name
Test status
Simulation time 767096352 ps
CPU time 18.39 seconds
Started Feb 19 01:04:42 PM PST 24
Finished Feb 19 01:05:03 PM PST 24
Peak memory 207636 kb
Host smart-bc40f9cc-8238-4e18-9260-03f395001078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670041582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.1670041582
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.1885775365
Short name T117
Test name
Test status
Simulation time 29353801 ps
CPU time 0.88 seconds
Started Feb 19 01:04:54 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205420 kb
Host smart-a314d293-0c20-406e-afa0-ebf51554fe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885775365 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
1885775365
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.578656383
Short name T133
Test name
Test status
Simulation time 69631832 ps
CPU time 0.73 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205228 kb
Host smart-92adfc3d-3c37-4e12-ba29-e7ff02cce39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578656383 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.578656383
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3693701038
Short name T106
Test name
Test status
Simulation time 37926735 ps
CPU time 0.66 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205304 kb
Host smart-8c890fe9-5e97-4c1d-a3fc-c6fcfd992d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693701038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3693701038
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.115179589
Short name T93
Test name
Test status
Simulation time 1007758382 ps
CPU time 19.66 seconds
Started Feb 19 01:04:55 PM PST 24
Finished Feb 19 01:05:17 PM PST 24
Peak memory 207724 kb
Host smart-fe341dd5-6ee9-48da-9d57-1d290e85657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115179589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.115179589
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3262983056
Short name T107
Test name
Test status
Simulation time 37785852 ps
CPU time 0.86 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205372 kb
Host smart-9db0f53d-f98b-4843-903d-a152a99006e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262983056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3262983056
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.745303112
Short name T152
Test name
Test status
Simulation time 2147211807 ps
CPU time 20.49 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:22 PM PST 24
Peak memory 208108 kb
Host smart-2dab092e-b007-45ea-b00f-ed95596e296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745303112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.745303112
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.2144399924
Short name T105
Test name
Test status
Simulation time 9206249 ps
CPU time 0.8 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205316 kb
Host smart-2497f741-80be-4442-9038-d8c70a4dc963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144399924 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
2144399924
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.2886901179
Short name T108
Test name
Test status
Simulation time 54104809 ps
CPU time 0.9 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:04:59 PM PST 24
Peak memory 205360 kb
Host smart-f22add9e-d5d5-4cd1-86b8-037ae2d63ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886901179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
2886901179
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.738958894
Short name T13
Test name
Test status
Simulation time 3110927884 ps
CPU time 72.21 seconds
Started Feb 19 01:04:56 PM PST 24
Finished Feb 19 01:06:09 PM PST 24
Peak memory 207592 kb
Host smart-b333c0f3-6a6a-449d-ba68-e0c59f4bb300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738958894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.738958894
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.450206557
Short name T121
Test name
Test status
Simulation time 21402845 ps
CPU time 0.84 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:04:59 PM PST 24
Peak memory 205316 kb
Host smart-00c74fed-a4e1-4ac3-9fa7-69ea845331e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450206557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.450206557
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2282916820
Short name T8
Test name
Test status
Simulation time 10008327998 ps
CPU time 209.08 seconds
Started Feb 19 01:05:07 PM PST 24
Finished Feb 19 01:08:38 PM PST 24
Peak memory 207564 kb
Host smart-a12d5ce6-1f80-4cd9-b86a-084a17244f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282916820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2282916820
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1263339041
Short name T142
Test name
Test status
Simulation time 67162852 ps
CPU time 1.03 seconds
Started Feb 19 01:04:55 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205484 kb
Host smart-fd22fd9f-55c3-470f-ac6a-4f71bed13757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263339041 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1263339041
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.1369266938
Short name T116
Test name
Test status
Simulation time 8786593 ps
CPU time 0.8 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205344 kb
Host smart-c95e82f7-3c08-4c51-8783-46090d022f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369266938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
1369266938
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.3517527228
Short name T154
Test name
Test status
Simulation time 581926161 ps
CPU time 9.08 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:10 PM PST 24
Peak memory 206040 kb
Host smart-6671e773-225d-4283-b84c-117149700f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517527228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.3517527228
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.1519226780
Short name T134
Test name
Test status
Simulation time 15006524 ps
CPU time 0.94 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205424 kb
Host smart-d6e6f7ec-9ae6-4b46-b4d4-32989d1050c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519226780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
1519226780
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.3941892781
Short name T34
Test name
Test status
Simulation time 40659735 ps
CPU time 0.78 seconds
Started Feb 19 01:04:43 PM PST 24
Finished Feb 19 01:04:46 PM PST 24
Peak memory 205324 kb
Host smart-936f914e-ab81-4655-ac02-823a060224b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941892781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.3
941892781
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.1827020061
Short name T23
Test name
Test status
Simulation time 723235468 ps
CPU time 20.99 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:05:08 PM PST 24
Peak memory 232292 kb
Host smart-71d6412b-ef19-4e74-9af1-648f36134d76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827020061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.1827020061
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.4198837854
Short name T139
Test name
Test status
Simulation time 24275043 ps
CPU time 0.72 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205268 kb
Host smart-492f04b2-2c20-40ff-9d39-102fe107ed48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198837854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
4198837854
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.74023859
Short name T35
Test name
Test status
Simulation time 869686359 ps
CPU time 18.84 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:05:16 PM PST 24
Peak memory 207840 kb
Host smart-3d27e85d-f2fc-4022-9c8e-2b5f68b8cfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74023859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.74023859
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3015702699
Short name T114
Test name
Test status
Simulation time 43616296 ps
CPU time 0.77 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205356 kb
Host smart-13dc1fc9-e93c-4a00-b70d-4e0679724a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015702699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3015702699
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.604097020
Short name T98
Test name
Test status
Simulation time 543836388 ps
CPU time 18.1 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:17 PM PST 24
Peak memory 208052 kb
Host smart-7a08f3f2-4afb-4d30-83e0-e788101ab3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604097020 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.604097020
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3612513282
Short name T130
Test name
Test status
Simulation time 14823410 ps
CPU time 0.96 seconds
Started Feb 19 01:05:03 PM PST 24
Finished Feb 19 01:05:05 PM PST 24
Peak memory 205508 kb
Host smart-11ae3827-f82e-486d-9a3a-59b425425577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612513282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3612513282
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1206057561
Short name T157
Test name
Test status
Simulation time 1017894221 ps
CPU time 19.03 seconds
Started Feb 19 01:05:09 PM PST 24
Finished Feb 19 01:05:29 PM PST 24
Peak memory 207016 kb
Host smart-674d2ba6-a405-4cc8-9c03-d95e9e710b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206057561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1206057561
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3294994946
Short name T32
Test name
Test status
Simulation time 14050423 ps
CPU time 0.94 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205248 kb
Host smart-1bf103e5-b352-41b5-96f9-c6984718407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294994946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3294994946
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.383536798
Short name T125
Test name
Test status
Simulation time 8102392174 ps
CPU time 45.07 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:46 PM PST 24
Peak memory 207944 kb
Host smart-3b459a2e-6b77-4067-a227-faea175fc168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383536798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.383536798
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.193959923
Short name T156
Test name
Test status
Simulation time 18057240 ps
CPU time 0.86 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205308 kb
Host smart-50af4c9c-475e-4129-bac7-4902d5162418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193959923 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.193959923
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3616222480
Short name T7
Test name
Test status
Simulation time 5223309991 ps
CPU time 27.79 seconds
Started Feb 19 01:04:53 PM PST 24
Finished Feb 19 01:05:24 PM PST 24
Peak memory 207412 kb
Host smart-c5c364b5-6c1d-43fe-ae1b-45f3a7f7fb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616222480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3616222480
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.283469691
Short name T145
Test name
Test status
Simulation time 7512802 ps
CPU time 0.71 seconds
Started Feb 19 01:04:58 PM PST 24
Finished Feb 19 01:05:00 PM PST 24
Peak memory 205344 kb
Host smart-7008c953-fefc-4e0d-b640-e2f921ecbe51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283469691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.283469691
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.1686411895
Short name T78
Test name
Test status
Simulation time 262613485 ps
CPU time 13.97 seconds
Started Feb 19 01:05:07 PM PST 24
Finished Feb 19 01:05:23 PM PST 24
Peak memory 206672 kb
Host smart-5e8f8140-4079-42ef-90c4-d2a0a1f3845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686411895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.1686411895
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.403440594
Short name T128
Test name
Test status
Simulation time 56620554 ps
CPU time 0.96 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205484 kb
Host smart-b0e8efd2-a838-4e90-81b3-a522d80ddf03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403440594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.403440594
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.635628765
Short name T80
Test name
Test status
Simulation time 1677952806 ps
CPU time 15.02 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:15 PM PST 24
Peak memory 206652 kb
Host smart-fc0c0906-a828-4409-9525-ae3f7a176f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635628765 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.635628765
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.976912702
Short name T122
Test name
Test status
Simulation time 35528417 ps
CPU time 1.03 seconds
Started Feb 19 01:05:01 PM PST 24
Finished Feb 19 01:05:03 PM PST 24
Peak memory 205344 kb
Host smart-1258ba8d-5be0-42c1-a4e8-c8be6a03dfb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976912702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.976912702
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.1274514041
Short name T149
Test name
Test status
Simulation time 1964209459 ps
CPU time 18.13 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:19 PM PST 24
Peak memory 207672 kb
Host smart-fa08e01c-7964-4540-9c6a-bb13a2b940e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274514041 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1274514041
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1660589582
Short name T140
Test name
Test status
Simulation time 12719171 ps
CPU time 0.99 seconds
Started Feb 19 01:05:01 PM PST 24
Finished Feb 19 01:05:03 PM PST 24
Peak memory 205512 kb
Host smart-58bb2941-073d-45b0-af4b-50432227038b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660589582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1660589582
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.421499277
Short name T86
Test name
Test status
Simulation time 1525916085 ps
CPU time 29.45 seconds
Started Feb 19 01:05:01 PM PST 24
Finished Feb 19 01:05:32 PM PST 24
Peak memory 208028 kb
Host smart-56132864-0cee-405e-94be-50ca0d3f5575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421499277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.421499277
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.28825721
Short name T124
Test name
Test status
Simulation time 20086923 ps
CPU time 0.73 seconds
Started Feb 19 01:05:12 PM PST 24
Finished Feb 19 01:05:14 PM PST 24
Peak memory 205348 kb
Host smart-c7dc6514-1a17-4255-91da-9112ec0af16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.28825721
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.4011820662
Short name T131
Test name
Test status
Simulation time 311048386 ps
CPU time 10.45 seconds
Started Feb 19 01:05:05 PM PST 24
Finished Feb 19 01:05:16 PM PST 24
Peak memory 208200 kb
Host smart-431b2949-e80d-4b18-96fd-49f90aa289d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011820662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.4011820662
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2148467402
Short name T153
Test name
Test status
Simulation time 40465761 ps
CPU time 0.84 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:04:48 PM PST 24
Peak memory 205320 kb
Host smart-2e4e6d6d-c686-4487-806e-69f3734237b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148467402 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
148467402
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3558690995
Short name T6
Test name
Test status
Simulation time 2327640400 ps
CPU time 18.62 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:05:06 PM PST 24
Peak memory 233280 kb
Host smart-316bf1f4-8815-4afc-bc02-99d0932f3134
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558690995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3558690995
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3293103674
Short name T132
Test name
Test status
Simulation time 921695716 ps
CPU time 21.34 seconds
Started Feb 19 01:04:50 PM PST 24
Finished Feb 19 01:05:11 PM PST 24
Peak memory 207936 kb
Host smart-2145d8eb-7cd3-493c-b9c5-4ccd27035b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293103674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3293103674
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.4005736325
Short name T135
Test name
Test status
Simulation time 32090079 ps
CPU time 0.69 seconds
Started Feb 19 01:05:06 PM PST 24
Finished Feb 19 01:05:08 PM PST 24
Peak memory 205372 kb
Host smart-d0d9d67a-ccc9-4294-ae32-586df3f0c24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005736325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
4005736325
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3900331745
Short name T119
Test name
Test status
Simulation time 10800863 ps
CPU time 0.73 seconds
Started Feb 19 01:04:57 PM PST 24
Finished Feb 19 01:04:58 PM PST 24
Peak memory 205304 kb
Host smart-097a3ffa-8a67-40bd-bc42-eacf9f28133c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900331745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3900331745
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.3416652836
Short name T17
Test name
Test status
Simulation time 13390034 ps
CPU time 0.83 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:02 PM PST 24
Peak memory 205320 kb
Host smart-d1a7c528-b17c-496d-83b6-40afadc73cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416652836 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
3416652836
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3323420046
Short name T141
Test name
Test status
Simulation time 1589354148 ps
CPU time 31.11 seconds
Started Feb 19 01:05:06 PM PST 24
Finished Feb 19 01:05:37 PM PST 24
Peak memory 207752 kb
Host smart-61b02255-3d6c-46c4-a25d-a36e4bbf73ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323420046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3323420046
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.927794958
Short name T31
Test name
Test status
Simulation time 17293458 ps
CPU time 0.87 seconds
Started Feb 19 01:05:04 PM PST 24
Finished Feb 19 01:05:06 PM PST 24
Peak memory 205340 kb
Host smart-f70ddc70-528b-4ce1-bbc0-5788942084e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927794958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.927794958
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.3988026103
Short name T143
Test name
Test status
Simulation time 3970522499 ps
CPU time 28.06 seconds
Started Feb 19 01:04:59 PM PST 24
Finished Feb 19 01:05:29 PM PST 24
Peak memory 208056 kb
Host smart-03ccf471-cd28-4ee4-8cf7-08cf4a127e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988026103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.3988026103
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.652967180
Short name T104
Test name
Test status
Simulation time 40154262 ps
CPU time 0.79 seconds
Started Feb 19 01:05:10 PM PST 24
Finished Feb 19 01:05:11 PM PST 24
Peak memory 205536 kb
Host smart-794b99b9-cb08-43fe-a01b-236902faff98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652967180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.652967180
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.256747134
Short name T75
Test name
Test status
Simulation time 8552391250 ps
CPU time 20.7 seconds
Started Feb 19 01:05:03 PM PST 24
Finished Feb 19 01:05:24 PM PST 24
Peak memory 207932 kb
Host smart-f7b6eba2-c738-48d3-b241-dbf34b589c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256747134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.256747134
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3461500680
Short name T118
Test name
Test status
Simulation time 9141514 ps
CPU time 0.74 seconds
Started Feb 19 01:05:10 PM PST 24
Finished Feb 19 01:05:11 PM PST 24
Peak memory 205536 kb
Host smart-a9ba8708-9312-4120-b9cd-a437aedbd9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461500680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3461500680
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.750436269
Short name T97
Test name
Test status
Simulation time 1143574808 ps
CPU time 21.51 seconds
Started Feb 19 01:05:00 PM PST 24
Finished Feb 19 01:05:22 PM PST 24
Peak memory 206208 kb
Host smart-5053b54c-0af0-4d6d-9743-063f2df51889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750436269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.750436269
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.17409039
Short name T147
Test name
Test status
Simulation time 38697063 ps
CPU time 0.85 seconds
Started Feb 19 01:05:14 PM PST 24
Finished Feb 19 01:05:16 PM PST 24
Peak memory 205316 kb
Host smart-8fa15356-f9f2-47f9-80f1-c8f5d531f983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17409039 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.17409039
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.452693151
Short name T136
Test name
Test status
Simulation time 12783860 ps
CPU time 0.79 seconds
Started Feb 19 01:05:16 PM PST 24
Finished Feb 19 01:05:18 PM PST 24
Peak memory 205312 kb
Host smart-30a97394-c641-4128-a5e4-835de5a655bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452693151 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.452693151
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2834467354
Short name T115
Test name
Test status
Simulation time 14757434 ps
CPU time 0.73 seconds
Started Feb 19 01:05:05 PM PST 24
Finished Feb 19 01:05:07 PM PST 24
Peak memory 205372 kb
Host smart-da69c0be-2a8d-4d44-8eee-3a9326c5989b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834467354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2834467354
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.1171619944
Short name T109
Test name
Test status
Simulation time 2787665347 ps
CPU time 27.13 seconds
Started Feb 19 01:05:01 PM PST 24
Finished Feb 19 01:05:30 PM PST 24
Peak memory 207720 kb
Host smart-82c85d65-fd94-4a84-a95a-d3e726899fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171619944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.1171619944
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.468260838
Short name T129
Test name
Test status
Simulation time 15274654 ps
CPU time 0.97 seconds
Started Feb 19 01:05:05 PM PST 24
Finished Feb 19 01:05:07 PM PST 24
Peak memory 205484 kb
Host smart-ab273809-db48-4d7a-af57-442b690a9eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468260838 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.468260838
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.3321736047
Short name T79
Test name
Test status
Simulation time 4622834418 ps
CPU time 38.83 seconds
Started Feb 19 01:05:14 PM PST 24
Finished Feb 19 01:05:53 PM PST 24
Peak memory 208180 kb
Host smart-a416e3d2-b604-4623-a60a-42afa8734acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321736047 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.3321736047
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.1212971865
Short name T137
Test name
Test status
Simulation time 14775943 ps
CPU time 0.77 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:04:48 PM PST 24
Peak memory 205320 kb
Host smart-9f618e4c-7aa9-4c6f-98e2-8a9021209689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212971865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.1
212971865
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3563879696
Short name T123
Test name
Test status
Simulation time 1975987286 ps
CPU time 34.89 seconds
Started Feb 19 01:04:43 PM PST 24
Finished Feb 19 01:05:20 PM PST 24
Peak memory 208120 kb
Host smart-bd2f570a-ff86-428e-b19a-039c2146ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563879696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3563879696
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1196773423
Short name T24
Test name
Test status
Simulation time 22011294 ps
CPU time 0.76 seconds
Started Feb 19 01:04:50 PM PST 24
Finished Feb 19 01:04:52 PM PST 24
Peak memory 205352 kb
Host smart-bbd80d0e-9924-4359-bc21-7ef4f4a399a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196773423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
196773423
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3279948469
Short name T10
Test name
Test status
Simulation time 12981925418 ps
CPU time 31.97 seconds
Started Feb 19 01:04:44 PM PST 24
Finished Feb 19 01:05:18 PM PST 24
Peak memory 207224 kb
Host smart-c693ecb6-79c2-4d0e-ae96-f60094a2971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279948469 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3279948469
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.270723666
Short name T68
Test name
Test status
Simulation time 11695808 ps
CPU time 0.88 seconds
Started Feb 19 01:04:42 PM PST 24
Finished Feb 19 01:04:45 PM PST 24
Peak memory 205264 kb
Host smart-fe58082a-d16b-40d0-82c3-e2152a229180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270723666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.270723666
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.937029666
Short name T155
Test name
Test status
Simulation time 12541306 ps
CPU time 0.86 seconds
Started Feb 19 01:04:42 PM PST 24
Finished Feb 19 01:04:45 PM PST 24
Peak memory 205272 kb
Host smart-e587f92a-7b25-4fe9-ae1d-e4d174570de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937029666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.937029666
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.1468331909
Short name T126
Test name
Test status
Simulation time 46187169558 ps
CPU time 110.49 seconds
Started Feb 19 01:04:46 PM PST 24
Finished Feb 19 01:06:38 PM PST 24
Peak memory 207708 kb
Host smart-8b1d5899-b856-4fa5-8eee-93393ed21f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468331909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.1468331909
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1491796355
Short name T69
Test name
Test status
Simulation time 16357993 ps
CPU time 0.8 seconds
Started Feb 19 01:05:07 PM PST 24
Finished Feb 19 01:05:10 PM PST 24
Peak memory 205304 kb
Host smart-2759d0f2-8ad4-4e95-a972-66c640795416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491796355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
491796355
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.647985325
Short name T96
Test name
Test status
Simulation time 1610416849 ps
CPU time 44.69 seconds
Started Feb 19 01:04:44 PM PST 24
Finished Feb 19 01:05:31 PM PST 24
Peak memory 207980 kb
Host smart-4615bc93-0ed0-4209-a9b7-af2fdaa9da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647985325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.647985325
Directory /workspace/9.keymgr_dpe_smoke/latest
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