Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.26 97.70 90.62 57.51 76.92 94.94 98.34 17.78


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.907310312 Feb 26 12:48:54 PM PST 24 Feb 26 12:49:00 PM PST 24 210336393 ps
T256 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.332440073 Feb 26 12:48:57 PM PST 24 Feb 26 12:48:58 PM PST 24 11518191 ps
T257 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.4208574637 Feb 26 12:48:41 PM PST 24 Feb 26 12:48:42 PM PST 24 15006976 ps
T258 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1888947342 Feb 26 12:48:56 PM PST 24 Feb 26 12:48:57 PM PST 24 21030039 ps
T259 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2265685946 Feb 26 12:49:04 PM PST 24 Feb 26 12:49:07 PM PST 24 391243949 ps
T260 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.4124405044 Feb 26 12:48:50 PM PST 24 Feb 26 12:48:52 PM PST 24 14323733 ps
T55 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4116937755 Feb 26 12:48:37 PM PST 24 Feb 26 12:48:42 PM PST 24 121509719 ps
T261 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3942719691 Feb 26 12:48:51 PM PST 24 Feb 26 12:48:52 PM PST 24 23690415 ps
T262 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1198332122 Feb 26 12:48:53 PM PST 24 Feb 26 12:48:55 PM PST 24 13485395 ps
T263 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3416755241 Feb 26 12:48:50 PM PST 24 Feb 26 12:48:51 PM PST 24 28383824 ps
T264 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.951596909 Feb 26 12:48:49 PM PST 24 Feb 26 12:48:52 PM PST 24 123355726 ps
T265 /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.676445668 Feb 26 12:49:04 PM PST 24 Feb 26 12:49:05 PM PST 24 37751012 ps
T266 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2508784484 Feb 26 12:48:46 PM PST 24 Feb 26 12:48:50 PM PST 24 86190285 ps
T267 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2521513310 Feb 26 12:48:51 PM PST 24 Feb 26 12:48:53 PM PST 24 80300356 ps
T268 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.630563163 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:39 PM PST 24 373573257 ps
T269 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2716348184 Feb 26 12:48:34 PM PST 24 Feb 26 12:48:41 PM PST 24 998560753 ps
T63 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3887567408 Feb 26 12:48:34 PM PST 24 Feb 26 12:48:39 PM PST 24 349622523 ps
T270 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3274222844 Feb 26 12:48:53 PM PST 24 Feb 26 12:48:54 PM PST 24 43037433 ps
T271 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3457162298 Feb 26 12:48:39 PM PST 24 Feb 26 12:48:45 PM PST 24 79658142 ps
T272 /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.257900904 Feb 26 12:48:48 PM PST 24 Feb 26 12:48:50 PM PST 24 35867425 ps
T273 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1160296430 Feb 26 12:48:39 PM PST 24 Feb 26 12:48:43 PM PST 24 1247666538 ps
T56 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3604681217 Feb 26 12:48:29 PM PST 24 Feb 26 12:48:34 PM PST 24 343289142 ps
T274 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2765416121 Feb 26 12:48:38 PM PST 24 Feb 26 12:48:40 PM PST 24 35335031 ps
T275 /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1354671672 Feb 26 12:49:07 PM PST 24 Feb 26 12:49:08 PM PST 24 47705735 ps
T276 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1117223063 Feb 26 12:49:03 PM PST 24 Feb 26 12:49:04 PM PST 24 11364044 ps
T277 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3242995455 Feb 26 12:49:09 PM PST 24 Feb 26 12:49:11 PM PST 24 16846564 ps
T278 /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.561081495 Feb 26 12:49:06 PM PST 24 Feb 26 12:49:07 PM PST 24 34425871 ps
T53 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3290846940 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:42 PM PST 24 636803552 ps
T279 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.1012104933 Feb 26 12:48:33 PM PST 24 Feb 26 12:48:37 PM PST 24 173554919 ps
T280 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1770762429 Feb 26 12:48:55 PM PST 24 Feb 26 12:48:58 PM PST 24 47724711 ps
T281 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1356442318 Feb 26 12:48:48 PM PST 24 Feb 26 12:48:52 PM PST 24 51406997 ps
T282 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.4286369137 Feb 26 12:48:39 PM PST 24 Feb 26 12:48:40 PM PST 24 44720090 ps
T283 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2319423294 Feb 26 12:48:48 PM PST 24 Feb 26 12:48:50 PM PST 24 37014209 ps
T284 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3201128064 Feb 26 12:48:45 PM PST 24 Feb 26 12:48:47 PM PST 24 16101953 ps
T285 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2070804519 Feb 26 12:48:39 PM PST 24 Feb 26 12:48:43 PM PST 24 644060838 ps
T286 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.714791696 Feb 26 12:48:35 PM PST 24 Feb 26 12:48:38 PM PST 24 14674994 ps
T287 /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.602600249 Feb 26 12:49:06 PM PST 24 Feb 26 12:49:07 PM PST 24 8890824 ps
T288 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3605478900 Feb 26 12:48:50 PM PST 24 Feb 26 12:48:55 PM PST 24 543345670 ps
T289 /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3666407445 Feb 26 12:49:00 PM PST 24 Feb 26 12:49:01 PM PST 24 20794435 ps
T290 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.112964478 Feb 26 12:48:42 PM PST 24 Feb 26 12:48:46 PM PST 24 105497439 ps
T291 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.4074491123 Feb 26 12:48:33 PM PST 24 Feb 26 12:48:35 PM PST 24 28943474 ps
T292 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3531124972 Feb 26 12:48:48 PM PST 24 Feb 26 12:48:52 PM PST 24 494986106 ps
T293 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1255231367 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:39 PM PST 24 23792568 ps
T294 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3515086746 Feb 26 12:48:35 PM PST 24 Feb 26 12:48:41 PM PST 24 411242900 ps
T295 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2014214427 Feb 26 12:48:52 PM PST 24 Feb 26 12:48:54 PM PST 24 40179546 ps
T296 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.787209664 Feb 26 12:48:53 PM PST 24 Feb 26 12:48:55 PM PST 24 96405206 ps
T297 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.1062997475 Feb 26 12:48:40 PM PST 24 Feb 26 12:48:43 PM PST 24 1277839917 ps
T298 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.855749691 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:38 PM PST 24 23092164 ps
T299 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2440297874 Feb 26 12:48:56 PM PST 24 Feb 26 12:48:58 PM PST 24 325295885 ps
T300 /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3688783509 Feb 26 12:48:40 PM PST 24 Feb 26 12:48:42 PM PST 24 10950507 ps
T301 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1519443346 Feb 26 12:48:51 PM PST 24 Feb 26 12:48:53 PM PST 24 10418454 ps
T302 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1732343307 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:40 PM PST 24 225147816 ps
T303 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1417955545 Feb 26 12:48:36 PM PST 24 Feb 26 12:48:38 PM PST 24 245696874 ps
T304 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2523558497 Feb 26 12:48:51 PM PST 24 Feb 26 12:48:53 PM PST 24 29704524 ps
T305 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1385233081 Feb 26 12:49:05 PM PST 24 Feb 26 12:49:06 PM PST 24 10170226 ps
T306 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2743442239 Feb 26 12:49:13 PM PST 24 Feb 26 12:49:14 PM PST 24 26188690 ps
T307 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3149348875 Feb 26 12:48:41 PM PST 24 Feb 26 12:48:45 PM PST 24 721520476 ps
T308 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2774710563 Feb 26 12:48:54 PM PST 24 Feb 26 12:48:55 PM PST 24 64440318 ps
T309 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.108145894 Feb 26 12:48:42 PM PST 24 Feb 26 12:48:45 PM PST 24 1340402253 ps

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.2249372027
Short name T5
Test name
Test status
Simulation time 2803209446 ps
CPU time 42.17 seconds
Started Feb 26 01:06:53 PM PST 24
Finished Feb 26 01:07:36 PM PST 24
Peak memory 207316 kb
Host smart-c7279930-2dd8-4cda-816e-5e077e5d3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249372027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.2249372027
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.3616546060
Short name T8
Test name
Test status
Simulation time 1403511042 ps
CPU time 15.88 seconds
Started Feb 26 01:06:38 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 232220 kb
Host smart-7531803a-9eb1-45d1-88ab-e2ab15700c04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616546060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.3616546060
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.1284256061
Short name T85
Test name
Test status
Simulation time 95068213 ps
CPU time 3.27 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 204440 kb
Host smart-015e969e-6a77-44cc-bbd5-24e3bdd31ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284256061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.1284256061
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.3017559026
Short name T4
Test name
Test status
Simulation time 413800101 ps
CPU time 15.64 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:20 PM PST 24
Peak memory 208204 kb
Host smart-0979c244-965c-42ab-a99c-c1d1729bd578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017559026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.3017559026
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.1624477865
Short name T22
Test name
Test status
Simulation time 30846452 ps
CPU time 1.83 seconds
Started Feb 26 12:48:34 PM PST 24
Finished Feb 26 12:48:36 PM PST 24
Peak memory 220284 kb
Host smart-144c44aa-f5ae-44b5-9e4d-43d06c2a6b20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624477865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.1
624477865
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3173022100
Short name T50
Test name
Test status
Simulation time 323723680 ps
CPU time 5.28 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:49:02 PM PST 24
Peak memory 212904 kb
Host smart-770cd480-63c2-427e-90ea-4ee7aa4abb98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173022100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3173022100
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.3904039423
Short name T20
Test name
Test status
Simulation time 25226607 ps
CPU time 0.81 seconds
Started Feb 26 01:06:46 PM PST 24
Finished Feb 26 01:06:47 PM PST 24
Peak memory 205480 kb
Host smart-0d103d18-77fc-4345-b261-7343bf8e09fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904039423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.3
904039423
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1253596446
Short name T54
Test name
Test status
Simulation time 351076509 ps
CPU time 4.77 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 212496 kb
Host smart-ed7e7d3e-aac2-45d6-b02c-0d22479476d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253596446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1253596446
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.2706904854
Short name T119
Test name
Test status
Simulation time 10974869 ps
CPU time 0.76 seconds
Started Feb 26 12:48:56 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204268 kb
Host smart-54fc31d6-2e5b-4b89-83b7-12d01bbb9917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706904854 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
2706904854
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.4292271263
Short name T43
Test name
Test status
Simulation time 76695770 ps
CPU time 1.81 seconds
Started Feb 26 12:48:29 PM PST 24
Finished Feb 26 12:48:32 PM PST 24
Peak memory 212736 kb
Host smart-d2b4f8f1-08c4-4f9c-8f33-104f1eaabcff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292271263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.4
292271263
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.2703134850
Short name T80
Test name
Test status
Simulation time 1282192335 ps
CPU time 14.17 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:16 PM PST 24
Peak memory 208164 kb
Host smart-fae61182-8f01-4eac-bd6c-f89646c26197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703134850 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.2703134850
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1439815294
Short name T52
Test name
Test status
Simulation time 789902118 ps
CPU time 6.42 seconds
Started Feb 26 12:48:42 PM PST 24
Finished Feb 26 12:48:48 PM PST 24
Peak memory 213936 kb
Host smart-ac825abc-809d-43b5-9a59-5e334e08850e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439815294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1439815294
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.4239028942
Short name T49
Test name
Test status
Simulation time 910105931 ps
CPU time 5.18 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 213552 kb
Host smart-b20c18e2-6cfa-4ef1-9cbd-4a8cadc0f8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239028942 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.4239028942
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2323215712
Short name T227
Test name
Test status
Simulation time 87154341 ps
CPU time 1.87 seconds
Started Feb 26 12:48:44 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 213056 kb
Host smart-6ae9038f-1512-4fc6-a57f-c474be9bdc22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323215712 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2323215712
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3826905823
Short name T13
Test name
Test status
Simulation time 523479393 ps
CPU time 14.48 seconds
Started Feb 26 01:06:51 PM PST 24
Finished Feb 26 01:07:08 PM PST 24
Peak memory 207940 kb
Host smart-c91a5fc5-df1f-40b4-8cc5-644ea1da713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826905823 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3826905823
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.906925617
Short name T35
Test name
Test status
Simulation time 1363975568 ps
CPU time 6.89 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:59 PM PST 24
Peak memory 213704 kb
Host smart-321442c9-933f-4c0a-9b84-53fba31968c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906925617 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.906925617
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.448240578
Short name T36
Test name
Test status
Simulation time 103610809 ps
CPU time 3.72 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:58 PM PST 24
Peak memory 212560 kb
Host smart-d31e0e12-87e1-4975-9bec-8837ecd7dbda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448240578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe
_tl_intg_err.448240578
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3887567408
Short name T63
Test name
Test status
Simulation time 349622523 ps
CPU time 4.01 seconds
Started Feb 26 12:48:34 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 212468 kb
Host smart-cca8981c-87f6-4454-9b70-a0d9e73b550d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887567408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3887567408
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.3353982502
Short name T60
Test name
Test status
Simulation time 161505441 ps
CPU time 2.34 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 212532 kb
Host smart-ae0ed991-6b0e-4388-b490-ada7bd024a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353982502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.3353982502
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3290846940
Short name T53
Test name
Test status
Simulation time 636803552 ps
CPU time 4.92 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 212696 kb
Host smart-816a5377-324e-4ca7-b73b-39148a547800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290846940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3290846940
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2361323985
Short name T24
Test name
Test status
Simulation time 2422562879 ps
CPU time 14.83 seconds
Started Feb 26 01:06:41 PM PST 24
Finished Feb 26 01:06:56 PM PST 24
Peak memory 231740 kb
Host smart-411efa86-a00b-45ea-b125-bf8c3b9592c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361323985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2361323985
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.2570090336
Short name T57
Test name
Test status
Simulation time 66145360 ps
CPU time 1.38 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 220128 kb
Host smart-33cda1ee-19c1-4f84-b449-18145cab27ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570090336 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.2570090336
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.486353921
Short name T110
Test name
Test status
Simulation time 4961150645 ps
CPU time 25.37 seconds
Started Feb 26 01:06:40 PM PST 24
Finished Feb 26 01:07:06 PM PST 24
Peak memory 207784 kb
Host smart-92f57a51-5e9f-4f0f-959f-bee614202b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486353921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.486353921
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.725432268
Short name T114
Test name
Test status
Simulation time 635702073 ps
CPU time 11.52 seconds
Started Feb 26 01:06:42 PM PST 24
Finished Feb 26 01:06:55 PM PST 24
Peak memory 206944 kb
Host smart-0babffbb-b21a-4317-8b0e-b56ebfb02bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725432268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.725432268
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3311912749
Short name T84
Test name
Test status
Simulation time 2542773365 ps
CPU time 22.84 seconds
Started Feb 26 01:06:55 PM PST 24
Finished Feb 26 01:07:18 PM PST 24
Peak memory 208080 kb
Host smart-1c7c4ab4-8109-4de3-943f-0f0ab4066924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311912749 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3311912749
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.4242144859
Short name T78
Test name
Test status
Simulation time 19175613666 ps
CPU time 159.96 seconds
Started Feb 26 01:06:57 PM PST 24
Finished Feb 26 01:09:37 PM PST 24
Peak memory 208424 kb
Host smart-a6eb22e6-894c-4264-af4d-e407212c731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242144859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.4242144859
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.4192610547
Short name T33
Test name
Test status
Simulation time 510583152 ps
CPU time 15.62 seconds
Started Feb 26 01:06:53 PM PST 24
Finished Feb 26 01:07:09 PM PST 24
Peak memory 207124 kb
Host smart-dbae2bcb-75da-4137-a433-4b983755eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192610547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.4192610547
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.553777017
Short name T108
Test name
Test status
Simulation time 695615033 ps
CPU time 15.41 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:16 PM PST 24
Peak memory 206452 kb
Host smart-88cb1e92-a078-454c-b125-62e00251dd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553777017 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.553777017
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.1321461108
Short name T81
Test name
Test status
Simulation time 3844912369 ps
CPU time 33.87 seconds
Started Feb 26 01:07:05 PM PST 24
Finished Feb 26 01:07:43 PM PST 24
Peak memory 206340 kb
Host smart-06d608a3-95f9-4062-b77c-f62d28592389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321461108 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.1321461108
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.1539411387
Short name T111
Test name
Test status
Simulation time 885090309 ps
CPU time 13.49 seconds
Started Feb 26 01:07:04 PM PST 24
Finished Feb 26 01:07:18 PM PST 24
Peak memory 205976 kb
Host smart-d7605158-710b-470a-a433-aa4afbbdda43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539411387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.1539411387
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3514244568
Short name T16
Test name
Test status
Simulation time 1083215964 ps
CPU time 13.82 seconds
Started Feb 26 01:07:04 PM PST 24
Finished Feb 26 01:07:19 PM PST 24
Peak memory 206424 kb
Host smart-3fe2bc94-8ce5-405e-a645-e0a57d13192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514244568 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3514244568
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.489718544
Short name T31
Test name
Test status
Simulation time 3405161325 ps
CPU time 29.19 seconds
Started Feb 26 01:07:08 PM PST 24
Finished Feb 26 01:07:38 PM PST 24
Peak memory 207368 kb
Host smart-d53cdca3-f6e0-46b1-aa59-5bedf86fdb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489718544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.489718544
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.2896619821
Short name T82
Test name
Test status
Simulation time 546085256 ps
CPU time 17.62 seconds
Started Feb 26 01:06:50 PM PST 24
Finished Feb 26 01:07:08 PM PST 24
Peak memory 207228 kb
Host smart-4ba1274d-eb6f-439b-b184-054838ca6542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896619821 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.2896619821
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.3646496112
Short name T109
Test name
Test status
Simulation time 256766082 ps
CPU time 13.77 seconds
Started Feb 26 01:06:46 PM PST 24
Finished Feb 26 01:07:01 PM PST 24
Peak memory 206712 kb
Host smart-a511fa98-da40-46df-aca8-0cb95ad3e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646496112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.3646496112
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.1012104933
Short name T279
Test name
Test status
Simulation time 173554919 ps
CPU time 3.09 seconds
Started Feb 26 12:48:33 PM PST 24
Finished Feb 26 12:48:37 PM PST 24
Peak memory 204392 kb
Host smart-c27f76b9-a849-4bad-ba95-f25997e577ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012104933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.1012104933
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.441856362
Short name T202
Test name
Test status
Simulation time 741916257 ps
CPU time 5.77 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 204360 kb
Host smart-62d185d6-f5c9-4d20-8d8e-99217f5d9b32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441856362 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_bit_bash.441856362
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.3083314495
Short name T209
Test name
Test status
Simulation time 17538629 ps
CPU time 1.04 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 204396 kb
Host smart-cd819c2c-87c2-41e4-a6c7-562267d95ba2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083314495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.3083314495
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3472600398
Short name T176
Test name
Test status
Simulation time 23296437 ps
CPU time 1.59 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:37 PM PST 24
Peak memory 212720 kb
Host smart-c7dfe668-75c7-4160-b57e-113f58bd20b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472600398 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3472600398
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.714791696
Short name T286
Test name
Test status
Simulation time 14674994 ps
CPU time 1.01 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 204388 kb
Host smart-12861103-5d50-4871-8b9e-4a3a527809c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714791696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.714791696
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.1142173665
Short name T193
Test name
Test status
Simulation time 12461298 ps
CPU time 0.85 seconds
Started Feb 26 12:48:33 PM PST 24
Finished Feb 26 12:48:35 PM PST 24
Peak memory 204232 kb
Host smart-9acccea0-a5df-455f-ba60-224ea68d5439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142173665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.1
142173665
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.2330091890
Short name T215
Test name
Test status
Simulation time 62683671 ps
CPU time 1.79 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 213104 kb
Host smart-e4d3d111-c6b9-4b86-9ee4-1764f12e5348
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330091890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.2330091890
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.293497201
Short name T104
Test name
Test status
Simulation time 255997709 ps
CPU time 4.81 seconds
Started Feb 26 12:48:28 PM PST 24
Finished Feb 26 12:48:34 PM PST 24
Peak memory 213012 kb
Host smart-248ca7df-abaa-4a3b-8523-77ab47ef8fdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293497201 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.293497201
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3025813566
Short name T199
Test name
Test status
Simulation time 1143421509 ps
CPU time 5.37 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204372 kb
Host smart-2b4609a0-8506-4eb0-a9cc-c65b7afb17c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025813566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.3025813566
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1806864194
Short name T164
Test name
Test status
Simulation time 343695235 ps
CPU time 8.13 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:45 PM PST 24
Peak memory 204440 kb
Host smart-ac8e80a6-037e-448f-9d38-df2fadf93e5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806864194 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1806864194
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1119021503
Short name T103
Test name
Test status
Simulation time 102926376 ps
CPU time 1.03 seconds
Started Feb 26 12:48:34 PM PST 24
Finished Feb 26 12:48:35 PM PST 24
Peak memory 204216 kb
Host smart-8eb8489a-37be-42b4-bd0a-7c984dd8b9c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119021503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1119021503
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1417955545
Short name T303
Test name
Test status
Simulation time 245696874 ps
CPU time 1.12 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 212584 kb
Host smart-a3c3f4e2-90e1-4aa2-b7ac-8e675d88f71b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417955545 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.1417955545
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2491637919
Short name T191
Test name
Test status
Simulation time 146941641 ps
CPU time 0.9 seconds
Started Feb 26 12:48:31 PM PST 24
Finished Feb 26 12:48:34 PM PST 24
Peak memory 204196 kb
Host smart-93ca5f48-3d1a-4269-a869-c5b31afa9aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491637919 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
491637919
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.855749691
Short name T298
Test name
Test status
Simulation time 23092164 ps
CPU time 0.78 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 204232 kb
Host smart-c9b2fb5b-8c1f-4613-94ce-e482637cbf3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855749691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.855749691
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2711077315
Short name T105
Test name
Test status
Simulation time 117205928 ps
CPU time 2.26 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204344 kb
Host smart-6200ed48-c20b-4780-b942-e807f96bc9a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711077315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.2711077315
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2681617133
Short name T179
Test name
Test status
Simulation time 36277410 ps
CPU time 1.29 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 212876 kb
Host smart-f7f2a22b-9ec6-40eb-a696-419ee14dc0b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681617133 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2681617133
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1355365160
Short name T248
Test name
Test status
Simulation time 264324246 ps
CPU time 6.99 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 217728 kb
Host smart-1091d446-db64-4ccc-90f3-456b50b4ab81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355365160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1355365160
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3604681217
Short name T56
Test name
Test status
Simulation time 343289142 ps
CPU time 3.86 seconds
Started Feb 26 12:48:29 PM PST 24
Finished Feb 26 12:48:34 PM PST 24
Peak memory 212608 kb
Host smart-704ae121-2c90-41d1-b17b-e1aab280230b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604681217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.3604681217
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3201128064
Short name T284
Test name
Test status
Simulation time 16101953 ps
CPU time 1.1 seconds
Started Feb 26 12:48:45 PM PST 24
Finished Feb 26 12:48:47 PM PST 24
Peak memory 204460 kb
Host smart-e5ddeb09-484a-4c54-9604-77e634abd9f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201128064 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3201128064
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.315082784
Short name T232
Test name
Test status
Simulation time 43848668 ps
CPU time 1.11 seconds
Started Feb 26 12:48:45 PM PST 24
Finished Feb 26 12:48:47 PM PST 24
Peak memory 204356 kb
Host smart-da4ba801-106a-4d34-8f6d-91365e61138e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315082784 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.315082784
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.425306443
Short name T225
Test name
Test status
Simulation time 250265316 ps
CPU time 2.76 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:51 PM PST 24
Peak memory 203848 kb
Host smart-3670eaa6-cc9f-4092-b486-bfa7fbfa6198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425306443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_dpe_same_csr_outstanding.425306443
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3531124972
Short name T292
Test name
Test status
Simulation time 494986106 ps
CPU time 3.06 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 212328 kb
Host smart-3bf18ab4-f959-412e-adba-3b6e49a17bd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531124972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3531124972
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.108145894
Short name T309
Test name
Test status
Simulation time 1340402253 ps
CPU time 2.59 seconds
Started Feb 26 12:48:42 PM PST 24
Finished Feb 26 12:48:45 PM PST 24
Peak memory 214212 kb
Host smart-6c874fe3-9826-48f1-9a53-ab5ad321e09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108145894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.108145894
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3980938766
Short name T61
Test name
Test status
Simulation time 477144084 ps
CPU time 4.73 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 213968 kb
Host smart-30e387be-296b-4c57-8884-52044c3ad6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980938766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3980938766
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.1126310829
Short name T71
Test name
Test status
Simulation time 15011163 ps
CPU time 1.15 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:50 PM PST 24
Peak memory 204480 kb
Host smart-f340a6d4-fc71-4326-b4f4-95235b414c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126310829 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.1126310829
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3942719691
Short name T261
Test name
Test status
Simulation time 23690415 ps
CPU time 1.08 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 204212 kb
Host smart-8a55c9ae-b914-4ff8-a364-6b619a8dadd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942719691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
3942719691
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1519443346
Short name T301
Test name
Test status
Simulation time 10418454 ps
CPU time 0.73 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 204236 kb
Host smart-a277f7f4-e74a-4b40-abca-268fedf2fc3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519443346 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1519443346
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2631385522
Short name T178
Test name
Test status
Simulation time 131334311 ps
CPU time 2.86 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:56 PM PST 24
Peak memory 204460 kb
Host smart-df1bfe46-4395-4ded-8696-0bfa8ef6b602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631385522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2631385522
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1066439131
Short name T213
Test name
Test status
Simulation time 128742131 ps
CPU time 1.27 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 212940 kb
Host smart-6072dd7f-ad17-4927-ae4e-6ed5093e7c41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066439131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1066439131
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.618603291
Short name T168
Test name
Test status
Simulation time 480825423 ps
CPU time 4.62 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:59 PM PST 24
Peak memory 213048 kb
Host smart-b0619034-d9e0-464f-b5b6-f1e40e52f110
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618603291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.618603291
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.2722299397
Short name T37
Test name
Test status
Simulation time 35505683 ps
CPU time 2.22 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 220848 kb
Host smart-c88c6fc2-398b-4036-afce-223b13175ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722299397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
2722299397
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2679497501
Short name T240
Test name
Test status
Simulation time 214214354 ps
CPU time 7.59 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:49:01 PM PST 24
Peak memory 212564 kb
Host smart-9a54471f-60fe-4e8a-900c-98d6631bebfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679497501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.2679497501
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3416755241
Short name T263
Test name
Test status
Simulation time 28383824 ps
CPU time 1.32 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:51 PM PST 24
Peak memory 212688 kb
Host smart-45c2beae-b158-4432-8dea-ac818414b112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416755241 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3416755241
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2670814078
Short name T101
Test name
Test status
Simulation time 183874467 ps
CPU time 1.24 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 204396 kb
Host smart-601382f7-9645-4117-8893-cbbd95168c5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670814078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2670814078
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.257900904
Short name T272
Test name
Test status
Simulation time 35867425 ps
CPU time 0.72 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:50 PM PST 24
Peak memory 204268 kb
Host smart-e90d71fd-8ed9-4a6c-8d19-974b49b05151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257900904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.257900904
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.4204297962
Short name T106
Test name
Test status
Simulation time 107581931 ps
CPU time 1.93 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 204324 kb
Host smart-e734fcba-ff18-4535-af31-1a6619063cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204297962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.4204297962
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.761700055
Short name T230
Test name
Test status
Simulation time 117031490 ps
CPU time 2.07 seconds
Started Feb 26 12:48:49 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 213024 kb
Host smart-42412da4-0c55-4a82-bd8e-a30cfe03c2f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761700055 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym
gr_dpe_shadow_reg_errors.761700055
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2208131883
Short name T170
Test name
Test status
Simulation time 544667681 ps
CPU time 4.46 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 212932 kb
Host smart-ef5ad312-ae52-4d76-9b72-58346c86b4af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208131883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.2208131883
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.1302874648
Short name T51
Test name
Test status
Simulation time 420784941 ps
CPU time 3.04 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 215020 kb
Host smart-d1394fa7-0ec4-4af0-9cc1-876a49f2428e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302874648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
1302874648
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.4203900169
Short name T21
Test name
Test status
Simulation time 248654637 ps
CPU time 8.12 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:49:01 PM PST 24
Peak memory 213752 kb
Host smart-ba0b5381-47c5-47d6-930c-22d2ba46322b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203900169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.4203900169
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3339119713
Short name T169
Test name
Test status
Simulation time 21596991 ps
CPU time 0.98 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 204464 kb
Host smart-066e8829-8960-4e09-b568-5ae76b853737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339119713 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
3339119713
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.3238523349
Short name T229
Test name
Test status
Simulation time 63009603 ps
CPU time 0.72 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:51 PM PST 24
Peak memory 204228 kb
Host smart-5d83f87e-f475-4cde-b06b-037f549345eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238523349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
3238523349
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.2319423294
Short name T283
Test name
Test status
Simulation time 37014209 ps
CPU time 1.56 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:50 PM PST 24
Peak memory 204424 kb
Host smart-c7af7288-79e9-4931-b805-9aa00a081421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319423294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.2319423294
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3573249449
Short name T182
Test name
Test status
Simulation time 192898621 ps
CPU time 1.62 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 212912 kb
Host smart-d5197192-7572-4538-a3a1-db4dc45877be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573249449 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.3573249449
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3605478900
Short name T288
Test name
Test status
Simulation time 543345670 ps
CPU time 4.07 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 218088 kb
Host smart-fcf40268-7f0d-4718-a958-58fa00b79db2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605478900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3605478900
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1286460480
Short name T44
Test name
Test status
Simulation time 144120001 ps
CPU time 2.26 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 212664 kb
Host smart-55c643ea-7068-4c0e-b919-95e3ef507419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286460480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1286460480
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2317998552
Short name T238
Test name
Test status
Simulation time 284851691 ps
CPU time 4.48 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 212524 kb
Host smart-ec371033-a266-4e58-9c73-77763358794f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317998552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2317998552
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.918803576
Short name T41
Test name
Test status
Simulation time 22280751 ps
CPU time 1.6 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:49 PM PST 24
Peak memory 212676 kb
Host smart-cbadc9d0-eca6-42c0-983f-edd3020a07e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918803576 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.918803576
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.4124405044
Short name T260
Test name
Test status
Simulation time 14323733 ps
CPU time 0.92 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 204288 kb
Host smart-50c01762-7b8d-4ee3-a43c-725df5920248
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124405044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
4124405044
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3274222844
Short name T270
Test name
Test status
Simulation time 43037433 ps
CPU time 0.75 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204248 kb
Host smart-9e196f25-b9f8-42b7-81ec-37b454f3f30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274222844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3274222844
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.2177243010
Short name T201
Test name
Test status
Simulation time 32225388 ps
CPU time 1.79 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:48:59 PM PST 24
Peak memory 204512 kb
Host smart-3c691a86-cfd9-4cd4-94e8-8d519fa73d1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177243010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.2177243010
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2521513310
Short name T267
Test name
Test status
Simulation time 80300356 ps
CPU time 1.44 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 212928 kb
Host smart-bf785699-e80f-4133-a261-8d0e73d7a836
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521513310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2521513310
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.139794307
Short name T172
Test name
Test status
Simulation time 64445186 ps
CPU time 3.05 seconds
Started Feb 26 12:48:49 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 218068 kb
Host smart-02c3c9cb-503d-49d7-b0b4-0901876451fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139794307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.139794307
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1356442318
Short name T281
Test name
Test status
Simulation time 51406997 ps
CPU time 3.24 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 220400 kb
Host smart-49f4a5af-ee60-4f51-b347-c2caa3963cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356442318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1356442318
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.787209664
Short name T296
Test name
Test status
Simulation time 96405206 ps
CPU time 1.85 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 212708 kb
Host smart-c93968aa-6af6-45b2-add7-d31a21fef8b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787209664 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.787209664
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1393891208
Short name T107
Test name
Test status
Simulation time 39384855 ps
CPU time 0.99 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 204244 kb
Host smart-abe30b99-0b30-405c-86b3-c5d78ef8e2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393891208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
1393891208
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.1547092894
Short name T252
Test name
Test status
Simulation time 10753037 ps
CPU time 0.86 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 204252 kb
Host smart-f96fe423-1858-45c7-a44e-b10accb07fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547092894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
1547092894
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2976937930
Short name T237
Test name
Test status
Simulation time 77069838 ps
CPU time 2.94 seconds
Started Feb 26 12:48:50 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204396 kb
Host smart-a705180d-0f99-4b0b-9a3f-72b907963a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976937930 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2976937930
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2523558497
Short name T304
Test name
Test status
Simulation time 29704524 ps
CPU time 1.45 seconds
Started Feb 26 12:48:51 PM PST 24
Finished Feb 26 12:48:53 PM PST 24
Peak memory 212936 kb
Host smart-bb849ba1-4e38-4960-8d68-94a7226d7b50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523558497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2523558497
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3681087142
Short name T196
Test name
Test status
Simulation time 276011469 ps
CPU time 9.67 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:49:04 PM PST 24
Peak memory 217912 kb
Host smart-304ae01d-597a-4d00-9dc6-d4da6db684cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681087142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3681087142
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2476213140
Short name T58
Test name
Test status
Simulation time 99978115 ps
CPU time 2.59 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:49:00 PM PST 24
Peak memory 213708 kb
Host smart-784464d2-97c5-4cfc-982c-f7ae3e9fbb02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476213140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2476213140
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.2344634448
Short name T236
Test name
Test status
Simulation time 62610892 ps
CPU time 1.42 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 212712 kb
Host smart-4e7fb7e5-dfd6-4871-9bed-cd89977c7dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344634448 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.2344634448
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1198332122
Short name T262
Test name
Test status
Simulation time 13485395 ps
CPU time 1.03 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 204264 kb
Host smart-d5aeb896-3bb3-41e3-b17b-548ab7f4c0db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198332122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1198332122
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.426586645
Short name T102
Test name
Test status
Simulation time 18031951 ps
CPU time 0.82 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204316 kb
Host smart-dac3e74a-ced5-419a-ad0d-1f800f9d5b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426586645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.426586645
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.3404897044
Short name T189
Test name
Test status
Simulation time 34125281 ps
CPU time 1.32 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204492 kb
Host smart-237daae0-c4ac-4fb1-a42e-1ae5632465fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404897044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.3404897044
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2508784484
Short name T266
Test name
Test status
Simulation time 86190285 ps
CPU time 2.71 seconds
Started Feb 26 12:48:46 PM PST 24
Finished Feb 26 12:48:50 PM PST 24
Peak memory 212908 kb
Host smart-f7fb2132-3aa5-48a0-98c5-7f80b5e26aa6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508784484 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2508784484
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1417789360
Short name T69
Test name
Test status
Simulation time 277122169 ps
CPU time 6.07 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:59 PM PST 24
Peak memory 213028 kb
Host smart-764eb71c-95d6-4ebf-869b-7e3f90cd4c4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417789360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1417789360
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2014214427
Short name T295
Test name
Test status
Simulation time 40179546 ps
CPU time 1.41 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 212728 kb
Host smart-40320f6a-0b78-469b-b44f-2045430acee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014214427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2014214427
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.951596909
Short name T264
Test name
Test status
Simulation time 123355726 ps
CPU time 2.81 seconds
Started Feb 26 12:48:49 PM PST 24
Finished Feb 26 12:48:52 PM PST 24
Peak memory 212568 kb
Host smart-025ff9b9-67f6-4018-9f31-cbd06fd9915a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951596909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe
_tl_intg_err.951596909
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.633908853
Short name T203
Test name
Test status
Simulation time 63281542 ps
CPU time 1.4 seconds
Started Feb 26 12:48:59 PM PST 24
Finished Feb 26 12:49:01 PM PST 24
Peak memory 212596 kb
Host smart-918eb543-8abf-424d-bc7f-54f583297aae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633908853 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.633908853
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2188225899
Short name T204
Test name
Test status
Simulation time 38717360 ps
CPU time 0.86 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204236 kb
Host smart-3b2937e1-a3cf-45b1-bff0-d42ea38966b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188225899 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2188225899
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.106328853
Short name T185
Test name
Test status
Simulation time 44674407 ps
CPU time 0.85 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:56 PM PST 24
Peak memory 204228 kb
Host smart-76f56ac1-b3e6-4e4f-a42a-0362af0877d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106328853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.106328853
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.197979514
Short name T188
Test name
Test status
Simulation time 33846651 ps
CPU time 1.34 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:56 PM PST 24
Peak memory 204488 kb
Host smart-efc605e2-b3df-4764-a8be-994d9b743893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197979514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_dpe_same_csr_outstanding.197979514
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2440297874
Short name T299
Test name
Test status
Simulation time 325295885 ps
CPU time 1.87 seconds
Started Feb 26 12:48:56 PM PST 24
Finished Feb 26 12:48:58 PM PST 24
Peak memory 213008 kb
Host smart-f04acf1a-9f62-495c-99f5-6fca772eb6a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440297874 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.2440297874
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1770762429
Short name T280
Test name
Test status
Simulation time 47724711 ps
CPU time 3 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:58 PM PST 24
Peak memory 212584 kb
Host smart-fb261f5c-4100-4ee9-a35c-f7996f4c6066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770762429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
1770762429
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2779271046
Short name T59
Test name
Test status
Simulation time 112503755 ps
CPU time 4.32 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:59 PM PST 24
Peak memory 212988 kb
Host smart-9463e8ee-cbc6-4708-b1d9-5bf03b084ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779271046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2779271046
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.330227326
Short name T218
Test name
Test status
Simulation time 54033832 ps
CPU time 1.55 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 212668 kb
Host smart-c33ce3e4-2c68-4d90-a5c8-e94a54b96fe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330227326 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.330227326
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2838453566
Short name T87
Test name
Test status
Simulation time 46114900 ps
CPU time 1.29 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204408 kb
Host smart-42360595-fa7a-4f5b-aa3c-8d95c6b16b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838453566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2838453566
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.4282871635
Short name T250
Test name
Test status
Simulation time 11329722 ps
CPU time 0.77 seconds
Started Feb 26 12:48:56 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204248 kb
Host smart-7a7ceade-c056-4439-b001-078e22b2ae18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282871635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
4282871635
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1669449738
Short name T223
Test name
Test status
Simulation time 179723042 ps
CPU time 3.22 seconds
Started Feb 26 12:49:05 PM PST 24
Finished Feb 26 12:49:08 PM PST 24
Peak memory 204600 kb
Host smart-9a0ebb5a-5331-4b33-8974-2e8968e1fe88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669449738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1669449738
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.670070525
Short name T68
Test name
Test status
Simulation time 529289635 ps
CPU time 2.45 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:49:00 PM PST 24
Peak memory 212964 kb
Host smart-9742d5d7-dcf9-4531-9996-9b2b2e3c0465
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670070525 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keym
gr_dpe_shadow_reg_errors.670070525
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.907310312
Short name T255
Test name
Test status
Simulation time 210336393 ps
CPU time 5.63 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:49:00 PM PST 24
Peak memory 219504 kb
Host smart-b64fc463-6e6d-4b06-8c7a-f3fb176df1c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907310312 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.907310312
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2290839931
Short name T234
Test name
Test status
Simulation time 68963041 ps
CPU time 2.48 seconds
Started Feb 26 12:49:00 PM PST 24
Finished Feb 26 12:49:02 PM PST 24
Peak memory 212752 kb
Host smart-4c458a04-56af-45d2-b57a-7978c03251a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290839931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
2290839931
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.3539496698
Short name T244
Test name
Test status
Simulation time 106336990 ps
CPU time 0.97 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:56 PM PST 24
Peak memory 204232 kb
Host smart-a0de941d-caf9-4f9c-84db-8405a6b8ca78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539496698 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.3539496698
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.332440073
Short name T256
Test name
Test status
Simulation time 11518191 ps
CPU time 0.89 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:48:58 PM PST 24
Peak memory 204272 kb
Host smart-4fc1c158-bcbd-4995-831f-4ef6a2369b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332440073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.332440073
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1878386853
Short name T226
Test name
Test status
Simulation time 14663442 ps
CPU time 0.89 seconds
Started Feb 26 12:48:52 PM PST 24
Finished Feb 26 12:48:54 PM PST 24
Peak memory 204356 kb
Host smart-c2060c91-1db7-46c9-a827-c7c9615a1c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878386853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
1878386853
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.1789081880
Short name T184
Test name
Test status
Simulation time 42615516 ps
CPU time 1.95 seconds
Started Feb 26 12:48:55 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204428 kb
Host smart-9e42de7f-7331-4942-aa38-1663cd134bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789081880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.1789081880
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2265685946
Short name T259
Test name
Test status
Simulation time 391243949 ps
CPU time 2.24 seconds
Started Feb 26 12:49:04 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 213176 kb
Host smart-88dc1d6b-f4fd-435b-8657-560a6bce9247
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265685946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2265685946
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1005904577
Short name T222
Test name
Test status
Simulation time 482828755 ps
CPU time 3.3 seconds
Started Feb 26 12:48:57 PM PST 24
Finished Feb 26 12:49:01 PM PST 24
Peak memory 213000 kb
Host smart-a22b7c4d-c68f-4540-ad1c-65ca230c6344
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005904577 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1005904577
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.944124481
Short name T48
Test name
Test status
Simulation time 119431310 ps
CPU time 3.14 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 212640 kb
Host smart-3b1079d2-25ad-4948-b70e-1505a5ffab93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944124481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.944124481
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.3109082553
Short name T217
Test name
Test status
Simulation time 344549676 ps
CPU time 4.72 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 204396 kb
Host smart-6ebd1297-8205-4aae-bebc-060bebe72772
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109082553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.3109082553
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.1674224962
Short name T40
Test name
Test status
Simulation time 297709101 ps
CPU time 8.66 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:49 PM PST 24
Peak memory 204452 kb
Host smart-87d9ac36-8735-48b7-beb4-8f33fb9c4431
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674224962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.1674224962
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.4286369137
Short name T282
Test name
Test status
Simulation time 44720090 ps
CPU time 0.98 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 204416 kb
Host smart-bac53273-0efe-44ff-8970-18cf7c3ded29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286369137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.4286369137
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.1920235155
Short name T70
Test name
Test status
Simulation time 24017094 ps
CPU time 1.3 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 212776 kb
Host smart-b2fde9e2-b42b-4c03-985d-7274c4246d48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920235155 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.1920235155
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.549751316
Short name T72
Test name
Test status
Simulation time 34940597 ps
CPU time 1.53 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 204428 kb
Host smart-0934be1f-1574-4aea-a600-78bcaae846f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549751316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.549751316
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.3688783509
Short name T300
Test name
Test status
Simulation time 10950507 ps
CPU time 0.82 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204276 kb
Host smart-83e4cc8d-7ea8-4743-bd63-04ca3a94a05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688783509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.3
688783509
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1732343307
Short name T302
Test name
Test status
Simulation time 225147816 ps
CPU time 2.6 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 204508 kb
Host smart-2209640f-b558-4261-ba08-e4325c023db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732343307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1732343307
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.648532590
Short name T233
Test name
Test status
Simulation time 422387852 ps
CPU time 2.42 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 212932 kb
Host smart-5b8afdeb-b8e2-4666-9923-a42d7ab7bb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648532590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymg
r_dpe_shadow_reg_errors.648532590
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1160296430
Short name T273
Test name
Test status
Simulation time 1247666538 ps
CPU time 3.43 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 217972 kb
Host smart-c13a3b49-5513-475a-a844-a8476b8cc3de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160296430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1160296430
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.3603841348
Short name T211
Test name
Test status
Simulation time 226068776 ps
CPU time 3.13 seconds
Started Feb 26 12:48:33 PM PST 24
Finished Feb 26 12:48:37 PM PST 24
Peak memory 212656 kb
Host smart-06c2ff98-9f1e-4280-97ed-8f8894890a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603841348 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.3
603841348
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.2070804519
Short name T285
Test name
Test status
Simulation time 644060838 ps
CPU time 3.09 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 212896 kb
Host smart-b9c69377-3c8b-4923-ac1f-d211410f8c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070804519 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.2070804519
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.676445668
Short name T265
Test name
Test status
Simulation time 37751012 ps
CPU time 0.75 seconds
Started Feb 26 12:49:04 PM PST 24
Finished Feb 26 12:49:05 PM PST 24
Peak memory 204504 kb
Host smart-9ca3ccd7-e07b-4b75-92c3-39b8f49a664b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676445668 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.676445668
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2743442239
Short name T306
Test name
Test status
Simulation time 26188690 ps
CPU time 0.75 seconds
Started Feb 26 12:49:13 PM PST 24
Finished Feb 26 12:49:14 PM PST 24
Peak memory 204268 kb
Host smart-636cfc86-5714-46bc-a7ff-d11a5762915e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743442239 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2743442239
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.992460473
Short name T180
Test name
Test status
Simulation time 25773964 ps
CPU time 0.84 seconds
Started Feb 26 12:49:07 PM PST 24
Finished Feb 26 12:49:08 PM PST 24
Peak memory 204316 kb
Host smart-aa686c77-ab65-47da-b7dd-f385f23529cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992460473 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.992460473
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.2385539757
Short name T165
Test name
Test status
Simulation time 27047274 ps
CPU time 0.82 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204216 kb
Host smart-7504cf05-3cad-4527-bfd9-7d658adf8603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385539757 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
2385539757
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.561081495
Short name T278
Test name
Test status
Simulation time 34425871 ps
CPU time 0.8 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204208 kb
Host smart-41111411-3540-43d3-ae4c-404c58a935b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561081495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.561081495
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.1946010024
Short name T198
Test name
Test status
Simulation time 10941705 ps
CPU time 0.73 seconds
Started Feb 26 12:49:02 PM PST 24
Finished Feb 26 12:49:03 PM PST 24
Peak memory 204232 kb
Host smart-747a355b-4f3e-4a06-81be-d752ed16735d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946010024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
1946010024
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.514695283
Short name T167
Test name
Test status
Simulation time 38974744 ps
CPU time 0.77 seconds
Started Feb 26 12:49:05 PM PST 24
Finished Feb 26 12:49:06 PM PST 24
Peak memory 204244 kb
Host smart-719a9df4-273c-4994-99fd-8ef0ff3f51bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514695283 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.514695283
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1385233081
Short name T305
Test name
Test status
Simulation time 10170226 ps
CPU time 0.83 seconds
Started Feb 26 12:49:05 PM PST 24
Finished Feb 26 12:49:06 PM PST 24
Peak memory 204204 kb
Host smart-b65a58d1-7825-4043-bd88-945a71bd7777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385233081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1385233081
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1117223063
Short name T276
Test name
Test status
Simulation time 11364044 ps
CPU time 0.81 seconds
Started Feb 26 12:49:03 PM PST 24
Finished Feb 26 12:49:04 PM PST 24
Peak memory 204236 kb
Host smart-9158a6aa-16c6-4cbf-8538-3f3f03d944d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117223063 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
1117223063
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.3180989858
Short name T192
Test name
Test status
Simulation time 15928834 ps
CPU time 0.82 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204208 kb
Host smart-b158ece2-e0ef-4071-b832-4872da63bd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180989858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
3180989858
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3457162298
Short name T271
Test name
Test status
Simulation time 79658142 ps
CPU time 4.48 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:45 PM PST 24
Peak memory 204416 kb
Host smart-605d29d1-01fe-41b9-9b07-37b9dfe9fbde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457162298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.3457162298
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1239382806
Short name T186
Test name
Test status
Simulation time 89672091 ps
CPU time 5.12 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 204316 kb
Host smart-ba879aa4-59e8-4646-971f-42937cc80a29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239382806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1239382806
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.1920654608
Short name T175
Test name
Test status
Simulation time 72419492 ps
CPU time 0.99 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 204392 kb
Host smart-1a640d83-2aeb-4c85-a151-baae13451261
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920654608 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.1920654608
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1255231367
Short name T293
Test name
Test status
Simulation time 23792568 ps
CPU time 1.38 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 212656 kb
Host smart-931af260-ecdd-422e-87d0-f511ff5565f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255231367 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1255231367
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.4231157965
Short name T92
Test name
Test status
Simulation time 23181074 ps
CPU time 1.12 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 204428 kb
Host smart-0db133ad-5cc0-4537-ae98-03eb68962966
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231157965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.4
231157965
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3382726352
Short name T246
Test name
Test status
Simulation time 37865118 ps
CPU time 0.74 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:36 PM PST 24
Peak memory 204204 kb
Host smart-50457518-de1a-4266-a72e-bea80f11714a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382726352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
382726352
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2815777638
Short name T221
Test name
Test status
Simulation time 105124596 ps
CPU time 1.26 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 204472 kb
Host smart-87029a08-ead5-470c-8a6c-bf4e8d280885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815777638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2815777638
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.4256470058
Short name T65
Test name
Test status
Simulation time 225013930 ps
CPU time 1.62 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 213000 kb
Host smart-92e1c10f-d4f4-45b5-9487-80c79b97404d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256470058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.4256470058
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2716348184
Short name T269
Test name
Test status
Simulation time 998560753 ps
CPU time 5.57 seconds
Started Feb 26 12:48:34 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 212908 kb
Host smart-c7cb29e1-37b7-48d5-92da-4b6f41b82d94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716348184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2716348184
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.2615301822
Short name T245
Test name
Test status
Simulation time 176867657 ps
CPU time 3.74 seconds
Started Feb 26 12:48:33 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 212748 kb
Host smart-eb43b25f-6668-46ae-8fd5-7078129bcab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615301822 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.2
615301822
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.3473454669
Short name T118
Test name
Test status
Simulation time 14791348 ps
CPU time 0.71 seconds
Started Feb 26 12:49:03 PM PST 24
Finished Feb 26 12:49:04 PM PST 24
Peak memory 204148 kb
Host smart-75affb01-98f4-4a85-8be0-83adaf842568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473454669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
3473454669
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.140365531
Short name T247
Test name
Test status
Simulation time 56543473 ps
CPU time 0.82 seconds
Started Feb 26 12:49:14 PM PST 24
Finished Feb 26 12:49:16 PM PST 24
Peak memory 204272 kb
Host smart-19a743c6-c388-484d-91c2-e048970020f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140365531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.140365531
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1581541678
Short name T171
Test name
Test status
Simulation time 16906944 ps
CPU time 0.71 seconds
Started Feb 26 12:49:01 PM PST 24
Finished Feb 26 12:49:02 PM PST 24
Peak memory 204260 kb
Host smart-36917f38-08a8-46c6-8aaa-a6da8f9f14e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581541678 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1581541678
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.127377745
Short name T89
Test name
Test status
Simulation time 29067006 ps
CPU time 0.73 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204236 kb
Host smart-6392b03f-e1b5-4bc9-9e41-7c719173608f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127377745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.127377745
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.3134167690
Short name T242
Test name
Test status
Simulation time 19475221 ps
CPU time 0.86 seconds
Started Feb 26 12:49:10 PM PST 24
Finished Feb 26 12:49:12 PM PST 24
Peak memory 204220 kb
Host smart-c2e2c15c-7652-4a31-bde3-70ab7147f074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134167690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
3134167690
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.491458355
Short name T173
Test name
Test status
Simulation time 50565697 ps
CPU time 0.7 seconds
Started Feb 26 12:49:05 PM PST 24
Finished Feb 26 12:49:06 PM PST 24
Peak memory 204236 kb
Host smart-af3fec5c-e53b-48a3-bd1f-1d49ff10a95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491458355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.491458355
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1407432024
Short name T243
Test name
Test status
Simulation time 13755365 ps
CPU time 0.76 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204232 kb
Host smart-f2e6e6eb-d9de-4f00-bec1-9dc73dfde7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407432024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1407432024
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3666407445
Short name T289
Test name
Test status
Simulation time 20794435 ps
CPU time 0.95 seconds
Started Feb 26 12:49:00 PM PST 24
Finished Feb 26 12:49:01 PM PST 24
Peak memory 204444 kb
Host smart-6d285c39-85fa-4818-91fb-6fc24ef113c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666407445 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3666407445
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.4284275605
Short name T224
Test name
Test status
Simulation time 84526299 ps
CPU time 0.72 seconds
Started Feb 26 12:49:19 PM PST 24
Finished Feb 26 12:49:20 PM PST 24
Peak memory 204216 kb
Host smart-8f561b1e-51ca-41a3-b9fd-cb2573e1dfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284275605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
4284275605
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.393632815
Short name T183
Test name
Test status
Simulation time 8930910 ps
CPU time 0.78 seconds
Started Feb 26 12:49:08 PM PST 24
Finished Feb 26 12:49:09 PM PST 24
Peak memory 204196 kb
Host smart-c64bd3bd-f56f-4ce5-a98e-ab9c822782fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393632815 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.393632815
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1410569786
Short name T249
Test name
Test status
Simulation time 309007899 ps
CPU time 4.69 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 204372 kb
Host smart-42fed52f-8d7b-480f-a7e1-1006b52a585c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410569786 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1410569786
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3863626219
Short name T210
Test name
Test status
Simulation time 339821307 ps
CPU time 8.77 seconds
Started Feb 26 12:48:37 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 204356 kb
Host smart-9c5e40fe-3814-40c4-965b-1ce4e6e0bdfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863626219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3863626219
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.4074491123
Short name T291
Test name
Test status
Simulation time 28943474 ps
CPU time 1.05 seconds
Started Feb 26 12:48:33 PM PST 24
Finished Feb 26 12:48:35 PM PST 24
Peak memory 204460 kb
Host smart-0708f8e0-5e40-4db0-8ee2-fe36a6ce0f61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074491123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.4074491123
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.983148722
Short name T254
Test name
Test status
Simulation time 467770436 ps
CPU time 1.63 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 212624 kb
Host smart-966eb00c-7ac4-4692-807b-6699eea621a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983148722 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.983148722
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.755224103
Short name T253
Test name
Test status
Simulation time 12285548 ps
CPU time 0.77 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 204224 kb
Host smart-d1fb21ec-d745-4f32-96a2-9ea629e67906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755224103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.755224103
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.539317900
Short name T197
Test name
Test status
Simulation time 20618781 ps
CPU time 0.79 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 204292 kb
Host smart-38cf756f-e5b7-473a-a863-c0659097f45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539317900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.539317900
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.565168285
Short name T231
Test name
Test status
Simulation time 15233390 ps
CPU time 1.19 seconds
Started Feb 26 12:48:37 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 204416 kb
Host smart-b8cc685d-0d66-4229-8761-e8b25146ed27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565168285 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_dpe_same_csr_outstanding.565168285
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.3125947691
Short name T207
Test name
Test status
Simulation time 121540579 ps
CPU time 1.77 seconds
Started Feb 26 12:48:38 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 213068 kb
Host smart-20053f42-b7a4-4fcf-9f61-d4f9a3eb6e33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125947691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.3125947691
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.983375306
Short name T205
Test name
Test status
Simulation time 498823629 ps
CPU time 3.82 seconds
Started Feb 26 12:48:38 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 213008 kb
Host smart-2b4b9677-5cab-4782-8b04-3343f3a34406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983375306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.983375306
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3013513894
Short name T42
Test name
Test status
Simulation time 70865093 ps
CPU time 1.7 seconds
Started Feb 26 12:48:37 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 212612 kb
Host smart-3c4023e5-2ec9-4714-a9dd-d3be39e45746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013513894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
013513894
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.1811387892
Short name T251
Test name
Test status
Simulation time 264123239 ps
CPU time 3.94 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 213120 kb
Host smart-e6c6eb21-448f-4f0d-8e70-70ab3594ca05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811387892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.1811387892
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.1357118398
Short name T177
Test name
Test status
Simulation time 42242410 ps
CPU time 0.75 seconds
Started Feb 26 12:49:08 PM PST 24
Finished Feb 26 12:49:09 PM PST 24
Peak memory 204148 kb
Host smart-2436ecae-9382-4ea1-ba3b-565c1a0734fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357118398 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
1357118398
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1748276456
Short name T46
Test name
Test status
Simulation time 38423466 ps
CPU time 0.7 seconds
Started Feb 26 12:49:04 PM PST 24
Finished Feb 26 12:49:05 PM PST 24
Peak memory 204224 kb
Host smart-a3c63620-8cad-44e5-8a53-52d8290f6b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748276456 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1748276456
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.602600249
Short name T287
Test name
Test status
Simulation time 8890824 ps
CPU time 0.74 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204232 kb
Host smart-539f47e3-d648-4829-a63b-b8fd916ad9e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602600249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.602600249
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2030714542
Short name T228
Test name
Test status
Simulation time 48379937 ps
CPU time 0.74 seconds
Started Feb 26 12:49:07 PM PST 24
Finished Feb 26 12:49:08 PM PST 24
Peak memory 204204 kb
Host smart-d0258b2b-2419-49ba-a5f1-cee99d4e76a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030714542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2030714542
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.4146580933
Short name T190
Test name
Test status
Simulation time 10029443 ps
CPU time 0.71 seconds
Started Feb 26 12:49:08 PM PST 24
Finished Feb 26 12:49:08 PM PST 24
Peak memory 204268 kb
Host smart-57e220ce-7af7-47cd-abd9-59edf93edccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146580933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
4146580933
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1354671672
Short name T275
Test name
Test status
Simulation time 47705735 ps
CPU time 0.93 seconds
Started Feb 26 12:49:07 PM PST 24
Finished Feb 26 12:49:08 PM PST 24
Peak memory 204172 kb
Host smart-be7eeb15-7123-46d7-8341-a08c0c746fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354671672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1354671672
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.47538420
Short name T47
Test name
Test status
Simulation time 12813608 ps
CPU time 0.83 seconds
Started Feb 26 12:49:14 PM PST 24
Finished Feb 26 12:49:17 PM PST 24
Peak memory 204252 kb
Host smart-b970197d-6e4f-400b-94cb-147e8434d29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47538420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.47538420
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2756733549
Short name T219
Test name
Test status
Simulation time 33517249 ps
CPU time 0.85 seconds
Started Feb 26 12:49:06 PM PST 24
Finished Feb 26 12:49:07 PM PST 24
Peak memory 204324 kb
Host smart-bbf81647-7247-49f4-b8cd-454e6116ce26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756733549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2756733549
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3242995455
Short name T277
Test name
Test status
Simulation time 16846564 ps
CPU time 0.81 seconds
Started Feb 26 12:49:09 PM PST 24
Finished Feb 26 12:49:11 PM PST 24
Peak memory 204296 kb
Host smart-66e38b75-9243-4aca-b407-7aaaa5ac8f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242995455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
3242995455
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.194569087
Short name T194
Test name
Test status
Simulation time 41833641 ps
CPU time 0.74 seconds
Started Feb 26 12:49:14 PM PST 24
Finished Feb 26 12:49:16 PM PST 24
Peak memory 204272 kb
Host smart-e495a1da-190f-4fc4-ae98-767fcd4f017e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194569087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.194569087
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3567240266
Short name T241
Test name
Test status
Simulation time 40927839 ps
CPU time 1.03 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:37 PM PST 24
Peak memory 212672 kb
Host smart-3a786348-2642-4808-9d4c-499cbefcd654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567240266 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.3567240266
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.2541663454
Short name T174
Test name
Test status
Simulation time 22257312 ps
CPU time 1.34 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204376 kb
Host smart-9af0ebb2-2442-4e69-b5f0-a886deded778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541663454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.2
541663454
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2405948333
Short name T166
Test name
Test status
Simulation time 114187253 ps
CPU time 0.87 seconds
Started Feb 26 12:48:38 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 204196 kb
Host smart-618b663b-e1ca-4014-a4d8-e37c279cf8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405948333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
405948333
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.630563163
Short name T268
Test name
Test status
Simulation time 373573257 ps
CPU time 1.99 seconds
Started Feb 26 12:48:36 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 204488 kb
Host smart-f17cd3d1-2ac0-4fd0-8b30-8f328543fa0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630563163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_dpe_same_csr_outstanding.630563163
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3257918792
Short name T67
Test name
Test status
Simulation time 105311659 ps
CPU time 1.29 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:38 PM PST 24
Peak memory 213080 kb
Host smart-75d6a2e7-e9cb-47c5-95f5-2a11686b29b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257918792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3257918792
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3515086746
Short name T294
Test name
Test status
Simulation time 411242900 ps
CPU time 5.14 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 212960 kb
Host smart-cc99862a-9854-4dbb-8358-1f22a692020f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515086746 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3515086746
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2765416121
Short name T274
Test name
Test status
Simulation time 35335031 ps
CPU time 2.13 seconds
Started Feb 26 12:48:38 PM PST 24
Finished Feb 26 12:48:40 PM PST 24
Peak memory 212792 kb
Host smart-fc2486d2-3ecf-4cbd-a48e-33ed2d5f1752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765416121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
765416121
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.397537636
Short name T235
Test name
Test status
Simulation time 24722761 ps
CPU time 1.11 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:49 PM PST 24
Peak memory 204684 kb
Host smart-ac14cc4f-5763-4741-bfa4-c17f71a7b135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397537636 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.397537636
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.979663296
Short name T88
Test name
Test status
Simulation time 47635671 ps
CPU time 1 seconds
Started Feb 26 12:48:45 PM PST 24
Finished Feb 26 12:48:47 PM PST 24
Peak memory 204388 kb
Host smart-b0416679-6191-40bf-9c6a-861284233cf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979663296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.979663296
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1888947342
Short name T258
Test name
Test status
Simulation time 21030039 ps
CPU time 0.74 seconds
Started Feb 26 12:48:56 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204236 kb
Host smart-db254c99-4660-4e13-819f-5aed758e68a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888947342 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
888947342
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2774710563
Short name T308
Test name
Test status
Simulation time 64440318 ps
CPU time 1.36 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 204392 kb
Host smart-5716f848-2da1-4b71-b9e7-fdd863fe45cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774710563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.2774710563
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.839092868
Short name T212
Test name
Test status
Simulation time 1008890850 ps
CPU time 3.45 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 212920 kb
Host smart-42cb60b9-757f-4bbb-be18-791e942182fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839092868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymg
r_dpe_shadow_reg_errors.839092868
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3575488187
Short name T39
Test name
Test status
Simulation time 124550671 ps
CPU time 5.86 seconds
Started Feb 26 12:48:38 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 213056 kb
Host smart-c0e1316d-9bda-473a-a1f0-0671933aa385
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575488187 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3575488187
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.1037217502
Short name T206
Test name
Test status
Simulation time 109617544 ps
CPU time 2.31 seconds
Started Feb 26 12:48:35 PM PST 24
Finished Feb 26 12:48:39 PM PST 24
Peak memory 212704 kb
Host smart-509a76f8-bc29-4e58-b9fd-ae4d7cf14bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037217502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.1
037217502
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4116937755
Short name T55
Test name
Test status
Simulation time 121509719 ps
CPU time 4.57 seconds
Started Feb 26 12:48:37 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 212624 kb
Host smart-91c28f84-ceab-49c1-a2e1-4ce1fce50cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116937755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.4116937755
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.3899414971
Short name T214
Test name
Test status
Simulation time 24660992 ps
CPU time 1.01 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:41 PM PST 24
Peak memory 204344 kb
Host smart-9e7be1c4-46cc-4ff8-b947-dc88c4ba24e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899414971 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.3899414971
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2519315385
Short name T90
Test name
Test status
Simulation time 59848442 ps
CPU time 1.11 seconds
Started Feb 26 12:48:42 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 204304 kb
Host smart-11e42d99-38ba-448b-a0ff-fc7d7ed1b8c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519315385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
519315385
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.3418928132
Short name T117
Test name
Test status
Simulation time 13963597 ps
CPU time 0.78 seconds
Started Feb 26 12:48:42 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 204208 kb
Host smart-29c2cce6-5d83-4c31-b5e7-ef8babe1560a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418928132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.3
418928132
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2025636253
Short name T86
Test name
Test status
Simulation time 154264899 ps
CPU time 1.93 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204312 kb
Host smart-c30655d6-a670-4b23-a5e5-f93df509815d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025636253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2025636253
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.4191887294
Short name T181
Test name
Test status
Simulation time 32399390 ps
CPU time 1.49 seconds
Started Feb 26 12:48:44 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 213052 kb
Host smart-d90ce286-d089-4b4b-a07c-6cc2271ab598
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191887294 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.4191887294
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.896047651
Short name T187
Test name
Test status
Simulation time 443432713 ps
CPU time 8.34 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:56 PM PST 24
Peak memory 213320 kb
Host smart-10b7e52f-48a1-4d19-8bf3-d6e76028dd32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896047651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.896047651
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3645533088
Short name T38
Test name
Test status
Simulation time 54039160 ps
CPU time 1.6 seconds
Started Feb 26 12:48:39 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 212648 kb
Host smart-828302c7-cac6-4d55-be03-f6d7aba63c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645533088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3
645533088
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.2001901649
Short name T23
Test name
Test status
Simulation time 16744118 ps
CPU time 1.14 seconds
Started Feb 26 12:48:44 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 204488 kb
Host smart-9a144be3-715f-4a73-b406-ce57c41217f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001901649 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.2001901649
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.4208574637
Short name T257
Test name
Test status
Simulation time 15006976 ps
CPU time 0.98 seconds
Started Feb 26 12:48:41 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204244 kb
Host smart-f1ca3c12-8fa8-4ca6-bf87-6b3d48184fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208574637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.4
208574637
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.357289056
Short name T239
Test name
Test status
Simulation time 15152000 ps
CPU time 0.73 seconds
Started Feb 26 12:48:54 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 204256 kb
Host smart-c36ff0ca-f448-4bd7-8c72-6ec9af8d255b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357289056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.357289056
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.4027743738
Short name T208
Test name
Test status
Simulation time 34503934 ps
CPU time 1.8 seconds
Started Feb 26 12:48:47 PM PST 24
Finished Feb 26 12:48:49 PM PST 24
Peak memory 204484 kb
Host smart-bbe0c6c9-9f33-49f8-b434-ca6aaea40378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027743738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.4027743738
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.4276331676
Short name T195
Test name
Test status
Simulation time 459676133 ps
CPU time 2.29 seconds
Started Feb 26 12:48:48 PM PST 24
Finished Feb 26 12:48:50 PM PST 24
Peak memory 213328 kb
Host smart-d2391d1c-bc0e-476f-8fe1-34e1a3568d03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276331676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.4276331676
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3269213126
Short name T220
Test name
Test status
Simulation time 47414697 ps
CPU time 3.04 seconds
Started Feb 26 12:48:45 PM PST 24
Finished Feb 26 12:48:49 PM PST 24
Peak memory 212956 kb
Host smart-e44986a0-dca6-4924-8fa4-bd2a49cded13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269213126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3269213126
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.1062997475
Short name T297
Test name
Test status
Simulation time 1277839917 ps
CPU time 2.02 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 212676 kb
Host smart-20441adf-eca6-4e04-a659-9dfccd90706d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062997475 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.1
062997475
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.4240947148
Short name T62
Test name
Test status
Simulation time 242883345 ps
CPU time 3.29 seconds
Started Feb 26 12:48:41 PM PST 24
Finished Feb 26 12:48:45 PM PST 24
Peak memory 213736 kb
Host smart-1aba7f0d-97de-48d8-9e01-6a1b6319f6ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240947148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.4240947148
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2044201234
Short name T200
Test name
Test status
Simulation time 51175389 ps
CPU time 1.66 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 212552 kb
Host smart-81b454c8-02d2-4725-b269-5e3da7859025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044201234 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2044201234
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.486869142
Short name T216
Test name
Test status
Simulation time 35067668 ps
CPU time 1.07 seconds
Started Feb 26 12:48:56 PM PST 24
Finished Feb 26 12:48:57 PM PST 24
Peak memory 204204 kb
Host smart-1eff5ae4-ca26-4fd1-9540-820a8db7f09a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486869142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.486869142
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.539177260
Short name T45
Test name
Test status
Simulation time 16880724 ps
CPU time 0.72 seconds
Started Feb 26 12:48:53 PM PST 24
Finished Feb 26 12:48:55 PM PST 24
Peak memory 204216 kb
Host smart-2b20c567-5863-4be8-9d98-fb08b76a81b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539177260 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.539177260
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2475563549
Short name T91
Test name
Test status
Simulation time 271273311 ps
CPU time 1.98 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:42 PM PST 24
Peak memory 204364 kb
Host smart-221cc494-7dd5-46b5-b1c5-e829bb264f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475563549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2475563549
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3772688741
Short name T66
Test name
Test status
Simulation time 298194498 ps
CPU time 2.09 seconds
Started Feb 26 12:48:40 PM PST 24
Finished Feb 26 12:48:43 PM PST 24
Peak memory 212900 kb
Host smart-c33d0c02-d65a-4626-9738-e080cd2c0d4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772688741 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.3772688741
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3149348875
Short name T307
Test name
Test status
Simulation time 721520476 ps
CPU time 3.62 seconds
Started Feb 26 12:48:41 PM PST 24
Finished Feb 26 12:48:45 PM PST 24
Peak memory 213000 kb
Host smart-939d410d-27ee-49f3-a355-e1a6e4676c33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149348875 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.3149348875
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.112964478
Short name T290
Test name
Test status
Simulation time 105497439 ps
CPU time 3.8 seconds
Started Feb 26 12:48:42 PM PST 24
Finished Feb 26 12:48:46 PM PST 24
Peak memory 212872 kb
Host smart-55b715db-5904-4b88-8bc4-6e11c22cc7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112964478 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.112964478
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.2223387873
Short name T64
Test name
Test status
Simulation time 226785676 ps
CPU time 3.13 seconds
Started Feb 26 12:48:41 PM PST 24
Finished Feb 26 12:48:44 PM PST 24
Peak memory 213644 kb
Host smart-423552bd-8f42-4d23-8639-d6e5759f1c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223387873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.2223387873
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2659381354
Short name T17
Test name
Test status
Simulation time 160060799 ps
CPU time 0.94 seconds
Started Feb 26 01:06:35 PM PST 24
Finished Feb 26 01:06:36 PM PST 24
Peak memory 205348 kb
Host smart-15b53676-9ddb-4eb0-97f7-9d2df6665720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659381354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
659381354
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2984060077
Short name T26
Test name
Test status
Simulation time 10274369 ps
CPU time 0.75 seconds
Started Feb 26 01:06:36 PM PST 24
Finished Feb 26 01:06:37 PM PST 24
Peak memory 205312 kb
Host smart-3ef0f2a9-194f-40bc-a116-5d1c8a3fd76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984060077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
984060077
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2264723736
Short name T25
Test name
Test status
Simulation time 3036430976 ps
CPU time 14.78 seconds
Started Feb 26 01:06:35 PM PST 24
Finished Feb 26 01:06:50 PM PST 24
Peak memory 231408 kb
Host smart-60a8858e-d9af-4b94-a7fa-c63f690d1727
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264723736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2264723736
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2471572805
Short name T6
Test name
Test status
Simulation time 4888783236 ps
CPU time 76.91 seconds
Started Feb 26 01:06:40 PM PST 24
Finished Feb 26 01:07:57 PM PST 24
Peak memory 207944 kb
Host smart-1ee6cdc3-e617-4549-b6cc-08b323122b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471572805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2471572805
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.1226528413
Short name T129
Test name
Test status
Simulation time 12264500 ps
CPU time 0.74 seconds
Started Feb 26 01:06:49 PM PST 24
Finished Feb 26 01:06:51 PM PST 24
Peak memory 205264 kb
Host smart-f51bb64d-db4d-474e-aaa2-2c4101179e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226528413 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
1226528413
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.337577886
Short name T98
Test name
Test status
Simulation time 1069678194 ps
CPU time 9.79 seconds
Started Feb 26 01:06:45 PM PST 24
Finished Feb 26 01:06:55 PM PST 24
Peak memory 208152 kb
Host smart-70f9ea3a-590b-4f13-bb84-b5e7887ed4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337577886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.337577886
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.488748510
Short name T155
Test name
Test status
Simulation time 83513367 ps
CPU time 0.75 seconds
Started Feb 26 01:06:52 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205324 kb
Host smart-128b12e1-afaf-42ce-9d54-c1ae25281004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488748510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.488748510
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.4013926233
Short name T29
Test name
Test status
Simulation time 15587206 ps
CPU time 0.78 seconds
Started Feb 26 01:06:55 PM PST 24
Finished Feb 26 01:06:56 PM PST 24
Peak memory 205324 kb
Host smart-17f2d86a-69ac-4868-9357-f20f8ff5efe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013926233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
4013926233
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.257008006
Short name T138
Test name
Test status
Simulation time 25421165 ps
CPU time 0.76 seconds
Started Feb 26 01:06:52 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205324 kb
Host smart-71318a21-ab40-4a23-b31c-a98d66ad3b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257008006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.257008006
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.144278925
Short name T157
Test name
Test status
Simulation time 1058336160 ps
CPU time 13.8 seconds
Started Feb 26 01:06:50 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 206124 kb
Host smart-ec0e676b-8ee8-4941-a72b-29a86bdfbf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144278925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.144278925
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.3323618116
Short name T153
Test name
Test status
Simulation time 11029118 ps
CPU time 0.75 seconds
Started Feb 26 01:06:51 PM PST 24
Finished Feb 26 01:06:52 PM PST 24
Peak memory 205296 kb
Host smart-f7a8a673-4054-4fa2-85d5-084e6d6698de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323618116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
3323618116
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.294923729
Short name T120
Test name
Test status
Simulation time 29017166 ps
CPU time 0.98 seconds
Started Feb 26 01:06:53 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205468 kb
Host smart-0f8b6351-7773-44d1-84f3-29408f0bd3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294923729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.294923729
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.439784134
Short name T133
Test name
Test status
Simulation time 190531483 ps
CPU time 0.84 seconds
Started Feb 26 01:06:55 PM PST 24
Finished Feb 26 01:06:56 PM PST 24
Peak memory 205252 kb
Host smart-934010f7-3db0-4cf2-bfe3-3932f36ff43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439784134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.439784134
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2645643572
Short name T149
Test name
Test status
Simulation time 1994988790 ps
CPU time 17.67 seconds
Started Feb 26 01:06:51 PM PST 24
Finished Feb 26 01:07:11 PM PST 24
Peak memory 206520 kb
Host smart-9204530b-ca69-491d-a074-7874b8a9e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645643572 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2645643572
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2386882903
Short name T146
Test name
Test status
Simulation time 26003494 ps
CPU time 0.8 seconds
Started Feb 26 01:06:52 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205236 kb
Host smart-767a6dc8-7757-4844-af0b-a735106b0c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386882903 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2386882903
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.1509216760
Short name T77
Test name
Test status
Simulation time 23548078323 ps
CPU time 197.29 seconds
Started Feb 26 01:06:53 PM PST 24
Finished Feb 26 01:10:11 PM PST 24
Peak memory 224460 kb
Host smart-fbdc3e81-81a2-4147-8784-7b0f5568c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509216760 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.1509216760
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.1480776737
Short name T137
Test name
Test status
Simulation time 88608357 ps
CPU time 0.76 seconds
Started Feb 26 01:06:53 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205356 kb
Host smart-16910f29-bbd2-42a1-9060-01996c8f33bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480776737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
1480776737
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.3838859341
Short name T148
Test name
Test status
Simulation time 20991646 ps
CPU time 0.88 seconds
Started Feb 26 01:06:51 PM PST 24
Finished Feb 26 01:06:54 PM PST 24
Peak memory 205296 kb
Host smart-d0565c52-b414-479a-9349-ca07f2a68340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838859341 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
3838859341
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.659169060
Short name T15
Test name
Test status
Simulation time 7761123248 ps
CPU time 70.54 seconds
Started Feb 26 01:06:51 PM PST 24
Finished Feb 26 01:08:02 PM PST 24
Peak memory 207568 kb
Host smart-9d56ae9e-2bef-40b2-9300-0f410575d721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659169060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.659169060
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1716048778
Short name T134
Test name
Test status
Simulation time 38460403 ps
CPU time 0.76 seconds
Started Feb 26 01:06:41 PM PST 24
Finished Feb 26 01:06:42 PM PST 24
Peak memory 205348 kb
Host smart-e9e6702c-d8ba-457e-81f2-f038f20cec7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716048778 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
716048778
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.1206610160
Short name T7
Test name
Test status
Simulation time 1007009691 ps
CPU time 22.51 seconds
Started Feb 26 01:06:39 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 237324 kb
Host smart-83b7ce2f-1c15-49e2-8d3a-2bb14f179a93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206610160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.1206610160
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.3229400353
Short name T156
Test name
Test status
Simulation time 4929587510 ps
CPU time 17.51 seconds
Started Feb 26 01:06:41 PM PST 24
Finished Feb 26 01:06:59 PM PST 24
Peak memory 208152 kb
Host smart-3e42bd14-b271-4ba0-8020-6babc8c44366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229400353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.3229400353
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3137315996
Short name T159
Test name
Test status
Simulation time 47411093 ps
CPU time 0.76 seconds
Started Feb 26 01:06:54 PM PST 24
Finished Feb 26 01:06:55 PM PST 24
Peak memory 205536 kb
Host smart-5f124d8a-8335-487b-ab4a-ace360a9a3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137315996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3137315996
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.3625355306
Short name T75
Test name
Test status
Simulation time 54292163 ps
CPU time 0.99 seconds
Started Feb 26 01:06:57 PM PST 24
Finished Feb 26 01:06:58 PM PST 24
Peak memory 205400 kb
Host smart-c10d0571-1556-488d-ab0f-b627d2f2c272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625355306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
3625355306
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.2545655353
Short name T99
Test name
Test status
Simulation time 912750281 ps
CPU time 18.4 seconds
Started Feb 26 01:06:50 PM PST 24
Finished Feb 26 01:07:08 PM PST 24
Peak memory 206160 kb
Host smart-143ed43f-ae43-42fd-a02a-e8b29ee42dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545655353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.2545655353
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3159885147
Short name T124
Test name
Test status
Simulation time 19329395 ps
CPU time 0.99 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 205440 kb
Host smart-ebb98ace-f7fc-4d5d-95dc-85c54f56051b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159885147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3159885147
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3295617560
Short name T154
Test name
Test status
Simulation time 1483407837 ps
CPU time 17.09 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:19 PM PST 24
Peak memory 207876 kb
Host smart-d0bebf4c-6546-4027-8441-7807cdc48216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295617560 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3295617560
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.2570256790
Short name T130
Test name
Test status
Simulation time 21711012 ps
CPU time 0.74 seconds
Started Feb 26 01:06:59 PM PST 24
Finished Feb 26 01:07:00 PM PST 24
Peak memory 205228 kb
Host smart-b77fceed-c995-4342-ab9e-c702138720cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570256790 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
2570256790
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3590587881
Short name T34
Test name
Test status
Simulation time 1687470445 ps
CPU time 30.44 seconds
Started Feb 26 01:07:05 PM PST 24
Finished Feb 26 01:07:39 PM PST 24
Peak memory 207080 kb
Host smart-0e191096-0129-424f-bcff-c5f7c179c760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590587881 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3590587881
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.3977902964
Short name T1
Test name
Test status
Simulation time 10553138 ps
CPU time 0.72 seconds
Started Feb 26 01:06:54 PM PST 24
Finished Feb 26 01:06:55 PM PST 24
Peak memory 205288 kb
Host smart-de56a6d8-dc71-40ee-83bf-4ba106032057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977902964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
3977902964
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.4077629286
Short name T145
Test name
Test status
Simulation time 75811040 ps
CPU time 0.79 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:03 PM PST 24
Peak memory 205232 kb
Host smart-660c1a58-c096-493f-8e93-747d2cd4d00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077629286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
4077629286
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.4008874884
Short name T10
Test name
Test status
Simulation time 1485397505 ps
CPU time 14.84 seconds
Started Feb 26 01:07:05 PM PST 24
Finished Feb 26 01:07:24 PM PST 24
Peak memory 207632 kb
Host smart-37361b92-4e3a-41d6-ac83-6d002dab4504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008874884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.4008874884
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.4062429698
Short name T123
Test name
Test status
Simulation time 27830818 ps
CPU time 0.7 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 204960 kb
Host smart-308b4fe3-157b-4e71-9f4a-bb35238bcd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062429698 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
4062429698
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.598049233
Short name T162
Test name
Test status
Simulation time 3916147973 ps
CPU time 34.12 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:43 PM PST 24
Peak memory 207728 kb
Host smart-64ddc9ec-2cf7-4a5c-89cf-b5296fe63c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598049233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.598049233
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.3150964060
Short name T125
Test name
Test status
Simulation time 21230898 ps
CPU time 0.72 seconds
Started Feb 26 01:07:04 PM PST 24
Finished Feb 26 01:07:06 PM PST 24
Peak memory 205316 kb
Host smart-d4cd42fe-d6e5-4bf0-b143-d4cef196bcfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150964060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
3150964060
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.4259994982
Short name T127
Test name
Test status
Simulation time 65311229 ps
CPU time 0.87 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 205324 kb
Host smart-148d3914-3f6a-44d2-a3aa-9a886fa6638f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259994982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
4259994982
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.1700786866
Short name T18
Test name
Test status
Simulation time 13751979 ps
CPU time 0.9 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 205284 kb
Host smart-6c592ed6-9543-4b09-9430-067441c8496d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700786866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
1700786866
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.338660105
Short name T140
Test name
Test status
Simulation time 986938606 ps
CPU time 14.54 seconds
Started Feb 26 01:06:58 PM PST 24
Finished Feb 26 01:07:13 PM PST 24
Peak memory 206340 kb
Host smart-2cf32d04-140f-460a-9b94-79c831e335fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338660105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.338660105
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1157728507
Short name T160
Test name
Test status
Simulation time 35270923 ps
CPU time 0.71 seconds
Started Feb 26 01:06:38 PM PST 24
Finished Feb 26 01:06:39 PM PST 24
Peak memory 205204 kb
Host smart-605fb8b8-a25a-4115-a61e-ac47faf55a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157728507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
157728507
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2358317306
Short name T14
Test name
Test status
Simulation time 889501882 ps
CPU time 16.59 seconds
Started Feb 26 01:06:36 PM PST 24
Finished Feb 26 01:06:53 PM PST 24
Peak memory 207820 kb
Host smart-50ddf6b3-397b-4119-8067-b47dbd06d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358317306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2358317306
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.1914455296
Short name T74
Test name
Test status
Simulation time 81534381 ps
CPU time 0.8 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 205308 kb
Host smart-0a5607e6-6b42-4d34-99da-2e0ba4929003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914455296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
1914455296
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3767913936
Short name T97
Test name
Test status
Simulation time 1845461903 ps
CPU time 17.95 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:19 PM PST 24
Peak memory 207380 kb
Host smart-beebe8e0-109a-41cc-813d-a37b8879d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767913936 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3767913936
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.1987787035
Short name T142
Test name
Test status
Simulation time 22508613 ps
CPU time 0.74 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:01 PM PST 24
Peak memory 205268 kb
Host smart-ac5b9032-5e86-4c7f-9479-be19ac6b8ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987787035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
1987787035
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.4129164780
Short name T27
Test name
Test status
Simulation time 8088479760 ps
CPU time 27.96 seconds
Started Feb 26 01:06:59 PM PST 24
Finished Feb 26 01:07:27 PM PST 24
Peak memory 207220 kb
Host smart-be3f8fa1-6dfa-4277-ac7d-4d12ad1ee8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129164780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.4129164780
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.1196360490
Short name T161
Test name
Test status
Simulation time 14323916 ps
CPU time 0.81 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:03 PM PST 24
Peak memory 205380 kb
Host smart-9335992c-b9ea-4d4e-844f-ee829f4a0f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196360490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
1196360490
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.520340251
Short name T115
Test name
Test status
Simulation time 2036797415 ps
CPU time 20.28 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:23 PM PST 24
Peak memory 206104 kb
Host smart-ce3da7ed-17ad-47ef-8ac7-0dfa648d0e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520340251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.520340251
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3537483409
Short name T143
Test name
Test status
Simulation time 41969140 ps
CPU time 0.78 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 205252 kb
Host smart-25679853-de9b-4fa1-b520-876fdf8cae56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537483409 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3537483409
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.1158176384
Short name T100
Test name
Test status
Simulation time 406323353 ps
CPU time 12.12 seconds
Started Feb 26 01:07:05 PM PST 24
Finished Feb 26 01:07:21 PM PST 24
Peak memory 206036 kb
Host smart-5c5fab92-d1e8-42ee-aa50-0a8d141654da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158176384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.1158176384
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.3950469225
Short name T3
Test name
Test status
Simulation time 11606571 ps
CPU time 0.75 seconds
Started Feb 26 01:07:05 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 205028 kb
Host smart-0a0cdeaf-723c-4512-a2ff-87489b5fd0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950469225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
3950469225
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3420235734
Short name T83
Test name
Test status
Simulation time 2067326284 ps
CPU time 19.15 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:23 PM PST 24
Peak memory 208132 kb
Host smart-24d0b3c9-beab-46d0-8d8f-b8ca247cb2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420235734 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3420235734
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.1346668851
Short name T144
Test name
Test status
Simulation time 44092659 ps
CPU time 0.85 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 205364 kb
Host smart-da9c48c2-023f-40b7-ae91-2b38e1638be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346668851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
1346668851
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.3676549590
Short name T132
Test name
Test status
Simulation time 24879749 ps
CPU time 1.04 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 205408 kb
Host smart-f202b046-13c6-4468-9bf2-8bf3ee816a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676549590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
3676549590
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.2622980695
Short name T150
Test name
Test status
Simulation time 1171470125 ps
CPU time 14.03 seconds
Started Feb 26 01:06:56 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 207780 kb
Host smart-6072b1d6-2af7-42d3-9297-81266925e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622980695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.2622980695
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.3430470856
Short name T122
Test name
Test status
Simulation time 39037137 ps
CPU time 0.74 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 205260 kb
Host smart-a97bbb1d-8feb-4459-811c-774b7429815c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430470856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
3430470856
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.3154605780
Short name T96
Test name
Test status
Simulation time 683749751 ps
CPU time 14.79 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:16 PM PST 24
Peak memory 206248 kb
Host smart-b896a4d0-4a2a-42fa-b3b9-920989d1e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154605780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.3154605780
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.2229893060
Short name T163
Test name
Test status
Simulation time 73807020 ps
CPU time 0.85 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:03 PM PST 24
Peak memory 205328 kb
Host smart-ac8e02b7-d652-4c15-90af-fbded4fb9a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229893060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
2229893060
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.1445541561
Short name T32
Test name
Test status
Simulation time 1277792702 ps
CPU time 22.2 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:25 PM PST 24
Peak memory 208200 kb
Host smart-aad8bd4c-7733-40ec-9bb2-4e1d53f315d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445541561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.1445541561
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.3927323388
Short name T121
Test name
Test status
Simulation time 16724688 ps
CPU time 0.77 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 205340 kb
Host smart-5f1a119a-7cbe-49f6-bb92-64a5e519e153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927323388 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
3927323388
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1553995008
Short name T131
Test name
Test status
Simulation time 26854103 ps
CPU time 0.71 seconds
Started Feb 26 01:06:45 PM PST 24
Finished Feb 26 01:06:46 PM PST 24
Peak memory 205108 kb
Host smart-3a38377a-ce7b-4cfb-a7e7-178b6119af33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553995008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
553995008
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3901898590
Short name T9
Test name
Test status
Simulation time 561504626 ps
CPU time 12.23 seconds
Started Feb 26 01:06:43 PM PST 24
Finished Feb 26 01:06:56 PM PST 24
Peak memory 228312 kb
Host smart-b1e58cec-0299-434f-941d-492d0ff005f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901898590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3901898590
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.773799447
Short name T76
Test name
Test status
Simulation time 30526943336 ps
CPU time 90.75 seconds
Started Feb 26 01:06:35 PM PST 24
Finished Feb 26 01:08:06 PM PST 24
Peak memory 207636 kb
Host smart-93300bd7-03a7-4245-b26b-7467ca1ae4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773799447 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.773799447
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.3097167687
Short name T152
Test name
Test status
Simulation time 44236311 ps
CPU time 0.83 seconds
Started Feb 26 01:07:01 PM PST 24
Finished Feb 26 01:07:02 PM PST 24
Peak memory 205348 kb
Host smart-6a4ababf-05da-4b84-bbde-49d41b379d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097167687 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
3097167687
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.288872838
Short name T126
Test name
Test status
Simulation time 69721329 ps
CPU time 1.25 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 205444 kb
Host smart-46225812-3cab-4a4d-9e49-d1bec0bc5b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288872838 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.288872838
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1311464510
Short name T12
Test name
Test status
Simulation time 2132762298 ps
CPU time 21.07 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:24 PM PST 24
Peak memory 208112 kb
Host smart-c912616a-6ba6-4b7e-9d3b-c920467317fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311464510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1311464510
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.105375935
Short name T128
Test name
Test status
Simulation time 62939151 ps
CPU time 0.79 seconds
Started Feb 26 01:07:04 PM PST 24
Finished Feb 26 01:07:06 PM PST 24
Peak memory 205316 kb
Host smart-f71d14a7-9234-417b-b420-d0e226af84f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105375935 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.105375935
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1023609983
Short name T73
Test name
Test status
Simulation time 1190468269 ps
CPU time 20.76 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:24 PM PST 24
Peak memory 207676 kb
Host smart-1002e7d3-5e95-47c8-9636-d2504a2c08f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023609983 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1023609983
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.1301142339
Short name T151
Test name
Test status
Simulation time 15390653 ps
CPU time 0.93 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:05 PM PST 24
Peak memory 205400 kb
Host smart-5f12b924-7300-44e9-b1d4-1c54067e478e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301142339 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
1301142339
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.1957361645
Short name T113
Test name
Test status
Simulation time 3302506033 ps
CPU time 49.24 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:54 PM PST 24
Peak memory 218608 kb
Host smart-2e79b896-8900-41ef-86fd-2f1e09deedb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957361645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.1957361645
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.3225370541
Short name T93
Test name
Test status
Simulation time 42826152 ps
CPU time 0.78 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 205328 kb
Host smart-db7669cf-15fc-4989-85b7-571e3362979d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225370541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
3225370541
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.3010443699
Short name T116
Test name
Test status
Simulation time 5042031099 ps
CPU time 19.24 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:22 PM PST 24
Peak memory 207772 kb
Host smart-5e070898-b80e-4e94-a460-712f693177d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010443699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.3010443699
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3861629700
Short name T158
Test name
Test status
Simulation time 27586099 ps
CPU time 0.86 seconds
Started Feb 26 01:07:04 PM PST 24
Finished Feb 26 01:07:06 PM PST 24
Peak memory 205340 kb
Host smart-4b5dde56-874e-4ce1-9727-042b64f7eeca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861629700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3861629700
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1898448347
Short name T139
Test name
Test status
Simulation time 810853111 ps
CPU time 17.17 seconds
Started Feb 26 01:07:06 PM PST 24
Finished Feb 26 01:07:26 PM PST 24
Peak memory 207380 kb
Host smart-ffe5c418-cef1-4c41-89e9-2807bdd22cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898448347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1898448347
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3734946237
Short name T19
Test name
Test status
Simulation time 51191882 ps
CPU time 0.91 seconds
Started Feb 26 01:07:13 PM PST 24
Finished Feb 26 01:07:14 PM PST 24
Peak memory 205380 kb
Host smart-9d1f66b6-af8b-4702-b3f9-5375a8594819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734946237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3734946237
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1982102752
Short name T79
Test name
Test status
Simulation time 2938675284 ps
CPU time 12.29 seconds
Started Feb 26 01:07:02 PM PST 24
Finished Feb 26 01:07:15 PM PST 24
Peak memory 208232 kb
Host smart-b3374e5c-90fd-45cf-a6ec-4337e8099f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982102752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1982102752
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.2434069978
Short name T135
Test name
Test status
Simulation time 12495119 ps
CPU time 0.93 seconds
Started Feb 26 01:07:00 PM PST 24
Finished Feb 26 01:07:01 PM PST 24
Peak memory 205296 kb
Host smart-5d080430-6c9b-43d8-bebe-64b26db0cf09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434069978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
2434069978
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3741538130
Short name T11
Test name
Test status
Simulation time 215427653 ps
CPU time 11.07 seconds
Started Feb 26 01:07:14 PM PST 24
Finished Feb 26 01:07:25 PM PST 24
Peak memory 208016 kb
Host smart-38f64f94-d00c-461f-a7f9-8b5fe145face
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741538130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3741538130
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2569738746
Short name T95
Test name
Test status
Simulation time 15393950 ps
CPU time 0.93 seconds
Started Feb 26 01:07:09 PM PST 24
Finished Feb 26 01:07:10 PM PST 24
Peak memory 205372 kb
Host smart-d7c7b7da-b693-4562-b1ab-8f51113bf4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569738746 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2569738746
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.681525358
Short name T94
Test name
Test status
Simulation time 55388251 ps
CPU time 0.74 seconds
Started Feb 26 01:07:03 PM PST 24
Finished Feb 26 01:07:04 PM PST 24
Peak memory 205364 kb
Host smart-23616c16-0462-43d9-9c38-9e52381d07a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681525358 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.681525358
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1959131328
Short name T141
Test name
Test status
Simulation time 15405880 ps
CPU time 0.95 seconds
Started Feb 26 01:06:49 PM PST 24
Finished Feb 26 01:06:51 PM PST 24
Peak memory 205420 kb
Host smart-51bde7af-990a-4d70-9426-35ad6001cfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959131328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
959131328
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.4259270081
Short name T28
Test name
Test status
Simulation time 6784963290 ps
CPU time 19.66 seconds
Started Feb 26 01:06:49 PM PST 24
Finished Feb 26 01:07:09 PM PST 24
Peak memory 208240 kb
Host smart-02e6eb7a-8d1d-40ff-a56c-b910b035039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259270081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.4259270081
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.4101477936
Short name T147
Test name
Test status
Simulation time 15934376 ps
CPU time 0.95 seconds
Started Feb 26 01:06:43 PM PST 24
Finished Feb 26 01:06:45 PM PST 24
Peak memory 205468 kb
Host smart-042de46f-53d9-4609-99dd-b3c3615dc425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101477936 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.4
101477936
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.554981804
Short name T112
Test name
Test status
Simulation time 9726836754 ps
CPU time 31.48 seconds
Started Feb 26 01:06:45 PM PST 24
Finished Feb 26 01:07:17 PM PST 24
Peak memory 207752 kb
Host smart-150119d5-edfa-4365-93f2-d9d353910642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554981804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.554981804
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.1287211460
Short name T2
Test name
Test status
Simulation time 11724374 ps
CPU time 0.87 seconds
Started Feb 26 01:06:43 PM PST 24
Finished Feb 26 01:06:45 PM PST 24
Peak memory 205300 kb
Host smart-4361ccc3-46fc-46a6-946f-96a500f82a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287211460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.1
287211460
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1818618900
Short name T30
Test name
Test status
Simulation time 47092190 ps
CPU time 0.96 seconds
Started Feb 26 01:06:45 PM PST 24
Finished Feb 26 01:06:46 PM PST 24
Peak memory 205360 kb
Host smart-c2a7f88e-2f5e-43e9-9284-c90c566a33a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818618900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
818618900
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.1429283925
Short name T136
Test name
Test status
Simulation time 55689650402 ps
CPU time 237.77 seconds
Started Feb 26 01:06:47 PM PST 24
Finished Feb 26 01:10:45 PM PST 24
Peak memory 208484 kb
Host smart-617dc9a4-2fdb-4930-84a3-d4dec1848e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429283925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.1429283925
Directory /workspace/9.keymgr_dpe_smoke/latest
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