Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.29 97.70 90.62 57.52 76.92 94.94 98.34 17.96


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.238357761 Mar 09 01:32:56 PM PST 24 Mar 09 01:32:58 PM PST 24 62713081 ps
T258 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2556438434 Mar 09 01:33:21 PM PST 24 Mar 09 01:33:23 PM PST 24 223182889 ps
T259 /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.371094962 Mar 09 01:33:39 PM PST 24 Mar 09 01:33:40 PM PST 24 12659538 ps
T260 /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.2067166863 Mar 09 01:33:39 PM PST 24 Mar 09 01:33:40 PM PST 24 18605617 ps
T261 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2835947780 Mar 09 01:33:00 PM PST 24 Mar 09 01:33:10 PM PST 24 281674240 ps
T49 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2177050840 Mar 09 01:33:25 PM PST 24 Mar 09 01:33:32 PM PST 24 1476516957 ps
T47 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1486758732 Mar 09 01:33:32 PM PST 24 Mar 09 01:33:37 PM PST 24 114391375 ps
T262 /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.4083469426 Mar 09 01:33:25 PM PST 24 Mar 09 01:33:26 PM PST 24 39956855 ps
T263 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3907567142 Mar 09 01:33:11 PM PST 24 Mar 09 01:33:16 PM PST 24 485471587 ps
T264 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.4248192411 Mar 09 01:33:10 PM PST 24 Mar 09 01:33:13 PM PST 24 156012351 ps
T265 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.426332641 Mar 09 01:33:21 PM PST 24 Mar 09 01:33:23 PM PST 24 307927557 ps
T266 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3618966856 Mar 09 01:32:54 PM PST 24 Mar 09 01:32:55 PM PST 24 251098412 ps
T267 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1501248404 Mar 09 01:33:21 PM PST 24 Mar 09 01:33:25 PM PST 24 240840831 ps
T268 /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3363190977 Mar 09 01:33:24 PM PST 24 Mar 09 01:33:25 PM PST 24 160109323 ps
T269 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2239531835 Mar 09 01:33:08 PM PST 24 Mar 09 01:33:13 PM PST 24 483443763 ps
T270 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1707090850 Mar 09 01:33:31 PM PST 24 Mar 09 01:33:36 PM PST 24 201665265 ps
T271 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1140754945 Mar 09 01:33:38 PM PST 24 Mar 09 01:33:42 PM PST 24 356201026 ps
T40 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3378867399 Mar 09 01:33:16 PM PST 24 Mar 09 01:33:19 PM PST 24 76935665 ps
T272 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.31475763 Mar 09 01:33:48 PM PST 24 Mar 09 01:33:49 PM PST 24 25103096 ps
T273 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2823915174 Mar 09 01:33:33 PM PST 24 Mar 09 01:33:35 PM PST 24 218149413 ps
T51 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.952522181 Mar 09 01:33:27 PM PST 24 Mar 09 01:33:32 PM PST 24 176612784 ps
T274 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3139777231 Mar 09 01:33:43 PM PST 24 Mar 09 01:33:44 PM PST 24 32510256 ps
T275 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.4195105286 Mar 09 01:33:43 PM PST 24 Mar 09 01:33:44 PM PST 24 29390618 ps
T276 /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1440366066 Mar 09 01:33:44 PM PST 24 Mar 09 01:33:45 PM PST 24 47358563 ps
T277 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.911988202 Mar 09 01:33:15 PM PST 24 Mar 09 01:33:16 PM PST 24 32685386 ps
T278 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.770717425 Mar 09 01:33:26 PM PST 24 Mar 09 01:33:27 PM PST 24 18510246 ps
T279 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2504101640 Mar 09 01:33:16 PM PST 24 Mar 09 01:33:17 PM PST 24 37386552 ps
T280 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2206909605 Mar 09 01:32:57 PM PST 24 Mar 09 01:33:06 PM PST 24 301040641 ps
T281 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2885589240 Mar 09 01:33:06 PM PST 24 Mar 09 01:33:09 PM PST 24 77801204 ps
T282 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3954873465 Mar 09 01:33:22 PM PST 24 Mar 09 01:33:25 PM PST 24 237596430 ps
T283 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2417360850 Mar 09 01:33:38 PM PST 24 Mar 09 01:33:41 PM PST 24 1397289395 ps
T284 /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.977689789 Mar 09 01:33:21 PM PST 24 Mar 09 01:33:23 PM PST 24 85256514 ps
T285 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3107351399 Mar 09 01:33:21 PM PST 24 Mar 09 01:33:24 PM PST 24 100502574 ps
T286 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3988710588 Mar 09 01:33:06 PM PST 24 Mar 09 01:33:07 PM PST 24 103141852 ps
T287 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3389518229 Mar 09 01:33:09 PM PST 24 Mar 09 01:33:18 PM PST 24 477536705 ps
T288 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2663049353 Mar 09 01:33:15 PM PST 24 Mar 09 01:33:16 PM PST 24 34866639 ps
T289 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.3883499292 Mar 09 01:33:06 PM PST 24 Mar 09 01:33:08 PM PST 24 144499417 ps
T290 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2017587531 Mar 09 01:33:25 PM PST 24 Mar 09 01:33:26 PM PST 24 28417728 ps
T291 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4229755332 Mar 09 01:32:58 PM PST 24 Mar 09 01:33:02 PM PST 24 476843553 ps
T292 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.4026831469 Mar 09 01:33:43 PM PST 24 Mar 09 01:33:44 PM PST 24 42488085 ps
T293 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.794056585 Mar 09 01:32:58 PM PST 24 Mar 09 01:32:59 PM PST 24 33734748 ps
T294 /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1382568737 Mar 09 01:33:26 PM PST 24 Mar 09 01:33:28 PM PST 24 343568311 ps
T56 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3465313327 Mar 09 01:33:15 PM PST 24 Mar 09 01:33:20 PM PST 24 97570563 ps
T295 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.2179606000 Mar 09 01:33:02 PM PST 24 Mar 09 01:33:04 PM PST 24 75892353 ps
T296 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.244695533 Mar 09 01:33:05 PM PST 24 Mar 09 01:33:10 PM PST 24 204652818 ps
T297 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2800608960 Mar 09 01:33:47 PM PST 24 Mar 09 01:33:48 PM PST 24 19870232 ps
T298 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2487290610 Mar 09 01:33:14 PM PST 24 Mar 09 01:33:16 PM PST 24 30054764 ps
T299 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.4018167100 Mar 09 01:33:39 PM PST 24 Mar 09 01:33:43 PM PST 24 173144006 ps
T300 /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1782455305 Mar 09 01:32:51 PM PST 24 Mar 09 01:32:54 PM PST 24 239780167 ps
T301 /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.1481455895 Mar 09 01:33:44 PM PST 24 Mar 09 01:33:45 PM PST 24 23069679 ps
T302 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1378417819 Mar 09 01:33:11 PM PST 24 Mar 09 01:33:13 PM PST 24 27418877 ps
T303 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1008200851 Mar 09 01:33:17 PM PST 24 Mar 09 01:33:19 PM PST 24 177530035 ps
T304 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2921147165 Mar 09 01:33:16 PM PST 24 Mar 09 01:33:17 PM PST 24 42638835 ps
T305 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1967400441 Mar 09 01:33:46 PM PST 24 Mar 09 01:33:47 PM PST 24 12592354 ps
T306 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.2535365873 Mar 09 01:33:27 PM PST 24 Mar 09 01:33:28 PM PST 24 41605835 ps
T53 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.2650051545 Mar 09 01:33:30 PM PST 24 Mar 09 01:33:33 PM PST 24 440744572 ps
T307 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1376343737 Mar 09 01:33:04 PM PST 24 Mar 09 01:33:06 PM PST 24 553202186 ps
T308 /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2024026067 Mar 09 01:33:17 PM PST 24 Mar 09 01:33:19 PM PST 24 25100981 ps
T309 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3143093833 Mar 09 01:33:05 PM PST 24 Mar 09 01:33:05 PM PST 24 43727457 ps

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.83231607
Short name T8
Test name
Test status
Simulation time 345658063 ps
CPU time 13.67 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:13 PM PST 24
Peak memory 208112 kb
Host smart-e933f6d4-9b34-4cf8-9a4d-7e75b83741a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83231607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.83231607
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.3566575428
Short name T7
Test name
Test status
Simulation time 235802864 ps
CPU time 7.43 seconds
Started Mar 09 01:56:46 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 230588 kb
Host smart-5dc5838a-ac80-44a5-973e-058be6861605
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566575428 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.3566575428
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.4172113311
Short name T30
Test name
Test status
Simulation time 260386024 ps
CPU time 8.61 seconds
Started Mar 09 01:33:18 PM PST 24
Finished Mar 09 01:33:27 PM PST 24
Peak memory 213052 kb
Host smart-a08f2e63-9b5e-4e78-9657-f774dceae717
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172113311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.4172113311
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.779542387
Short name T19
Test name
Test status
Simulation time 313428006 ps
CPU time 3.78 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 212772 kb
Host smart-b73d9195-62de-4872-b2af-6cbda0109ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779542387 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.779542387
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.4175706639
Short name T9
Test name
Test status
Simulation time 1943555666 ps
CPU time 20.15 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:21 PM PST 24
Peak memory 207680 kb
Host smart-abdc7d50-0321-4b0e-84f5-62108c86af64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175706639 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.4175706639
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1980655812
Short name T34
Test name
Test status
Simulation time 51520268 ps
CPU time 3.07 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:09 PM PST 24
Peak memory 212788 kb
Host smart-1a3cb047-42b0-4c8f-a624-001b76d17021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980655812 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
980655812
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.4124644874
Short name T24
Test name
Test status
Simulation time 189197278 ps
CPU time 3.64 seconds
Started Mar 09 01:33:17 PM PST 24
Finished Mar 09 01:33:22 PM PST 24
Peak memory 212564 kb
Host smart-594dcee3-de12-4995-bc03-44b1781c3637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124644874 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.4124644874
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3648589660
Short name T116
Test name
Test status
Simulation time 30242923 ps
CPU time 0.8 seconds
Started Mar 09 01:33:34 PM PST 24
Finished Mar 09 01:33:35 PM PST 24
Peak memory 204288 kb
Host smart-058ce341-9bfd-4e7e-a04e-bf3108407d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648589660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3648589660
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.3567288331
Short name T17
Test name
Test status
Simulation time 11640509 ps
CPU time 0.73 seconds
Started Mar 09 01:56:54 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 205264 kb
Host smart-bb083f87-ff19-4f44-b85f-44b9d2740346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567288331 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.3
567288331
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.4212681347
Short name T2
Test name
Test status
Simulation time 11583968501 ps
CPU time 27.94 seconds
Started Mar 09 01:56:48 PM PST 24
Finished Mar 09 01:57:16 PM PST 24
Peak memory 208324 kb
Host smart-322ac4d6-edf6-4213-93f8-451fd84e75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212681347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.4212681347
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.4096704215
Short name T69
Test name
Test status
Simulation time 5999930862 ps
CPU time 19.66 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:57:09 PM PST 24
Peak memory 206344 kb
Host smart-9d485f55-60ca-488d-bf6d-d1f36939d882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096704215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.4096704215
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.2220123694
Short name T6
Test name
Test status
Simulation time 2957063983 ps
CPU time 10.59 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:56:58 PM PST 24
Peak memory 229860 kb
Host smart-70fe1f91-77cd-47cb-b9f9-d526c5fb9aa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220123694 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.2220123694
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1139444632
Short name T46
Test name
Test status
Simulation time 838092094 ps
CPU time 6.41 seconds
Started Mar 09 01:33:27 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 214276 kb
Host smart-58b066e1-4076-4c94-8482-2478458aa60e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139444632 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.1139444632
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2332018227
Short name T42
Test name
Test status
Simulation time 336373081 ps
CPU time 7.08 seconds
Started Mar 09 01:33:26 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 213644 kb
Host smart-a67d0cbd-a71c-476d-8c0d-5474a9aecffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332018227 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.2332018227
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.231870123
Short name T26
Test name
Test status
Simulation time 432834898 ps
CPU time 4.01 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:10 PM PST 24
Peak memory 212652 kb
Host smart-a74791f7-02e9-4b8c-8d3a-171e7e35a98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231870123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_
tl_intg_err.231870123
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2737061340
Short name T39
Test name
Test status
Simulation time 161994923 ps
CPU time 3.77 seconds
Started Mar 09 01:33:08 PM PST 24
Finished Mar 09 01:33:12 PM PST 24
Peak memory 213788 kb
Host smart-f571f750-c3a1-4965-9563-89dc673afd95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737061340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2737061340
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.725584842
Short name T54
Test name
Test status
Simulation time 328695268 ps
CPU time 4.68 seconds
Started Mar 09 01:33:37 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 212616 kb
Host smart-d452b088-da99-457a-af36-6815f3bd3475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725584842 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe
_tl_intg_err.725584842
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.952522181
Short name T51
Test name
Test status
Simulation time 176612784 ps
CPU time 4.77 seconds
Started Mar 09 01:33:27 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 212648 kb
Host smart-cbead32d-909a-4eb5-90d7-223f6e0d914b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952522181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe
_tl_intg_err.952522181
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3070081883
Short name T45
Test name
Test status
Simulation time 232566889 ps
CPU time 3.27 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:09 PM PST 24
Peak memory 213556 kb
Host smart-e453fe06-4742-4d28-9acc-331f31596715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070081883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3070081883
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3107351399
Short name T285
Test name
Test status
Simulation time 100502574 ps
CPU time 1.88 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:24 PM PST 24
Peak memory 212620 kb
Host smart-31ccc3dd-6ea0-451f-a1e0-bc825b89180b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107351399 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3107351399
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2826255585
Short name T197
Test name
Test status
Simulation time 51271126 ps
CPU time 0.73 seconds
Started Mar 09 01:33:25 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 204220 kb
Host smart-ba160fe9-266f-467d-b075-b388eb2cee88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826255585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2826255585
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2937726994
Short name T164
Test name
Test status
Simulation time 820108276 ps
CPU time 12.45 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:57:06 PM PST 24
Peak memory 208040 kb
Host smart-8e53dbaa-0052-40d2-89a2-8b3d2dccdb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937726994 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2937726994
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.325171061
Short name T11
Test name
Test status
Simulation time 4768029057 ps
CPU time 73.08 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:58:02 PM PST 24
Peak memory 207300 kb
Host smart-adc03292-f481-4e41-a0bc-1e14ebd40a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325171061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.325171061
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.1905336104
Short name T106
Test name
Test status
Simulation time 36153264713 ps
CPU time 140.36 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:59:10 PM PST 24
Peak memory 207396 kb
Host smart-d66b9bc6-c0c0-4dde-9693-7b824eb1fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905336104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.1905336104
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3891603772
Short name T77
Test name
Test status
Simulation time 2675151388 ps
CPU time 14.24 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:57:03 PM PST 24
Peak memory 206408 kb
Host smart-d968678c-2141-457f-b83c-ba773661cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891603772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3891603772
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1183010861
Short name T107
Test name
Test status
Simulation time 8404776074 ps
CPU time 45.98 seconds
Started Mar 09 01:56:58 PM PST 24
Finished Mar 09 01:57:44 PM PST 24
Peak memory 207644 kb
Host smart-5dfc65cd-f4ef-47bd-a03b-00a7bf199ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183010861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1183010861
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.2018419392
Short name T112
Test name
Test status
Simulation time 1026151067 ps
CPU time 16.4 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:57:08 PM PST 24
Peak memory 206016 kb
Host smart-20b12674-07c5-469e-be40-6121d884e49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018419392 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.2018419392
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.692145989
Short name T87
Test name
Test status
Simulation time 20920450776 ps
CPU time 168.26 seconds
Started Mar 09 01:56:54 PM PST 24
Finished Mar 09 01:59:42 PM PST 24
Peak memory 208644 kb
Host smart-666227c7-f517-4394-9198-04e1bed57213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692145989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.692145989
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.1503304287
Short name T104
Test name
Test status
Simulation time 254229345 ps
CPU time 13.92 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:13 PM PST 24
Peak memory 207880 kb
Host smart-76241866-3794-4cf0-8604-169f9b00bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503304287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.1503304287
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3395336969
Short name T74
Test name
Test status
Simulation time 896831232 ps
CPU time 19.54 seconds
Started Mar 09 01:57:05 PM PST 24
Finished Mar 09 01:57:25 PM PST 24
Peak memory 207568 kb
Host smart-3efdfabc-cfcd-48b3-bb8f-2d0b633c2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395336969 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3395336969
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3047907958
Short name T102
Test name
Test status
Simulation time 161310200 ps
CPU time 10.75 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:09 PM PST 24
Peak memory 206224 kb
Host smart-c9922f72-458f-4b63-8779-8250754c1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047907958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3047907958
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.507338967
Short name T100
Test name
Test status
Simulation time 28998059031 ps
CPU time 241.47 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 02:01:02 PM PST 24
Peak memory 208608 kb
Host smart-5a4a9e4d-6fe1-445f-97d0-2dc08b442b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507338967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.507338967
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3622305912
Short name T105
Test name
Test status
Simulation time 1358404466 ps
CPU time 34.36 seconds
Started Mar 09 01:57:00 PM PST 24
Finished Mar 09 01:57:35 PM PST 24
Peak memory 207900 kb
Host smart-d6a91c36-2b78-4ff7-8e77-e8541043b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622305912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3622305912
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1713415720
Short name T75
Test name
Test status
Simulation time 2657057690 ps
CPU time 14.97 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:17 PM PST 24
Peak memory 206508 kb
Host smart-2013290a-022c-45bb-9018-3a292dc3004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713415720 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1713415720
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2991350655
Short name T72
Test name
Test status
Simulation time 2929117144 ps
CPU time 68.51 seconds
Started Mar 09 01:57:00 PM PST 24
Finished Mar 09 01:58:09 PM PST 24
Peak memory 207180 kb
Host smart-064585bf-5879-4de6-b1e3-a2168a3038ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991350655 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2991350655
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.1948291849
Short name T109
Test name
Test status
Simulation time 354797738 ps
CPU time 12.43 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:16 PM PST 24
Peak memory 206248 kb
Host smart-8ca06145-b5fd-40ef-a72d-85e3397e0cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948291849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.1948291849
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1163264274
Short name T10
Test name
Test status
Simulation time 2487400577 ps
CPU time 45.77 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:48 PM PST 24
Peak memory 207816 kb
Host smart-c8963f2b-b678-4d1d-89e5-4ba834f6ff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163264274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1163264274
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.2624227827
Short name T4
Test name
Test status
Simulation time 511589451 ps
CPU time 12.4 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:15 PM PST 24
Peak memory 207680 kb
Host smart-cf84e28e-2e0a-4ab5-9ce6-98af071c3532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624227827 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.2624227827
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.4065534962
Short name T103
Test name
Test status
Simulation time 434093542 ps
CPU time 16.32 seconds
Started Mar 09 01:57:05 PM PST 24
Finished Mar 09 01:57:23 PM PST 24
Peak memory 207548 kb
Host smart-1b003e21-859e-41ab-a619-a3be3a724d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065534962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.4065534962
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.394814194
Short name T172
Test name
Test status
Simulation time 827968273 ps
CPU time 6.02 seconds
Started Mar 09 01:32:53 PM PST 24
Finished Mar 09 01:32:59 PM PST 24
Peak memory 204296 kb
Host smart-3a7a9c54-cf67-43cf-8343-144ea109fbdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394814194 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.394814194
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2734842585
Short name T82
Test name
Test status
Simulation time 1509142848 ps
CPU time 7.19 seconds
Started Mar 09 01:33:07 PM PST 24
Finished Mar 09 01:33:15 PM PST 24
Peak memory 204316 kb
Host smart-173cdecb-d100-4f6a-9b16-cdd1922a2b15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734842585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2734842585
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.238357761
Short name T257
Test name
Test status
Simulation time 62713081 ps
CPU time 0.87 seconds
Started Mar 09 01:32:56 PM PST 24
Finished Mar 09 01:32:58 PM PST 24
Peak memory 204292 kb
Host smart-7ddb0595-61b6-4404-b2e5-adb48e32d838
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238357761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_hw_reset.238357761
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.151852900
Short name T234
Test name
Test status
Simulation time 23562628 ps
CPU time 1.13 seconds
Started Mar 09 01:32:52 PM PST 24
Finished Mar 09 01:32:53 PM PST 24
Peak memory 204416 kb
Host smart-90ff578a-adc4-4dcd-bf79-e1bd17a51671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151852900 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.151852900
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3618966856
Short name T266
Test name
Test status
Simulation time 251098412 ps
CPU time 1.15 seconds
Started Mar 09 01:32:54 PM PST 24
Finished Mar 09 01:32:55 PM PST 24
Peak memory 204292 kb
Host smart-b701cd81-759b-40c5-a582-a945865f92c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618966856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3
618966856
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.219897710
Short name T37
Test name
Test status
Simulation time 7987711 ps
CPU time 0.76 seconds
Started Mar 09 01:33:02 PM PST 24
Finished Mar 09 01:33:02 PM PST 24
Peak memory 204232 kb
Host smart-968c22c3-40b8-4a43-b40d-a3d7d7fbbac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219897710 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.219897710
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3148255482
Short name T31
Test name
Test status
Simulation time 18041793 ps
CPU time 1.22 seconds
Started Mar 09 01:32:52 PM PST 24
Finished Mar 09 01:32:53 PM PST 24
Peak memory 204360 kb
Host smart-a23f53ec-6ec6-4756-8bb1-4d11aa18cd0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148255482 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3148255482
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.1660890939
Short name T248
Test name
Test status
Simulation time 226711619 ps
CPU time 3.61 seconds
Started Mar 09 01:32:54 PM PST 24
Finished Mar 09 01:32:58 PM PST 24
Peak memory 212976 kb
Host smart-7e96e960-ff09-4253-9b65-0e9650840305
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660890939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.1660890939
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1782455305
Short name T300
Test name
Test status
Simulation time 239780167 ps
CPU time 3.12 seconds
Started Mar 09 01:32:51 PM PST 24
Finished Mar 09 01:32:54 PM PST 24
Peak memory 212928 kb
Host smart-6bfb2d9b-8b13-4d55-9143-8272ecb61fa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782455305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1782455305
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.648432952
Short name T212
Test name
Test status
Simulation time 557200832 ps
CPU time 5.61 seconds
Started Mar 09 01:32:53 PM PST 24
Finished Mar 09 01:32:59 PM PST 24
Peak memory 212588 kb
Host smart-06d1203e-6ee4-43a3-95c7-c20fbdfc71e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648432952 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.648432952
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3561113540
Short name T50
Test name
Test status
Simulation time 387878103 ps
CPU time 7.47 seconds
Started Mar 09 01:32:53 PM PST 24
Finished Mar 09 01:33:00 PM PST 24
Peak memory 214972 kb
Host smart-01d67ab7-ce2c-4735-983d-89f6c76b8016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561113540 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3561113540
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4229755332
Short name T291
Test name
Test status
Simulation time 476843553 ps
CPU time 4.14 seconds
Started Mar 09 01:32:58 PM PST 24
Finished Mar 09 01:33:02 PM PST 24
Peak memory 204380 kb
Host smart-73fc3529-2bc9-4c81-a9d0-8f11147ed25d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229755332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.4229755332
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.2206909605
Short name T280
Test name
Test status
Simulation time 301040641 ps
CPU time 8.98 seconds
Started Mar 09 01:32:57 PM PST 24
Finished Mar 09 01:33:06 PM PST 24
Peak memory 204452 kb
Host smart-c331f2db-e7c7-431c-958e-07dae2c06a9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206909605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.2206909605
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.3883499292
Short name T289
Test name
Test status
Simulation time 144499417 ps
CPU time 1.06 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:08 PM PST 24
Peak memory 204164 kb
Host smart-d49ce8f5-7abb-4763-a1d9-1640495dd2ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883499292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.3883499292
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.876383468
Short name T181
Test name
Test status
Simulation time 42253599 ps
CPU time 0.9 seconds
Started Mar 09 01:33:01 PM PST 24
Finished Mar 09 01:33:03 PM PST 24
Peak memory 204256 kb
Host smart-5908e4e8-54df-42a1-9a6c-d0d7b5fdb38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876383468 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.876383468
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.3680029745
Short name T247
Test name
Test status
Simulation time 171162275 ps
CPU time 1.34 seconds
Started Mar 09 01:33:04 PM PST 24
Finished Mar 09 01:33:06 PM PST 24
Peak memory 204312 kb
Host smart-707f962e-6bfc-4e28-9d6d-7bdc6395cd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680029745 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.3
680029745
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1540178511
Short name T188
Test name
Test status
Simulation time 12657971 ps
CPU time 0.85 seconds
Started Mar 09 01:33:04 PM PST 24
Finished Mar 09 01:33:05 PM PST 24
Peak memory 204212 kb
Host smart-233a1e75-4a47-47d2-9c02-c51ea9f4e7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540178511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1
540178511
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2401897438
Short name T179
Test name
Test status
Simulation time 150848512 ps
CPU time 1.49 seconds
Started Mar 09 01:33:01 PM PST 24
Finished Mar 09 01:33:03 PM PST 24
Peak memory 204436 kb
Host smart-9b831b7a-ecfa-40cd-ad2d-4119e015199f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401897438 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.2401897438
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.3496729661
Short name T228
Test name
Test status
Simulation time 137473700 ps
CPU time 1.6 seconds
Started Mar 09 01:32:53 PM PST 24
Finished Mar 09 01:32:55 PM PST 24
Peak memory 213016 kb
Host smart-e6d58008-3f20-4545-b662-2929a37cad07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496729661 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.3496729661
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2835947780
Short name T261
Test name
Test status
Simulation time 281674240 ps
CPU time 9.8 seconds
Started Mar 09 01:33:00 PM PST 24
Finished Mar 09 01:33:10 PM PST 24
Peak memory 212960 kb
Host smart-a2053df5-5ac5-4c31-9ea5-f767e13cf7ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835947780 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2835947780
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.798038940
Short name T209
Test name
Test status
Simulation time 169556076 ps
CPU time 3.32 seconds
Started Mar 09 01:32:59 PM PST 24
Finished Mar 09 01:33:03 PM PST 24
Peak memory 214760 kb
Host smart-468be428-5f91-4e1c-a5a2-ae90349c59ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798038940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.798038940
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3625188712
Short name T210
Test name
Test status
Simulation time 46582838 ps
CPU time 1.49 seconds
Started Mar 09 01:33:19 PM PST 24
Finished Mar 09 01:33:22 PM PST 24
Peak memory 212612 kb
Host smart-d324e0aa-9efe-4bd4-9b69-4e5fdc094b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625188712 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3625188712
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.1978928644
Short name T84
Test name
Test status
Simulation time 23495105 ps
CPU time 1.16 seconds
Started Mar 09 01:33:22 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204384 kb
Host smart-36697eb3-91c9-4f3b-9002-a8644491777a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978928644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
1978928644
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.932954583
Short name T237
Test name
Test status
Simulation time 18471904 ps
CPU time 0.84 seconds
Started Mar 09 01:33:19 PM PST 24
Finished Mar 09 01:33:21 PM PST 24
Peak memory 204280 kb
Host smart-ef7b3b6a-1d3f-428d-88c8-36cd0cb7ae87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932954583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.932954583
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3363190977
Short name T268
Test name
Test status
Simulation time 160109323 ps
CPU time 1.26 seconds
Started Mar 09 01:33:24 PM PST 24
Finished Mar 09 01:33:25 PM PST 24
Peak memory 204412 kb
Host smart-8906dc86-d3ab-494b-9ce1-1bc4b91ea863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363190977 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.3363190977
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2370392281
Short name T174
Test name
Test status
Simulation time 243695321 ps
CPU time 3.99 seconds
Started Mar 09 01:33:17 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 212844 kb
Host smart-9f8d69e5-6d09-4d96-8e72-0b1ee8af5f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370392281 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2370392281
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1501248404
Short name T267
Test name
Test status
Simulation time 240840831 ps
CPU time 3.25 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:25 PM PST 24
Peak memory 212948 kb
Host smart-99ce6340-a5b4-42f4-9a1e-1bc71c6219b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501248404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.1501248404
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.2556438434
Short name T258
Test name
Test status
Simulation time 223182889 ps
CPU time 1.75 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 212732 kb
Host smart-ec77d21f-b3e3-4e40-96ce-e78926751c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556438434 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
2556438434
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.2177050840
Short name T49
Test name
Test status
Simulation time 1476516957 ps
CPU time 6.57 seconds
Started Mar 09 01:33:25 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 213764 kb
Host smart-0367435c-9be5-4e3d-bf9f-3f722f2b4639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177050840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.2177050840
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3220471147
Short name T62
Test name
Test status
Simulation time 40077882 ps
CPU time 0.95 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204364 kb
Host smart-f1baade4-9a13-40c6-ad43-615d5bc75ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220471147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
3220471147
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.1490444799
Short name T229
Test name
Test status
Simulation time 11159195 ps
CPU time 0.69 seconds
Started Mar 09 01:33:22 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204224 kb
Host smart-25260c6f-367f-4e26-a012-30d632b9f328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490444799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
1490444799
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.209709213
Short name T183
Test name
Test status
Simulation time 206744223 ps
CPU time 1.95 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204472 kb
Host smart-7c5c7170-bd4e-4346-a5ff-4a45b37b3d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209709213 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_dpe_same_csr_outstanding.209709213
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.214095945
Short name T244
Test name
Test status
Simulation time 105408188 ps
CPU time 1.82 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 212980 kb
Host smart-a1aace05-38cc-48de-a14b-52795bb14738
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214095945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keym
gr_dpe_shadow_reg_errors.214095945
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1415317588
Short name T92
Test name
Test status
Simulation time 157476423 ps
CPU time 3.61 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:24 PM PST 24
Peak memory 213080 kb
Host smart-e9cf9632-c2fc-4c6e-8690-1e1ad6386102
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415317588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1415317588
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.695964782
Short name T43
Test name
Test status
Simulation time 311709378 ps
CPU time 3.74 seconds
Started Mar 09 01:33:22 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 215792 kb
Host smart-6e2314d4-341e-40ed-8937-ba1e5061a5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695964782 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.695964782
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3724886032
Short name T25
Test name
Test status
Simulation time 72292897 ps
CPU time 1.45 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 220268 kb
Host smart-8b319831-0fa0-4bd4-a5d9-4709d5621965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724886032 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3724886032
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2017587531
Short name T290
Test name
Test status
Simulation time 28417728 ps
CPU time 1.02 seconds
Started Mar 09 01:33:25 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 204420 kb
Host smart-aab89763-651a-4ba4-817b-afbb45930cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017587531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2017587531
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2744621172
Short name T83
Test name
Test status
Simulation time 40184143 ps
CPU time 1.45 seconds
Started Mar 09 01:33:24 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 204452 kb
Host smart-a4477522-db05-4d44-81b6-e54669d8b276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744621172 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.2744621172
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.2436357740
Short name T252
Test name
Test status
Simulation time 98626820 ps
CPU time 2.06 seconds
Started Mar 09 01:33:24 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 212988 kb
Host smart-575217e9-60ac-4654-a453-32c35edd8be1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436357740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.2436357740
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3284793148
Short name T29
Test name
Test status
Simulation time 116662396 ps
CPU time 2.83 seconds
Started Mar 09 01:33:24 PM PST 24
Finished Mar 09 01:33:27 PM PST 24
Peak memory 212988 kb
Host smart-d7a3cc05-c9e7-41ee-b40e-a169f3ed4201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284793148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3284793148
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3954873465
Short name T282
Test name
Test status
Simulation time 237596430 ps
CPU time 2.95 seconds
Started Mar 09 01:33:22 PM PST 24
Finished Mar 09 01:33:25 PM PST 24
Peak memory 212608 kb
Host smart-ba85282d-94a3-4682-a392-ac58c2172240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954873465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3954873465
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.2623446754
Short name T55
Test name
Test status
Simulation time 92983695 ps
CPU time 3.7 seconds
Started Mar 09 01:33:22 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 212616 kb
Host smart-c366f722-4bb5-4858-b215-443369ee8bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623446754 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.2623446754
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3222193155
Short name T61
Test name
Test status
Simulation time 35810386 ps
CPU time 0.92 seconds
Started Mar 09 01:33:26 PM PST 24
Finished Mar 09 01:33:27 PM PST 24
Peak memory 204432 kb
Host smart-6e9e35f6-abc9-4fdb-95fb-10483352969e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222193155 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.3222193155
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.2535365873
Short name T306
Test name
Test status
Simulation time 41605835 ps
CPU time 0.89 seconds
Started Mar 09 01:33:27 PM PST 24
Finished Mar 09 01:33:28 PM PST 24
Peak memory 204208 kb
Host smart-64c94146-514f-4430-af53-566d9a9804f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535365873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
2535365873
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1205462109
Short name T189
Test name
Test status
Simulation time 16497648 ps
CPU time 0.76 seconds
Started Mar 09 01:33:29 PM PST 24
Finished Mar 09 01:33:30 PM PST 24
Peak memory 204212 kb
Host smart-e2a30dd1-4aef-4c5a-be9f-f8b6ea21d30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205462109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1205462109
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1540969345
Short name T221
Test name
Test status
Simulation time 80471299 ps
CPU time 1.93 seconds
Started Mar 09 01:33:29 PM PST 24
Finished Mar 09 01:33:31 PM PST 24
Peak memory 204428 kb
Host smart-55c03510-9cf2-4669-adc0-d407d7da5c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540969345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1540969345
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.426332641
Short name T265
Test name
Test status
Simulation time 307927557 ps
CPU time 2.17 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 213068 kb
Host smart-9ed7cc3e-0697-4d15-9b5a-5f33d1a877e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426332641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keym
gr_dpe_shadow_reg_errors.426332641
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.36769660
Short name T198
Test name
Test status
Simulation time 898902032 ps
CPU time 8.32 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 213112 kb
Host smart-7c39e39f-44ab-4244-aaf4-b1bfb4947e1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36769660 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.36769660
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1382568737
Short name T294
Test name
Test status
Simulation time 343568311 ps
CPU time 1.99 seconds
Started Mar 09 01:33:26 PM PST 24
Finished Mar 09 01:33:28 PM PST 24
Peak memory 212660 kb
Host smart-d7620a49-7c9d-44fe-aea6-9984efffef3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382568737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1382568737
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.2038920351
Short name T35
Test name
Test status
Simulation time 45604209 ps
CPU time 1.43 seconds
Started Mar 09 01:33:27 PM PST 24
Finished Mar 09 01:33:28 PM PST 24
Peak memory 212664 kb
Host smart-0b5a15de-780b-494f-8f89-a1ce2d56bfbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038920351 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.2038920351
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.658618088
Short name T236
Test name
Test status
Simulation time 42798779 ps
CPU time 0.98 seconds
Started Mar 09 01:33:26 PM PST 24
Finished Mar 09 01:33:27 PM PST 24
Peak memory 204372 kb
Host smart-a606fb8e-c0b3-44d8-a41a-f07032aca6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658618088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.658618088
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.770717425
Short name T278
Test name
Test status
Simulation time 18510246 ps
CPU time 0.73 seconds
Started Mar 09 01:33:26 PM PST 24
Finished Mar 09 01:33:27 PM PST 24
Peak memory 204264 kb
Host smart-976ae9de-3c2d-4f1d-940e-9f09c673c3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770717425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.770717425
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.976996727
Short name T227
Test name
Test status
Simulation time 192972087 ps
CPU time 1.39 seconds
Started Mar 09 01:33:28 PM PST 24
Finished Mar 09 01:33:30 PM PST 24
Peak memory 204396 kb
Host smart-07e9a04e-1cca-4bf6-9e3f-808fe538e218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976996727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.976996727
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1970020685
Short name T175
Test name
Test status
Simulation time 364555708 ps
CPU time 2.26 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 213028 kb
Host smart-7b75b94d-a30f-4a56-ba71-6ae51290abe0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970020685 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.1970020685
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3459635086
Short name T66
Test name
Test status
Simulation time 1150806211 ps
CPU time 5.49 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:37 PM PST 24
Peak memory 213136 kb
Host smart-f90fb707-bd4e-4807-a421-d0933c4cd66c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459635086 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3459635086
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.31507861
Short name T240
Test name
Test status
Simulation time 368772122 ps
CPU time 2.73 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:34 PM PST 24
Peak memory 212724 kb
Host smart-b7649984-c62a-47bf-81fc-d2bac7c83372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.31507861
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.1014749604
Short name T93
Test name
Test status
Simulation time 99632434 ps
CPU time 1.8 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 212780 kb
Host smart-84a23adc-45e8-474f-b247-162b6f75ff82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014749604 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.1014749604
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.2416463128
Short name T171
Test name
Test status
Simulation time 66364429 ps
CPU time 0.85 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 204264 kb
Host smart-41b662bd-79cf-4d6e-81b8-a3ba0e3c5839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416463128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
2416463128
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2099826264
Short name T204
Test name
Test status
Simulation time 31920368 ps
CPU time 0.73 seconds
Started Mar 09 01:33:40 PM PST 24
Finished Mar 09 01:33:41 PM PST 24
Peak memory 204056 kb
Host smart-5761cff5-5eeb-4421-aad6-21f94815b5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099826264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2099826264
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2740432962
Short name T215
Test name
Test status
Simulation time 37495959 ps
CPU time 2.29 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 204324 kb
Host smart-971783d8-9cbc-4142-ba70-9492969ca7c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740432962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2740432962
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.299341460
Short name T177
Test name
Test status
Simulation time 458635378 ps
CPU time 3.48 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:34 PM PST 24
Peak memory 213016 kb
Host smart-be17ec8b-263a-4925-a93d-342131f57776
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299341460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.299341460
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1707090850
Short name T270
Test name
Test status
Simulation time 201665265 ps
CPU time 5.31 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:36 PM PST 24
Peak memory 212980 kb
Host smart-0d3c1f67-4916-49e2-ae88-61827dd32cd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707090850 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1707090850
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1833406913
Short name T41
Test name
Test status
Simulation time 674768919 ps
CPU time 2.81 seconds
Started Mar 09 01:33:29 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 220672 kb
Host smart-a4f46c60-eb47-4e74-9ec3-b91245809838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833406913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1833406913
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.2650051545
Short name T53
Test name
Test status
Simulation time 440744572 ps
CPU time 3.25 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 212648 kb
Host smart-71a398bf-7ba8-44e0-b951-9264458e98f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650051545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.2650051545
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.1702255428
Short name T243
Test name
Test status
Simulation time 16499052 ps
CPU time 0.91 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 204364 kb
Host smart-455f43d6-d17b-4296-9948-6b2f7057661b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702255428 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.1702255428
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1553705103
Short name T199
Test name
Test status
Simulation time 39020634 ps
CPU time 0.84 seconds
Started Mar 09 01:33:40 PM PST 24
Finished Mar 09 01:33:41 PM PST 24
Peak memory 204100 kb
Host smart-71acb10c-9e28-4cd7-a601-3844ebb05958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553705103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1553705103
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.466831105
Short name T202
Test name
Test status
Simulation time 77134631 ps
CPU time 0.73 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:32 PM PST 24
Peak memory 204268 kb
Host smart-c10c2640-a682-4bc9-8e8e-e0c5cd64ce62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466831105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.466831105
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.3696835168
Short name T81
Test name
Test status
Simulation time 133289958 ps
CPU time 2.05 seconds
Started Mar 09 01:33:31 PM PST 24
Finished Mar 09 01:33:34 PM PST 24
Peak memory 204364 kb
Host smart-8c374b20-5c28-49f5-aac6-2ec089fd742a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696835168 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.3696835168
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2823915174
Short name T273
Test name
Test status
Simulation time 218149413 ps
CPU time 1.74 seconds
Started Mar 09 01:33:33 PM PST 24
Finished Mar 09 01:33:35 PM PST 24
Peak memory 212924 kb
Host smart-15b2338d-5bdd-4493-9bcf-3253fab82458
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823915174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2823915174
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.4284297304
Short name T68
Test name
Test status
Simulation time 190712193 ps
CPU time 6.08 seconds
Started Mar 09 01:33:33 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 212948 kb
Host smart-817a1e7e-08c3-42ed-85c8-84a5b5d4bfd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284297304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.4284297304
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1140754945
Short name T271
Test name
Test status
Simulation time 356201026 ps
CPU time 4.3 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 213816 kb
Host smart-21c7563d-f097-48a8-8126-0a7a483a9094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140754945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.1140754945
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2557413437
Short name T20
Test name
Test status
Simulation time 42128675 ps
CPU time 1 seconds
Started Mar 09 01:33:35 PM PST 24
Finished Mar 09 01:33:36 PM PST 24
Peak memory 204356 kb
Host smart-98f72959-47d1-41ac-be09-7520e77272cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557413437 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2557413437
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.1878283539
Short name T239
Test name
Test status
Simulation time 22520223 ps
CPU time 0.83 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:31 PM PST 24
Peak memory 204164 kb
Host smart-7b46e850-7269-4e70-9178-182ed8ae4648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878283539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
1878283539
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1164912497
Short name T59
Test name
Test status
Simulation time 103411575 ps
CPU time 2.95 seconds
Started Mar 09 01:33:40 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 204260 kb
Host smart-d5cf1919-d1e1-442a-80ab-8cf3c1b82c4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164912497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.1164912497
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.3504085607
Short name T224
Test name
Test status
Simulation time 66153376 ps
CPU time 2.49 seconds
Started Mar 09 01:33:30 PM PST 24
Finished Mar 09 01:33:33 PM PST 24
Peak memory 212988 kb
Host smart-1cb6c59f-e2e8-4412-a32b-c14b93e9110d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504085607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.3504085607
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.991328233
Short name T207
Test name
Test status
Simulation time 114384434 ps
CPU time 4.49 seconds
Started Mar 09 01:33:34 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 218812 kb
Host smart-211491de-f1a8-4a54-80c4-237b6528b6c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991328233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.991328233
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.2417360850
Short name T283
Test name
Test status
Simulation time 1397289395 ps
CPU time 2.76 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:41 PM PST 24
Peak memory 212836 kb
Host smart-3c9b759b-b3e3-43ca-ba57-f5d425228a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417360850 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
2417360850
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1486758732
Short name T47
Test name
Test status
Simulation time 114391375 ps
CPU time 5 seconds
Started Mar 09 01:33:32 PM PST 24
Finished Mar 09 01:33:37 PM PST 24
Peak memory 213760 kb
Host smart-a910279d-6fc7-4c78-ac0b-e18a62fe702e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486758732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1486758732
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3266280352
Short name T67
Test name
Test status
Simulation time 26541092 ps
CPU time 1.42 seconds
Started Mar 09 01:33:39 PM PST 24
Finished Mar 09 01:33:41 PM PST 24
Peak memory 212684 kb
Host smart-f14bee6d-fff3-4f04-9196-25b9b41cba33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266280352 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3266280352
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.416349331
Short name T94
Test name
Test status
Simulation time 27034948 ps
CPU time 1.04 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204432 kb
Host smart-33daaa06-9022-4621-8157-27788b6e1f02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416349331 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.416349331
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.1574778578
Short name T208
Test name
Test status
Simulation time 25604218 ps
CPU time 0.71 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204268 kb
Host smart-5333bcab-0cb1-4851-aada-224f2ad6d6b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574778578 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
1574778578
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3745045834
Short name T251
Test name
Test status
Simulation time 321900837 ps
CPU time 1.21 seconds
Started Mar 09 01:33:37 PM PST 24
Finished Mar 09 01:33:38 PM PST 24
Peak memory 204468 kb
Host smart-198a6763-00f0-4ecd-9959-8f96d132c66e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745045834 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.3745045834
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.789066380
Short name T225
Test name
Test status
Simulation time 128036121 ps
CPU time 2.35 seconds
Started Mar 09 01:33:40 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 212816 kb
Host smart-8cfe7df4-7c6c-48d1-9df2-225f5c492aa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789066380 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keym
gr_dpe_shadow_reg_errors.789066380
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.1945448778
Short name T185
Test name
Test status
Simulation time 3281679839 ps
CPU time 6.29 seconds
Started Mar 09 01:33:34 PM PST 24
Finished Mar 09 01:33:40 PM PST 24
Peak memory 212996 kb
Host smart-03710a6f-39ec-4a49-92be-1a307e123338
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945448778 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.1945448778
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1874900852
Short name T33
Test name
Test status
Simulation time 109677946 ps
CPU time 1.69 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:40 PM PST 24
Peak memory 204516 kb
Host smart-219ee614-2076-4a24-9fd8-221156f1b230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874900852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1874900852
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.2425998147
Short name T203
Test name
Test status
Simulation time 79040562 ps
CPU time 1.18 seconds
Started Mar 09 01:33:41 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 212700 kb
Host smart-e4606857-dcff-4535-9857-66f36df471c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425998147 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.2425998147
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.2067166863
Short name T260
Test name
Test status
Simulation time 18605617 ps
CPU time 0.9 seconds
Started Mar 09 01:33:39 PM PST 24
Finished Mar 09 01:33:40 PM PST 24
Peak memory 204296 kb
Host smart-fdf230a7-6d43-46b7-84ac-f139e9733335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067166863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
2067166863
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.1098813649
Short name T182
Test name
Test status
Simulation time 12588223 ps
CPU time 0.86 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204200 kb
Host smart-4676fa27-0418-4142-8cfb-c67bc68e6c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098813649 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
1098813649
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.4018167100
Short name T299
Test name
Test status
Simulation time 173144006 ps
CPU time 3.37 seconds
Started Mar 09 01:33:39 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 204464 kb
Host smart-15ffda49-5b5d-4cf2-aa4d-b510507e2de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018167100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.4018167100
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.4229419825
Short name T184
Test name
Test status
Simulation time 107185958 ps
CPU time 1.92 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 212852 kb
Host smart-0210b9a8-1234-42af-b22d-3673fc11579b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229419825 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.4229419825
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3830068755
Short name T97
Test name
Test status
Simulation time 204262372 ps
CPU time 5.54 seconds
Started Mar 09 01:33:37 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 212956 kb
Host smart-4bee8de6-3ed7-46eb-a1ad-3cf58636d2ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830068755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.3830068755
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3206458682
Short name T226
Test name
Test status
Simulation time 476162136 ps
CPU time 3.22 seconds
Started Mar 09 01:33:40 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 212600 kb
Host smart-08a05181-bc5c-48af-9583-b47925f5ca59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206458682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3206458682
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.553512654
Short name T32
Test name
Test status
Simulation time 122019353 ps
CPU time 3.55 seconds
Started Mar 09 01:33:36 PM PST 24
Finished Mar 09 01:33:40 PM PST 24
Peak memory 213588 kb
Host smart-469c9838-3250-4c9b-bd62-2c9b06077789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553512654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.553512654
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1066939955
Short name T79
Test name
Test status
Simulation time 1171917587 ps
CPU time 10.26 seconds
Started Mar 09 01:33:07 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 204484 kb
Host smart-0b082387-c5e0-4d75-9b6f-d3a76e7b339b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066939955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.1066939955
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.2913056112
Short name T80
Test name
Test status
Simulation time 2075607912 ps
CPU time 11.27 seconds
Started Mar 09 01:33:03 PM PST 24
Finished Mar 09 01:33:14 PM PST 24
Peak memory 204452 kb
Host smart-5c49ab0d-d257-49e8-9dcc-948efef05bb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913056112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.2913056112
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.794056585
Short name T293
Test name
Test status
Simulation time 33734748 ps
CPU time 1.07 seconds
Started Mar 09 01:32:58 PM PST 24
Finished Mar 09 01:32:59 PM PST 24
Peak memory 204384 kb
Host smart-b422d371-27a4-4047-a847-315325a1446b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794056585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.794056585
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.3698861084
Short name T18
Test name
Test status
Simulation time 30231854 ps
CPU time 1.51 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:08 PM PST 24
Peak memory 212720 kb
Host smart-d5f8a027-9019-4321-87d4-58fe7b3bceed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698861084 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.3698861084
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.2921147165
Short name T304
Test name
Test status
Simulation time 42638835 ps
CPU time 0.96 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:17 PM PST 24
Peak memory 204288 kb
Host smart-1d6fcefb-df41-4c64-9e3b-6c018ba707c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921147165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.2
921147165
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1227645505
Short name T194
Test name
Test status
Simulation time 29676835 ps
CPU time 0.81 seconds
Started Mar 09 01:32:58 PM PST 24
Finished Mar 09 01:32:59 PM PST 24
Peak memory 204204 kb
Host smart-ad79ceae-2361-44cc-b28d-903f6cf15918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227645505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.1
227645505
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.2885589240
Short name T281
Test name
Test status
Simulation time 77801204 ps
CPU time 2.68 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:09 PM PST 24
Peak memory 204432 kb
Host smart-d85ff667-5a61-46d6-913b-b75e8dcd699b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885589240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.2885589240
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.3960037686
Short name T176
Test name
Test status
Simulation time 56623288 ps
CPU time 1.24 seconds
Started Mar 09 01:32:57 PM PST 24
Finished Mar 09 01:32:59 PM PST 24
Peak memory 212980 kb
Host smart-19b8a198-3ebe-4e42-8ef9-cb8413478395
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960037686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.3960037686
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2192376232
Short name T65
Test name
Test status
Simulation time 96106563 ps
CPU time 3.72 seconds
Started Mar 09 01:32:59 PM PST 24
Finished Mar 09 01:33:03 PM PST 24
Peak memory 213036 kb
Host smart-0f1d8451-64d5-4b1a-be48-453b5d1e04af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192376232 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.2192376232
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1104330029
Short name T218
Test name
Test status
Simulation time 119675828 ps
CPU time 4.09 seconds
Started Mar 09 01:33:01 PM PST 24
Finished Mar 09 01:33:05 PM PST 24
Peak memory 215792 kb
Host smart-6a060bfc-f3ee-4c79-b634-7e8066eeee60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104330029 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.1
104330029
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.1929798863
Short name T211
Test name
Test status
Simulation time 16620532 ps
CPU time 0.71 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204268 kb
Host smart-7afaa594-992a-441e-95cc-2b9f7edff173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929798863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
1929798863
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.4195105286
Short name T275
Test name
Test status
Simulation time 29390618 ps
CPU time 0.69 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204120 kb
Host smart-6a87f3a7-fc4f-4f19-ad61-c9def19c7dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195105286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
4195105286
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.308603097
Short name T232
Test name
Test status
Simulation time 48088586 ps
CPU time 0.77 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204180 kb
Host smart-6ddd73a5-32ff-4f12-af07-8c0a7a3133df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308603097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.308603097
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.371094962
Short name T259
Test name
Test status
Simulation time 12659538 ps
CPU time 0.74 seconds
Started Mar 09 01:33:39 PM PST 24
Finished Mar 09 01:33:40 PM PST 24
Peak memory 204264 kb
Host smart-d4d94708-22ff-49e6-b893-cf405b4d6145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371094962 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.371094962
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.4185151091
Short name T254
Test name
Test status
Simulation time 52249109 ps
CPU time 0.69 seconds
Started Mar 09 01:33:38 PM PST 24
Finished Mar 09 01:33:39 PM PST 24
Peak memory 204252 kb
Host smart-d198571c-8b28-4b67-9d90-276aa1970df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185151091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
4185151091
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.3652554509
Short name T115
Test name
Test status
Simulation time 16496243 ps
CPU time 0.87 seconds
Started Mar 09 01:33:47 PM PST 24
Finished Mar 09 01:33:48 PM PST 24
Peak memory 204252 kb
Host smart-fb3a33c6-490b-431e-8038-d013bbdeac6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652554509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
3652554509
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.31475763
Short name T272
Test name
Test status
Simulation time 25103096 ps
CPU time 0.83 seconds
Started Mar 09 01:33:48 PM PST 24
Finished Mar 09 01:33:49 PM PST 24
Peak memory 204276 kb
Host smart-0e288f13-8f34-4c1d-b705-df0dc6735af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31475763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.31475763
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1967400441
Short name T305
Test name
Test status
Simulation time 12592354 ps
CPU time 0.74 seconds
Started Mar 09 01:33:46 PM PST 24
Finished Mar 09 01:33:47 PM PST 24
Peak memory 204200 kb
Host smart-975f511b-b1ce-443e-bb01-ae5a442122e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967400441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1967400441
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3895709307
Short name T38
Test name
Test status
Simulation time 32760968 ps
CPU time 0.73 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204248 kb
Host smart-c3fa4256-2810-48e1-8516-fbe8253ea289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895709307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
3895709307
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2691049758
Short name T213
Test name
Test status
Simulation time 34717386 ps
CPU time 0.79 seconds
Started Mar 09 01:33:44 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204268 kb
Host smart-a7c33fc5-d7b7-44ba-9ae7-e5bd7d957e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691049758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
2691049758
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.244695533
Short name T296
Test name
Test status
Simulation time 204652818 ps
CPU time 4.2 seconds
Started Mar 09 01:33:05 PM PST 24
Finished Mar 09 01:33:10 PM PST 24
Peak memory 204648 kb
Host smart-63dc64c6-7ea8-4ba1-8053-f6aa1c377fec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244695533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_aliasing.244695533
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.729529945
Short name T193
Test name
Test status
Simulation time 176483043 ps
CPU time 8.22 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:14 PM PST 24
Peak memory 204516 kb
Host smart-2f6d29ad-8830-4789-a8eb-1273e24a8dbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729529945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr
_bit_bash.729529945
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.1746007545
Short name T98
Test name
Test status
Simulation time 65238832 ps
CPU time 1.13 seconds
Started Mar 09 01:33:08 PM PST 24
Finished Mar 09 01:33:09 PM PST 24
Peak memory 204444 kb
Host smart-cb7709ed-8f40-4572-87d2-3906066f7dda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746007545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.1746007545
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1322805222
Short name T230
Test name
Test status
Simulation time 47640367 ps
CPU time 1.98 seconds
Started Mar 09 01:33:05 PM PST 24
Finished Mar 09 01:33:08 PM PST 24
Peak memory 212692 kb
Host smart-03c67909-1853-4f26-9e70-1ed782624a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322805222 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1322805222
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2723259846
Short name T238
Test name
Test status
Simulation time 48253599 ps
CPU time 0.91 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:07 PM PST 24
Peak memory 204264 kb
Host smart-28532c90-c549-4173-bf2d-821a67c06c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723259846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.2
723259846
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.3911201639
Short name T255
Test name
Test status
Simulation time 18679919 ps
CPU time 0.8 seconds
Started Mar 09 01:33:05 PM PST 24
Finished Mar 09 01:33:06 PM PST 24
Peak memory 204272 kb
Host smart-a2d5f82d-ad93-4235-b39b-80195ba85ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911201639 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.3
911201639
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.4248192411
Short name T264
Test name
Test status
Simulation time 156012351 ps
CPU time 1.25 seconds
Started Mar 09 01:33:10 PM PST 24
Finished Mar 09 01:33:13 PM PST 24
Peak memory 204460 kb
Host smart-1d93e1fa-79be-41f4-bdd2-8d215ebadcb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248192411 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.4248192411
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.4057730310
Short name T173
Test name
Test status
Simulation time 67190797 ps
CPU time 2.22 seconds
Started Mar 09 01:33:03 PM PST 24
Finished Mar 09 01:33:05 PM PST 24
Peak memory 213028 kb
Host smart-105eaf54-51bd-4d21-ac20-829a2afa041f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057730310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.4057730310
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3383431132
Short name T180
Test name
Test status
Simulation time 205550765 ps
CPU time 5.34 seconds
Started Mar 09 01:33:04 PM PST 24
Finished Mar 09 01:33:10 PM PST 24
Peak memory 212932 kb
Host smart-6ec1f371-5c65-4797-bfd7-de09ce1118a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383431132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3383431132
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.910250863
Short name T219
Test name
Test status
Simulation time 12498762 ps
CPU time 0.72 seconds
Started Mar 09 01:33:41 PM PST 24
Finished Mar 09 01:33:42 PM PST 24
Peak memory 204216 kb
Host smart-6bd197d8-ac5a-4478-9355-325a88529de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910250863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.910250863
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.1062270127
Short name T91
Test name
Test status
Simulation time 53853213 ps
CPU time 0.71 seconds
Started Mar 09 01:33:42 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204324 kb
Host smart-aed0c5e8-7e0a-45a2-b7a9-2bf46c215daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062270127 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
1062270127
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.804192310
Short name T117
Test name
Test status
Simulation time 49165892 ps
CPU time 0.77 seconds
Started Mar 09 01:33:42 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 204220 kb
Host smart-529a483f-18d6-48cf-bef4-6e6121fc4ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804192310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.804192310
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.93702499
Short name T36
Test name
Test status
Simulation time 50025519 ps
CPU time 0.75 seconds
Started Mar 09 01:33:45 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204232 kb
Host smart-7b6454d9-4869-42b5-a6ba-3adfa206c688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93702499 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.93702499
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.4029224122
Short name T217
Test name
Test status
Simulation time 13756074 ps
CPU time 0.79 seconds
Started Mar 09 01:33:45 PM PST 24
Finished Mar 09 01:33:46 PM PST 24
Peak memory 204264 kb
Host smart-70f1a927-20a1-4562-b787-9f3c2f5d0dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029224122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
4029224122
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3139777231
Short name T274
Test name
Test status
Simulation time 32510256 ps
CPU time 0.81 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204312 kb
Host smart-fd99ccc9-4aa8-4411-b8c6-79ec26883046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139777231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3139777231
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1440366066
Short name T276
Test name
Test status
Simulation time 47358563 ps
CPU time 0.74 seconds
Started Mar 09 01:33:44 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204216 kb
Host smart-23b9c29b-a409-45b9-a641-e24430c62b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440366066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1440366066
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.644379828
Short name T222
Test name
Test status
Simulation time 13158874 ps
CPU time 0.75 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:43 PM PST 24
Peak memory 204264 kb
Host smart-117e4ab9-864b-4cab-b2c7-53cb5c199398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644379828 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.644379828
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.2734401282
Short name T114
Test name
Test status
Simulation time 12274751 ps
CPU time 0.88 seconds
Started Mar 09 01:33:47 PM PST 24
Finished Mar 09 01:33:48 PM PST 24
Peak memory 204252 kb
Host smart-de919cc8-da91-45da-9563-4a1f12459bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734401282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
2734401282
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2800608960
Short name T297
Test name
Test status
Simulation time 19870232 ps
CPU time 0.79 seconds
Started Mar 09 01:33:47 PM PST 24
Finished Mar 09 01:33:48 PM PST 24
Peak memory 204180 kb
Host smart-cc28991a-4347-425f-9164-27e6364b56b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800608960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2800608960
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.2239531835
Short name T269
Test name
Test status
Simulation time 483443763 ps
CPU time 4.33 seconds
Started Mar 09 01:33:08 PM PST 24
Finished Mar 09 01:33:13 PM PST 24
Peak memory 204452 kb
Host smart-9ea9c7d0-f93d-4729-bd36-0eb01705e636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239531835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.2239531835
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3389518229
Short name T287
Test name
Test status
Simulation time 477536705 ps
CPU time 9.11 seconds
Started Mar 09 01:33:09 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 204368 kb
Host smart-4bbaf6b0-8906-4201-933b-a7ba0bf4d9f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389518229 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3389518229
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3988710588
Short name T286
Test name
Test status
Simulation time 103141852 ps
CPU time 1.04 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:07 PM PST 24
Peak memory 204232 kb
Host smart-99751417-ec7e-4e1c-a652-b5facf01a306
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988710588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3988710588
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.911988202
Short name T277
Test name
Test status
Simulation time 32685386 ps
CPU time 1.11 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:16 PM PST 24
Peak memory 204508 kb
Host smart-1ff8eaaa-1b89-4d8d-bd9d-20eca5d34aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911988202 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.911988202
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.948085058
Short name T201
Test name
Test status
Simulation time 23901649 ps
CPU time 1.32 seconds
Started Mar 09 01:33:06 PM PST 24
Finished Mar 09 01:33:08 PM PST 24
Peak memory 204380 kb
Host smart-b62e3460-d55f-4b45-add3-0d8fe6d208d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948085058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.948085058
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.3143093833
Short name T309
Test name
Test status
Simulation time 43727457 ps
CPU time 0.77 seconds
Started Mar 09 01:33:05 PM PST 24
Finished Mar 09 01:33:05 PM PST 24
Peak memory 204216 kb
Host smart-00b0329e-467d-419e-bafd-0f908b17b727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143093833 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.3
143093833
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1691753771
Short name T63
Test name
Test status
Simulation time 202304257 ps
CPU time 2.79 seconds
Started Mar 09 01:33:12 PM PST 24
Finished Mar 09 01:33:15 PM PST 24
Peak memory 220660 kb
Host smart-597fb08a-6862-405d-86e9-9b0f1308e9db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691753771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1691753771
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1376343737
Short name T307
Test name
Test status
Simulation time 553202186 ps
CPU time 2.13 seconds
Started Mar 09 01:33:04 PM PST 24
Finished Mar 09 01:33:06 PM PST 24
Peak memory 213040 kb
Host smart-3296339c-42af-4db7-9b03-2ff3130d5fba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376343737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1376343737
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2865543441
Short name T200
Test name
Test status
Simulation time 132708128 ps
CPU time 2.99 seconds
Started Mar 09 01:33:07 PM PST 24
Finished Mar 09 01:33:10 PM PST 24
Peak memory 212932 kb
Host smart-a386b94e-f5a4-436d-83f5-37e0dfa0ba84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865543441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.2865543441
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.34068796
Short name T28
Test name
Test status
Simulation time 94695351 ps
CPU time 2.12 seconds
Started Mar 09 01:33:03 PM PST 24
Finished Mar 09 01:33:05 PM PST 24
Peak memory 212604 kb
Host smart-16f5c8f1-fe83-4d0f-8273-f5ee55aa4063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34068796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.34068796
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.2190713011
Short name T64
Test name
Test status
Simulation time 10862179 ps
CPU time 0.74 seconds
Started Mar 09 01:33:44 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204260 kb
Host smart-f04d1637-f4fc-464c-9fdd-82eb787d517b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190713011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
2190713011
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2069192570
Short name T186
Test name
Test status
Simulation time 16691987 ps
CPU time 0.81 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204212 kb
Host smart-7ee8a50d-6733-489e-b43c-cb0fd57ca17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069192570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
2069192570
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.575268689
Short name T241
Test name
Test status
Simulation time 12942787 ps
CPU time 0.74 seconds
Started Mar 09 01:33:47 PM PST 24
Finished Mar 09 01:33:48 PM PST 24
Peak memory 204272 kb
Host smart-09a7c1b6-5ac8-4409-9fa2-4788770cf5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575268689 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.575268689
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.4026831469
Short name T292
Test name
Test status
Simulation time 42488085 ps
CPU time 0.72 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204216 kb
Host smart-706f81f3-e0c0-48b0-8141-552fd0647132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026831469 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
4026831469
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.3401741746
Short name T223
Test name
Test status
Simulation time 9096901 ps
CPU time 0.78 seconds
Started Mar 09 01:33:48 PM PST 24
Finished Mar 09 01:33:49 PM PST 24
Peak memory 204232 kb
Host smart-0d622381-61ea-49a7-a1b1-8a980eb10bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401741746 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
3401741746
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1241696762
Short name T60
Test name
Test status
Simulation time 36094464 ps
CPU time 0.81 seconds
Started Mar 09 01:33:43 PM PST 24
Finished Mar 09 01:33:44 PM PST 24
Peak memory 204212 kb
Host smart-bae2e813-5e54-4ee1-8760-916fb76b1032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241696762 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1241696762
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.1325763840
Short name T256
Test name
Test status
Simulation time 16699633 ps
CPU time 0.77 seconds
Started Mar 09 01:33:48 PM PST 24
Finished Mar 09 01:33:49 PM PST 24
Peak memory 204268 kb
Host smart-6497d20c-cfbf-4a3a-9e81-47f25c1f3d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325763840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
1325763840
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.1481455895
Short name T301
Test name
Test status
Simulation time 23069679 ps
CPU time 0.82 seconds
Started Mar 09 01:33:44 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204280 kb
Host smart-b1b2ca12-241c-44f4-b65c-06439047d7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481455895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
1481455895
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.4180129575
Short name T187
Test name
Test status
Simulation time 27387103 ps
CPU time 0.8 seconds
Started Mar 09 01:33:44 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204252 kb
Host smart-d7291f1a-7521-48fd-8caa-962955a1b945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180129575 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
4180129575
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.2801129784
Short name T246
Test name
Test status
Simulation time 8877360 ps
CPU time 0.74 seconds
Started Mar 09 01:33:45 PM PST 24
Finished Mar 09 01:33:45 PM PST 24
Peak memory 204220 kb
Host smart-a177ca9f-1b77-458d-ba44-5d9d779d4fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801129784 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
2801129784
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2780522710
Short name T233
Test name
Test status
Simulation time 62504742 ps
CPU time 0.97 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:17 PM PST 24
Peak memory 212644 kb
Host smart-61ad7789-ffa6-4341-8f46-1e4319a573a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780522710 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2780522710
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1831042817
Short name T245
Test name
Test status
Simulation time 193498599 ps
CPU time 1 seconds
Started Mar 09 01:33:13 PM PST 24
Finished Mar 09 01:33:14 PM PST 24
Peak memory 204200 kb
Host smart-e592190d-7d7f-4f09-9ff9-229368a3b801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831042817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.1
831042817
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1378417819
Short name T302
Test name
Test status
Simulation time 27418877 ps
CPU time 0.83 seconds
Started Mar 09 01:33:11 PM PST 24
Finished Mar 09 01:33:13 PM PST 24
Peak memory 204276 kb
Host smart-0a057cc3-56b2-4641-8a95-94d70e735476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378417819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.1
378417819
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.3639368566
Short name T250
Test name
Test status
Simulation time 42906961 ps
CPU time 1.62 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204316 kb
Host smart-ab107979-124d-4c25-b22e-db454cc9756b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639368566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.3639368566
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.2179606000
Short name T295
Test name
Test status
Simulation time 75892353 ps
CPU time 1.35 seconds
Started Mar 09 01:33:02 PM PST 24
Finished Mar 09 01:33:04 PM PST 24
Peak memory 213092 kb
Host smart-8541385e-1cbe-41ff-80b4-7864b3b9400e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179606000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.2179606000
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.531992799
Short name T214
Test name
Test status
Simulation time 505188000 ps
CPU time 5.79 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:21 PM PST 24
Peak memory 212964 kb
Host smart-2d7097e4-e82f-42a0-83be-f3cf876d2425
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531992799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.531992799
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2691541315
Short name T249
Test name
Test status
Simulation time 30774542 ps
CPU time 1.83 seconds
Started Mar 09 01:33:05 PM PST 24
Finished Mar 09 01:33:07 PM PST 24
Peak memory 212716 kb
Host smart-88fc6c11-aeaf-48c3-bddd-6e1fd3e16207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691541315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
691541315
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.972866385
Short name T52
Test name
Test status
Simulation time 195192179 ps
CPU time 2.94 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 212604 kb
Host smart-472142bf-a81a-43f6-9557-4d604ff0b334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972866385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.972866385
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2663049353
Short name T288
Test name
Test status
Simulation time 34866639 ps
CPU time 0.86 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:16 PM PST 24
Peak memory 204216 kb
Host smart-f029bf00-cd56-4677-a47e-932f7d1e2716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663049353 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2663049353
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2487290610
Short name T298
Test name
Test status
Simulation time 30054764 ps
CPU time 1.12 seconds
Started Mar 09 01:33:14 PM PST 24
Finished Mar 09 01:33:16 PM PST 24
Peak memory 204336 kb
Host smart-abf64c71-4404-49a2-9665-adf4a29ef161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487290610 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
487290610
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.779147121
Short name T216
Test name
Test status
Simulation time 10138597 ps
CPU time 0.87 seconds
Started Mar 09 01:33:11 PM PST 24
Finished Mar 09 01:33:13 PM PST 24
Peak memory 204336 kb
Host smart-43199cf7-b748-43be-88b5-125cfa9d1afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779147121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.779147121
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.3232239163
Short name T190
Test name
Test status
Simulation time 162577200 ps
CPU time 1.74 seconds
Started Mar 09 01:33:18 PM PST 24
Finished Mar 09 01:33:21 PM PST 24
Peak memory 204440 kb
Host smart-0695a177-1074-49f8-b03e-8d6d8a0799d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232239163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.3232239163
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.1653247183
Short name T192
Test name
Test status
Simulation time 155060043 ps
CPU time 1.66 seconds
Started Mar 09 01:33:09 PM PST 24
Finished Mar 09 01:33:11 PM PST 24
Peak memory 213020 kb
Host smart-aac7fb43-5052-4444-a359-c7278c23effb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653247183 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.1653247183
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3300743693
Short name T95
Test name
Test status
Simulation time 1352834106 ps
CPU time 8.26 seconds
Started Mar 09 01:33:10 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 213052 kb
Host smart-592634ee-f1df-4bc3-9dea-af07342516e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300743693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.3300743693
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3907567142
Short name T263
Test name
Test status
Simulation time 485471587 ps
CPU time 4.73 seconds
Started Mar 09 01:33:11 PM PST 24
Finished Mar 09 01:33:16 PM PST 24
Peak memory 212656 kb
Host smart-88376d85-7368-45d9-98ed-5c7386200e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907567142 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.3
907567142
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.4109358705
Short name T27
Test name
Test status
Simulation time 607082197 ps
CPU time 3.93 seconds
Started Mar 09 01:33:11 PM PST 24
Finished Mar 09 01:33:15 PM PST 24
Peak memory 204260 kb
Host smart-2569fd33-3ce7-48a5-b6fb-d25f07ac9fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109358705 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.4109358705
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.2024026067
Short name T308
Test name
Test status
Simulation time 25100981 ps
CPU time 1.17 seconds
Started Mar 09 01:33:17 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 212744 kb
Host smart-a5740f8f-178a-431b-9418-ccab8781e3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024026067 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.2024026067
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.3138546174
Short name T220
Test name
Test status
Simulation time 19678750 ps
CPU time 0.94 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:17 PM PST 24
Peak memory 204276 kb
Host smart-0ce1b39e-3c13-43be-90d2-e8892cf554eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138546174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.3
138546174
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.1008200851
Short name T303
Test name
Test status
Simulation time 177530035 ps
CPU time 0.7 seconds
Started Mar 09 01:33:17 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 204132 kb
Host smart-ca2ec152-b14f-4b3b-8399-d319325c8744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008200851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.1
008200851
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1913032559
Short name T205
Test name
Test status
Simulation time 94323478 ps
CPU time 1.22 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:17 PM PST 24
Peak memory 204468 kb
Host smart-d935878e-2ca7-41c1-8e8d-ac03c9e21f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913032559 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1913032559
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.3269043232
Short name T178
Test name
Test status
Simulation time 81131617 ps
CPU time 1.66 seconds
Started Mar 09 01:33:19 PM PST 24
Finished Mar 09 01:33:22 PM PST 24
Peak memory 212992 kb
Host smart-cf98d06b-a494-46cb-9aed-d7e63438340b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269043232 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.3269043232
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1812124391
Short name T58
Test name
Test status
Simulation time 658306139 ps
CPU time 3.46 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 213048 kb
Host smart-27dd1db1-eee4-417b-a834-fa57388542f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812124391 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1812124391
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.629578026
Short name T48
Test name
Test status
Simulation time 1850408514 ps
CPU time 5.21 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:20 PM PST 24
Peak memory 220860 kb
Host smart-e74eedd4-525b-4f96-a72e-8db5eef73afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629578026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.629578026
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.3465313327
Short name T56
Test name
Test status
Simulation time 97570563 ps
CPU time 4.37 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:20 PM PST 24
Peak memory 213772 kb
Host smart-601d269b-1ca8-4ba3-9810-537157b49f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465313327 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.3465313327
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3098069160
Short name T206
Test name
Test status
Simulation time 18308040 ps
CPU time 1 seconds
Started Mar 09 01:33:20 PM PST 24
Finished Mar 09 01:33:22 PM PST 24
Peak memory 204364 kb
Host smart-b97173ca-fa06-483c-ae27-1e38073e7181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098069160 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3098069160
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.91961248
Short name T196
Test name
Test status
Simulation time 23812092 ps
CPU time 0.88 seconds
Started Mar 09 01:33:17 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 204312 kb
Host smart-f1321101-14c0-4a3a-a60c-6c9c74220813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91961248 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.91961248
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.822153392
Short name T253
Test name
Test status
Simulation time 46961247 ps
CPU time 0.74 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:16 PM PST 24
Peak memory 204304 kb
Host smart-194b7b48-277e-4cd4-a704-a0e08807688f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822153392 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.822153392
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.977689789
Short name T284
Test name
Test status
Simulation time 85256514 ps
CPU time 1.36 seconds
Started Mar 09 01:33:21 PM PST 24
Finished Mar 09 01:33:23 PM PST 24
Peak memory 204420 kb
Host smart-d12b1dd4-567a-4635-ad22-709791a497e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977689789 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.977689789
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.269763233
Short name T57
Test name
Test status
Simulation time 158805471 ps
CPU time 4.21 seconds
Started Mar 09 01:33:20 PM PST 24
Finished Mar 09 01:33:25 PM PST 24
Peak memory 212996 kb
Host smart-52614486-f52f-4f12-984a-11f13a0b56cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269763233 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.269763233
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2263678052
Short name T235
Test name
Test status
Simulation time 869662762 ps
CPU time 5.65 seconds
Started Mar 09 01:33:20 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 213008 kb
Host smart-8553afd9-c44c-4bd7-8a57-421bcca22e85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263678052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.2263678052
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.1540178664
Short name T231
Test name
Test status
Simulation time 904689173 ps
CPU time 2.32 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 220844 kb
Host smart-927d2001-7c07-41b4-91cc-c1d0ee0c80ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540178664 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.1
540178664
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1665461852
Short name T44
Test name
Test status
Simulation time 191162315 ps
CPU time 4.92 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:20 PM PST 24
Peak memory 213908 kb
Host smart-21a66305-e98d-478e-9d20-9ff2624e6869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665461852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.1665461852
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2504101640
Short name T279
Test name
Test status
Simulation time 37386552 ps
CPU time 1.1 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:17 PM PST 24
Peak memory 220192 kb
Host smart-3ab46485-9b8e-4f5c-af56-9a0f409a4c69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504101640 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2504101640
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2012637011
Short name T191
Test name
Test status
Simulation time 24691634 ps
CPU time 1.07 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 204268 kb
Host smart-b0adbcd1-5d24-4f0d-8630-ea8176873f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012637011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.2
012637011
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.4083469426
Short name T262
Test name
Test status
Simulation time 39956855 ps
CPU time 0.74 seconds
Started Mar 09 01:33:25 PM PST 24
Finished Mar 09 01:33:26 PM PST 24
Peak memory 204064 kb
Host smart-6863ee79-b718-442b-abab-22c0d03ea155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083469426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.4
083469426
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2465502771
Short name T195
Test name
Test status
Simulation time 275635055 ps
CPU time 2.86 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 212592 kb
Host smart-afc55080-bdb7-4790-a17b-ca34b8ff915e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465502771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2465502771
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.755079840
Short name T96
Test name
Test status
Simulation time 76681330 ps
CPU time 1.74 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 212920 kb
Host smart-67b433c7-ed53-4ded-b397-0c292c96acdb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755079840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymg
r_dpe_shadow_reg_errors.755079840
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3550822860
Short name T242
Test name
Test status
Simulation time 140429154 ps
CPU time 2.32 seconds
Started Mar 09 01:33:15 PM PST 24
Finished Mar 09 01:33:18 PM PST 24
Peak memory 215848 kb
Host smart-be3c679c-9bdd-418f-8fdc-0147883e8e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550822860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
550822860
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.3378867399
Short name T40
Test name
Test status
Simulation time 76935665 ps
CPU time 3.04 seconds
Started Mar 09 01:33:16 PM PST 24
Finished Mar 09 01:33:19 PM PST 24
Peak memory 213624 kb
Host smart-24d64ae9-223d-4def-8222-acc5a8db91d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378867399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.3378867399
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.344695582
Short name T158
Test name
Test status
Simulation time 78347346 ps
CPU time 0.83 seconds
Started Mar 09 01:56:40 PM PST 24
Finished Mar 09 01:56:42 PM PST 24
Peak memory 205380 kb
Host smart-c0fab658-d536-4ebd-ae7f-d547bece8d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344695582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.344695582
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.300846013
Short name T21
Test name
Test status
Simulation time 3791014118 ps
CPU time 11.22 seconds
Started Mar 09 01:56:43 PM PST 24
Finished Mar 09 01:56:55 PM PST 24
Peak memory 234476 kb
Host smart-af2b37b9-aada-4b04-b700-4f64a288eece
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300846013 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.300846013
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1771389890
Short name T5
Test name
Test status
Simulation time 775730472 ps
CPU time 5.34 seconds
Started Mar 09 01:56:42 PM PST 24
Finished Mar 09 01:56:48 PM PST 24
Peak memory 233124 kb
Host smart-5e1a6c03-30a0-4a2e-b108-1a0ad17e7c4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771389890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1771389890
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2341556317
Short name T151
Test name
Test status
Simulation time 632406787 ps
CPU time 13.8 seconds
Started Mar 09 01:56:43 PM PST 24
Finished Mar 09 01:56:58 PM PST 24
Peak memory 207760 kb
Host smart-66aeac13-ee57-4abd-94bd-d6fed57f476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341556317 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2341556317
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.1324847511
Short name T147
Test name
Test status
Simulation time 84064578 ps
CPU time 0.85 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:56:48 PM PST 24
Peak memory 205180 kb
Host smart-607d9f5f-1b6f-41b3-ba2e-be8ab4cf7644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324847511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
1324847511
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.3411164492
Short name T108
Test name
Test status
Simulation time 1813789325 ps
CPU time 19.73 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:57:11 PM PST 24
Peak memory 208088 kb
Host smart-f20afe36-0ecb-46d5-9040-3118b03fcd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411164492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.3411164492
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2044567936
Short name T157
Test name
Test status
Simulation time 10093620 ps
CPU time 0.71 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 205240 kb
Host smart-d56741b0-6c06-4013-b8e5-ab349c32cf42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044567936 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2044567936
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1468345403
Short name T128
Test name
Test status
Simulation time 47992593 ps
CPU time 0.73 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:56:51 PM PST 24
Peak memory 205376 kb
Host smart-ebdefbce-3244-4e7e-9e36-2496768bc89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468345403 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1468345403
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.2162922174
Short name T140
Test name
Test status
Simulation time 21784862 ps
CPU time 0.74 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:56:52 PM PST 24
Peak memory 205284 kb
Host smart-30e0a2bf-4640-42a3-b9be-bbb3d1d27bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162922174 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
2162922174
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.321489139
Short name T170
Test name
Test status
Simulation time 13742800 ps
CPU time 0.79 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:56:50 PM PST 24
Peak memory 205368 kb
Host smart-d78eb23f-cea2-4e19-a49a-0481d35bdfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321489139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.321489139
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.3816998128
Short name T90
Test name
Test status
Simulation time 815998913 ps
CPU time 13.28 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 206544 kb
Host smart-9221c38c-73b7-4f4e-9899-60cc18c40ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816998128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.3816998128
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.2598790654
Short name T153
Test name
Test status
Simulation time 14902891 ps
CPU time 0.74 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:56:52 PM PST 24
Peak memory 205356 kb
Host smart-a3ec1d17-6485-4eb6-a6f2-8d41950c0100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598790654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
2598790654
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1454210755
Short name T145
Test name
Test status
Simulation time 8936095 ps
CPU time 0.76 seconds
Started Mar 09 01:56:57 PM PST 24
Finished Mar 09 01:56:58 PM PST 24
Peak memory 205352 kb
Host smart-5c5fe436-7be4-43d5-9b08-5b7dd53ab7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454210755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1454210755
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.3839010138
Short name T154
Test name
Test status
Simulation time 1910869892 ps
CPU time 17.2 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:57:07 PM PST 24
Peak memory 207892 kb
Host smart-0c6aacc7-1ef5-4ebf-a3f8-8410b68aeadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839010138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.3839010138
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.599951851
Short name T146
Test name
Test status
Simulation time 62087337 ps
CPU time 0.73 seconds
Started Mar 09 01:56:58 PM PST 24
Finished Mar 09 01:56:59 PM PST 24
Peak memory 205308 kb
Host smart-bdcd5ffe-efd7-4aef-89da-d3c242cc16c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599951851 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.599951851
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.819322125
Short name T162
Test name
Test status
Simulation time 18052662 ps
CPU time 0.8 seconds
Started Mar 09 01:56:52 PM PST 24
Finished Mar 09 01:56:53 PM PST 24
Peak memory 205320 kb
Host smart-baa320b9-dfb0-4e03-bf9b-cf249d9a6bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819322125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.819322125
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.1384774959
Short name T130
Test name
Test status
Simulation time 1348758440 ps
CPU time 22.86 seconds
Started Mar 09 01:56:52 PM PST 24
Finished Mar 09 01:57:15 PM PST 24
Peak memory 207652 kb
Host smart-69f2a463-386e-40c6-ab3d-9f1ebecfd94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384774959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.1384774959
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.2739834526
Short name T120
Test name
Test status
Simulation time 11575667 ps
CPU time 0.84 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205360 kb
Host smart-75da88e0-2156-4324-b4ae-7f4c9a4e5f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739834526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
2739834526
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.840592214
Short name T89
Test name
Test status
Simulation time 5608263923 ps
CPU time 60.88 seconds
Started Mar 09 01:56:52 PM PST 24
Finished Mar 09 01:57:53 PM PST 24
Peak memory 208548 kb
Host smart-e81222de-20f5-4ce7-91da-31d9dc1d61e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840592214 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.840592214
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1896561863
Short name T16
Test name
Test status
Simulation time 77282984 ps
CPU time 1.04 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:56:50 PM PST 24
Peak memory 205508 kb
Host smart-375f6537-51dc-44fc-bf32-737ce445a025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896561863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
896561863
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.2480518763
Short name T22
Test name
Test status
Simulation time 24144723510 ps
CPU time 44.42 seconds
Started Mar 09 01:56:46 PM PST 24
Finished Mar 09 01:57:31 PM PST 24
Peak memory 231552 kb
Host smart-4bd1cb81-9c18-4864-b7fa-d211a33ad707
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480518763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.2480518763
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.183553335
Short name T163
Test name
Test status
Simulation time 5922813373 ps
CPU time 26.23 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:57:18 PM PST 24
Peak memory 208300 kb
Host smart-1f077c54-b2fc-4f77-9c2b-9cab35cbcd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183553335 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.183553335
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.4018222647
Short name T124
Test name
Test status
Simulation time 10555063 ps
CPU time 0.88 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 205248 kb
Host smart-ea8eee85-4ec6-45d0-8edc-95e06469b8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018222647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
4018222647
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.51289744
Short name T73
Test name
Test status
Simulation time 2617761414 ps
CPU time 22.73 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:57:16 PM PST 24
Peak memory 207260 kb
Host smart-570b4a64-f122-418c-8f85-88f8cac10820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51289744 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.51289744
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2791938140
Short name T138
Test name
Test status
Simulation time 106561128 ps
CPU time 0.81 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:03 PM PST 24
Peak memory 205344 kb
Host smart-13be24aa-372e-408a-b770-cb9a478c4b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791938140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2791938140
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.1405724230
Short name T121
Test name
Test status
Simulation time 25486104 ps
CPU time 0.81 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:56:52 PM PST 24
Peak memory 205360 kb
Host smart-ed440686-758d-42bb-ae05-7ed6e58a930f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405724230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
1405724230
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.916421856
Short name T148
Test name
Test status
Simulation time 31065371 ps
CPU time 0.78 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 205360 kb
Host smart-2f524060-290b-4c5a-872e-b6167e1baa5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916421856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.916421856
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.338183606
Short name T161
Test name
Test status
Simulation time 18449829 ps
CPU time 0.92 seconds
Started Mar 09 01:56:58 PM PST 24
Finished Mar 09 01:56:59 PM PST 24
Peak memory 205460 kb
Host smart-90cad5a1-e443-4fcf-8e97-86531be8fbb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338183606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.338183606
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.477646640
Short name T143
Test name
Test status
Simulation time 3318121893 ps
CPU time 30.82 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:57:24 PM PST 24
Peak memory 207480 kb
Host smart-17c67872-25c3-4b3d-96c4-e5391bb9927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477646640 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.477646640
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.161302699
Short name T123
Test name
Test status
Simulation time 23833301 ps
CPU time 0.9 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205296 kb
Host smart-0aca0f70-590d-44ef-b281-24198ea9c060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161302699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.161302699
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.61716738
Short name T131
Test name
Test status
Simulation time 277795222 ps
CPU time 0.82 seconds
Started Mar 09 01:56:53 PM PST 24
Finished Mar 09 01:56:54 PM PST 24
Peak memory 205372 kb
Host smart-44a3adc0-6a7a-4a61-8650-02f00aa9391f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61716738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.61716738
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.2258220270
Short name T3
Test name
Test status
Simulation time 1897436419 ps
CPU time 21.12 seconds
Started Mar 09 01:56:55 PM PST 24
Finished Mar 09 01:57:16 PM PST 24
Peak memory 206204 kb
Host smart-69a117dd-be96-4e01-9dbc-4744b2dd81e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258220270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.2258220270
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.913137239
Short name T155
Test name
Test status
Simulation time 51614636 ps
CPU time 0.85 seconds
Started Mar 09 01:56:55 PM PST 24
Finished Mar 09 01:56:57 PM PST 24
Peak memory 205376 kb
Host smart-19b80eb9-7ba2-4c00-98cb-e2e0c625637d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913137239 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.913137239
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.3903018427
Short name T110
Test name
Test status
Simulation time 686550989 ps
CPU time 22.98 seconds
Started Mar 09 01:56:58 PM PST 24
Finished Mar 09 01:57:21 PM PST 24
Peak memory 207808 kb
Host smart-3fa96654-dbff-4731-a6a1-cdfe42768cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903018427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.3903018427
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2641882964
Short name T129
Test name
Test status
Simulation time 51447257 ps
CPU time 0.8 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205360 kb
Host smart-7bd0dffc-c12d-4e2d-bdea-8da2497560c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641882964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2641882964
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1892557054
Short name T12
Test name
Test status
Simulation time 1176288531 ps
CPU time 22.22 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:21 PM PST 24
Peak memory 206036 kb
Host smart-d3f4b534-23f3-464c-b341-953562dfa2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892557054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1892557054
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2364832208
Short name T168
Test name
Test status
Simulation time 14204847 ps
CPU time 0.9 seconds
Started Mar 09 01:56:52 PM PST 24
Finished Mar 09 01:56:53 PM PST 24
Peak memory 205308 kb
Host smart-00dad4b6-2788-49f8-92de-b3c7c543d04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364832208 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2364832208
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.1172168070
Short name T144
Test name
Test status
Simulation time 69622411 ps
CPU time 0.79 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:56:51 PM PST 24
Peak memory 205196 kb
Host smart-cddf7c5c-b66e-4192-9fbe-03dfabca7571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172168070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.1
172168070
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1275237070
Short name T167
Test name
Test status
Simulation time 1012897935 ps
CPU time 17.14 seconds
Started Mar 09 01:56:54 PM PST 24
Finished Mar 09 01:57:11 PM PST 24
Peak memory 207748 kb
Host smart-fdb4079a-2bf2-4093-b0a6-5435fbf607e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275237070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1275237070
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.3703822139
Short name T118
Test name
Test status
Simulation time 28844409 ps
CPU time 0.76 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205384 kb
Host smart-0749dfd5-24c4-437b-a65f-ab4443bf11a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703822139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
3703822139
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.583607032
Short name T1
Test name
Test status
Simulation time 20460363 ps
CPU time 0.87 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205268 kb
Host smart-fc58cbca-4445-49d2-a603-68b32e1a4240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583607032 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.583607032
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2468248665
Short name T165
Test name
Test status
Simulation time 23534428 ps
CPU time 0.72 seconds
Started Mar 09 01:57:00 PM PST 24
Finished Mar 09 01:57:01 PM PST 24
Peak memory 205356 kb
Host smart-aa7da01a-0fc7-4398-85f1-e9758f453681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468248665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2468248665
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1347887114
Short name T14
Test name
Test status
Simulation time 5375237953 ps
CPU time 30.68 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:33 PM PST 24
Peak memory 207580 kb
Host smart-94d95553-ba35-4b5e-b465-9cecc06f631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347887114 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1347887114
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3193280959
Short name T126
Test name
Test status
Simulation time 24223121 ps
CPU time 0.81 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205280 kb
Host smart-4571792e-1322-4508-9b50-a1c8ab201a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193280959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3193280959
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.1727735739
Short name T127
Test name
Test status
Simulation time 35491098 ps
CPU time 0.73 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:04 PM PST 24
Peak memory 205344 kb
Host smart-ca8115ab-1eb0-4ff4-bac2-3c684cf4a4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727735739 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
1727735739
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3939913529
Short name T13
Test name
Test status
Simulation time 11729097522 ps
CPU time 47.81 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:50 PM PST 24
Peak memory 207824 kb
Host smart-fe3ba07b-fedc-4309-91ad-f822dd19f7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939913529 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3939913529
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.2632408034
Short name T134
Test name
Test status
Simulation time 31529048 ps
CPU time 0.78 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:03 PM PST 24
Peak memory 205352 kb
Host smart-e5e61786-13fb-41b3-97a0-ac2b8c7e1776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632408034 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
2632408034
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.1504645167
Short name T99
Test name
Test status
Simulation time 1680552120 ps
CPU time 17.33 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:18 PM PST 24
Peak memory 208048 kb
Host smart-8c0210a7-a7f3-439b-99d4-7d29965082d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504645167 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.1504645167
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.3354151505
Short name T135
Test name
Test status
Simulation time 118728622 ps
CPU time 0.81 seconds
Started Mar 09 01:57:00 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205256 kb
Host smart-3ec27491-0343-4f59-9c8d-15b9070941ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354151505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
3354151505
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.1091548820
Short name T149
Test name
Test status
Simulation time 2141558119 ps
CPU time 20.42 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:23 PM PST 24
Peak memory 206068 kb
Host smart-4751217b-ef54-4201-b9f1-21d1922b9927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091548820 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.1091548820
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.1676197230
Short name T166
Test name
Test status
Simulation time 36033502 ps
CPU time 0.78 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:56:59 PM PST 24
Peak memory 205264 kb
Host smart-a20c1d3f-125f-47fe-95c2-dd7838ff0fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676197230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
1676197230
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.3213922903
Short name T159
Test name
Test status
Simulation time 9285933 ps
CPU time 0.72 seconds
Started Mar 09 01:57:01 PM PST 24
Finished Mar 09 01:57:02 PM PST 24
Peak memory 205284 kb
Host smart-ed2e2e2d-7ac7-40fc-b0a1-89bbc8964fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213922903 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
3213922903
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.1747805095
Short name T150
Test name
Test status
Simulation time 854902419 ps
CPU time 27.28 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:27 PM PST 24
Peak memory 207468 kb
Host smart-c52775d2-be57-43ff-a321-9546d0355427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747805095 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.1747805095
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1703867196
Short name T132
Test name
Test status
Simulation time 35161730 ps
CPU time 0.74 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205308 kb
Host smart-c416a9f3-a58c-41c7-8edb-c5e5d7586910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703867196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1703867196
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.3111218432
Short name T76
Test name
Test status
Simulation time 52959071607 ps
CPU time 158.41 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:59:42 PM PST 24
Peak memory 227156 kb
Host smart-1cc027a5-aad1-4860-b812-94578c3fb9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111218432 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.3111218432
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.3916683416
Short name T125
Test name
Test status
Simulation time 13692885 ps
CPU time 0.77 seconds
Started Mar 09 01:56:48 PM PST 24
Finished Mar 09 01:56:49 PM PST 24
Peak memory 205300 kb
Host smart-be0aadaa-4833-4d0e-bef5-ca2cf57a8d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916683416 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.3
916683416
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.548010702
Short name T86
Test name
Test status
Simulation time 1017376793 ps
CPU time 13.11 seconds
Started Mar 09 01:56:48 PM PST 24
Finished Mar 09 01:57:01 PM PST 24
Peak memory 206152 kb
Host smart-6aa65fe7-0197-43de-8e0e-efc96e42a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548010702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.548010702
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1135802230
Short name T71
Test name
Test status
Simulation time 20596151 ps
CPU time 0.83 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:04 PM PST 24
Peak memory 205360 kb
Host smart-3c1ba95f-a62a-44a8-9d4a-7462b328a2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135802230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1135802230
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.2311767073
Short name T122
Test name
Test status
Simulation time 16576098 ps
CPU time 0.96 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205420 kb
Host smart-310ce849-c4f0-474c-bd1e-430a4896ae5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311767073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
2311767073
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1143632195
Short name T113
Test name
Test status
Simulation time 7567034708 ps
CPU time 19.43 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:22 PM PST 24
Peak memory 208176 kb
Host smart-5270e29f-0d2e-4b0c-83bc-27d20a5616a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143632195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1143632195
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.4139571106
Short name T23
Test name
Test status
Simulation time 13892985 ps
CPU time 0.74 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205256 kb
Host smart-fdc91548-f220-4773-b610-d971f67de0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139571106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
4139571106
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.2122548326
Short name T119
Test name
Test status
Simulation time 41259485 ps
CPU time 0.77 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:00 PM PST 24
Peak memory 205324 kb
Host smart-88be5095-d0d3-4c26-b7d9-cb8ea8ed8625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122548326 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
2122548326
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.3618700087
Short name T152
Test name
Test status
Simulation time 38355099 ps
CPU time 0.81 seconds
Started Mar 09 01:57:02 PM PST 24
Finished Mar 09 01:57:03 PM PST 24
Peak memory 205300 kb
Host smart-68b829de-bf06-4469-ade3-2787c9a9c741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618700087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
3618700087
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2833843438
Short name T101
Test name
Test status
Simulation time 254851599 ps
CPU time 13.31 seconds
Started Mar 09 01:57:05 PM PST 24
Finished Mar 09 01:57:19 PM PST 24
Peak memory 206096 kb
Host smart-282bfb9b-c5b8-4153-8b70-488f0811e0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833843438 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2833843438
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.1307278216
Short name T142
Test name
Test status
Simulation time 16401647 ps
CPU time 0.79 seconds
Started Mar 09 01:56:59 PM PST 24
Finished Mar 09 01:57:01 PM PST 24
Peak memory 205340 kb
Host smart-943491b6-f6ea-45d7-924a-12f418cd624d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307278216 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
1307278216
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.465763945
Short name T141
Test name
Test status
Simulation time 41058570 ps
CPU time 0.86 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:04 PM PST 24
Peak memory 205324 kb
Host smart-dd5ef488-58c5-43ca-952b-57bc0efc6476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465763945 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.465763945
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.410584871
Short name T15
Test name
Test status
Simulation time 51897674 ps
CPU time 0.76 seconds
Started Mar 09 01:57:05 PM PST 24
Finished Mar 09 01:57:07 PM PST 24
Peak memory 205324 kb
Host smart-1f2b4abb-77f0-4b7f-a706-81c06dcb50e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410584871 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.410584871
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.437967371
Short name T136
Test name
Test status
Simulation time 34255294 ps
CPU time 0.76 seconds
Started Mar 09 01:57:06 PM PST 24
Finished Mar 09 01:57:08 PM PST 24
Peak memory 205284 kb
Host smart-c8be5ff9-9b65-4098-a4f1-8e8232730bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437967371 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.437967371
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.3038815130
Short name T139
Test name
Test status
Simulation time 30232326 ps
CPU time 0.82 seconds
Started Mar 09 01:57:04 PM PST 24
Finished Mar 09 01:57:05 PM PST 24
Peak memory 205348 kb
Host smart-5c3a5c60-121d-43d7-8cd7-cf1dde7ff495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038815130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
3038815130
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.696176960
Short name T85
Test name
Test status
Simulation time 862794469 ps
CPU time 12.18 seconds
Started Mar 09 01:57:03 PM PST 24
Finished Mar 09 01:57:16 PM PST 24
Peak memory 206356 kb
Host smart-04d7ad44-74a4-4d77-9463-4601c64fc6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696176960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.696176960
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.2370813116
Short name T78
Test name
Test status
Simulation time 23695368 ps
CPU time 0.94 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:56:48 PM PST 24
Peak memory 205328 kb
Host smart-90594a38-a550-4224-b05f-0e50913b7e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370813116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.2
370813116
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3985725628
Short name T160
Test name
Test status
Simulation time 18268262 ps
CPU time 0.82 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:56:51 PM PST 24
Peak memory 205272 kb
Host smart-e58e456c-fb8a-42ca-adbd-06aa90f27763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985725628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
985725628
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3324693641
Short name T70
Test name
Test status
Simulation time 2609189963 ps
CPU time 56.93 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:57:46 PM PST 24
Peak memory 207580 kb
Host smart-2b216a7b-42fe-40db-a9e6-685e74075048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324693641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3324693641
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.1916028470
Short name T156
Test name
Test status
Simulation time 38764628 ps
CPU time 0.86 seconds
Started Mar 09 01:56:50 PM PST 24
Finished Mar 09 01:56:51 PM PST 24
Peak memory 205324 kb
Host smart-071830db-4beb-4e65-af13-2f398605687f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916028470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1
916028470
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.1848057288
Short name T88
Test name
Test status
Simulation time 1133692615 ps
CPU time 20.53 seconds
Started Mar 09 01:56:46 PM PST 24
Finished Mar 09 01:57:07 PM PST 24
Peak memory 207488 kb
Host smart-ef28686c-e158-48b2-8ca7-dc0d183e64c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848057288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.1848057288
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2812588628
Short name T169
Test name
Test status
Simulation time 135421929 ps
CPU time 0.77 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:56:48 PM PST 24
Peak memory 205340 kb
Host smart-1ed0cf3c-2b84-44b3-9884-9753dce15ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812588628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
812588628
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2061638352
Short name T133
Test name
Test status
Simulation time 4147616324 ps
CPU time 74.39 seconds
Started Mar 09 01:56:47 PM PST 24
Finished Mar 09 01:58:01 PM PST 24
Peak memory 221996 kb
Host smart-238cef90-3ffc-45eb-af6c-952e12dd860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061638352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2061638352
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.2304564347
Short name T137
Test name
Test status
Simulation time 38625121 ps
CPU time 0.72 seconds
Started Mar 09 01:56:51 PM PST 24
Finished Mar 09 01:56:51 PM PST 24
Peak memory 205376 kb
Host smart-d1bfe036-c1df-4e9d-bb83-8b813bd75949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304564347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.2
304564347
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.183158
Short name T111
Test name
Test status
Simulation time 11070301008 ps
CPU time 100.64 seconds
Started Mar 09 01:56:49 PM PST 24
Finished Mar 09 01:58:30 PM PST 24
Peak memory 221908 kb
Host smart-80385092-bd65-49df-bd7d-67d5ef064f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183158 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.183158
Directory /workspace/9.keymgr_dpe_smoke/latest
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