Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::reseed_interval_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::reseed_interval_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
48.65 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv



Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::reseed_interval_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 37 19 18 48.65


Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::reseed_interval_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
reseed_interval_cp 37 19 18 48.65 100 1 1 0


Summary for Variable reseed_interval_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 37 19 18 48.65


User Defined Bins for reseed_interval_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
large_values[1] 0 1 1
large_values[2] 0 1 1
large_values[4] 0 1 1
large_values[6] 0 1 1
large_values[7] 0 1 1
large_values[8] 0 1 1
large_values[9] 0 1 1
large_values[10] 0 1 1
large_values[11] 0 1 1
large_values[14] 0 1 1
large_values[15] 0 1 1
large_values[16] 0 1 1
large_values[17] 0 1 1
large_values[18] 0 1 1
large_values[20] 0 1 1
large_values[22] 0 1 1
large_values[24] 0 1 1
large_values[26] 0 1 1
large_values[30] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
large_values[0] 69 1 T1 1 T4 2 T8 1
large_values[3] 1 1 T13 1 - - - -
large_values[5] 5 1 T1 1 T12 1 T21 1
large_values[12] 1 1 T79 1 - - - -
large_values[13] 1 1 T15 1 - - - -
large_values[19] 2 1 T23 1 T98 1 - -
large_values[21] 2 1 T14 1 T99 1 - -
large_values[23] 1 1 T8 1 - - - -
large_values[25] 1 1 T100 1 - - - -
large_values[27] 2 1 T101 1 T102 1 - -
large_values[28] 1 1 T103 1 - - - -
large_values[29] 1 1 T104 1 - - - -
large_values[31] 1 1 T105 1 - - - -
small_values[0] 3 1 T106 1 T89 1 T107 1
small_values[1] 1 1 T88 1 - - - -
small_values[2] 3 1 T22 1 T108 1 T109 1
small_values[3] 2 1 T90 1 T110 1 - -
small_values[4] 3 1 T11 1 T78 1 T87 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%