Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
17.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	17	4	13	76.47
Crosses	240	208	32	13.33

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	1	1	50.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	1	4	80.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	4	2	2	50.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	160	144	16	10.00	100	1	1	0
op_x_status_cross	80	64	16	20.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cdi_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Attestation]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

7037

1

T1

169

T4

154

T8

150

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	1754	1			T1	35		T4	45		T8	36
auto[Aes]	1746	1			T1	43		T4	33		T8	39
auto[Kmac]	1771	1			T1	41		T4	41		T8	42
auto[Otbn]	1766	1			T1	50		T4	35		T8	33

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeErase]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpDpeAdvance]	1566	1			T1	35		T4	33		T8	34
auto[OpDpeGenSwOut]	3519	1			T1	82		T4	91		T8	78
auto[OpDpeGenHwOut]	3518	1			T1	87		T4	63		T8	72
auto[OpDpeDisable]	100	1			T1	2		T4	2		T8	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

3655

1

T1

106

T4

94

T8

65

auto[OpDoneFail]

5048

1

T1

100

T4

95

T8

121

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

288

1

T1

13

T4

16

T8

5

auto[StWorkDpeAvailable]

8415

1

T1

193

T4

173

T8

181

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	144	16	10.00	144

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	64
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Sealing]]	*	[auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	--	--	16
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	32
[auto[OpDpeDisable]]	*	*	*	--	--	32

Covered bins

op_cp

cdi_cp

dest_cp

state_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

33

1

T4

2

T9

3

T10

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

854

1

T1

12

T4

22

T8

18

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

14

1

T1

1

T4

2

T13

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

853

1

T1

17

T4

17

T8

25

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

25

1

T1

1

T4

3

T8

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

867

1

T1

20

T4

22

T8

15

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

23

1

T1

4

T4

2

T9

2

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

850

1

T1

27

T4

21

T8

19

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

23

1

T1

1

T4

3

T8

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

844

1

T1

22

T4

18

T8

16

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

23

1

T1

3

T4

1

T9

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

856

1

T1

22

T4

13

T8

14

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

23

1

T4

1

T9

1

T10

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

856

1

T1

20

T4

15

T8

26

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

24

1

T1

1

T9

4

T13

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

869

1

T1

18

T4

12

T8

14

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	64	16	20.00	64

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	32
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	16
[auto[OpDpeDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase] , auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut] , auto[OpDpeDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp

cdi_cp

dest_cp

op_status_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

409

1

T1

7

T4

10

T8

10

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

478

1

T1

5

T4

14

T8

8

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

412

1

T1

13

T4

9

T8

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

455

1

T1

5

T4

10

T8

12

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

409

1

T1

8

T4

14

T8

3

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

483

1

T1

13

T4

11

T8

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

388

1

T1

13

T4

13

T8

3

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

485

1

T1

18

T4

10

T8

16

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

385

1

T1

16

T4

12

T8

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

482

1

T1

7

T4

9

T8

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

379

1

T1

13

T4

9

T8

6

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

500

1

T1

12

T4

5

T8

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

415

1

T1

14

T4

12

T8

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

464

1

T1

6

T4

4

T8

18

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

388

1

T1

13

T4

6

T8

5

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

505

1

T1

6

T4

6

T8

9