Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.25 97.70 90.54 57.52 76.92 94.94 98.34 17.82


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1522445497 Mar 16 12:21:01 PM PDT 24 Mar 16 12:21:03 PM PDT 24 93512676 ps
T257 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.182963395 Mar 16 12:20:39 PM PDT 24 Mar 16 12:20:42 PM PDT 24 362526638 ps
T258 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.144218557 Mar 16 12:20:17 PM PDT 24 Mar 16 12:20:20 PM PDT 24 102486526 ps
T259 /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3239122929 Mar 16 12:20:27 PM PDT 24 Mar 16 12:20:30 PM PDT 24 76445878 ps
T260 /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1051688108 Mar 16 12:20:47 PM PDT 24 Mar 16 12:20:48 PM PDT 24 89736225 ps
T261 /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2978958571 Mar 16 12:21:56 PM PDT 24 Mar 16 12:21:57 PM PDT 24 11528880 ps
T262 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.4160911185 Mar 16 12:20:14 PM PDT 24 Mar 16 12:20:18 PM PDT 24 209930438 ps
T263 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3960664289 Mar 16 12:20:23 PM PDT 24 Mar 16 12:20:36 PM PDT 24 9527374713 ps
T264 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3068490006 Mar 16 12:20:40 PM PDT 24 Mar 16 12:20:45 PM PDT 24 369916681 ps
T265 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.771585931 Mar 16 12:20:48 PM PDT 24 Mar 16 12:20:49 PM PDT 24 31733924 ps
T57 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.617677748 Mar 16 12:20:46 PM PDT 24 Mar 16 12:20:49 PM PDT 24 190012122 ps
T266 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3939961027 Mar 16 12:20:27 PM PDT 24 Mar 16 12:20:30 PM PDT 24 175391806 ps
T267 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.299013029 Mar 16 12:20:24 PM PDT 24 Mar 16 12:20:25 PM PDT 24 14092929 ps
T268 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.849851800 Mar 16 12:20:56 PM PDT 24 Mar 16 12:20:59 PM PDT 24 649736270 ps
T269 /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.4033181901 Mar 16 12:20:47 PM PDT 24 Mar 16 12:20:48 PM PDT 24 32605885 ps
T270 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3508044738 Mar 16 12:21:10 PM PDT 24 Mar 16 12:21:12 PM PDT 24 32112526 ps
T44 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3045696957 Mar 16 12:20:11 PM PDT 24 Mar 16 12:20:15 PM PDT 24 355808723 ps
T271 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.3977261680 Mar 16 12:20:31 PM PDT 24 Mar 16 12:20:32 PM PDT 24 45239597 ps
T45 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.453183551 Mar 16 12:21:22 PM PDT 24 Mar 16 12:21:28 PM PDT 24 576219178 ps
T272 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1178859078 Mar 16 12:20:27 PM PDT 24 Mar 16 12:20:28 PM PDT 24 76586506 ps
T273 /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2689468441 Mar 16 12:21:02 PM PDT 24 Mar 16 12:21:02 PM PDT 24 9279411 ps
T274 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3003392121 Mar 16 12:20:46 PM PDT 24 Mar 16 12:20:49 PM PDT 24 68212445 ps
T275 /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.879685180 Mar 16 12:20:46 PM PDT 24 Mar 16 12:20:46 PM PDT 24 38098519 ps
T276 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3945779468 Mar 16 12:20:45 PM PDT 24 Mar 16 12:20:51 PM PDT 24 780447864 ps
T277 /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2085783098 Mar 16 12:20:39 PM PDT 24 Mar 16 12:20:46 PM PDT 24 117903253 ps
T278 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.826389907 Mar 16 12:20:36 PM PDT 24 Mar 16 12:20:40 PM PDT 24 215500759 ps
T279 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1727942606 Mar 16 12:20:12 PM PDT 24 Mar 16 12:20:15 PM PDT 24 109867062 ps
T280 /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.2639766006 Mar 16 12:20:51 PM PDT 24 Mar 16 12:20:53 PM PDT 24 57584073 ps
T281 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3202498523 Mar 16 12:20:39 PM PDT 24 Mar 16 12:20:40 PM PDT 24 35118327 ps
T282 /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3648164067 Mar 16 12:20:53 PM PDT 24 Mar 16 12:20:53 PM PDT 24 27148424 ps
T283 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.2102310733 Mar 16 12:20:35 PM PDT 24 Mar 16 12:20:36 PM PDT 24 19575770 ps
T284 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3138586726 Mar 16 12:21:01 PM PDT 24 Mar 16 12:21:02 PM PDT 24 12384069 ps
T285 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.4182951885 Mar 16 12:20:33 PM PDT 24 Mar 16 12:20:35 PM PDT 24 101860074 ps
T286 /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.1792587296 Mar 16 12:20:48 PM PDT 24 Mar 16 12:20:52 PM PDT 24 113735441 ps
T49 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.731951444 Mar 16 12:20:31 PM PDT 24 Mar 16 12:20:36 PM PDT 24 852819025 ps
T287 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1377014091 Mar 16 12:20:26 PM PDT 24 Mar 16 12:20:29 PM PDT 24 178974336 ps
T288 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.940317644 Mar 16 12:21:10 PM PDT 24 Mar 16 12:21:13 PM PDT 24 277721279 ps
T289 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1847952654 Mar 16 12:20:30 PM PDT 24 Mar 16 12:20:32 PM PDT 24 258055055 ps
T290 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1684799504 Mar 16 12:20:46 PM PDT 24 Mar 16 12:20:49 PM PDT 24 89394397 ps
T291 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1500925508 Mar 16 12:20:53 PM PDT 24 Mar 16 12:21:00 PM PDT 24 440017673 ps
T42 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.978202355 Mar 16 12:20:28 PM PDT 24 Mar 16 12:20:32 PM PDT 24 292903309 ps
T292 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3197389478 Mar 16 12:20:46 PM PDT 24 Mar 16 12:20:47 PM PDT 24 12694326 ps
T293 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4171730972 Mar 16 12:21:35 PM PDT 24 Mar 16 12:21:39 PM PDT 24 1718603996 ps
T294 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219088866 Mar 16 12:20:44 PM PDT 24 Mar 16 12:20:48 PM PDT 24 443622014 ps
T295 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.280105462 Mar 16 12:20:48 PM PDT 24 Mar 16 12:20:49 PM PDT 24 34626879 ps
T296 /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2853810547 Mar 16 12:20:08 PM PDT 24 Mar 16 12:20:12 PM PDT 24 845890120 ps
T297 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.3071409882 Mar 16 12:20:43 PM PDT 24 Mar 16 12:20:45 PM PDT 24 57015010 ps
T298 /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2974207993 Mar 16 12:20:45 PM PDT 24 Mar 16 12:20:46 PM PDT 24 39568265 ps
T299 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2619411788 Mar 16 12:20:14 PM PDT 24 Mar 16 12:20:15 PM PDT 24 13087093 ps
T300 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.211730443 Mar 16 12:20:50 PM PDT 24 Mar 16 12:20:53 PM PDT 24 103311057 ps
T301 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.4286834905 Mar 16 12:20:43 PM PDT 24 Mar 16 12:20:45 PM PDT 24 18059403 ps
T302 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.657141855 Mar 16 12:20:55 PM PDT 24 Mar 16 12:20:57 PM PDT 24 37096666 ps
T303 /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.81475789 Mar 16 12:21:01 PM PDT 24 Mar 16 12:21:03 PM PDT 24 31915682 ps
T304 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2030935348 Mar 16 12:20:34 PM PDT 24 Mar 16 12:20:35 PM PDT 24 31861912 ps
T305 /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1203519129 Mar 16 12:20:31 PM PDT 24 Mar 16 12:20:32 PM PDT 24 37717721 ps
T306 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.646870084 Mar 16 12:20:41 PM PDT 24 Mar 16 12:20:45 PM PDT 24 593840909 ps
T307 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.3147619144 Mar 16 12:20:17 PM PDT 24 Mar 16 12:20:18 PM PDT 24 21896128 ps
T308 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1264134921 Mar 16 12:20:23 PM PDT 24 Mar 16 12:20:28 PM PDT 24 354034429 ps
T309 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.940672354 Mar 16 12:20:53 PM PDT 24 Mar 16 12:20:56 PM PDT 24 78206282 ps
T310 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.3291298947 Mar 16 12:20:36 PM PDT 24 Mar 16 12:20:37 PM PDT 24 36122518 ps

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.1956104038
Short name T8
Test name
Test status
Simulation time 2137081995 ps
CPU time 20.91 seconds
Started Mar 16 04:34:04 PM PDT 24
Finished Mar 16 04:34:25 PM PDT 24
Peak memory 207856 kb
Host smart-88fcd7a7-6fff-47ae-a5cc-54b07440d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956104038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.1956104038
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.848752713
Short name T5
Test name
Test status
Simulation time 598836180 ps
CPU time 7.16 seconds
Started Mar 16 04:33:53 PM PDT 24
Finished Mar 16 04:34:00 PM PDT 24
Peak memory 230376 kb
Host smart-7b27fdae-e76a-42b1-ac2f-49834981859a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848752713 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.848752713
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3825624690
Short name T34
Test name
Test status
Simulation time 127472222 ps
CPU time 4.6 seconds
Started Mar 16 12:20:38 PM PDT 24
Finished Mar 16 12:20:42 PM PDT 24
Peak memory 212944 kb
Host smart-3e31876f-492c-4ce0-90e4-e6205c571e5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825624690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3825624690
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.3501672875
Short name T29
Test name
Test status
Simulation time 119093069 ps
CPU time 3.75 seconds
Started Mar 16 12:20:17 PM PDT 24
Finished Mar 16 12:20:21 PM PDT 24
Peak memory 220320 kb
Host smart-d224bf58-8cc0-4ea4-a7f5-7b72c5c12161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501672875 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.3
501672875
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.3293012492
Short name T21
Test name
Test status
Simulation time 3746453659 ps
CPU time 33.49 seconds
Started Mar 16 04:34:29 PM PDT 24
Finished Mar 16 04:35:04 PM PDT 24
Peak memory 208180 kb
Host smart-d4f6c161-c49c-4270-927f-e751a1c9173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293012492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.3293012492
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.2730709041
Short name T14
Test name
Test status
Simulation time 1340870664 ps
CPU time 12.55 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:40 PM PDT 24
Peak memory 207996 kb
Host smart-3fb655fc-df75-4916-9c21-ac9cbfebfaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730709041 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.2730709041
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.249523884
Short name T30
Test name
Test status
Simulation time 345335228 ps
CPU time 6.87 seconds
Started Mar 16 12:20:38 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 213512 kb
Host smart-84ac31fa-12f9-48e6-a61d-c9273b4ad5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249523884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.249523884
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.1896344975
Short name T62
Test name
Test status
Simulation time 978908875 ps
CPU time 1.98 seconds
Started Mar 16 12:20:09 PM PDT 24
Finished Mar 16 12:20:12 PM PDT 24
Peak memory 212744 kb
Host smart-43ce7b98-9c35-45f5-9f59-26ae77199159
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896344975 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.1896344975
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.1538422278
Short name T114
Test name
Test status
Simulation time 139226914 ps
CPU time 0.83 seconds
Started Mar 16 04:34:14 PM PDT 24
Finished Mar 16 04:34:15 PM PDT 24
Peak memory 205308 kb
Host smart-10f02c61-aafb-4531-8828-bf6447530dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538422278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
1538422278
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.1508263141
Short name T112
Test name
Test status
Simulation time 12979227 ps
CPU time 0.69 seconds
Started Mar 16 12:21:00 PM PDT 24
Finished Mar 16 12:21:01 PM PDT 24
Peak memory 204144 kb
Host smart-5e7a05e9-2585-410e-9d81-3aeb2cb74e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508263141 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
1508263141
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.65116742
Short name T254
Test name
Test status
Simulation time 69149097 ps
CPU time 1.84 seconds
Started Mar 16 12:20:16 PM PDT 24
Finished Mar 16 12:20:18 PM PDT 24
Peak memory 212592 kb
Host smart-e01ddc87-0989-40ac-8282-dc0fd89727eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65116742 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.65116742
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2788687536
Short name T18
Test name
Test status
Simulation time 306601402 ps
CPU time 3.62 seconds
Started Mar 16 12:20:13 PM PDT 24
Finished Mar 16 12:20:16 PM PDT 24
Peak memory 213928 kb
Host smart-b51f65b8-9098-4ffc-8908-6c84c4296d23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788687536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2788687536
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.1203271630
Short name T13
Test name
Test status
Simulation time 253120934 ps
CPU time 12.49 seconds
Started Mar 16 04:34:31 PM PDT 24
Finished Mar 16 04:34:44 PM PDT 24
Peak memory 207992 kb
Host smart-4dbc9645-b212-486a-b439-79f716da3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203271630 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.1203271630
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.2848629635
Short name T24
Test name
Test status
Simulation time 445651151 ps
CPU time 10.19 seconds
Started Mar 16 04:33:54 PM PDT 24
Finished Mar 16 04:34:04 PM PDT 24
Peak memory 228992 kb
Host smart-36dce82c-9e9b-4045-a94e-074a0a4dbf4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848629635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.2848629635
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1381575075
Short name T36
Test name
Test status
Simulation time 802992405 ps
CPU time 6.71 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 213852 kb
Host smart-073708a4-6446-45b1-b03a-66ffeb86685b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381575075 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1381575075
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1416573679
Short name T55
Test name
Test status
Simulation time 188675353 ps
CPU time 2.52 seconds
Started Mar 16 12:21:10 PM PDT 24
Finished Mar 16 12:21:13 PM PDT 24
Peak memory 212968 kb
Host smart-f1e9db86-adeb-435b-9dc9-dda51e21be7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416573679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.1416573679
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.978202355
Short name T42
Test name
Test status
Simulation time 292903309 ps
CPU time 3.47 seconds
Started Mar 16 12:20:28 PM PDT 24
Finished Mar 16 12:20:32 PM PDT 24
Peak memory 212552 kb
Host smart-7c7d637b-558a-4ef3-888d-a0179540be94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978202355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_
tl_intg_err.978202355
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.660269102
Short name T53
Test name
Test status
Simulation time 47320124 ps
CPU time 1.66 seconds
Started Mar 16 12:20:42 PM PDT 24
Finished Mar 16 12:20:44 PM PDT 24
Peak memory 220572 kb
Host smart-7a555879-b567-4826-8b03-9b2cd0a20858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660269102 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.660269102
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3322478636
Short name T177
Test name
Test status
Simulation time 40654870 ps
CPU time 0.72 seconds
Started Mar 16 12:20:44 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 204116 kb
Host smart-854edeb9-9482-4da0-86b9-01767905133b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322478636 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3322478636
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3045696957
Short name T44
Test name
Test status
Simulation time 355808723 ps
CPU time 3.69 seconds
Started Mar 16 12:20:11 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 212460 kb
Host smart-a2e43dc2-1ea6-4129-8fc2-5750a3113f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045696957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3045696957
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3740758155
Short name T54
Test name
Test status
Simulation time 101043656 ps
CPU time 3.89 seconds
Started Mar 16 12:20:44 PM PDT 24
Finished Mar 16 12:20:48 PM PDT 24
Peak memory 212552 kb
Host smart-24038061-ce78-4f26-aceb-a9b526875ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740758155 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3740758155
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.617677748
Short name T57
Test name
Test status
Simulation time 190012122 ps
CPU time 2.49 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 212636 kb
Host smart-5b17919a-0934-467c-933d-9137af67c36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617677748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe
_tl_intg_err.617677748
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3789586481
Short name T56
Test name
Test status
Simulation time 216783547 ps
CPU time 7.49 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 213484 kb
Host smart-6d10fe35-f771-44dc-9c40-d4d9ee22ea2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789586481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3789586481
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2978801602
Short name T48
Test name
Test status
Simulation time 97309550 ps
CPU time 3.58 seconds
Started Mar 16 12:21:21 PM PDT 24
Finished Mar 16 12:21:26 PM PDT 24
Peak memory 212508 kb
Host smart-a40ef214-5896-4f53-ba8f-2d5220650a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978801602 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2978801602
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.1119282292
Short name T98
Test name
Test status
Simulation time 3569569413 ps
CPU time 21.12 seconds
Started Mar 16 04:33:49 PM PDT 24
Finished Mar 16 04:34:10 PM PDT 24
Peak memory 207944 kb
Host smart-c6b63bdc-3579-4df6-9459-15e5e2de40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119282292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.1119282292
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.1483846245
Short name T89
Test name
Test status
Simulation time 22643299250 ps
CPU time 92 seconds
Started Mar 16 04:33:54 PM PDT 24
Finished Mar 16 04:35:26 PM PDT 24
Peak memory 208216 kb
Host smart-a1564094-c4e0-4302-aff8-799edc0d1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483846245 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.1483846245
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.3390113381
Short name T22
Test name
Test status
Simulation time 1667058852 ps
CPU time 26.09 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:33 PM PDT 24
Peak memory 207692 kb
Host smart-71338ee0-58c0-4285-81f3-e53d3c6636da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390113381 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.3390113381
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3482902763
Short name T15
Test name
Test status
Simulation time 3711376067 ps
CPU time 33.6 seconds
Started Mar 16 04:34:15 PM PDT 24
Finished Mar 16 04:34:49 PM PDT 24
Peak memory 207320 kb
Host smart-7a6e0a38-7f7f-42b6-ad1f-e1929f0cc512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482902763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3482902763
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.401668644
Short name T11
Test name
Test status
Simulation time 506915052 ps
CPU time 17.12 seconds
Started Mar 16 04:34:14 PM PDT 24
Finished Mar 16 04:34:31 PM PDT 24
Peak memory 207908 kb
Host smart-92ad1ece-3091-49aa-91aa-f107a3446200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401668644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.401668644
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.503234033
Short name T110
Test name
Test status
Simulation time 407038678 ps
CPU time 15.59 seconds
Started Mar 16 04:33:56 PM PDT 24
Finished Mar 16 04:34:11 PM PDT 24
Peak memory 207920 kb
Host smart-e233d751-c40b-4abd-8340-050d58b56493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503234033 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.503234033
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.3114750008
Short name T101
Test name
Test status
Simulation time 1984475268 ps
CPU time 22.53 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:44 PM PDT 24
Peak memory 206636 kb
Host smart-9d137cda-157e-498e-99c4-4fe5a6e7287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114750008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.3114750008
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.3217178905
Short name T79
Test name
Test status
Simulation time 8418640904 ps
CPU time 23.58 seconds
Started Mar 16 04:34:28 PM PDT 24
Finished Mar 16 04:34:53 PM PDT 24
Peak memory 207276 kb
Host smart-8712ab93-337c-4820-a46e-39d2d0e57d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217178905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.3217178905
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3263642396
Short name T104
Test name
Test status
Simulation time 1121497800 ps
CPU time 16.2 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:45 PM PDT 24
Peak memory 206032 kb
Host smart-7e314b6f-0ada-499d-abe0-0c000536dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263642396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3263642396
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.2948409313
Short name T105
Test name
Test status
Simulation time 1038678324 ps
CPU time 22.34 seconds
Started Mar 16 04:34:43 PM PDT 24
Finished Mar 16 04:35:05 PM PDT 24
Peak memory 207216 kb
Host smart-bb891a7d-418c-4333-bb45-26edae4599d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948409313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.2948409313
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.1131976279
Short name T103
Test name
Test status
Simulation time 897791612 ps
CPU time 12.42 seconds
Started Mar 16 04:34:42 PM PDT 24
Finished Mar 16 04:34:55 PM PDT 24
Peak memory 206108 kb
Host smart-52f19e59-48ba-4b65-a6d9-e3bbc2a53dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131976279 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.1131976279
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2607389121
Short name T88
Test name
Test status
Simulation time 558650728 ps
CPU time 9.62 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:17 PM PDT 24
Peak memory 208152 kb
Host smart-e4da3ee4-8191-447a-ad92-033b47066737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607389121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2607389121
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.2058460591
Short name T100
Test name
Test status
Simulation time 434479790 ps
CPU time 15.71 seconds
Started Mar 16 04:34:06 PM PDT 24
Finished Mar 16 04:34:22 PM PDT 24
Peak memory 206116 kb
Host smart-0e1f8091-f753-4ff4-ba99-b731c0e51e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058460591 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.2058460591
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.2989894533
Short name T209
Test name
Test status
Simulation time 606394766 ps
CPU time 3.79 seconds
Started Mar 16 12:20:09 PM PDT 24
Finished Mar 16 12:20:14 PM PDT 24
Peak memory 204368 kb
Host smart-5ce5e9d0-bb57-410c-8b55-1301db7c9de9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989894533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.2989894533
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.1264134921
Short name T308
Test name
Test status
Simulation time 354034429 ps
CPU time 4.23 seconds
Started Mar 16 12:20:23 PM PDT 24
Finished Mar 16 12:20:28 PM PDT 24
Peak memory 204332 kb
Host smart-07a54c13-1a6f-4e10-8def-ac6129fba4cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264134921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.1264134921
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.3490182034
Short name T240
Test name
Test status
Simulation time 102515867 ps
CPU time 1 seconds
Started Mar 16 12:20:11 PM PDT 24
Finished Mar 16 12:20:12 PM PDT 24
Peak memory 204116 kb
Host smart-b7908345-97fc-4d51-9929-a7bcec553c25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490182034 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.3490182034
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1746557714
Short name T242
Test name
Test status
Simulation time 30697049 ps
CPU time 1.52 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:26 PM PDT 24
Peak memory 220700 kb
Host smart-24ebcad2-fd7c-4f5c-bf17-a613b18d55fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746557714 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1746557714
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.4242324431
Short name T96
Test name
Test status
Simulation time 15832436 ps
CPU time 0.86 seconds
Started Mar 16 12:20:14 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 204072 kb
Host smart-a86a2137-7ab5-4610-afc5-2c9f7e4de623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242324431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.4
242324431
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.375715679
Short name T174
Test name
Test status
Simulation time 51975613 ps
CPU time 0.74 seconds
Started Mar 16 12:20:14 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 204128 kb
Host smart-1173712f-eb16-453b-b7b1-a69bca99352a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375715679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.375715679
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2269617731
Short name T84
Test name
Test status
Simulation time 324891374 ps
CPU time 2.1 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:26 PM PDT 24
Peak memory 204188 kb
Host smart-76ddcce4-1eea-44d7-9c20-f5443b0d339d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269617731 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2269617731
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2853810547
Short name T296
Test name
Test status
Simulation time 845890120 ps
CPU time 3.95 seconds
Started Mar 16 12:20:08 PM PDT 24
Finished Mar 16 12:20:12 PM PDT 24
Peak memory 212776 kb
Host smart-2090722b-4998-4311-a167-25151b5c5638
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853810547 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.2853810547
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.2745810811
Short name T205
Test name
Test status
Simulation time 1150048005 ps
CPU time 9.79 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204264 kb
Host smart-e28195ae-ad91-4cab-ab46-ff05109f9fd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745810811 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.2745810811
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1588584598
Short name T245
Test name
Test status
Simulation time 140155407 ps
CPU time 5.26 seconds
Started Mar 16 12:20:38 PM PDT 24
Finished Mar 16 12:20:43 PM PDT 24
Peak memory 204360 kb
Host smart-851ebe8f-dc3c-493a-b66a-9b45a7f1a682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588584598 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1588584598
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.631022972
Short name T82
Test name
Test status
Simulation time 13523421 ps
CPU time 0.97 seconds
Started Mar 16 12:20:16 PM PDT 24
Finished Mar 16 12:20:17 PM PDT 24
Peak memory 204292 kb
Host smart-3802f46e-ab1f-4592-b5ba-90f5ffa61bf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631022972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_hw_reset.631022972
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.1819407863
Short name T203
Test name
Test status
Simulation time 12580548 ps
CPU time 1.03 seconds
Started Mar 16 12:20:13 PM PDT 24
Finished Mar 16 12:20:14 PM PDT 24
Peak memory 204324 kb
Host smart-ca2286a2-26d4-451c-9fc6-24f0dc2f6b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819407863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.1
819407863
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.3291298947
Short name T310
Test name
Test status
Simulation time 36122518 ps
CPU time 0.83 seconds
Started Mar 16 12:20:36 PM PDT 24
Finished Mar 16 12:20:37 PM PDT 24
Peak memory 204140 kb
Host smart-1f430034-514d-486c-9f76-f9e384c9e519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291298947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.3
291298947
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.940317644
Short name T288
Test name
Test status
Simulation time 277721279 ps
CPU time 2.96 seconds
Started Mar 16 12:21:10 PM PDT 24
Finished Mar 16 12:21:13 PM PDT 24
Peak memory 204296 kb
Host smart-9a048bfc-e6a5-4dfa-9f2a-593da1779bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940317644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.940317644
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.1792587296
Short name T286
Test name
Test status
Simulation time 113735441 ps
CPU time 3.3 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:52 PM PDT 24
Peak memory 212932 kb
Host smart-06100a07-5d51-40ec-94d1-eee3596e42d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792587296 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.1792587296
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1727942606
Short name T279
Test name
Test status
Simulation time 109867062 ps
CPU time 3.24 seconds
Started Mar 16 12:20:12 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 219748 kb
Host smart-0f228b55-192e-42ef-a4f1-1f4ed4ad6317
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727942606 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1727942606
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2280765863
Short name T60
Test name
Test status
Simulation time 183380567 ps
CPU time 2.93 seconds
Started Mar 16 12:20:17 PM PDT 24
Finished Mar 16 12:20:20 PM PDT 24
Peak memory 204272 kb
Host smart-fb4820a5-488d-40bb-8451-ac28863c4030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280765863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2280765863
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3527507093
Short name T70
Test name
Test status
Simulation time 21487353 ps
CPU time 1.28 seconds
Started Mar 16 12:20:41 PM PDT 24
Finished Mar 16 12:20:43 PM PDT 24
Peak memory 212916 kb
Host smart-b9013372-e47d-4584-959d-b4d09e90a338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527507093 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3527507093
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2691570800
Short name T72
Test name
Test status
Simulation time 21127521 ps
CPU time 0.92 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:57 PM PDT 24
Peak memory 204068 kb
Host smart-88c4fd37-091b-4a7c-beb5-1dc6b93e988e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691570800 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2691570800
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.1203519129
Short name T305
Test name
Test status
Simulation time 37717721 ps
CPU time 0.82 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:32 PM PDT 24
Peak memory 204128 kb
Host smart-1ba231f5-b054-4425-ba7b-829db803b10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203519129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
1203519129
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.2103347584
Short name T236
Test name
Test status
Simulation time 162951136 ps
CPU time 1.31 seconds
Started Mar 16 12:20:16 PM PDT 24
Finished Mar 16 12:20:17 PM PDT 24
Peak memory 204340 kb
Host smart-8016cc9c-bc3b-4558-bee2-84bdc76cb534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103347584 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.2103347584
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2598425354
Short name T200
Test name
Test status
Simulation time 392300857 ps
CPU time 2.11 seconds
Started Mar 16 12:20:54 PM PDT 24
Finished Mar 16 12:20:56 PM PDT 24
Peak memory 212832 kb
Host smart-5e99ee58-6ba1-4b71-88a4-c73588d3f70f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598425354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2598425354
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2726251339
Short name T33
Test name
Test status
Simulation time 320932617 ps
CPU time 2.21 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:59 PM PDT 24
Peak memory 204304 kb
Host smart-260600d8-c5b6-4862-9ab7-40cea08e0a00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726251339 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2726251339
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.826389907
Short name T278
Test name
Test status
Simulation time 215500759 ps
CPU time 3.83 seconds
Started Mar 16 12:20:36 PM PDT 24
Finished Mar 16 12:20:40 PM PDT 24
Peak memory 212568 kb
Host smart-70135bf8-112b-4331-ac1d-a5365a710c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826389907 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.826389907
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.142396516
Short name T41
Test name
Test status
Simulation time 233415169 ps
CPU time 4.69 seconds
Started Mar 16 12:20:16 PM PDT 24
Finished Mar 16 12:20:20 PM PDT 24
Peak memory 212436 kb
Host smart-c0e1fa7b-bd7c-40d8-9413-59ab096c73be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142396516 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe
_tl_intg_err.142396516
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2639406351
Short name T248
Test name
Test status
Simulation time 38487484 ps
CPU time 0.94 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 204412 kb
Host smart-070f5758-0a59-4db2-a9c0-3d5586bbf24d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639406351 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2639406351
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.2102310733
Short name T283
Test name
Test status
Simulation time 19575770 ps
CPU time 1.11 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204168 kb
Host smart-a3e4be85-cc49-4f8f-aed8-353e1df319bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102310733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
2102310733
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.4286834905
Short name T301
Test name
Test status
Simulation time 18059403 ps
CPU time 0.75 seconds
Started Mar 16 12:20:43 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 204100 kb
Host smart-2bfb839b-87b2-412f-8eae-75d0d9d19334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286834905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
4286834905
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1190009312
Short name T81
Test name
Test status
Simulation time 79416841 ps
CPU time 1.94 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:48 PM PDT 24
Peak memory 204480 kb
Host smart-cac5615a-ee41-4b63-8ea3-c68204bfcd92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190009312 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1190009312
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.2843147593
Short name T230
Test name
Test status
Simulation time 131862687 ps
CPU time 2.03 seconds
Started Mar 16 12:20:49 PM PDT 24
Finished Mar 16 12:20:51 PM PDT 24
Peak memory 212832 kb
Host smart-a05d6362-08c6-437c-9b3d-e68a5af15e63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843147593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.2843147593
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.646870084
Short name T306
Test name
Test status
Simulation time 593840909 ps
CPU time 3.15 seconds
Started Mar 16 12:20:41 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 212828 kb
Host smart-b4bcb582-a7e4-4478-b258-d8a726338d8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646870084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.646870084
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1684799504
Short name T290
Test name
Test status
Simulation time 89394397 ps
CPU time 2.39 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 212500 kb
Host smart-c27874a3-14ca-40fc-a9b7-de9999967bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684799504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1684799504
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3571895838
Short name T253
Test name
Test status
Simulation time 40444713 ps
CPU time 0.88 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204220 kb
Host smart-d13f18f2-d31f-4c3c-83fb-cd56cb38d930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571895838 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3571895838
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.4182192695
Short name T197
Test name
Test status
Simulation time 39417489 ps
CPU time 1.07 seconds
Started Mar 16 12:20:30 PM PDT 24
Finished Mar 16 12:20:31 PM PDT 24
Peak memory 204296 kb
Host smart-75a71995-c804-4163-a572-039b7c5fb2cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182192695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
4182192695
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1894979125
Short name T226
Test name
Test status
Simulation time 62188909 ps
CPU time 0.81 seconds
Started Mar 16 12:20:40 PM PDT 24
Finished Mar 16 12:20:40 PM PDT 24
Peak memory 204148 kb
Host smart-0c372e48-9fa1-4cbb-9e7f-aa5865aac7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894979125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
1894979125
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1818716057
Short name T239
Test name
Test status
Simulation time 122075991 ps
CPU time 1.95 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 204356 kb
Host smart-7027871e-4dbb-4bfd-8f27-e2680d2c73e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818716057 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1818716057
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.3062395569
Short name T198
Test name
Test status
Simulation time 132636457 ps
CPU time 1.54 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:37 PM PDT 24
Peak memory 212920 kb
Host smart-d3ffcba7-f3c9-47d1-8c0a-07cc8e25f75a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062395569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.3062395569
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3003392121
Short name T274
Test name
Test status
Simulation time 68212445 ps
CPU time 2.85 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 215692 kb
Host smart-894e656e-c4ce-4406-a1fe-121c8a4cc31a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003392121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3003392121
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.3071409882
Short name T297
Test name
Test status
Simulation time 57015010 ps
CPU time 2.65 seconds
Started Mar 16 12:20:43 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 204364 kb
Host smart-2994a91b-2742-469b-9c88-005b34af7dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071409882 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.3071409882
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3251571690
Short name T97
Test name
Test status
Simulation time 20379344 ps
CPU time 1.08 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:54 PM PDT 24
Peak memory 204300 kb
Host smart-cfd380a5-c636-4aaf-b713-2bee338cf591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251571690 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.3251571690
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.2366219129
Short name T169
Test name
Test status
Simulation time 14532577 ps
CPU time 0.85 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:25 PM PDT 24
Peak memory 204152 kb
Host smart-f211d2f1-2883-48a0-b164-303ca9f0a87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366219129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
2366219129
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.829259579
Short name T39
Test name
Test status
Simulation time 20245922 ps
CPU time 0.72 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:56 PM PDT 24
Peak memory 204172 kb
Host smart-a2c0f6c7-21de-4625-aa82-5d27dcece36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829259579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.829259579
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.3641815051
Short name T237
Test name
Test status
Simulation time 69946573 ps
CPU time 2.68 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 204300 kb
Host smart-0a8d3e41-fd63-47b3-b2e0-21494b4073f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641815051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.3641815051
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3267577659
Short name T61
Test name
Test status
Simulation time 244048392 ps
CPU time 2.37 seconds
Started Mar 16 12:20:25 PM PDT 24
Finished Mar 16 12:20:28 PM PDT 24
Peak memory 212864 kb
Host smart-a44a085e-5219-42e7-be1d-a907cb8f1b19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267577659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.3267577659
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.940672354
Short name T309
Test name
Test status
Simulation time 78206282 ps
CPU time 3.52 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:56 PM PDT 24
Peak memory 213128 kb
Host smart-6ca0694e-67c3-4951-a620-071a5e64c9c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940672354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.940672354
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.783889357
Short name T247
Test name
Test status
Simulation time 37840341 ps
CPU time 2.17 seconds
Started Mar 16 12:20:52 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 212544 kb
Host smart-e4df76dd-af0e-46cf-bdd3-a3999d6e8f20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783889357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.783889357
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.4237785211
Short name T31
Test name
Test status
Simulation time 252133718 ps
CPU time 4.94 seconds
Started Mar 16 12:20:23 PM PDT 24
Finished Mar 16 12:20:28 PM PDT 24
Peak memory 212516 kb
Host smart-fbedb6b5-e78b-4362-a156-4bd7b97bf33d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237785211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.4237785211
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.762119674
Short name T94
Test name
Test status
Simulation time 86619820 ps
CPU time 1.21 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 212412 kb
Host smart-7865c218-8035-453e-ac08-73131f177db1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762119674 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.762119674
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.3238542902
Short name T229
Test name
Test status
Simulation time 20497219 ps
CPU time 1.01 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:32 PM PDT 24
Peak memory 204172 kb
Host smart-405654c1-f35e-4373-a51a-65fe12bb4f68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238542902 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
3238542902
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2708546654
Short name T190
Test name
Test status
Simulation time 8168874 ps
CPU time 0.71 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204100 kb
Host smart-9e182fb9-e8b0-41bb-9731-f696ec0223b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708546654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2708546654
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.4083204074
Short name T220
Test name
Test status
Simulation time 125371985 ps
CPU time 2.07 seconds
Started Mar 16 12:20:26 PM PDT 24
Finished Mar 16 12:20:28 PM PDT 24
Peak memory 204308 kb
Host smart-033e7e18-2f74-46bd-816c-ca44d2df97be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083204074 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.4083204074
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.756706576
Short name T170
Test name
Test status
Simulation time 86173640 ps
CPU time 2.56 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:27 PM PDT 24
Peak memory 217364 kb
Host smart-d92bf15f-b381-407c-979b-40fef5641bde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756706576 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keym
gr_dpe_shadow_reg_errors.756706576
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2207378425
Short name T213
Test name
Test status
Simulation time 124707222 ps
CPU time 5.23 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 221052 kb
Host smart-dc21aaed-9b86-4fe0-a28b-3f0b05417ee8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207378425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2207378425
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.718890531
Short name T50
Test name
Test status
Simulation time 137731154 ps
CPU time 2.61 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:38 PM PDT 24
Peak memory 212540 kb
Host smart-23f48647-0dd4-4dc0-9a2e-49ddebd5c4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718890531 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.718890531
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.2659077641
Short name T250
Test name
Test status
Simulation time 64357073 ps
CPU time 1.12 seconds
Started Mar 16 12:21:03 PM PDT 24
Finished Mar 16 12:21:04 PM PDT 24
Peak memory 204400 kb
Host smart-76df09a3-7372-4d3a-b999-89b40e9ce7db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659077641 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.2659077641
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.416485083
Short name T180
Test name
Test status
Simulation time 11734464 ps
CPU time 0.78 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 204064 kb
Host smart-50efec79-8f33-4b42-8cfb-9e3b85894c11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416485083 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.416485083
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2978958571
Short name T261
Test name
Test status
Simulation time 11528880 ps
CPU time 0.8 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 204048 kb
Host smart-ba45aeaa-19b1-40d7-bd2b-16b47856fbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978958571 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2978958571
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3909316059
Short name T183
Test name
Test status
Simulation time 40838940 ps
CPU time 1.1 seconds
Started Mar 16 12:20:59 PM PDT 24
Finished Mar 16 12:21:00 PM PDT 24
Peak memory 204312 kb
Host smart-d18c4e9b-1d22-401f-a75e-185e628b5e92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909316059 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3909316059
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2773690404
Short name T221
Test name
Test status
Simulation time 144565582 ps
CPU time 1.53 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204384 kb
Host smart-5a69de9f-1e07-49b1-8314-5b7ebf9eb8d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773690404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2773690404
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1296660895
Short name T63
Test name
Test status
Simulation time 115892543 ps
CPU time 2.83 seconds
Started Mar 16 12:21:00 PM PDT 24
Finished Mar 16 12:21:03 PM PDT 24
Peak memory 212908 kb
Host smart-2f40a72d-661a-408f-b6bc-c70ebd707cec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296660895 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1296660895
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2164993493
Short name T51
Test name
Test status
Simulation time 143399246 ps
CPU time 4.61 seconds
Started Mar 16 12:21:35 PM PDT 24
Finished Mar 16 12:21:40 PM PDT 24
Peak memory 211356 kb
Host smart-cd2e5214-6efa-4e35-8d69-509a8125d44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164993493 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2164993493
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.3021964673
Short name T20
Test name
Test status
Simulation time 38862100 ps
CPU time 1.26 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 214472 kb
Host smart-a70cde9f-10db-4986-9ca1-50dcafd2da8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021964673 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.3021964673
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1668259206
Short name T64
Test name
Test status
Simulation time 60512096 ps
CPU time 1.06 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:54 PM PDT 24
Peak memory 204336 kb
Host smart-4513e7ac-0aa4-4c74-b7e9-79c8db7055a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668259206 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1668259206
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3138586726
Short name T284
Test name
Test status
Simulation time 12384069 ps
CPU time 0.84 seconds
Started Mar 16 12:21:01 PM PDT 24
Finished Mar 16 12:21:02 PM PDT 24
Peak memory 204180 kb
Host smart-a3071ed9-14c5-48a8-9ed4-6efdb19a6a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138586726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
3138586726
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.1125839073
Short name T171
Test name
Test status
Simulation time 480688408 ps
CPU time 1.35 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 204288 kb
Host smart-a8007750-ed1b-4a72-9cc4-12ef0229636d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125839073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.1125839073
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.3970398844
Short name T235
Test name
Test status
Simulation time 151130270 ps
CPU time 2.15 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:50 PM PDT 24
Peak memory 212824 kb
Host smart-c08895d9-1a49-4046-9fb0-2ebbd52660c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970398844 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.3970398844
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3979331481
Short name T194
Test name
Test status
Simulation time 63866537 ps
CPU time 2.45 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:34 PM PDT 24
Peak memory 212884 kb
Host smart-e2a75449-72c4-4321-b639-f2b4a51c1e10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979331481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3979331481
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.211730443
Short name T300
Test name
Test status
Simulation time 103311057 ps
CPU time 1.79 seconds
Started Mar 16 12:20:50 PM PDT 24
Finished Mar 16 12:20:53 PM PDT 24
Peak memory 212648 kb
Host smart-9881f30d-701e-4089-a4e8-ea6fcaba41e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211730443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.211730443
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2783167749
Short name T68
Test name
Test status
Simulation time 14101129 ps
CPU time 0.81 seconds
Started Mar 16 12:21:06 PM PDT 24
Finished Mar 16 12:21:07 PM PDT 24
Peak memory 204220 kb
Host smart-9288f138-677c-4563-8e97-cd2e5be93266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783167749 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2783167749
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.657141855
Short name T302
Test name
Test status
Simulation time 37096666 ps
CPU time 1.27 seconds
Started Mar 16 12:20:55 PM PDT 24
Finished Mar 16 12:20:57 PM PDT 24
Peak memory 204328 kb
Host smart-9f0eb57a-85bd-44dc-ae08-cdb1aef5936e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657141855 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.657141855
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2505745990
Short name T255
Test name
Test status
Simulation time 9684775 ps
CPU time 0.8 seconds
Started Mar 16 12:21:00 PM PDT 24
Finished Mar 16 12:21:01 PM PDT 24
Peak memory 204224 kb
Host smart-3cb9fdeb-6d4b-482f-ab99-212378893ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505745990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2505745990
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.81475789
Short name T303
Test name
Test status
Simulation time 31915682 ps
CPU time 1.06 seconds
Started Mar 16 12:21:01 PM PDT 24
Finished Mar 16 12:21:03 PM PDT 24
Peak memory 204276 kb
Host smart-654f924f-c171-433f-95f1-c5d691cf0ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81475789 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=k
eymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ke
ymgr_dpe_same_csr_outstanding.81475789
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1946139485
Short name T201
Test name
Test status
Simulation time 136917588 ps
CPU time 3.32 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:22:00 PM PDT 24
Peak memory 212768 kb
Host smart-3007582c-21d4-49bf-91be-cb694d962d04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946139485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1946139485
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2839212096
Short name T225
Test name
Test status
Simulation time 277948711 ps
CPU time 5.99 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:21:02 PM PDT 24
Peak memory 217748 kb
Host smart-44a849d6-6b43-4591-a631-6547cf1555f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839212096 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.2839212096
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.849851800
Short name T268
Test name
Test status
Simulation time 649736270 ps
CPU time 2.87 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:59 PM PDT 24
Peak memory 212564 kb
Host smart-67c50d91-1f53-4850-ac57-1363e79e85ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849851800 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.849851800
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.3488517389
Short name T46
Test name
Test status
Simulation time 322580418 ps
CPU time 3.32 seconds
Started Mar 16 12:21:03 PM PDT 24
Finished Mar 16 12:21:06 PM PDT 24
Peak memory 212540 kb
Host smart-d1996417-fb61-4944-a59b-f8a78c6e1e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488517389 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.3488517389
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.219852506
Short name T191
Test name
Test status
Simulation time 22613381 ps
CPU time 1.24 seconds
Started Mar 16 12:21:02 PM PDT 24
Finished Mar 16 12:21:03 PM PDT 24
Peak memory 204396 kb
Host smart-ffed7588-be02-46aa-bbca-ee5e0f463261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219852506 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.219852506
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3202498523
Short name T281
Test name
Test status
Simulation time 35118327 ps
CPU time 0.84 seconds
Started Mar 16 12:20:39 PM PDT 24
Finished Mar 16 12:20:40 PM PDT 24
Peak memory 204172 kb
Host smart-0465e474-3366-4680-b962-81524d46fcb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202498523 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3202498523
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.879685180
Short name T275
Test name
Test status
Simulation time 38098519 ps
CPU time 0.69 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204124 kb
Host smart-99fd102f-a95f-45d6-a256-ecc181ce4964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879685180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.879685180
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1522445497
Short name T256
Test name
Test status
Simulation time 93512676 ps
CPU time 1.95 seconds
Started Mar 16 12:21:01 PM PDT 24
Finished Mar 16 12:21:03 PM PDT 24
Peak memory 204240 kb
Host smart-21090090-057c-43b4-9068-ce3f00014b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522445497 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1522445497
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3314393276
Short name T172
Test name
Test status
Simulation time 60077147 ps
CPU time 1.31 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 212940 kb
Host smart-1b44b05c-9075-4abc-942b-c60c60891a22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314393276 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3314393276
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2179847618
Short name T176
Test name
Test status
Simulation time 502497053 ps
CPU time 3.61 seconds
Started Mar 16 12:21:06 PM PDT 24
Finished Mar 16 12:21:10 PM PDT 24
Peak memory 212928 kb
Host smart-773f4a1f-e0f4-4ab1-ab85-855971ee5091
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179847618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.2179847618
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1842075688
Short name T232
Test name
Test status
Simulation time 97109059 ps
CPU time 1.47 seconds
Started Mar 16 12:21:03 PM PDT 24
Finished Mar 16 12:21:05 PM PDT 24
Peak memory 214780 kb
Host smart-edacce15-a097-4bb2-ad0a-9a5c2e9779f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842075688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1842075688
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2587130625
Short name T52
Test name
Test status
Simulation time 174939787 ps
CPU time 2.08 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 212500 kb
Host smart-dc299da8-90c7-4af0-afb3-3a8d7403aa23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587130625 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.2587130625
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.3135981023
Short name T234
Test name
Test status
Simulation time 60428580 ps
CPU time 1.22 seconds
Started Mar 16 12:20:59 PM PDT 24
Finished Mar 16 12:21:00 PM PDT 24
Peak memory 212620 kb
Host smart-098905c5-f741-4199-8df6-4970c898e5a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135981023 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.3135981023
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.3077695006
Short name T207
Test name
Test status
Simulation time 24042015 ps
CPU time 0.98 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204152 kb
Host smart-4f29c989-08bf-439c-bf38-89ade602fdcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077695006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
3077695006
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2291053236
Short name T241
Test name
Test status
Simulation time 8617710 ps
CPU time 0.74 seconds
Started Mar 16 12:21:05 PM PDT 24
Finished Mar 16 12:21:07 PM PDT 24
Peak memory 204136 kb
Host smart-b2343188-4dc1-40a2-8835-de88e25c5b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291053236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2291053236
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.262366280
Short name T178
Test name
Test status
Simulation time 278918271 ps
CPU time 2.79 seconds
Started Mar 16 12:20:58 PM PDT 24
Finished Mar 16 12:21:01 PM PDT 24
Peak memory 204244 kb
Host smart-6adba3bd-cffd-41a4-a6c2-0650ab7623ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262366280 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.262366280
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.1444307441
Short name T185
Test name
Test status
Simulation time 1296585322 ps
CPU time 2.43 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:27 PM PDT 24
Peak memory 212976 kb
Host smart-d4e4708b-8d10-49ce-80f0-b02750bc66aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444307441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.1444307441
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.371525771
Short name T192
Test name
Test status
Simulation time 1000197462 ps
CPU time 4.81 seconds
Started Mar 16 12:20:26 PM PDT 24
Finished Mar 16 12:20:31 PM PDT 24
Peak memory 212716 kb
Host smart-9a6a058d-b5d1-4004-9ac6-ed9c30b9a283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371525771 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.371525771
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.182963395
Short name T257
Test name
Test status
Simulation time 362526638 ps
CPU time 3.1 seconds
Started Mar 16 12:20:39 PM PDT 24
Finished Mar 16 12:20:42 PM PDT 24
Peak memory 212448 kb
Host smart-0f0a6dfc-f06c-4676-8789-7db31ce71664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182963395 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.182963395
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1377014091
Short name T287
Test name
Test status
Simulation time 178974336 ps
CPU time 2.97 seconds
Started Mar 16 12:20:26 PM PDT 24
Finished Mar 16 12:20:29 PM PDT 24
Peak memory 204244 kb
Host smart-b633b2dc-2ad5-40f5-ba6f-b5bac812a7b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377014091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.1377014091
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3945779468
Short name T276
Test name
Test status
Simulation time 780447864 ps
CPU time 5.78 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:51 PM PDT 24
Peak memory 204312 kb
Host smart-de1a37ed-9fd5-4f3e-97e3-48b054ca9c9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945779468 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3945779468
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.280105462
Short name T295
Test name
Test status
Simulation time 34626879 ps
CPU time 0.97 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 204092 kb
Host smart-27bed19b-3436-4ab5-97ed-c0756a2a829c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280105462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_hw_reset.280105462
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2584266456
Short name T92
Test name
Test status
Simulation time 25531239 ps
CPU time 0.9 seconds
Started Mar 16 12:20:14 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 204160 kb
Host smart-246a6cd8-a053-47a8-8208-865b86518221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584266456 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2584266456
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1868285696
Short name T187
Test name
Test status
Simulation time 26268924 ps
CPU time 0.82 seconds
Started Mar 16 12:20:36 PM PDT 24
Finished Mar 16 12:20:37 PM PDT 24
Peak memory 204116 kb
Host smart-21bee558-4d84-44cf-81bc-77e87f788788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868285696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
868285696
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.2090877793
Short name T227
Test name
Test status
Simulation time 8822440 ps
CPU time 0.8 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204084 kb
Host smart-c3ef6eb3-486b-4346-9dd8-eef83fd5d11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090877793 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.2
090877793
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.4182951885
Short name T285
Test name
Test status
Simulation time 101860074 ps
CPU time 1.53 seconds
Started Mar 16 12:20:33 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 204276 kb
Host smart-d1557b6f-c6f5-4183-8ed7-ed890abb30ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182951885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.4182951885
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.1931491231
Short name T186
Test name
Test status
Simulation time 125583166 ps
CPU time 1.57 seconds
Started Mar 16 12:20:32 PM PDT 24
Finished Mar 16 12:20:34 PM PDT 24
Peak memory 212748 kb
Host smart-bcaefe2c-be02-4f13-9580-aa4d47ea8f88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931491231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.1931491231
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1448491878
Short name T243
Test name
Test status
Simulation time 93857276 ps
CPU time 2.73 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 213004 kb
Host smart-dd54977d-1a83-452b-b420-65df334dd506
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448491878 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1448491878
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.1369718623
Short name T35
Test name
Test status
Simulation time 351515541 ps
CPU time 3.36 seconds
Started Mar 16 12:20:23 PM PDT 24
Finished Mar 16 12:20:27 PM PDT 24
Peak memory 212528 kb
Host smart-0ee14b68-8a56-4f45-aec8-2b786e83c4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369718623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.1
369718623
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2689468441
Short name T273
Test name
Test status
Simulation time 9279411 ps
CPU time 0.68 seconds
Started Mar 16 12:21:02 PM PDT 24
Finished Mar 16 12:21:02 PM PDT 24
Peak memory 204104 kb
Host smart-0c50081a-ee33-4b1c-a18e-ce6c6ab8b941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689468441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2689468441
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.262581292
Short name T38
Test name
Test status
Simulation time 52105695 ps
CPU time 0.71 seconds
Started Mar 16 12:20:38 PM PDT 24
Finished Mar 16 12:20:38 PM PDT 24
Peak memory 204092 kb
Host smart-3cfa1dc6-2940-480e-8624-078e31d1e534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262581292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.262581292
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3688682236
Short name T71
Test name
Test status
Simulation time 13043095 ps
CPU time 0.73 seconds
Started Mar 16 12:20:40 PM PDT 24
Finished Mar 16 12:20:41 PM PDT 24
Peak memory 204180 kb
Host smart-25128bae-b0a6-44fa-80ab-5e70fef3e209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688682236 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3688682236
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.56734123
Short name T246
Test name
Test status
Simulation time 28545241 ps
CPU time 0.79 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204116 kb
Host smart-3852b69a-25f2-4122-baae-2db4eeb469bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56734123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.56734123
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.763268926
Short name T211
Test name
Test status
Simulation time 16193410 ps
CPU time 0.82 seconds
Started Mar 16 12:20:39 PM PDT 24
Finished Mar 16 12:20:40 PM PDT 24
Peak memory 204056 kb
Host smart-8cbda8c6-3577-4c20-bcfe-221c38d06cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763268926 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.763268926
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.70326507
Short name T196
Test name
Test status
Simulation time 41463477 ps
CPU time 0.69 seconds
Started Mar 16 12:20:42 PM PDT 24
Finished Mar 16 12:20:43 PM PDT 24
Peak memory 204168 kb
Host smart-b23dec6e-ca0b-4330-a06f-ad96e126f8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70326507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.70326507
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3000244318
Short name T37
Test name
Test status
Simulation time 14429497 ps
CPU time 0.76 seconds
Started Mar 16 12:20:55 PM PDT 24
Finished Mar 16 12:20:56 PM PDT 24
Peak memory 204188 kb
Host smart-3b12e900-52b8-4c79-a2a4-ff707e616506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000244318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3000244318
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.3179687795
Short name T215
Test name
Test status
Simulation time 9020077 ps
CPU time 0.78 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204160 kb
Host smart-7aea6e3a-8451-4d55-ab34-f1d8f78b49bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179687795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
3179687795
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.4033181901
Short name T269
Test name
Test status
Simulation time 32605885 ps
CPU time 0.68 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:48 PM PDT 24
Peak memory 204064 kb
Host smart-bec8bc17-c959-4ba2-861d-035f44d709ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033181901 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
4033181901
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.1863043195
Short name T181
Test name
Test status
Simulation time 12806429 ps
CPU time 0.73 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:34 PM PDT 24
Peak memory 204080 kb
Host smart-50fdad0c-f682-4b06-8d0c-01be33d8560e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863043195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
1863043195
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.3695458666
Short name T212
Test name
Test status
Simulation time 192445679 ps
CPU time 2.47 seconds
Started Mar 16 12:20:39 PM PDT 24
Finished Mar 16 12:20:42 PM PDT 24
Peak memory 204276 kb
Host smart-7da2533c-f923-42ed-9e15-8e1a106a95d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695458666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.3695458666
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.2083576795
Short name T233
Test name
Test status
Simulation time 172468736 ps
CPU time 9.73 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:59 PM PDT 24
Peak memory 204340 kb
Host smart-7a0151bc-1451-4827-b71d-e650d76012f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083576795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.2083576795
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.3954744252
Short name T65
Test name
Test status
Simulation time 20816554 ps
CPU time 0.92 seconds
Started Mar 16 12:20:25 PM PDT 24
Finished Mar 16 12:20:26 PM PDT 24
Peak memory 204144 kb
Host smart-13840ce6-4aec-49b4-9173-f72d0dc58db8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954744252 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.3954744252
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4246053342
Short name T40
Test name
Test status
Simulation time 77618955 ps
CPU time 1.43 seconds
Started Mar 16 12:20:33 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 212624 kb
Host smart-9880d34c-d3d9-4ba0-bfd1-f1af67760bd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246053342 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.4246053342
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.2619411788
Short name T299
Test name
Test status
Simulation time 13087093 ps
CPU time 1.09 seconds
Started Mar 16 12:20:14 PM PDT 24
Finished Mar 16 12:20:15 PM PDT 24
Peak memory 204268 kb
Host smart-7d405e81-b446-4e95-91a6-25508e8dcc4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619411788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.2
619411788
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.881860318
Short name T238
Test name
Test status
Simulation time 19029772 ps
CPU time 0.85 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:57 PM PDT 24
Peak memory 204160 kb
Host smart-daf76948-625c-41b3-bead-103e1a73f1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881860318 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.881860318
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3508044738
Short name T270
Test name
Test status
Simulation time 32112526 ps
CPU time 2.04 seconds
Started Mar 16 12:21:10 PM PDT 24
Finished Mar 16 12:21:12 PM PDT 24
Peak memory 204256 kb
Host smart-a807cc68-de1b-4532-a0c0-7f3f0b62669e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508044738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.3508044738
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3069951737
Short name T218
Test name
Test status
Simulation time 119260325 ps
CPU time 2.86 seconds
Started Mar 16 12:20:28 PM PDT 24
Finished Mar 16 12:20:31 PM PDT 24
Peak memory 212800 kb
Host smart-e613a49a-f13d-4b15-ba25-356c34071a05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069951737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3069951737
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.4032278726
Short name T188
Test name
Test status
Simulation time 124508247 ps
CPU time 3.41 seconds
Started Mar 16 12:20:18 PM PDT 24
Finished Mar 16 12:20:22 PM PDT 24
Peak memory 212824 kb
Host smart-5c7884e3-2559-450f-92f9-1f029840c79d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032278726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.4032278726
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.2632941060
Short name T224
Test name
Test status
Simulation time 38329836 ps
CPU time 2.24 seconds
Started Mar 16 12:20:49 PM PDT 24
Finished Mar 16 12:20:52 PM PDT 24
Peak memory 212536 kb
Host smart-5df20280-8e7a-4e01-8865-dd7186b052e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632941060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.2
632941060
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.731951444
Short name T49
Test name
Test status
Simulation time 852819025 ps
CPU time 5.39 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 214048 kb
Host smart-f87f8f03-4cbc-4dc5-a925-062c34aacccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731951444 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_
tl_intg_err.731951444
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1051688108
Short name T260
Test name
Test status
Simulation time 89736225 ps
CPU time 0.79 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:48 PM PDT 24
Peak memory 204208 kb
Host smart-f2458e0d-c747-4f9c-8dc7-71f3134af906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051688108 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
1051688108
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.2639766006
Short name T280
Test name
Test status
Simulation time 57584073 ps
CPU time 0.78 seconds
Started Mar 16 12:20:51 PM PDT 24
Finished Mar 16 12:20:53 PM PDT 24
Peak memory 204144 kb
Host smart-197099b6-296b-44af-88a9-c270c84bb6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639766006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
2639766006
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.771585931
Short name T265
Test name
Test status
Simulation time 31733924 ps
CPU time 0.73 seconds
Started Mar 16 12:20:48 PM PDT 24
Finished Mar 16 12:20:49 PM PDT 24
Peak memory 204064 kb
Host smart-68824583-821a-4909-a79d-b521e6e64250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771585931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.771585931
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3028056818
Short name T214
Test name
Test status
Simulation time 12535537 ps
CPU time 0.69 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204052 kb
Host smart-bba5ae54-94b9-4913-91c3-87068d36b9e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028056818 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3028056818
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.652510224
Short name T66
Test name
Test status
Simulation time 14548454 ps
CPU time 0.73 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204088 kb
Host smart-47710a18-9e8c-4595-a176-eda1b5f707cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652510224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.652510224
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.1501919113
Short name T91
Test name
Test status
Simulation time 9684928 ps
CPU time 0.87 seconds
Started Mar 16 12:20:56 PM PDT 24
Finished Mar 16 12:20:57 PM PDT 24
Peak memory 204176 kb
Host smart-6da344d2-31c9-41b7-885b-d95e8db0be23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501919113 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
1501919113
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.644898269
Short name T223
Test name
Test status
Simulation time 9444996 ps
CPU time 0.76 seconds
Started Mar 16 12:20:59 PM PDT 24
Finished Mar 16 12:21:00 PM PDT 24
Peak memory 204140 kb
Host smart-14b71167-7a54-4d12-bdf3-aae0fdc44139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644898269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.644898269
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2974207993
Short name T298
Test name
Test status
Simulation time 39568265 ps
CPU time 0.82 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204128 kb
Host smart-7b5049e8-ffee-4802-b488-94da0aeb76b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974207993 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2974207993
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1500925508
Short name T291
Test name
Test status
Simulation time 440017673 ps
CPU time 7.06 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:21:00 PM PDT 24
Peak memory 204256 kb
Host smart-4b262479-6149-45e6-8d74-47569f2ecec6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500925508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1500925508
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3960664289
Short name T263
Test name
Test status
Simulation time 9527374713 ps
CPU time 12.89 seconds
Started Mar 16 12:20:23 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204464 kb
Host smart-d87c90ec-260d-4f59-b19c-9e3ed6401893
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960664289 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3960664289
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3455503088
Short name T175
Test name
Test status
Simulation time 148382418 ps
CPU time 0.87 seconds
Started Mar 16 12:20:25 PM PDT 24
Finished Mar 16 12:20:26 PM PDT 24
Peak memory 204104 kb
Host smart-68e87e91-926f-4f92-a7e4-c66985360ee4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455503088 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3455503088
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.3993222077
Short name T19
Test name
Test status
Simulation time 21398916 ps
CPU time 1.06 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:54 PM PDT 24
Peak memory 204344 kb
Host smart-c4862e33-4c08-491e-adfd-7f387c9bcda5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993222077 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.3993222077
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.355065249
Short name T208
Test name
Test status
Simulation time 17975649 ps
CPU time 0.91 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:25 PM PDT 24
Peak memory 204168 kb
Host smart-6aa1fda0-fb8d-48e1-8a71-317032370e39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355065249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.355065249
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1655891345
Short name T111
Test name
Test status
Simulation time 15617404 ps
CPU time 0.84 seconds
Started Mar 16 12:20:17 PM PDT 24
Finished Mar 16 12:20:18 PM PDT 24
Peak memory 204320 kb
Host smart-679c17d6-a68b-430f-9ad5-2aaafe6f64d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655891345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
655891345
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3239122929
Short name T259
Test name
Test status
Simulation time 76445878 ps
CPU time 3.07 seconds
Started Mar 16 12:20:27 PM PDT 24
Finished Mar 16 12:20:30 PM PDT 24
Peak memory 204240 kb
Host smart-04a0d708-b020-4306-9030-926edfd33648
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239122929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.3239122929
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1847952654
Short name T289
Test name
Test status
Simulation time 258055055 ps
CPU time 1.94 seconds
Started Mar 16 12:20:30 PM PDT 24
Finished Mar 16 12:20:32 PM PDT 24
Peak memory 212764 kb
Host smart-7423eaab-1a73-4896-85d9-89edb547b22f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847952654 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1847952654
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3068490006
Short name T264
Test name
Test status
Simulation time 369916681 ps
CPU time 5.02 seconds
Started Mar 16 12:20:40 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 212848 kb
Host smart-24448af6-3800-4a3a-a071-3324cbf5ff8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068490006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.3068490006
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.4160911185
Short name T262
Test name
Test status
Simulation time 209930438 ps
CPU time 3.46 seconds
Started Mar 16 12:20:14 PM PDT 24
Finished Mar 16 12:20:18 PM PDT 24
Peak memory 214748 kb
Host smart-41818a68-3df3-4bf8-aee1-f13426f7530f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160911185 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.4
160911185
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3495887522
Short name T58
Test name
Test status
Simulation time 117036285 ps
CPU time 2.86 seconds
Started Mar 16 12:21:13 PM PDT 24
Finished Mar 16 12:21:16 PM PDT 24
Peak memory 213480 kb
Host smart-a05e5f91-2dd1-45d2-89c7-fcee2facd090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495887522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.3495887522
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.1252279459
Short name T219
Test name
Test status
Simulation time 11042677 ps
CPU time 0.81 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204088 kb
Host smart-ab67d750-36d2-43f2-92c0-f818b4fecfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252279459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
1252279459
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.3977261680
Short name T271
Test name
Test status
Simulation time 45239597 ps
CPU time 0.73 seconds
Started Mar 16 12:20:31 PM PDT 24
Finished Mar 16 12:20:32 PM PDT 24
Peak memory 203980 kb
Host smart-e3b2cb2f-93ed-4a7d-b329-aa02c692512d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977261680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
3977261680
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.4063645880
Short name T69
Test name
Test status
Simulation time 38814857 ps
CPU time 0.71 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204132 kb
Host smart-96ed527b-78e9-461b-a5a8-c56af9ff6e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063645880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
4063645880
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2066900998
Short name T244
Test name
Test status
Simulation time 37574530 ps
CPU time 0.71 seconds
Started Mar 16 12:20:47 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204108 kb
Host smart-fdbeaf24-fac3-4186-bf21-3354f61d3c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066900998 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2066900998
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1194786627
Short name T206
Test name
Test status
Simulation time 133149800 ps
CPU time 0.71 seconds
Started Mar 16 12:20:57 PM PDT 24
Finished Mar 16 12:20:58 PM PDT 24
Peak memory 204232 kb
Host smart-db4b6741-8237-4fdc-9ce1-76a1b747a203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194786627 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1194786627
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3573057008
Short name T113
Test name
Test status
Simulation time 21660825 ps
CPU time 0.79 seconds
Started Mar 16 12:20:36 PM PDT 24
Finished Mar 16 12:20:37 PM PDT 24
Peak memory 204060 kb
Host smart-dbae8d14-bc12-4cc2-985c-6ea68228a5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573057008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
3573057008
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.504096066
Short name T184
Test name
Test status
Simulation time 18642376 ps
CPU time 0.92 seconds
Started Mar 16 12:20:32 PM PDT 24
Finished Mar 16 12:20:33 PM PDT 24
Peak memory 204264 kb
Host smart-fc2c1040-ec0c-4d06-9eaf-cf704c05e750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504096066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.504096066
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3648164067
Short name T282
Test name
Test status
Simulation time 27148424 ps
CPU time 0.69 seconds
Started Mar 16 12:20:53 PM PDT 24
Finished Mar 16 12:20:53 PM PDT 24
Peak memory 204176 kb
Host smart-703c0665-7eb8-4395-8446-301e4e62260c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648164067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3648164067
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.863476611
Short name T216
Test name
Test status
Simulation time 33204599 ps
CPU time 0.75 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 204140 kb
Host smart-ff70f910-1fb6-429b-8311-ecc374cce650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863476611 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.863476611
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3197389478
Short name T292
Test name
Test status
Simulation time 12694326 ps
CPU time 0.69 seconds
Started Mar 16 12:20:46 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 204164 kb
Host smart-87f9a706-7e94-4790-a62f-0e1b5d44ddb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197389478 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3197389478
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.2528725491
Short name T93
Test name
Test status
Simulation time 71855135 ps
CPU time 0.94 seconds
Started Mar 16 12:20:51 PM PDT 24
Finished Mar 16 12:20:53 PM PDT 24
Peak memory 204176 kb
Host smart-ba08a5a9-86ab-4107-a2ab-beaf015a1de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528725491 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.2528725491
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.4285278721
Short name T249
Test name
Test status
Simulation time 39702415 ps
CPU time 0.75 seconds
Started Mar 16 12:20:06 PM PDT 24
Finished Mar 16 12:20:07 PM PDT 24
Peak memory 204164 kb
Host smart-1fd0ceef-379b-47fa-a837-6f4728dcf227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285278721 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.4
285278721
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.2695743148
Short name T179
Test name
Test status
Simulation time 32600328 ps
CPU time 0.66 seconds
Started Mar 16 12:20:41 PM PDT 24
Finished Mar 16 12:20:41 PM PDT 24
Peak memory 204068 kb
Host smart-a6d5dafb-6265-4d8e-a90e-69b13bd6ca69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695743148 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.2
695743148
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2085783098
Short name T277
Test name
Test status
Simulation time 117903253 ps
CPU time 2.51 seconds
Started Mar 16 12:20:39 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204364 kb
Host smart-cfa5d288-8115-4220-8ce8-8a5c42ce0305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085783098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.2085783098
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1676645651
Short name T202
Test name
Test status
Simulation time 146367163 ps
CPU time 1.76 seconds
Started Mar 16 12:20:45 PM PDT 24
Finished Mar 16 12:20:47 PM PDT 24
Peak memory 212664 kb
Host smart-1562bbf9-84a3-458c-bf08-4d934a475b2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676645651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1676645651
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219088866
Short name T294
Test name
Test status
Simulation time 443622014 ps
CPU time 3.76 seconds
Started Mar 16 12:20:44 PM PDT 24
Finished Mar 16 12:20:48 PM PDT 24
Peak memory 212896 kb
Host smart-5fc2f64b-bb60-476d-8d6d-5e2aa2bcd65e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219088866 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219088866
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.3777628098
Short name T32
Test name
Test status
Simulation time 102760829 ps
CPU time 2.71 seconds
Started Mar 16 12:20:33 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 214868 kb
Host smart-2c453448-ad63-4b73-b75b-058bf354cf24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777628098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.3
777628098
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.3147619144
Short name T307
Test name
Test status
Simulation time 21896128 ps
CPU time 1.17 seconds
Started Mar 16 12:20:17 PM PDT 24
Finished Mar 16 12:20:18 PM PDT 24
Peak memory 204056 kb
Host smart-90bd2b55-1d31-4429-b8ef-520f4f7976ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147619144 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.3147619144
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.3595333165
Short name T195
Test name
Test status
Simulation time 173938573 ps
CPU time 1.03 seconds
Started Mar 16 12:20:11 PM PDT 24
Finished Mar 16 12:20:12 PM PDT 24
Peak memory 204020 kb
Host smart-952575e5-bfd8-4f2f-8596-c1d0e9f75b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595333165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.3
595333165
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1596731633
Short name T193
Test name
Test status
Simulation time 19119284 ps
CPU time 0.74 seconds
Started Mar 16 12:20:30 PM PDT 24
Finished Mar 16 12:20:31 PM PDT 24
Peak memory 204144 kb
Host smart-1d5f0e78-769e-4836-9aed-b2593223ba26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596731633 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
596731633
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2278454530
Short name T85
Test name
Test status
Simulation time 235456254 ps
CPU time 2.55 seconds
Started Mar 16 12:21:10 PM PDT 24
Finished Mar 16 12:21:13 PM PDT 24
Peak memory 204404 kb
Host smart-344854a4-3ee5-4fbf-b2aa-0958360658be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278454530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.2278454530
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.716279345
Short name T173
Test name
Test status
Simulation time 39665040 ps
CPU time 0.99 seconds
Started Mar 16 12:20:33 PM PDT 24
Finished Mar 16 12:20:34 PM PDT 24
Peak memory 212820 kb
Host smart-05fc9e03-041a-4446-bcea-5bc3c809c8ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716279345 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymg
r_dpe_shadow_reg_errors.716279345
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.144218557
Short name T258
Test name
Test status
Simulation time 102486526 ps
CPU time 2.75 seconds
Started Mar 16 12:20:17 PM PDT 24
Finished Mar 16 12:20:20 PM PDT 24
Peak memory 212884 kb
Host smart-5685259b-ffe3-446c-9074-ee776a2200df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144218557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.144218557
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.2991299763
Short name T28
Test name
Test status
Simulation time 40483032 ps
CPU time 2.92 seconds
Started Mar 16 12:20:16 PM PDT 24
Finished Mar 16 12:20:19 PM PDT 24
Peak memory 220568 kb
Host smart-b27443ae-2aba-4788-9ec9-4d05b4b7fe4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991299763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.2
991299763
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.896895822
Short name T217
Test name
Test status
Simulation time 25500866 ps
CPU time 1.18 seconds
Started Mar 16 12:21:22 PM PDT 24
Finished Mar 16 12:21:25 PM PDT 24
Peak memory 204260 kb
Host smart-a7dad03c-b1cb-4345-9c39-16ad73ca58dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896895822 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.896895822
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.2747295741
Short name T251
Test name
Test status
Simulation time 11315392 ps
CPU time 0.83 seconds
Started Mar 16 12:20:07 PM PDT 24
Finished Mar 16 12:20:08 PM PDT 24
Peak memory 204028 kb
Host smart-bcff27b8-c473-4858-bb23-3e1bb93c973a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747295741 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.2
747295741
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2030935348
Short name T304
Test name
Test status
Simulation time 31861912 ps
CPU time 0.68 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 204152 kb
Host smart-c3374d1b-dc5c-41db-8afc-7711b8c2ae09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030935348 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.2
030935348
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1178859078
Short name T272
Test name
Test status
Simulation time 76586506 ps
CPU time 1.33 seconds
Started Mar 16 12:20:27 PM PDT 24
Finished Mar 16 12:20:28 PM PDT 24
Peak memory 204368 kb
Host smart-fded648a-9ad8-4625-bebb-972bbbde667e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178859078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1178859078
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1609129997
Short name T67
Test name
Test status
Simulation time 83978395 ps
CPU time 1.62 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:35 PM PDT 24
Peak memory 212880 kb
Host smart-c2cf4fe7-95d3-4a3e-9146-40bf9e7ef54e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609129997 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1609129997
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1197543964
Short name T43
Test name
Test status
Simulation time 223037789 ps
CPU time 2.9 seconds
Started Mar 16 12:20:26 PM PDT 24
Finished Mar 16 12:20:29 PM PDT 24
Peak memory 212852 kb
Host smart-2ca8fa25-00e8-42f8-b25a-61ce09e8e59b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197543964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1197543964
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2583653267
Short name T47
Test name
Test status
Simulation time 95503040 ps
CPU time 2.08 seconds
Started Mar 16 12:21:22 PM PDT 24
Finished Mar 16 12:21:26 PM PDT 24
Peak memory 220516 kb
Host smart-dd1540e3-70a4-468a-a8f9-707297922894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583653267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
583653267
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.453183551
Short name T45
Test name
Test status
Simulation time 576219178 ps
CPU time 4.77 seconds
Started Mar 16 12:21:22 PM PDT 24
Finished Mar 16 12:21:28 PM PDT 24
Peak memory 213792 kb
Host smart-1d8c4b81-c95a-4ab3-9dde-e8cccc91676c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453183551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_
tl_intg_err.453183551
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.299013029
Short name T267
Test name
Test status
Simulation time 14092929 ps
CPU time 1.31 seconds
Started Mar 16 12:20:24 PM PDT 24
Finished Mar 16 12:20:25 PM PDT 24
Peak memory 215668 kb
Host smart-062e9d66-d3fd-46eb-ba27-f6abf4f5b155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299013029 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.299013029
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.36178743
Short name T189
Test name
Test status
Simulation time 18928341 ps
CPU time 0.83 seconds
Started Mar 16 12:20:50 PM PDT 24
Finished Mar 16 12:20:51 PM PDT 24
Peak memory 204144 kb
Host smart-3b59a544-6d17-4796-ac8e-5849898d4506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.36178743
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.1252971136
Short name T231
Test name
Test status
Simulation time 37098363 ps
CPU time 0.79 seconds
Started Mar 16 12:20:20 PM PDT 24
Finished Mar 16 12:20:21 PM PDT 24
Peak memory 204112 kb
Host smart-db7bcc62-ada3-4f7d-aa10-36543f535b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252971136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.1
252971136
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.2729688703
Short name T95
Test name
Test status
Simulation time 185862226 ps
CPU time 1.88 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204140 kb
Host smart-895aa6c1-aceb-4df9-ba70-7e65745b0a32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729688703 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.2729688703
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1136444457
Short name T182
Test name
Test status
Simulation time 66190167 ps
CPU time 1.39 seconds
Started Mar 16 12:21:10 PM PDT 24
Finished Mar 16 12:21:11 PM PDT 24
Peak memory 212780 kb
Host smart-2c76a519-35fc-45fd-bc86-8dd829449194
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136444457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1136444457
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4171730972
Short name T293
Test name
Test status
Simulation time 1718603996 ps
CPU time 3.05 seconds
Started Mar 16 12:21:35 PM PDT 24
Finished Mar 16 12:21:39 PM PDT 24
Peak memory 211532 kb
Host smart-12a7d2ae-393c-44d2-b8d8-8e614de476d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171730972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4171730972
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.45214889
Short name T222
Test name
Test status
Simulation time 184210458 ps
CPU time 3.27 seconds
Started Mar 16 12:21:22 PM PDT 24
Finished Mar 16 12:21:27 PM PDT 24
Peak memory 212428 kb
Host smart-812eb72d-b159-4332-bb3c-330d7fc97fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45214889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.45214889
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.3762961513
Short name T228
Test name
Test status
Simulation time 462646541 ps
CPU time 1.47 seconds
Started Mar 16 12:20:29 PM PDT 24
Finished Mar 16 12:20:30 PM PDT 24
Peak memory 212440 kb
Host smart-839c8948-400e-405f-8e2b-49dee518d315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762961513 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.3762961513
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.392330128
Short name T210
Test name
Test status
Simulation time 25640873 ps
CPU time 1.05 seconds
Started Mar 16 12:20:54 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 204208 kb
Host smart-f053f73f-e31c-4bb2-a1ac-df4357aef8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392330128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.392330128
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.147189441
Short name T199
Test name
Test status
Simulation time 65397610 ps
CPU time 0.69 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 204064 kb
Host smart-aa93ce93-0b51-4696-a9e0-49577aa4412d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147189441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.147189441
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.3103003922
Short name T252
Test name
Test status
Simulation time 118392180 ps
CPU time 1.63 seconds
Started Mar 16 12:20:43 PM PDT 24
Finished Mar 16 12:20:46 PM PDT 24
Peak memory 204168 kb
Host smart-4e851708-ac8f-4ce8-86c2-62b191c00325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103003922 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.3103003922
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.232930121
Short name T204
Test name
Test status
Simulation time 602503867 ps
CPU time 1.8 seconds
Started Mar 16 12:20:34 PM PDT 24
Finished Mar 16 12:20:36 PM PDT 24
Peak memory 212664 kb
Host smart-f07cc625-37b5-4662-a016-fd88d6220a50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232930121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymg
r_dpe_shadow_reg_errors.232930121
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2344194168
Short name T83
Test name
Test status
Simulation time 344986042 ps
CPU time 9.38 seconds
Started Mar 16 12:20:35 PM PDT 24
Finished Mar 16 12:20:45 PM PDT 24
Peak memory 217972 kb
Host smart-65080965-3b51-4d1d-8d70-0f2d705cb6d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344194168 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2344194168
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3939961027
Short name T266
Test name
Test status
Simulation time 175391806 ps
CPU time 3.1 seconds
Started Mar 16 12:20:27 PM PDT 24
Finished Mar 16 12:20:30 PM PDT 24
Peak memory 220712 kb
Host smart-ec0f10cc-326a-4f7a-a147-deebb46ce331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939961027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
939961027
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.241930276
Short name T59
Test name
Test status
Simulation time 77456773 ps
CPU time 3.05 seconds
Started Mar 16 12:20:52 PM PDT 24
Finished Mar 16 12:20:55 PM PDT 24
Peak memory 212488 kb
Host smart-d7df847c-220c-4f75-9a31-993071f6b31e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241930276 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_
tl_intg_err.241930276
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2240784904
Short name T134
Test name
Test status
Simulation time 12694174 ps
CPU time 0.68 seconds
Started Mar 16 04:33:55 PM PDT 24
Finished Mar 16 04:33:56 PM PDT 24
Peak memory 205376 kb
Host smart-9af365f5-f438-4a4d-8f3a-d399c77fec9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240784904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
240784904
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.1614264149
Short name T25
Test name
Test status
Simulation time 731716723 ps
CPU time 10.3 seconds
Started Mar 16 04:33:49 PM PDT 24
Finished Mar 16 04:33:59 PM PDT 24
Peak memory 233864 kb
Host smart-28a24dc8-8f90-44fd-8874-36ec80caa484
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614264149 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.1614264149
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.1629414770
Short name T145
Test name
Test status
Simulation time 179848520 ps
CPU time 0.86 seconds
Started Mar 16 04:33:54 PM PDT 24
Finished Mar 16 04:33:55 PM PDT 24
Peak memory 205380 kb
Host smart-a94c593e-88e4-45db-957c-8013c8d213ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629414770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.1
629414770
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2086690979
Short name T6
Test name
Test status
Simulation time 1450678511 ps
CPU time 10.91 seconds
Started Mar 16 04:33:52 PM PDT 24
Finished Mar 16 04:34:03 PM PDT 24
Peak memory 230820 kb
Host smart-c28da080-9307-4ab4-ab60-781ebff22ad3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086690979 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2086690979
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.987941087
Short name T126
Test name
Test status
Simulation time 8653554 ps
CPU time 0.72 seconds
Started Mar 16 04:34:06 PM PDT 24
Finished Mar 16 04:34:07 PM PDT 24
Peak memory 205300 kb
Host smart-1c0cbe30-f2e1-4a82-8041-2bf9846eff24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987941087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.987941087
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.143919433
Short name T140
Test name
Test status
Simulation time 21158362 ps
CPU time 0.98 seconds
Started Mar 16 04:34:06 PM PDT 24
Finished Mar 16 04:34:07 PM PDT 24
Peak memory 205480 kb
Host smart-305b08ab-7eda-4122-a4fb-f79ccb4d9c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143919433 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.143919433
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.700845004
Short name T10
Test name
Test status
Simulation time 6056883140 ps
CPU time 30.35 seconds
Started Mar 16 04:34:06 PM PDT 24
Finished Mar 16 04:34:36 PM PDT 24
Peak memory 208204 kb
Host smart-84554d72-75eb-4ef1-a13e-a4f1cb71f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700845004 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.700845004
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.3696386994
Short name T142
Test name
Test status
Simulation time 69357735 ps
CPU time 0.86 seconds
Started Mar 16 04:34:09 PM PDT 24
Finished Mar 16 04:34:10 PM PDT 24
Peak memory 205256 kb
Host smart-4e9254af-cd08-4044-9a58-58afd0850c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696386994 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
3696386994
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2787491622
Short name T123
Test name
Test status
Simulation time 2468048414 ps
CPU time 22.25 seconds
Started Mar 16 04:34:08 PM PDT 24
Finished Mar 16 04:34:31 PM PDT 24
Peak memory 206232 kb
Host smart-f1b93957-a159-4c42-8ea4-0ab4e6e10dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787491622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2787491622
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.4033071166
Short name T146
Test name
Test status
Simulation time 33174486 ps
CPU time 0.71 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:08 PM PDT 24
Peak memory 205372 kb
Host smart-cdb61241-bde5-486c-b0a6-92a9751e2a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033071166 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
4033071166
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3121412492
Short name T9
Test name
Test status
Simulation time 1788232928 ps
CPU time 30.5 seconds
Started Mar 16 04:34:09 PM PDT 24
Finished Mar 16 04:34:39 PM PDT 24
Peak memory 208092 kb
Host smart-36744e54-210c-4931-889c-30811dd20141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121412492 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3121412492
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.4267699763
Short name T138
Test name
Test status
Simulation time 46966620 ps
CPU time 0.87 seconds
Started Mar 16 04:34:09 PM PDT 24
Finished Mar 16 04:34:10 PM PDT 24
Peak memory 205276 kb
Host smart-870e7329-f8c8-4b34-bbf9-87f266739f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267699763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
4267699763
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.1844807667
Short name T147
Test name
Test status
Simulation time 6797047565 ps
CPU time 160.89 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:36:48 PM PDT 24
Peak memory 207840 kb
Host smart-ca0b42cf-a0d4-4500-ad19-1e72c4f0d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844807667 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.1844807667
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.3726962322
Short name T161
Test name
Test status
Simulation time 11947967 ps
CPU time 0.77 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:08 PM PDT 24
Peak memory 205376 kb
Host smart-f4d2519a-10ec-404b-8a18-638b22807715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726962322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
3726962322
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.1203734716
Short name T76
Test name
Test status
Simulation time 711944699 ps
CPU time 15.15 seconds
Started Mar 16 04:34:09 PM PDT 24
Finished Mar 16 04:34:24 PM PDT 24
Peak memory 206064 kb
Host smart-95c60690-dc28-4229-b404-c2d060be4947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203734716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.1203734716
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.370087917
Short name T99
Test name
Test status
Simulation time 24679436808 ps
CPU time 46.66 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:54 PM PDT 24
Peak memory 208344 kb
Host smart-f517c3bf-3112-4b39-9567-1ac776062c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370087917 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.370087917
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2587313631
Short name T74
Test name
Test status
Simulation time 39492340 ps
CPU time 0.81 seconds
Started Mar 16 04:34:15 PM PDT 24
Finished Mar 16 04:34:15 PM PDT 24
Peak memory 205304 kb
Host smart-8c28608e-3631-4213-9dc7-fd96d425b616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587313631 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2587313631
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.267499812
Short name T121
Test name
Test status
Simulation time 32484667 ps
CPU time 0.84 seconds
Started Mar 16 04:34:14 PM PDT 24
Finished Mar 16 04:34:15 PM PDT 24
Peak memory 205356 kb
Host smart-b524d708-c343-43b8-bb69-17ce80bb76fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267499812 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.267499812
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.3878153420
Short name T144
Test name
Test status
Simulation time 1598116210 ps
CPU time 16.92 seconds
Started Mar 16 04:34:12 PM PDT 24
Finished Mar 16 04:34:29 PM PDT 24
Peak memory 208216 kb
Host smart-8354f28f-1604-427c-8e22-11cab4e2679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878153420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.3878153420
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.2672774340
Short name T75
Test name
Test status
Simulation time 23745889 ps
CPU time 0.74 seconds
Started Mar 16 04:34:14 PM PDT 24
Finished Mar 16 04:34:14 PM PDT 24
Peak memory 205400 kb
Host smart-022691a6-ceb7-471c-bd1f-513d1581f197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672774340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
2672774340
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.4139299360
Short name T129
Test name
Test status
Simulation time 32459012 ps
CPU time 0.86 seconds
Started Mar 16 04:33:54 PM PDT 24
Finished Mar 16 04:33:54 PM PDT 24
Peak memory 205364 kb
Host smart-e8e52a30-df6c-4a72-a18c-4b1e001cab3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139299360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.4
139299360
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.1429836446
Short name T118
Test name
Test status
Simulation time 55831373 ps
CPU time 0.91 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:22 PM PDT 24
Peak memory 205532 kb
Host smart-6d42f8fb-b2fc-4bf8-bb46-e25368a5a10a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429836446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
1429836446
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.478167262
Short name T153
Test name
Test status
Simulation time 51514737332 ps
CPU time 110.4 seconds
Started Mar 16 04:34:21 PM PDT 24
Finished Mar 16 04:36:12 PM PDT 24
Peak memory 208544 kb
Host smart-b2c32439-a799-4e58-b0f9-5aa06938d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478167262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.478167262
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.1053264424
Short name T154
Test name
Test status
Simulation time 31718107 ps
CPU time 0.76 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:22 PM PDT 24
Peak memory 205376 kb
Host smart-fb6aa66a-c535-4e1f-8e07-6c1192f81170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053264424 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
1053264424
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1685776441
Short name T87
Test name
Test status
Simulation time 1939414273 ps
CPU time 31.4 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:53 PM PDT 24
Peak memory 207432 kb
Host smart-dc95ad96-6d5d-46b6-8593-7b28970b8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685776441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1685776441
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.1000571292
Short name T3
Test name
Test status
Simulation time 12830530 ps
CPU time 0.77 seconds
Started Mar 16 04:34:21 PM PDT 24
Finished Mar 16 04:34:22 PM PDT 24
Peak memory 205396 kb
Host smart-d26d812a-1ba4-4996-b5f5-1415be1760d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000571292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
1000571292
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.246025751
Short name T90
Test name
Test status
Simulation time 1317441307 ps
CPU time 35.87 seconds
Started Mar 16 04:34:21 PM PDT 24
Finished Mar 16 04:34:57 PM PDT 24
Peak memory 207712 kb
Host smart-b1f0c66b-ab8c-4520-a7c3-e71c4433d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246025751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.246025751
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.2196354926
Short name T26
Test name
Test status
Simulation time 49734621 ps
CPU time 0.76 seconds
Started Mar 16 04:34:22 PM PDT 24
Finished Mar 16 04:34:23 PM PDT 24
Peak memory 205224 kb
Host smart-dfd7f1c9-ad0e-4ef2-a602-02b5bc30f59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196354926 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
2196354926
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.2421371281
Short name T77
Test name
Test status
Simulation time 27588525 ps
CPU time 0.73 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:21 PM PDT 24
Peak memory 205360 kb
Host smart-54537d30-0e9d-4957-baef-7e2de2dfb8e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421371281 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
2421371281
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.1822881500
Short name T165
Test name
Test status
Simulation time 5955226268 ps
CPU time 21.5 seconds
Started Mar 16 04:34:20 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 206172 kb
Host smart-5530c664-5cb9-461f-8312-680d6cdc84db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822881500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.1822881500
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1540346367
Short name T155
Test name
Test status
Simulation time 38677780 ps
CPU time 0.71 seconds
Started Mar 16 04:34:29 PM PDT 24
Finished Mar 16 04:34:31 PM PDT 24
Peak memory 205264 kb
Host smart-041571de-24df-4a94-b6dd-1ec63bc33f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540346367 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1540346367
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2300094565
Short name T17
Test name
Test status
Simulation time 11286151 ps
CPU time 0.71 seconds
Started Mar 16 04:34:26 PM PDT 24
Finished Mar 16 04:34:27 PM PDT 24
Peak memory 205384 kb
Host smart-8e7a15f8-5a68-46a2-abe3-969b05affb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300094565 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2300094565
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.1647243950
Short name T120
Test name
Test status
Simulation time 13032429 ps
CPU time 0.74 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:29 PM PDT 24
Peak memory 205352 kb
Host smart-57c7b71e-c8e5-4262-93ce-a0c778666610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647243950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
1647243950
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.2966051581
Short name T149
Test name
Test status
Simulation time 1484020150 ps
CPU time 37.04 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:35:05 PM PDT 24
Peak memory 207516 kb
Host smart-95d5667f-20b6-42d9-8ca2-cabad2f84a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966051581 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.2966051581
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2230640585
Short name T125
Test name
Test status
Simulation time 90851741 ps
CPU time 0.83 seconds
Started Mar 16 04:34:26 PM PDT 24
Finished Mar 16 04:34:27 PM PDT 24
Peak memory 205352 kb
Host smart-021f2ef0-872e-4009-bfcb-06e06ccc643a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230640585 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2230640585
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.1657538750
Short name T108
Test name
Test status
Simulation time 13734605999 ps
CPU time 201.36 seconds
Started Mar 16 04:34:28 PM PDT 24
Finished Mar 16 04:37:50 PM PDT 24
Peak memory 222380 kb
Host smart-52ac5508-0691-4f5b-addd-37e546b67e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657538750 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.1657538750
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.3253240012
Short name T132
Test name
Test status
Simulation time 10992669 ps
CPU time 0.74 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:29 PM PDT 24
Peak memory 205304 kb
Host smart-e1627f15-aa75-4988-8818-72e6062f5fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253240012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
3253240012
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3363508830
Short name T107
Test name
Test status
Simulation time 1813128157 ps
CPU time 30.43 seconds
Started Mar 16 04:34:28 PM PDT 24
Finished Mar 16 04:35:00 PM PDT 24
Peak memory 207124 kb
Host smart-f72a53a2-2e5b-43a9-b526-491a53631d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363508830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3363508830
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.537575794
Short name T168
Test name
Test status
Simulation time 17973473 ps
CPU time 0.87 seconds
Started Mar 16 04:34:02 PM PDT 24
Finished Mar 16 04:34:03 PM PDT 24
Peak memory 205280 kb
Host smart-39ee9733-3491-457c-b516-2222fe9cd208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537575794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.537575794
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1782012014
Short name T157
Test name
Test status
Simulation time 1852739103 ps
CPU time 14.98 seconds
Started Mar 16 04:33:55 PM PDT 24
Finished Mar 16 04:34:10 PM PDT 24
Peak memory 207832 kb
Host smart-995659e2-38d9-4064-bf47-f88b85190a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782012014 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1782012014
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.100664237
Short name T167
Test name
Test status
Simulation time 10539569 ps
CPU time 0.83 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:29 PM PDT 24
Peak memory 205264 kb
Host smart-c9f68fd0-8cd7-4d83-8890-9c9dfc7c34dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100664237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.100664237
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.3294216431
Short name T139
Test name
Test status
Simulation time 40982583 ps
CPU time 0.78 seconds
Started Mar 16 04:34:27 PM PDT 24
Finished Mar 16 04:34:29 PM PDT 24
Peak memory 205376 kb
Host smart-6ed41d11-0343-48cb-a432-caea4d6937ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294216431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
3294216431
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.212233082
Short name T151
Test name
Test status
Simulation time 13746130 ps
CPU time 0.72 seconds
Started Mar 16 04:34:26 PM PDT 24
Finished Mar 16 04:34:28 PM PDT 24
Peak memory 205268 kb
Host smart-b1872b0d-c83b-4392-bb69-00b80211a173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212233082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.212233082
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1472198885
Short name T106
Test name
Test status
Simulation time 5546454516 ps
CPU time 31.91 seconds
Started Mar 16 04:34:25 PM PDT 24
Finished Mar 16 04:34:58 PM PDT 24
Peak memory 207736 kb
Host smart-459c49e0-e2e2-4877-9609-ae8dcd1fdbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472198885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1472198885
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3575956069
Short name T150
Test name
Test status
Simulation time 74622694 ps
CPU time 0.82 seconds
Started Mar 16 04:34:37 PM PDT 24
Finished Mar 16 04:34:40 PM PDT 24
Peak memory 205300 kb
Host smart-4f3020b9-a030-4730-91b0-d6ed58d35b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575956069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3575956069
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.572169248
Short name T141
Test name
Test status
Simulation time 23272233 ps
CPU time 1.11 seconds
Started Mar 16 04:34:37 PM PDT 24
Finished Mar 16 04:34:40 PM PDT 24
Peak memory 205516 kb
Host smart-45311178-2ceb-4e60-a0e6-2b74d922d1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572169248 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.572169248
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.178349196
Short name T12
Test name
Test status
Simulation time 5801187080 ps
CPU time 48.3 seconds
Started Mar 16 04:34:38 PM PDT 24
Finished Mar 16 04:35:27 PM PDT 24
Peak memory 207596 kb
Host smart-963f2a7d-e7cb-4dc1-bd42-dd9e0743a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178349196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.178349196
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.3421018702
Short name T163
Test name
Test status
Simulation time 12226313 ps
CPU time 0.75 seconds
Started Mar 16 04:34:33 PM PDT 24
Finished Mar 16 04:34:35 PM PDT 24
Peak memory 205344 kb
Host smart-5d7c8037-886c-4404-b55b-8feec974ba1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421018702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
3421018702
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3210011023
Short name T127
Test name
Test status
Simulation time 491470657 ps
CPU time 18.83 seconds
Started Mar 16 04:34:37 PM PDT 24
Finished Mar 16 04:34:58 PM PDT 24
Peak memory 206360 kb
Host smart-0d5a3ea8-4ab5-4892-a260-b80b4f922ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210011023 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3210011023
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.2090414157
Short name T133
Test name
Test status
Simulation time 9063245 ps
CPU time 0.81 seconds
Started Mar 16 04:34:39 PM PDT 24
Finished Mar 16 04:34:40 PM PDT 24
Peak memory 205364 kb
Host smart-e36fa930-8171-4ea3-8e93-251973a4d686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090414157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
2090414157
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.3758432179
Short name T80
Test name
Test status
Simulation time 1098693316 ps
CPU time 19.53 seconds
Started Mar 16 04:34:32 PM PDT 24
Finished Mar 16 04:34:52 PM PDT 24
Peak memory 208244 kb
Host smart-3b8af439-0dc7-47e8-87e5-5e51ac5f248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758432179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.3758432179
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.904951471
Short name T130
Test name
Test status
Simulation time 97115577 ps
CPU time 0.81 seconds
Started Mar 16 04:34:43 PM PDT 24
Finished Mar 16 04:34:44 PM PDT 24
Peak memory 205284 kb
Host smart-6d39067d-8059-411e-9451-4dc3e1339075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904951471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.904951471
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.386468234
Short name T4
Test name
Test status
Simulation time 160664068 ps
CPU time 10.56 seconds
Started Mar 16 04:34:32 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 208292 kb
Host smart-71ddeb2f-dfc9-450e-91de-d161350464cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386468234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.386468234
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.1976453427
Short name T166
Test name
Test status
Simulation time 13386613 ps
CPU time 0.79 seconds
Started Mar 16 04:34:38 PM PDT 24
Finished Mar 16 04:34:40 PM PDT 24
Peak memory 205364 kb
Host smart-1df82d48-38b9-40a7-a578-88c315c68c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976453427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
1976453427
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.1272130623
Short name T109
Test name
Test status
Simulation time 2041780000 ps
CPU time 25.15 seconds
Started Mar 16 04:34:32 PM PDT 24
Finished Mar 16 04:34:58 PM PDT 24
Peak memory 207836 kb
Host smart-08eaa307-c9d8-4d37-b8b1-cdecf80f84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272130623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.1272130623
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.4294067501
Short name T152
Test name
Test status
Simulation time 75969455 ps
CPU time 0.7 seconds
Started Mar 16 04:34:34 PM PDT 24
Finished Mar 16 04:34:35 PM PDT 24
Peak memory 205380 kb
Host smart-1d785397-20e1-4af4-8abe-af2e5cae4362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294067501 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
4294067501
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.3407447500
Short name T135
Test name
Test status
Simulation time 778626688 ps
CPU time 17.7 seconds
Started Mar 16 04:34:38 PM PDT 24
Finished Mar 16 04:34:57 PM PDT 24
Peak memory 207164 kb
Host smart-ad53bd22-c504-4182-a148-4607f230a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407447500 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.3407447500
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1165591485
Short name T27
Test name
Test status
Simulation time 12712913 ps
CPU time 0.75 seconds
Started Mar 16 04:34:02 PM PDT 24
Finished Mar 16 04:34:03 PM PDT 24
Peak memory 205236 kb
Host smart-4ae74dc2-fd47-4394-9e17-e7630f1cad24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165591485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
165591485
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.1884874738
Short name T7
Test name
Test status
Simulation time 5254420486 ps
CPU time 15.13 seconds
Started Mar 16 04:34:01 PM PDT 24
Finished Mar 16 04:34:17 PM PDT 24
Peak memory 233036 kb
Host smart-dd6ddd14-661f-405c-89af-6433528bb90e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884874738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.1884874738
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.1561490806
Short name T128
Test name
Test status
Simulation time 599854261 ps
CPU time 14.15 seconds
Started Mar 16 04:34:04 PM PDT 24
Finished Mar 16 04:34:18 PM PDT 24
Peak memory 206236 kb
Host smart-ce64734c-15f0-4631-ab21-ae8a23d8abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561490806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.1561490806
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.2851187397
Short name T117
Test name
Test status
Simulation time 24238025 ps
CPU time 0.8 seconds
Started Mar 16 04:34:33 PM PDT 24
Finished Mar 16 04:34:35 PM PDT 24
Peak memory 205244 kb
Host smart-72cb6c9d-db6d-4d0c-9284-bbee1b3ae1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851187397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
2851187397
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2860826356
Short name T115
Test name
Test status
Simulation time 1470894263 ps
CPU time 16.84 seconds
Started Mar 16 04:34:34 PM PDT 24
Finished Mar 16 04:34:52 PM PDT 24
Peak memory 208132 kb
Host smart-4caf9f25-8056-4a1c-9b53-68ce9b441fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860826356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2860826356
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3678778645
Short name T16
Test name
Test status
Simulation time 11808561 ps
CPU time 0.88 seconds
Started Mar 16 04:34:32 PM PDT 24
Finished Mar 16 04:34:33 PM PDT 24
Peak memory 205352 kb
Host smart-faeedca0-4df2-4fcf-b87d-0d41352f15f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678778645 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3678778645
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.1698610732
Short name T122
Test name
Test status
Simulation time 1485426122 ps
CPU time 27.51 seconds
Started Mar 16 04:34:34 PM PDT 24
Finished Mar 16 04:35:02 PM PDT 24
Peak memory 207536 kb
Host smart-1a7b8a39-2521-46f7-af73-871e62170972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698610732 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.1698610732
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.1795259808
Short name T73
Test name
Test status
Simulation time 11035190 ps
CPU time 0.86 seconds
Started Mar 16 04:34:34 PM PDT 24
Finished Mar 16 04:34:35 PM PDT 24
Peak memory 205320 kb
Host smart-3366a47e-ef5d-4303-aa65-1731a2598d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795259808 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
1795259808
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.3320536191
Short name T158
Test name
Test status
Simulation time 787459927 ps
CPU time 17.62 seconds
Started Mar 16 04:34:33 PM PDT 24
Finished Mar 16 04:34:52 PM PDT 24
Peak memory 207732 kb
Host smart-11cf35cb-df25-422e-aea8-7d3d08076315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320536191 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.3320536191
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.939496168
Short name T156
Test name
Test status
Simulation time 11376171 ps
CPU time 0.9 seconds
Started Mar 16 04:34:34 PM PDT 24
Finished Mar 16 04:34:36 PM PDT 24
Peak memory 205376 kb
Host smart-235eaddc-aea1-4e21-a205-299a0758454b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939496168 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.939496168
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2596270637
Short name T102
Test name
Test status
Simulation time 545372711 ps
CPU time 9.5 seconds
Started Mar 16 04:34:35 PM PDT 24
Finished Mar 16 04:34:44 PM PDT 24
Peak memory 206500 kb
Host smart-06653168-b795-41e0-94d1-b20df93db196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596270637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2596270637
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.1717312375
Short name T136
Test name
Test status
Simulation time 29220040 ps
CPU time 0.69 seconds
Started Mar 16 04:34:43 PM PDT 24
Finished Mar 16 04:34:44 PM PDT 24
Peak memory 205268 kb
Host smart-6c8da7c4-10fe-4261-9fc7-1bbdcd259d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717312375 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
1717312375
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2029526928
Short name T1
Test name
Test status
Simulation time 5832369298 ps
CPU time 89.65 seconds
Started Mar 16 04:34:33 PM PDT 24
Finished Mar 16 04:36:02 PM PDT 24
Peak memory 207772 kb
Host smart-3c89aa21-a104-4b5a-bed8-6567a732dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029526928 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2029526928
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3395961363
Short name T164
Test name
Test status
Simulation time 62963782 ps
CPU time 0.85 seconds
Started Mar 16 04:34:41 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 205376 kb
Host smart-0c8c8c26-fd49-4771-87a0-6c614de5b4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395961363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3395961363
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.3393233981
Short name T86
Test name
Test status
Simulation time 3759018739 ps
CPU time 39.04 seconds
Started Mar 16 04:34:44 PM PDT 24
Finished Mar 16 04:35:24 PM PDT 24
Peak memory 207300 kb
Host smart-8d86dbeb-22fb-469f-839d-6b5b40277929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393233981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.3393233981
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3346561386
Short name T124
Test name
Test status
Simulation time 19496883 ps
CPU time 0.8 seconds
Started Mar 16 04:34:42 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 205332 kb
Host smart-88f3cb15-06dd-420c-a9f4-fde805eadce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346561386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3346561386
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.740668171
Short name T162
Test name
Test status
Simulation time 26757152 ps
CPU time 0.94 seconds
Started Mar 16 04:34:42 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 205528 kb
Host smart-391d5374-2f65-4116-bd24-ec40d11cedbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740668171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.740668171
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.1820454828
Short name T148
Test name
Test status
Simulation time 48664574 ps
CPU time 0.8 seconds
Started Mar 16 04:34:41 PM PDT 24
Finished Mar 16 04:34:43 PM PDT 24
Peak memory 205276 kb
Host smart-153db889-6668-4408-86dc-ec91eedcb20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820454828 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
1820454828
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.609199343
Short name T137
Test name
Test status
Simulation time 397063045 ps
CPU time 14.39 seconds
Started Mar 16 04:34:43 PM PDT 24
Finished Mar 16 04:34:57 PM PDT 24
Peak memory 207736 kb
Host smart-7d546900-02af-4ba4-8162-c55fc43e9feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609199343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.609199343
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.2200747737
Short name T159
Test name
Test status
Simulation time 42574429 ps
CPU time 0.74 seconds
Started Mar 16 04:34:41 PM PDT 24
Finished Mar 16 04:34:42 PM PDT 24
Peak memory 205268 kb
Host smart-6ada55fc-4e9b-45cc-a8d8-f7e1a3c66179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200747737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
2200747737
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.1010176918
Short name T160
Test name
Test status
Simulation time 2502405842 ps
CPU time 19.33 seconds
Started Mar 16 04:34:42 PM PDT 24
Finished Mar 16 04:35:02 PM PDT 24
Peak memory 206600 kb
Host smart-d191b35c-941d-4a16-ad6f-f319369bc0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010176918 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.1010176918
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.729466349
Short name T116
Test name
Test status
Simulation time 12917093 ps
CPU time 0.8 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:07 PM PDT 24
Peak memory 205376 kb
Host smart-1d39c4b1-c92e-4d07-846e-b4ef651335a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729466349 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.729466349
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.4103576947
Short name T23
Test name
Test status
Simulation time 982205069 ps
CPU time 24.9 seconds
Started Mar 16 04:34:02 PM PDT 24
Finished Mar 16 04:34:27 PM PDT 24
Peak memory 206456 kb
Host smart-8a8e3d8d-74b0-4cbc-b1f9-099899543e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103576947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.4103576947
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.2582464676
Short name T119
Test name
Test status
Simulation time 129261535 ps
CPU time 0.78 seconds
Started Mar 16 04:34:07 PM PDT 24
Finished Mar 16 04:34:08 PM PDT 24
Peak memory 205380 kb
Host smart-771e1c8b-760e-42ce-ac28-2f6701de8e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582464676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.2
582464676
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3505299006
Short name T78
Test name
Test status
Simulation time 1187042283 ps
CPU time 21.95 seconds
Started Mar 16 04:34:01 PM PDT 24
Finished Mar 16 04:34:23 PM PDT 24
Peak memory 208176 kb
Host smart-927dffa7-4de8-40a8-a946-7d88eb301d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505299006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3505299006
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.1669357461
Short name T2
Test name
Test status
Simulation time 26917195 ps
CPU time 0.7 seconds
Started Mar 16 04:34:06 PM PDT 24
Finished Mar 16 04:34:07 PM PDT 24
Peak memory 205304 kb
Host smart-62d8cc53-108e-4a1b-9373-a7b7e8b9e42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669357461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1
669357461
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2588270024
Short name T143
Test name
Test status
Simulation time 19328879 ps
CPU time 0.78 seconds
Started Mar 16 04:34:03 PM PDT 24
Finished Mar 16 04:34:04 PM PDT 24
Peak memory 205360 kb
Host smart-46752531-dae6-4a38-a031-79658d05c51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588270024 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
588270024
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.877626515
Short name T131
Test name
Test status
Simulation time 12270491 ps
CPU time 0.83 seconds
Started Mar 16 04:34:12 PM PDT 24
Finished Mar 16 04:34:13 PM PDT 24
Peak memory 205376 kb
Host smart-442cf003-6a04-4206-b6e1-bf8ba877cd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877626515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.877626515
Directory /workspace/9.keymgr_dpe_alert_test/latest
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