Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.28 97.70 90.58 57.52 76.92 94.94 98.34 17.96


Total test records in report: 308
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T256 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.3916714674 Mar 23 01:16:33 PM PDT 24 Mar 23 01:16:34 PM PDT 24 187270326 ps
T257 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2049219215 Mar 23 01:16:21 PM PDT 24 Mar 23 01:16:22 PM PDT 24 49925370 ps
T258 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2566180151 Mar 23 01:16:22 PM PDT 24 Mar 23 01:16:23 PM PDT 24 149638651 ps
T259 /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1261541112 Mar 23 01:17:25 PM PDT 24 Mar 23 01:17:28 PM PDT 24 335803201 ps
T260 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2199886219 Mar 23 01:17:35 PM PDT 24 Mar 23 01:17:36 PM PDT 24 43917476 ps
T261 /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2130915354 Mar 23 01:17:02 PM PDT 24 Mar 23 01:17:03 PM PDT 24 14864642 ps
T262 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.4050249516 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 74256407 ps
T60 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3386422778 Mar 23 01:16:48 PM PDT 24 Mar 23 01:16:53 PM PDT 24 992212675 ps
T263 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713900525 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 274726490 ps
T264 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2254611180 Mar 23 01:17:34 PM PDT 24 Mar 23 01:17:36 PM PDT 24 197769682 ps
T265 /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2142704806 Mar 23 01:16:20 PM PDT 24 Mar 23 01:16:23 PM PDT 24 305233320 ps
T266 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.2387118442 Mar 23 01:17:06 PM PDT 24 Mar 23 01:17:07 PM PDT 24 67519900 ps
T267 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.2804724359 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 39802191 ps
T268 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3667517249 Mar 23 01:17:24 PM PDT 24 Mar 23 01:17:28 PM PDT 24 116460762 ps
T269 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1519012334 Mar 23 01:16:33 PM PDT 24 Mar 23 01:16:34 PM PDT 24 200699916 ps
T270 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.4100865372 Mar 23 01:16:49 PM PDT 24 Mar 23 01:16:52 PM PDT 24 72539269 ps
T271 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3694645550 Mar 23 01:17:11 PM PDT 24 Mar 23 01:17:19 PM PDT 24 767650892 ps
T272 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.644530126 Mar 23 01:16:21 PM PDT 24 Mar 23 01:16:22 PM PDT 24 11463925 ps
T273 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3740270965 Mar 23 01:17:04 PM PDT 24 Mar 23 01:17:07 PM PDT 24 132769114 ps
T274 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2024499156 Mar 23 01:17:41 PM PDT 24 Mar 23 01:17:44 PM PDT 24 248165384 ps
T275 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.123132810 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 22972755 ps
T276 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1611051105 Mar 23 01:17:13 PM PDT 24 Mar 23 01:17:15 PM PDT 24 238784596 ps
T277 /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.2983047793 Mar 23 01:17:51 PM PDT 24 Mar 23 01:17:52 PM PDT 24 49426492 ps
T278 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.621590316 Mar 23 01:18:01 PM PDT 24 Mar 23 01:18:02 PM PDT 24 15231260 ps
T279 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1174675176 Mar 23 01:16:32 PM PDT 24 Mar 23 01:16:34 PM PDT 24 96260677 ps
T280 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3598290327 Mar 23 01:17:02 PM PDT 24 Mar 23 01:17:06 PM PDT 24 174711955 ps
T281 /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1250867889 Mar 23 01:18:02 PM PDT 24 Mar 23 01:18:03 PM PDT 24 53277931 ps
T282 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.706865758 Mar 23 01:16:34 PM PDT 24 Mar 23 01:16:35 PM PDT 24 42763019 ps
T283 /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.2963897441 Mar 23 01:16:48 PM PDT 24 Mar 23 01:16:49 PM PDT 24 123179803 ps
T284 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2455011879 Mar 23 01:17:01 PM PDT 24 Mar 23 01:17:04 PM PDT 24 839259267 ps
T285 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.543984791 Mar 23 01:16:48 PM PDT 24 Mar 23 01:16:57 PM PDT 24 444939133 ps
T286 /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.708188775 Mar 23 01:17:36 PM PDT 24 Mar 23 01:17:38 PM PDT 24 138243499 ps
T287 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.4096497385 Mar 23 01:17:03 PM PDT 24 Mar 23 01:17:04 PM PDT 24 133974053 ps
T288 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3969197263 Mar 23 01:17:02 PM PDT 24 Mar 23 01:17:06 PM PDT 24 280384501 ps
T289 /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.2841770082 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:53 PM PDT 24 56703120 ps
T51 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.709390064 Mar 23 01:16:32 PM PDT 24 Mar 23 01:16:37 PM PDT 24 671061603 ps
T65 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1014940646 Mar 23 01:17:42 PM PDT 24 Mar 23 01:17:48 PM PDT 24 977478070 ps
T290 /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.525462277 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 11197129 ps
T58 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3436170905 Mar 23 01:17:12 PM PDT 24 Mar 23 01:17:19 PM PDT 24 342052881 ps
T291 /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3405585232 Mar 23 01:17:52 PM PDT 24 Mar 23 01:17:53 PM PDT 24 34214348 ps
T292 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1336048837 Mar 23 01:17:27 PM PDT 24 Mar 23 01:17:32 PM PDT 24 168332884 ps
T293 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.1026714446 Mar 23 01:17:36 PM PDT 24 Mar 23 01:17:38 PM PDT 24 51580518 ps
T294 /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2721323591 Mar 23 01:17:37 PM PDT 24 Mar 23 01:17:41 PM PDT 24 88103293 ps
T295 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.4096692082 Mar 23 01:17:37 PM PDT 24 Mar 23 01:17:38 PM PDT 24 93673725 ps
T296 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1874147414 Mar 23 01:17:38 PM PDT 24 Mar 23 01:17:40 PM PDT 24 175547605 ps
T53 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3553413283 Mar 23 01:17:04 PM PDT 24 Mar 23 01:17:11 PM PDT 24 221683207 ps
T297 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3170542109 Mar 23 01:17:42 PM PDT 24 Mar 23 01:17:46 PM PDT 24 485809159 ps
T298 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1305171589 Mar 23 01:17:48 PM PDT 24 Mar 23 01:17:49 PM PDT 24 26258623 ps
T299 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.636086301 Mar 23 01:17:40 PM PDT 24 Mar 23 01:17:42 PM PDT 24 88132338 ps
T300 /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2835193206 Mar 23 01:17:50 PM PDT 24 Mar 23 01:17:52 PM PDT 24 12730603 ps
T301 /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1979186092 Mar 23 01:18:07 PM PDT 24 Mar 23 01:18:09 PM PDT 24 13305642 ps
T302 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3552857199 Mar 23 01:16:50 PM PDT 24 Mar 23 01:17:09 PM PDT 24 2288213855 ps
T303 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2753554091 Mar 23 01:17:28 PM PDT 24 Mar 23 01:17:29 PM PDT 24 14178178 ps
T304 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3810236185 Mar 23 01:16:34 PM PDT 24 Mar 23 01:16:40 PM PDT 24 1121843499 ps
T305 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.4130775442 Mar 23 01:17:24 PM PDT 24 Mar 23 01:17:26 PM PDT 24 232164609 ps
T306 /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2320290587 Mar 23 01:17:10 PM PDT 24 Mar 23 01:17:11 PM PDT 24 37194736 ps
T307 /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.1724520025 Mar 23 01:17:53 PM PDT 24 Mar 23 01:17:53 PM PDT 24 31103994 ps
T308 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2916333385 Mar 23 01:17:48 PM PDT 24 Mar 23 01:17:52 PM PDT 24 142321891 ps

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2594548045
Short name T3
Test name
Test status
Simulation time 22458550613 ps
CPU time 98.16 seconds
Started Mar 23 01:45:40 PM PDT 24
Finished Mar 23 01:47:19 PM PDT 24
Peak memory 207936 kb
Host smart-ee7b0fde-feb4-4519-b614-1e4b99ef2395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594548045 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2594548045
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1013763662
Short name T67
Test name
Test status
Simulation time 267374540 ps
CPU time 5.91 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:55 PM PDT 24
Peak memory 212988 kb
Host smart-2d406917-ba31-4282-b409-c7309c247eca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013763662 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1013763662
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1782368412
Short name T6
Test name
Test status
Simulation time 962692800 ps
CPU time 16.22 seconds
Started Mar 23 01:44:53 PM PDT 24
Finished Mar 23 01:45:09 PM PDT 24
Peak memory 231092 kb
Host smart-33e7f8a3-ff1f-46e0-b943-7329fcc1ac0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782368412 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1782368412
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.711645374
Short name T42
Test name
Test status
Simulation time 104349840 ps
CPU time 2.58 seconds
Started Mar 23 01:17:53 PM PDT 24
Finished Mar 23 01:17:56 PM PDT 24
Peak memory 213684 kb
Host smart-5b48488a-bc63-4488-9a71-40ad3dfd2d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711645374 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.711645374
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.92096860
Short name T10
Test name
Test status
Simulation time 263332271 ps
CPU time 14.15 seconds
Started Mar 23 01:45:20 PM PDT 24
Finished Mar 23 01:45:34 PM PDT 24
Peak memory 207860 kb
Host smart-1df48c1f-ac0f-4c9f-9d9b-197d84c28463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92096860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.92096860
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.1837125070
Short name T21
Test name
Test status
Simulation time 25213502 ps
CPU time 0.78 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:18 PM PDT 24
Peak memory 205348 kb
Host smart-a15210dd-e663-4ece-a20b-d790fd5427e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837125070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
1837125070
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2671143788
Short name T38
Test name
Test status
Simulation time 178838414 ps
CPU time 3.61 seconds
Started Mar 23 01:17:23 PM PDT 24
Finished Mar 23 01:17:27 PM PDT 24
Peak memory 212812 kb
Host smart-95e5465f-a193-459a-86ab-13680c1dc5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671143788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2671143788
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.1572637128
Short name T120
Test name
Test status
Simulation time 11308319 ps
CPU time 0.73 seconds
Started Mar 23 01:16:32 PM PDT 24
Finished Mar 23 01:16:33 PM PDT 24
Peak memory 204252 kb
Host smart-d4734032-2274-4478-95d2-bbfd84945c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572637128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.1
572637128
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.38397591
Short name T68
Test name
Test status
Simulation time 203014486 ps
CPU time 5.04 seconds
Started Mar 23 01:17:24 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 212896 kb
Host smart-cf268174-1e83-4315-9ca1-b67ea5cc112a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38397591 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_T
EST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.38397591
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2614787938
Short name T35
Test name
Test status
Simulation time 1473956174 ps
CPU time 24.3 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:42 PM PDT 24
Peak memory 207864 kb
Host smart-5cf1fad7-3e5a-4266-8132-5cf8d012a4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614787938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2614787938
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.1231843518
Short name T37
Test name
Test status
Simulation time 993659075 ps
CPU time 6.92 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:58 PM PDT 24
Peak memory 213896 kb
Host smart-51e89675-bbbe-49e4-821f-b98d5cf42eae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231843518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.1231843518
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.2699647066
Short name T59
Test name
Test status
Simulation time 187526937 ps
CPU time 4.95 seconds
Started Mar 23 01:16:10 PM PDT 24
Finished Mar 23 01:16:15 PM PDT 24
Peak memory 213628 kb
Host smart-2b4baee0-7704-4480-a636-12b2d09721d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699647066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.2699647066
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.840564495
Short name T218
Test name
Test status
Simulation time 136837314 ps
CPU time 2.23 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:13 PM PDT 24
Peak memory 212652 kb
Host smart-4ee50cfd-740c-4f0f-9206-9380cf820208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840564495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.840564495
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3436170905
Short name T58
Test name
Test status
Simulation time 342052881 ps
CPU time 6.99 seconds
Started Mar 23 01:17:12 PM PDT 24
Finished Mar 23 01:17:19 PM PDT 24
Peak memory 204564 kb
Host smart-1e2d55a6-4d74-4605-be1e-7fb565f4696e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436170905 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3436170905
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.1329513569
Short name T5
Test name
Test status
Simulation time 1851624669 ps
CPU time 20.3 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:40 PM PDT 24
Peak memory 207684 kb
Host smart-47c36ed9-ab66-4b83-8721-c034d610ebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329513569 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.1329513569
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1216164661
Short name T24
Test name
Test status
Simulation time 152713346 ps
CPU time 3.96 seconds
Started Mar 23 01:17:38 PM PDT 24
Finished Mar 23 01:17:42 PM PDT 24
Peak memory 212568 kb
Host smart-3e3836a1-3706-4c9e-bb27-d5725fa364f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216164661 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1216164661
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.281424230
Short name T66
Test name
Test status
Simulation time 905011034 ps
CPU time 8.25 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:18:01 PM PDT 24
Peak memory 213640 kb
Host smart-01cec513-a0af-45d2-96b6-ba81124beec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281424230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe
_tl_intg_err.281424230
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3386422778
Short name T60
Test name
Test status
Simulation time 992212675 ps
CPU time 4.59 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:53 PM PDT 24
Peak memory 212616 kb
Host smart-daf8e2bc-3dc0-4e1d-ad1d-8bdfdd805807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386422778 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.3386422778
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.722630281
Short name T62
Test name
Test status
Simulation time 1119935446 ps
CPU time 5.16 seconds
Started Mar 23 01:17:03 PM PDT 24
Finished Mar 23 01:17:08 PM PDT 24
Peak memory 212592 kb
Host smart-c3b394c6-d797-41d3-aa72-3b4f9d148bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722630281 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_
tl_intg_err.722630281
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1122812170
Short name T180
Test name
Test status
Simulation time 18333416 ps
CPU time 1.28 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:23 PM PDT 24
Peak memory 214664 kb
Host smart-37a95183-592b-4614-b21a-dece8c402bce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122812170 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1122812170
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.179232056
Short name T179
Test name
Test status
Simulation time 23943472 ps
CPU time 0.74 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:37 PM PDT 24
Peak memory 204216 kb
Host smart-4659c8a0-7c4e-4fa7-83bb-ff9177c6aee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179232056 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.179232056
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.3634588682
Short name T33
Test name
Test status
Simulation time 152182854 ps
CPU time 10.14 seconds
Started Mar 23 01:44:54 PM PDT 24
Finished Mar 23 01:45:04 PM PDT 24
Peak memory 206104 kb
Host smart-85d01389-5d2d-4cf2-a33d-3172adbd2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634588682 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.3634588682
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.831659271
Short name T4
Test name
Test status
Simulation time 2350023485 ps
CPU time 21.28 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:29 PM PDT 24
Peak memory 207444 kb
Host smart-f40fffcf-82a6-4976-849e-0e1de0448c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831659271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.831659271
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.2274260848
Short name T115
Test name
Test status
Simulation time 366429492 ps
CPU time 14.13 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 206152 kb
Host smart-dc932906-e852-410d-bf21-5683302423b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274260848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.2274260848
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3313198904
Short name T29
Test name
Test status
Simulation time 3209639801 ps
CPU time 57.09 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:46:04 PM PDT 24
Peak memory 207576 kb
Host smart-4a7dff53-cac1-49fb-a0f7-f647addb8e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313198904 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3313198904
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.1545806964
Short name T102
Test name
Test status
Simulation time 9441735892 ps
CPU time 77.97 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:46:38 PM PDT 24
Peak memory 208144 kb
Host smart-5150fa84-7108-48b3-bee5-4dc53bcf2821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545806964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.1545806964
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.2831739553
Short name T111
Test name
Test status
Simulation time 4967654318 ps
CPU time 26.37 seconds
Started Mar 23 01:45:22 PM PDT 24
Finished Mar 23 01:45:48 PM PDT 24
Peak memory 207624 kb
Host smart-4ca74c83-4ec1-4e68-b79f-66e94eac4d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831739553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.2831739553
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.3153946869
Short name T104
Test name
Test status
Simulation time 736069274 ps
CPU time 23 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:42 PM PDT 24
Peak memory 208060 kb
Host smart-062b8fd5-9f3d-4184-a2fa-45170a024918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153946869 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.3153946869
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.552817244
Short name T117
Test name
Test status
Simulation time 12072593427 ps
CPU time 105.01 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:47:03 PM PDT 24
Peak memory 208384 kb
Host smart-10d2f782-9c15-42f8-8302-cc6fd0b69967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552817244 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.552817244
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.3606970125
Short name T106
Test name
Test status
Simulation time 1270960178 ps
CPU time 18.96 seconds
Started Mar 23 01:44:54 PM PDT 24
Finished Mar 23 01:45:13 PM PDT 24
Peak memory 207932 kb
Host smart-b31d8130-e757-4098-ac5f-f2dfc08c9677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606970125 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.3606970125
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.742913595
Short name T109
Test name
Test status
Simulation time 1086728522 ps
CPU time 15.28 seconds
Started Mar 23 01:45:22 PM PDT 24
Finished Mar 23 01:45:38 PM PDT 24
Peak memory 207720 kb
Host smart-c4810a5a-f32c-4ed4-81d6-c5673835c8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742913595 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.742913595
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.2835616460
Short name T34
Test name
Test status
Simulation time 4815977967 ps
CPU time 38.26 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:46:08 PM PDT 24
Peak memory 207952 kb
Host smart-8aa77c3c-6964-44b9-a849-558c51ed6a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835616460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.2835616460
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.3955453282
Short name T101
Test name
Test status
Simulation time 4441404793 ps
CPU time 18.12 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:47 PM PDT 24
Peak memory 207768 kb
Host smart-ec50a81f-d75a-4b8a-9760-c059ba98c0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955453282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.3955453282
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.926480736
Short name T112
Test name
Test status
Simulation time 3912191317 ps
CPU time 22.23 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:53 PM PDT 24
Peak memory 207824 kb
Host smart-b5da50cc-5fe7-4a41-96f4-9bd58a88efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926480736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.926480736
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.218593389
Short name T90
Test name
Test status
Simulation time 1367743174 ps
CPU time 16.17 seconds
Started Mar 23 01:45:27 PM PDT 24
Finished Mar 23 01:45:43 PM PDT 24
Peak memory 207860 kb
Host smart-b846d3c9-dbc8-4764-bf70-d84fee595ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218593389 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.218593389
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3442986954
Short name T15
Test name
Test status
Simulation time 26334121222 ps
CPU time 207.53 seconds
Started Mar 23 01:45:33 PM PDT 24
Finished Mar 23 01:49:00 PM PDT 24
Peak memory 207204 kb
Host smart-416a868a-6f34-40cb-92fd-550267d7bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442986954 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3442986954
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.3823681268
Short name T110
Test name
Test status
Simulation time 667531579 ps
CPU time 19.54 seconds
Started Mar 23 01:45:35 PM PDT 24
Finished Mar 23 01:45:55 PM PDT 24
Peak memory 207344 kb
Host smart-0abbcfe0-6bb7-4229-a66a-4e1fb4c94f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823681268 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.3823681268
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.3913683323
Short name T105
Test name
Test status
Simulation time 3474090597 ps
CPU time 20.96 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:27 PM PDT 24
Peak memory 207324 kb
Host smart-c96c6ab9-6f0b-4999-b22d-36c53321920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913683323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.3913683323
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3195485240
Short name T108
Test name
Test status
Simulation time 916328596 ps
CPU time 17.11 seconds
Started Mar 23 01:45:08 PM PDT 24
Finished Mar 23 01:45:25 PM PDT 24
Peak memory 206204 kb
Host smart-77e0cbfa-a573-49b1-aa6c-0111794af832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195485240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3195485240
Directory /workspace/9.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.2496937426
Short name T25
Test name
Test status
Simulation time 1276154225 ps
CPU time 19.33 seconds
Started Mar 23 01:44:52 PM PDT 24
Finished Mar 23 01:45:12 PM PDT 24
Peak memory 232480 kb
Host smart-0d1d2f40-c50d-47a4-99e2-67f9dbef71ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496937426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.2496937426
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.826249140
Short name T76
Test name
Test status
Simulation time 56034495 ps
CPU time 3.06 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:25 PM PDT 24
Peak memory 204636 kb
Host smart-0614b87d-aeec-4408-a927-c2ece777c528
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826249140 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.826249140
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2246436584
Short name T168
Test name
Test status
Simulation time 905536609 ps
CPU time 15.23 seconds
Started Mar 23 01:16:21 PM PDT 24
Finished Mar 23 01:16:36 PM PDT 24
Peak memory 204392 kb
Host smart-afce060d-e3f3-4e6b-b182-a1a93d98684d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246436584 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2246436584
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.3201465625
Short name T167
Test name
Test status
Simulation time 11632964 ps
CPU time 0.83 seconds
Started Mar 23 01:16:23 PM PDT 24
Finished Mar 23 01:16:24 PM PDT 24
Peak memory 204176 kb
Host smart-20599d36-d0fb-4fe4-b5eb-30e109edbb0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201465625 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.3201465625
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.876291344
Short name T40
Test name
Test status
Simulation time 45084683 ps
CPU time 0.94 seconds
Started Mar 23 01:16:20 PM PDT 24
Finished Mar 23 01:16:21 PM PDT 24
Peak memory 204032 kb
Host smart-0e38bffe-67cf-434a-a77b-3717dd6701f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876291344 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.876291344
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2572440408
Short name T226
Test name
Test status
Simulation time 32787618 ps
CPU time 0.82 seconds
Started Mar 23 01:16:12 PM PDT 24
Finished Mar 23 01:16:13 PM PDT 24
Peak memory 204204 kb
Host smart-63e106e9-0b06-4501-a3c9-d144b9862eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572440408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
572440408
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2142704806
Short name T265
Test name
Test status
Simulation time 305233320 ps
CPU time 3.23 seconds
Started Mar 23 01:16:20 PM PDT 24
Finished Mar 23 01:16:23 PM PDT 24
Peak memory 204424 kb
Host smart-d3b3424b-6fd7-4d45-8498-c850093cbbb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142704806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2142704806
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.702695414
Short name T71
Test name
Test status
Simulation time 87030227 ps
CPU time 2.66 seconds
Started Mar 23 01:16:11 PM PDT 24
Finished Mar 23 01:16:13 PM PDT 24
Peak memory 212924 kb
Host smart-c406e0f1-8398-4744-8c09-99952119942c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702695414 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg
r_dpe_shadow_reg_errors.702695414
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.424467913
Short name T189
Test name
Test status
Simulation time 948844244 ps
CPU time 2.98 seconds
Started Mar 23 01:16:10 PM PDT 24
Finished Mar 23 01:16:13 PM PDT 24
Peak memory 212952 kb
Host smart-fdae7fe7-0346-4aa7-a6fe-c97cd3e91be9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424467913 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.424467913
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2985491933
Short name T213
Test name
Test status
Simulation time 114349976 ps
CPU time 3.78 seconds
Started Mar 23 01:16:12 PM PDT 24
Finished Mar 23 01:16:16 PM PDT 24
Peak memory 212580 kb
Host smart-e34fb8d7-5913-42b5-b4f3-92ffc9f2938f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985491933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
985491933
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.1083757972
Short name T222
Test name
Test status
Simulation time 231198183 ps
CPU time 5.93 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:40 PM PDT 24
Peak memory 204284 kb
Host smart-4e94a078-79e6-46cb-a6eb-cd047fc230c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083757972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.1083757972
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.508898510
Short name T39
Test name
Test status
Simulation time 184528002 ps
CPU time 4.4 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:27 PM PDT 24
Peak memory 204432 kb
Host smart-55a3bc68-8c8a-4317-a83a-ee3bbe292305
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508898510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.508898510
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.2049219215
Short name T257
Test name
Test status
Simulation time 49925370 ps
CPU time 0.98 seconds
Started Mar 23 01:16:21 PM PDT 24
Finished Mar 23 01:16:22 PM PDT 24
Peak memory 204332 kb
Host smart-a54b672c-f93c-4405-831b-2a34a966dde1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049219215 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.2049219215
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.1519012334
Short name T269
Test name
Test status
Simulation time 200699916 ps
CPU time 1.03 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:34 PM PDT 24
Peak memory 204336 kb
Host smart-a6704507-ec27-473c-9021-b7ba0b90fddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519012334 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.1519012334
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.2566180151
Short name T258
Test name
Test status
Simulation time 149638651 ps
CPU time 0.93 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:23 PM PDT 24
Peak memory 204132 kb
Host smart-ddacf270-5dc2-4b9e-ad6f-d306a582808c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566180151 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.2
566180151
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.644530126
Short name T272
Test name
Test status
Simulation time 11463925 ps
CPU time 0.83 seconds
Started Mar 23 01:16:21 PM PDT 24
Finished Mar 23 01:16:22 PM PDT 24
Peak memory 204272 kb
Host smart-6d612085-5c76-4d86-ac80-03279c3dcda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644530126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.644530126
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.2693694435
Short name T50
Test name
Test status
Simulation time 478635584 ps
CPU time 1.61 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:35 PM PDT 24
Peak memory 204408 kb
Host smart-a9af6349-0ee9-4ccb-8968-6314f3188f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693694435 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.2693694435
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.3483501777
Short name T239
Test name
Test status
Simulation time 58905357 ps
CPU time 1.92 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:24 PM PDT 24
Peak memory 212880 kb
Host smart-0d16659e-6f0e-4145-a280-1dccb26d9749
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483501777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.3483501777
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2106556961
Short name T234
Test name
Test status
Simulation time 57056460 ps
CPU time 2.46 seconds
Started Mar 23 01:16:20 PM PDT 24
Finished Mar 23 01:16:23 PM PDT 24
Peak memory 204812 kb
Host smart-c2f75e2d-0d85-4a60-9825-063757c437ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106556961 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.2106556961
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.2822850502
Short name T215
Test name
Test status
Simulation time 241923792 ps
CPU time 2.24 seconds
Started Mar 23 01:16:22 PM PDT 24
Finished Mar 23 01:16:24 PM PDT 24
Peak memory 212588 kb
Host smart-d159e16a-0bc5-45ae-892a-3be3db9c049e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822850502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.2
822850502
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.1999313646
Short name T61
Test name
Test status
Simulation time 166169244 ps
CPU time 2.61 seconds
Started Mar 23 01:16:20 PM PDT 24
Finished Mar 23 01:16:23 PM PDT 24
Peak memory 212896 kb
Host smart-08fdcc4a-0b1a-4a3f-ba02-cdaae46ad095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999313646 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.1999313646
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2743752236
Short name T211
Test name
Test status
Simulation time 23739810 ps
CPU time 1.33 seconds
Started Mar 23 01:17:12 PM PDT 24
Finished Mar 23 01:17:13 PM PDT 24
Peak memory 212628 kb
Host smart-9790a14b-919f-4298-870d-d88ec01f4f7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743752236 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2743752236
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.4107015251
Short name T247
Test name
Test status
Simulation time 60767213 ps
CPU time 0.93 seconds
Started Mar 23 01:17:12 PM PDT 24
Finished Mar 23 01:17:13 PM PDT 24
Peak memory 204296 kb
Host smart-1f8f135e-de33-4705-ba30-fcc5938555f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107015251 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
4107015251
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.3551120008
Short name T122
Test name
Test status
Simulation time 36592992 ps
CPU time 0.68 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:12 PM PDT 24
Peak memory 204216 kb
Host smart-a39e34eb-2cc2-40f5-b1e4-f2455e5dd58a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551120008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
3551120008
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.381485938
Short name T87
Test name
Test status
Simulation time 141476976 ps
CPU time 1.68 seconds
Started Mar 23 01:17:12 PM PDT 24
Finished Mar 23 01:17:14 PM PDT 24
Peak memory 204372 kb
Host smart-9f465c68-2d6b-45fe-8939-8ed54829032a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381485938 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.k
eymgr_dpe_same_csr_outstanding.381485938
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.4073131576
Short name T233
Test name
Test status
Simulation time 450095383 ps
CPU time 1.65 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:13 PM PDT 24
Peak memory 212744 kb
Host smart-7a60f5f7-b906-4923-bdaf-854dc4d70b2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073131576 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.4073131576
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3694645550
Short name T271
Test name
Test status
Simulation time 767650892 ps
CPU time 7.56 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:19 PM PDT 24
Peak memory 212972 kb
Host smart-bec5a16c-9dd3-4b9d-88f3-3d9b637aea98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694645550 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.3694645550
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.2892132695
Short name T199
Test name
Test status
Simulation time 142613360 ps
CPU time 1.2 seconds
Started Mar 23 01:17:25 PM PDT 24
Finished Mar 23 01:17:26 PM PDT 24
Peak memory 212736 kb
Host smart-819cefb5-a309-4f88-9b29-0a00623edb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892132695 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.2892132695
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.2260963272
Short name T169
Test name
Test status
Simulation time 20804407 ps
CPU time 0.97 seconds
Started Mar 23 01:17:28 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 204164 kb
Host smart-5d47bcf6-9ad7-41a7-8880-c46fb76b135f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260963272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
2260963272
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.3819056761
Short name T221
Test name
Test status
Simulation time 24370515 ps
CPU time 0.8 seconds
Started Mar 23 01:17:27 PM PDT 24
Finished Mar 23 01:17:28 PM PDT 24
Peak memory 204244 kb
Host smart-1ca0fce5-0a89-4387-aa65-30f8c4bce2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819056761 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
3819056761
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.2661563658
Short name T182
Test name
Test status
Simulation time 326863624 ps
CPU time 3.02 seconds
Started Mar 23 01:17:26 PM PDT 24
Finished Mar 23 01:17:30 PM PDT 24
Peak memory 204464 kb
Host smart-d29c9788-22f5-4fb1-9e38-72b7fb03559a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661563658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.2661563658
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1611051105
Short name T276
Test name
Test status
Simulation time 238784596 ps
CPU time 2.39 seconds
Started Mar 23 01:17:13 PM PDT 24
Finished Mar 23 01:17:15 PM PDT 24
Peak memory 213000 kb
Host smart-2a13de0c-8064-4b7d-bb48-59fa25b9adff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611051105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1611051105
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1051322769
Short name T191
Test name
Test status
Simulation time 266664116 ps
CPU time 5.33 seconds
Started Mar 23 01:17:14 PM PDT 24
Finished Mar 23 01:17:19 PM PDT 24
Peak memory 213084 kb
Host smart-4a53c47b-d338-4105-a018-a80369a299a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051322769 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.1051322769
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.3382808448
Short name T254
Test name
Test status
Simulation time 72175527 ps
CPU time 1.99 seconds
Started Mar 23 01:17:12 PM PDT 24
Finished Mar 23 01:17:14 PM PDT 24
Peak memory 220752 kb
Host smart-fa41cda3-1ab8-40e1-9412-98f7f1631a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382808448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
3382808448
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.1843586860
Short name T197
Test name
Test status
Simulation time 48744727 ps
CPU time 2.35 seconds
Started Mar 23 01:17:25 PM PDT 24
Finished Mar 23 01:17:27 PM PDT 24
Peak memory 212492 kb
Host smart-58b3c478-7a9f-43e6-9924-8868c6c459dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843586860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.1843586860
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.338634858
Short name T181
Test name
Test status
Simulation time 30966397 ps
CPU time 1.34 seconds
Started Mar 23 01:17:27 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 204396 kb
Host smart-9131f6bf-c971-4d39-83bf-9f763fa3ae93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338634858 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.338634858
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.2753554091
Short name T303
Test name
Test status
Simulation time 14178178 ps
CPU time 1.13 seconds
Started Mar 23 01:17:28 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 204432 kb
Host smart-4c9945a2-42b5-4400-ab04-40d68123e433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753554091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
2753554091
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1111147696
Short name T238
Test name
Test status
Simulation time 38051944 ps
CPU time 0.72 seconds
Started Mar 23 01:17:28 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 204180 kb
Host smart-f0c37f3e-433f-4172-abe5-68fa521304f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111147696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
1111147696
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.909587570
Short name T250
Test name
Test status
Simulation time 195764503 ps
CPU time 1.54 seconds
Started Mar 23 01:17:24 PM PDT 24
Finished Mar 23 01:17:26 PM PDT 24
Peak memory 204380 kb
Host smart-3561384f-d664-40f8-b3c3-a2bfffcf42ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909587570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.k
eymgr_dpe_same_csr_outstanding.909587570
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.4130775442
Short name T305
Test name
Test status
Simulation time 232164609 ps
CPU time 1.95 seconds
Started Mar 23 01:17:24 PM PDT 24
Finished Mar 23 01:17:26 PM PDT 24
Peak memory 212936 kb
Host smart-32b39d20-ef25-469a-ad0f-9355ee6b8846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130775442 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.4130775442
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.4185748109
Short name T245
Test name
Test status
Simulation time 291543743 ps
CPU time 3.52 seconds
Started Mar 23 01:17:25 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 212952 kb
Host smart-500ab323-577c-4f85-9fe8-8421c9d9746b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185748109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.4185748109
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.3667517249
Short name T268
Test name
Test status
Simulation time 116460762 ps
CPU time 4.11 seconds
Started Mar 23 01:17:24 PM PDT 24
Finished Mar 23 01:17:28 PM PDT 24
Peak memory 212644 kb
Host smart-7867ee18-e22c-470f-898d-79cd72df1121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667517249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
3667517249
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.429962438
Short name T119
Test name
Test status
Simulation time 259533598 ps
CPU time 4.93 seconds
Started Mar 23 01:17:24 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 212656 kb
Host smart-6ff26b3b-5df1-40de-97df-104476ac7178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429962438 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe
_tl_intg_err.429962438
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.4130312862
Short name T41
Test name
Test status
Simulation time 286518508 ps
CPU time 1.72 seconds
Started Mar 23 01:17:27 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 212748 kb
Host smart-75377828-4d4e-4c25-b9d4-c1f75c5e20f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130312862 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.4130312862
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.3258775880
Short name T172
Test name
Test status
Simulation time 22384354 ps
CPU time 0.93 seconds
Started Mar 23 01:17:23 PM PDT 24
Finished Mar 23 01:17:24 PM PDT 24
Peak memory 204248 kb
Host smart-d6c166c4-5469-4a71-bab9-58683bd86008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258775880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
3258775880
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.3983979195
Short name T73
Test name
Test status
Simulation time 35781623 ps
CPU time 0.72 seconds
Started Mar 23 01:17:23 PM PDT 24
Finished Mar 23 01:17:24 PM PDT 24
Peak memory 204064 kb
Host smart-187260fb-bafe-45b1-a046-2c189a6cf05c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983979195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
3983979195
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1261541112
Short name T259
Test name
Test status
Simulation time 335803201 ps
CPU time 3.17 seconds
Started Mar 23 01:17:25 PM PDT 24
Finished Mar 23 01:17:28 PM PDT 24
Peak memory 204364 kb
Host smart-3fb39d29-2beb-4ac1-b570-eb52e5231947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261541112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1261541112
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1336048837
Short name T292
Test name
Test status
Simulation time 168332884 ps
CPU time 4.63 seconds
Started Mar 23 01:17:27 PM PDT 24
Finished Mar 23 01:17:32 PM PDT 24
Peak memory 212988 kb
Host smart-ee9169b4-d3f6-4213-8bb1-a43aee3b6e53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336048837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1336048837
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2408443153
Short name T70
Test name
Test status
Simulation time 252185214 ps
CPU time 4.29 seconds
Started Mar 23 01:17:26 PM PDT 24
Finished Mar 23 01:17:31 PM PDT 24
Peak memory 213020 kb
Host smart-64f3ad34-fbeb-482b-92f5-4cc66e5c6878
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408443153 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2408443153
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1265176425
Short name T46
Test name
Test status
Simulation time 137152166 ps
CPU time 2.06 seconds
Started Mar 23 01:17:28 PM PDT 24
Finished Mar 23 01:17:30 PM PDT 24
Peak memory 212660 kb
Host smart-9ea802fe-b467-4c88-a1c5-2614bcb537bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265176425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1265176425
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3448985062
Short name T95
Test name
Test status
Simulation time 30020797 ps
CPU time 1.71 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204708 kb
Host smart-173c6b16-e220-4735-b866-de76e138f80a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448985062 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3448985062
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2137090162
Short name T86
Test name
Test status
Simulation time 55407107 ps
CPU time 0.98 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:37 PM PDT 24
Peak memory 204200 kb
Host smart-9104b819-6dd4-4163-a124-04990be4361d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137090162 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2137090162
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.2199886219
Short name T260
Test name
Test status
Simulation time 43917476 ps
CPU time 0.74 seconds
Started Mar 23 01:17:35 PM PDT 24
Finished Mar 23 01:17:36 PM PDT 24
Peak memory 204224 kb
Host smart-d3f8bb4c-2cad-468f-bf44-3b8ff298ae4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199886219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
2199886219
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.708188775
Short name T286
Test name
Test status
Simulation time 138243499 ps
CPU time 2.31 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204388 kb
Host smart-3a721c44-3ce0-406e-af61-cbd817b9b408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708188775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.708188775
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.2078260742
Short name T207
Test name
Test status
Simulation time 80814417 ps
CPU time 1.52 seconds
Started Mar 23 01:17:27 PM PDT 24
Finished Mar 23 01:17:29 PM PDT 24
Peak memory 213004 kb
Host smart-e6eacca3-caf6-423b-a101-0ca5e350fd55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078260742 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.2078260742
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1874147414
Short name T296
Test name
Test status
Simulation time 175547605 ps
CPU time 2.66 seconds
Started Mar 23 01:17:38 PM PDT 24
Finished Mar 23 01:17:40 PM PDT 24
Peak memory 212628 kb
Host smart-df89b220-e871-4020-a9c8-efa4b40729c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874147414 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1874147414
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.901774146
Short name T194
Test name
Test status
Simulation time 85327924 ps
CPU time 1.23 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:37 PM PDT 24
Peak memory 204372 kb
Host smart-de00dd61-cdc6-4cce-8b51-b1f0944c11f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901774146 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.901774146
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.4096692082
Short name T295
Test name
Test status
Simulation time 93673725 ps
CPU time 1.42 seconds
Started Mar 23 01:17:37 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204412 kb
Host smart-842c4418-2b32-4a64-8ecc-259828322afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096692082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
4096692082
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.1820834336
Short name T206
Test name
Test status
Simulation time 25797715 ps
CPU time 2.03 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204424 kb
Host smart-a3785ceb-a2b2-44cd-9049-5bc484041522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820834336 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.1820834336
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.2254611180
Short name T264
Test name
Test status
Simulation time 197769682 ps
CPU time 2.01 seconds
Started Mar 23 01:17:34 PM PDT 24
Finished Mar 23 01:17:36 PM PDT 24
Peak memory 212988 kb
Host smart-67ffda5b-315c-455e-9940-35b2c027d23f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254611180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.2254611180
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3170542109
Short name T297
Test name
Test status
Simulation time 485809159 ps
CPU time 3.28 seconds
Started Mar 23 01:17:42 PM PDT 24
Finished Mar 23 01:17:46 PM PDT 24
Peak memory 213080 kb
Host smart-5303e85b-55b3-4401-97a3-684a2298c65e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170542109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3170542109
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2604595206
Short name T36
Test name
Test status
Simulation time 161197615 ps
CPU time 3.29 seconds
Started Mar 23 01:17:41 PM PDT 24
Finished Mar 23 01:17:45 PM PDT 24
Peak memory 215848 kb
Host smart-14c0a1af-f211-4999-89ea-7e4868d65837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604595206 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2604595206
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.4178402298
Short name T229
Test name
Test status
Simulation time 90991749 ps
CPU time 2.41 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 212604 kb
Host smart-4fe80f83-c44e-4b82-a2e4-1468a75532d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178402298 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.4178402298
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.1710962014
Short name T91
Test name
Test status
Simulation time 99760950 ps
CPU time 1.48 seconds
Started Mar 23 01:17:37 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 212616 kb
Host smart-5bb17271-f6d9-4c44-b5f9-7ed595cc7522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710962014 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.1710962014
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.1736973102
Short name T227
Test name
Test status
Simulation time 49533004 ps
CPU time 1.17 seconds
Started Mar 23 01:17:38 PM PDT 24
Finished Mar 23 01:17:39 PM PDT 24
Peak memory 204428 kb
Host smart-66181c1c-44fd-4189-a9bf-374399484212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736973102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
1736973102
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.68178360
Short name T187
Test name
Test status
Simulation time 31533483 ps
CPU time 0.7 seconds
Started Mar 23 01:17:37 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204208 kb
Host smart-e6f109d7-b302-465c-a188-cae0dfdcb611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68178360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.68178360
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.1026714446
Short name T293
Test name
Test status
Simulation time 51580518 ps
CPU time 2.04 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:38 PM PDT 24
Peak memory 204408 kb
Host smart-d0e7c974-deac-413a-8b26-37f636e7cd3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026714446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.1026714446
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2024499156
Short name T274
Test name
Test status
Simulation time 248165384 ps
CPU time 2.47 seconds
Started Mar 23 01:17:41 PM PDT 24
Finished Mar 23 01:17:44 PM PDT 24
Peak memory 212956 kb
Host smart-b360afc5-04e6-4ebe-908e-d93804a629ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024499156 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2024499156
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2721323591
Short name T294
Test name
Test status
Simulation time 88103293 ps
CPU time 3.76 seconds
Started Mar 23 01:17:37 PM PDT 24
Finished Mar 23 01:17:41 PM PDT 24
Peak memory 212944 kb
Host smart-85b87151-5111-4a2d-919e-8d61a62c174e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721323591 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2721323591
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2106791399
Short name T100
Test name
Test status
Simulation time 2153275166 ps
CPU time 3.49 seconds
Started Mar 23 01:17:39 PM PDT 24
Finished Mar 23 01:17:43 PM PDT 24
Peak memory 215108 kb
Host smart-2386f720-afe7-4fa6-a39d-4f89839cfda7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106791399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2106791399
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.1014940646
Short name T65
Test name
Test status
Simulation time 977478070 ps
CPU time 5.3 seconds
Started Mar 23 01:17:42 PM PDT 24
Finished Mar 23 01:17:48 PM PDT 24
Peak memory 212652 kb
Host smart-1aa85419-993d-41b1-aaa5-8b21b4eacb98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014940646 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.1014940646
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.4050249516
Short name T262
Test name
Test status
Simulation time 74256407 ps
CPU time 1.09 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 212476 kb
Host smart-2aed904a-b9d8-41ef-ad07-dcbcdf7dd4f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050249516 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.4050249516
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.123132810
Short name T275
Test name
Test status
Simulation time 22972755 ps
CPU time 1.07 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204504 kb
Host smart-c502a174-9c24-495c-a31c-811d5b6919d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123132810 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.123132810
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2473951756
Short name T204
Test name
Test status
Simulation time 16431355 ps
CPU time 0.75 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:50 PM PDT 24
Peak memory 204208 kb
Host smart-0956f8d2-d32f-42da-9c2d-9c9a56a4288b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473951756 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2473951756
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.2841770082
Short name T289
Test name
Test status
Simulation time 56703120 ps
CPU time 1.93 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204388 kb
Host smart-ac2e8bcd-b8b8-4c51-977e-a84b0998d323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841770082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.2841770082
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.2460210607
Short name T99
Test name
Test status
Simulation time 1155500277 ps
CPU time 2.86 seconds
Started Mar 23 01:17:42 PM PDT 24
Finished Mar 23 01:17:45 PM PDT 24
Peak memory 212944 kb
Host smart-a3d7aaad-79df-45f0-ae63-3245584796d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460210607 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.2460210607
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3932236652
Short name T217
Test name
Test status
Simulation time 217729597 ps
CPU time 4.67 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:41 PM PDT 24
Peak memory 212924 kb
Host smart-23beec99-3734-4722-a396-0e357a21260d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932236652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3932236652
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.636086301
Short name T299
Test name
Test status
Simulation time 88132338 ps
CPU time 1.65 seconds
Started Mar 23 01:17:40 PM PDT 24
Finished Mar 23 01:17:42 PM PDT 24
Peak memory 212636 kb
Host smart-6bdc143e-e731-46bd-b60d-ae0a9821fb61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636086301 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.636086301
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2489799440
Short name T63
Test name
Test status
Simulation time 799457459 ps
CPU time 5.78 seconds
Started Mar 23 01:17:36 PM PDT 24
Finished Mar 23 01:17:42 PM PDT 24
Peak memory 214260 kb
Host smart-aaa79d2f-fabe-4735-8bf1-e72b2ffb68ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489799440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2489799440
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713900525
Short name T263
Test name
Test status
Simulation time 274726490 ps
CPU time 1.83 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 212552 kb
Host smart-7ed69afe-6386-4552-bdd6-38b49f458f26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713900525 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.2713900525
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.2677180534
Short name T225
Test name
Test status
Simulation time 31486897 ps
CPU time 0.94 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204204 kb
Host smart-4bfb29b4-edb5-49f9-aead-a8785db5d648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677180534 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
2677180534
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.3783101425
Short name T96
Test name
Test status
Simulation time 14627963 ps
CPU time 0.7 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204164 kb
Host smart-db80228e-e159-4860-ab93-c8cd303b5890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783101425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
3783101425
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.3259065509
Short name T75
Test name
Test status
Simulation time 211331921 ps
CPU time 1.41 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:51 PM PDT 24
Peak memory 204392 kb
Host smart-b84404d2-ad51-4474-9889-0e9673bce909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259065509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.3259065509
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3803412217
Short name T205
Test name
Test status
Simulation time 310827670 ps
CPU time 2.06 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:17:55 PM PDT 24
Peak memory 213052 kb
Host smart-e1ad5e2c-6da4-48c5-81e3-999896636de6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803412217 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3803412217
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.895125334
Short name T240
Test name
Test status
Simulation time 210934046 ps
CPU time 4.41 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:56 PM PDT 24
Peak memory 213040 kb
Host smart-37cb6ea8-2eb0-4940-9ec9-11dd680173f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895125334 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.895125334
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1608052506
Short name T236
Test name
Test status
Simulation time 57116973 ps
CPU time 1.36 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:50 PM PDT 24
Peak memory 212928 kb
Host smart-3c49b817-61a6-4714-8814-348f8b51cea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608052506 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1608052506
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.2663695863
Short name T214
Test name
Test status
Simulation time 102667629 ps
CPU time 0.99 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204244 kb
Host smart-1bcb8b90-e5df-41dc-8797-189e5c6acbe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663695863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
2663695863
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.3715177307
Short name T175
Test name
Test status
Simulation time 55885271 ps
CPU time 0.69 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:50 PM PDT 24
Peak memory 204280 kb
Host smart-e97dbbff-6a92-4473-96f7-62af9ae920b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715177307 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
3715177307
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.2804724359
Short name T267
Test name
Test status
Simulation time 39802191 ps
CPU time 1.35 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204332 kb
Host smart-3d034932-b255-4960-af21-f4d21f8b5931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804724359 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.2804724359
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2916333385
Short name T308
Test name
Test status
Simulation time 142321891 ps
CPU time 2.5 seconds
Started Mar 23 01:17:48 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 212940 kb
Host smart-82dc68fb-0e4c-42c5-b036-203d6c1f28b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916333385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2916333385
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3073164940
Short name T224
Test name
Test status
Simulation time 112887222 ps
CPU time 2.26 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 214628 kb
Host smart-e15f0937-1484-4432-86ac-20e3855c5574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073164940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3073164940
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.387653853
Short name T242
Test name
Test status
Simulation time 310325622 ps
CPU time 5.76 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:39 PM PDT 24
Peak memory 204328 kb
Host smart-871f6607-4f87-4f2a-9f86-bfb2e87705d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387653853 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_aliasing.387653853
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.589897302
Short name T235
Test name
Test status
Simulation time 89564913 ps
CPU time 4.92 seconds
Started Mar 23 01:16:35 PM PDT 24
Finished Mar 23 01:16:40 PM PDT 24
Peak memory 204384 kb
Host smart-673c7ac1-b977-4b96-89d7-053252f79b0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589897302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.589897302
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.83218679
Short name T203
Test name
Test status
Simulation time 32776730 ps
CPU time 1.07 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:35 PM PDT 24
Peak memory 204432 kb
Host smart-086f9647-31d7-4cc3-950a-368be658665b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83218679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_
hw_reset.83218679
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2143098414
Short name T55
Test name
Test status
Simulation time 70981865 ps
CPU time 1.39 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:34 PM PDT 24
Peak memory 212656 kb
Host smart-99683495-e936-4c09-bf06-de6cd4fa273d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143098414 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2143098414
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.3916714674
Short name T256
Test name
Test status
Simulation time 187270326 ps
CPU time 1.11 seconds
Started Mar 23 01:16:33 PM PDT 24
Finished Mar 23 01:16:34 PM PDT 24
Peak memory 204220 kb
Host smart-becb9cc7-3086-400c-a263-d67edceab8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916714674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.3
916714674
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1174675176
Short name T279
Test name
Test status
Simulation time 96260677 ps
CPU time 1.99 seconds
Started Mar 23 01:16:32 PM PDT 24
Finished Mar 23 01:16:34 PM PDT 24
Peak memory 204280 kb
Host smart-db5eae20-7834-49b2-b5a1-efc5e77d9d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174675176 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1174675176
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.1447408411
Short name T170
Test name
Test status
Simulation time 258386531 ps
CPU time 1.77 seconds
Started Mar 23 01:16:35 PM PDT 24
Finished Mar 23 01:16:37 PM PDT 24
Peak memory 212872 kb
Host smart-ca84363c-3a2e-4076-9c69-bb13f8a15094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447408411 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.1447408411
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3810236185
Short name T304
Test name
Test status
Simulation time 1121843499 ps
CPU time 6.07 seconds
Started Mar 23 01:16:34 PM PDT 24
Finished Mar 23 01:16:40 PM PDT 24
Peak memory 213180 kb
Host smart-0022947a-e368-4d07-9f8c-5791823ffe51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810236185 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.3810236185
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.706865758
Short name T282
Test name
Test status
Simulation time 42763019 ps
CPU time 1.42 seconds
Started Mar 23 01:16:34 PM PDT 24
Finished Mar 23 01:16:35 PM PDT 24
Peak memory 214780 kb
Host smart-ffbc071d-13f2-4ca2-a196-fd897664ea68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706865758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.706865758
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.709390064
Short name T51
Test name
Test status
Simulation time 671061603 ps
CPU time 5.06 seconds
Started Mar 23 01:16:32 PM PDT 24
Finished Mar 23 01:16:37 PM PDT 24
Peak memory 213676 kb
Host smart-6887b11c-c1be-40a4-bbde-ebfb5a2e4011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709390064 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_
tl_intg_err.709390064
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.2734684476
Short name T200
Test name
Test status
Simulation time 13614235 ps
CPU time 0.87 seconds
Started Mar 23 01:17:48 PM PDT 24
Finished Mar 23 01:17:49 PM PDT 24
Peak memory 204216 kb
Host smart-385042c3-f373-43ad-8ccf-2111d614dad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734684476 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
2734684476
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.330718788
Short name T253
Test name
Test status
Simulation time 37616780 ps
CPU time 0.75 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:51 PM PDT 24
Peak memory 204292 kb
Host smart-f4cf35cf-f019-4d07-9051-41a0c9ae0ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330718788 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.330718788
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.702378953
Short name T208
Test name
Test status
Simulation time 13679695 ps
CPU time 0.99 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204232 kb
Host smart-6f954538-bf33-4a22-9062-53360b61ef39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702378953 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.702378953
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.1724520025
Short name T307
Test name
Test status
Simulation time 31103994 ps
CPU time 0.68 seconds
Started Mar 23 01:17:53 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204156 kb
Host smart-044780a2-5f65-47d9-a3b9-fa807b8e0c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724520025 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
1724520025
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.2861245130
Short name T185
Test name
Test status
Simulation time 10277036 ps
CPU time 0.81 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:50 PM PDT 24
Peak memory 204232 kb
Host smart-9c50de6e-a5fa-4348-81a6-dfecb01f2e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861245130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
2861245130
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2676793035
Short name T174
Test name
Test status
Simulation time 41298725 ps
CPU time 0.76 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204296 kb
Host smart-a8fe3547-307b-4dc5-8afe-27a8c70d0cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676793035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2676793035
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.3915278069
Short name T230
Test name
Test status
Simulation time 33395527 ps
CPU time 0.74 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204196 kb
Host smart-c4f14f74-681e-4c4f-ab28-88b7cb85cd9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915278069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
3915278069
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1305171589
Short name T298
Test name
Test status
Simulation time 26258623 ps
CPU time 0.86 seconds
Started Mar 23 01:17:48 PM PDT 24
Finished Mar 23 01:17:49 PM PDT 24
Peak memory 204184 kb
Host smart-8162d0d2-b7a6-4222-9df4-b0b75ab029c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305171589 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1305171589
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.3568554881
Short name T244
Test name
Test status
Simulation time 63913372 ps
CPU time 0.76 seconds
Started Mar 23 01:17:49 PM PDT 24
Finished Mar 23 01:17:50 PM PDT 24
Peak memory 204220 kb
Host smart-b9474941-9693-4387-a991-020bcfd5d34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568554881 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
3568554881
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2835193206
Short name T300
Test name
Test status
Simulation time 12730603 ps
CPU time 0.85 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204236 kb
Host smart-bffcc0f4-3de8-452e-95bd-84efacf904f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835193206 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
2835193206
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1295045583
Short name T210
Test name
Test status
Simulation time 444313293 ps
CPU time 3.21 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:53 PM PDT 24
Peak memory 204400 kb
Host smart-e0aa5cf1-e7a1-4d65-8795-f0098f2de93a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295045583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1295045583
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1360599980
Short name T201
Test name
Test status
Simulation time 469591842 ps
CPU time 9.24 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:58 PM PDT 24
Peak memory 204400 kb
Host smart-0d3565ff-7756-4b8b-8afd-a7bc24c83ed2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360599980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1360599980
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.2127863355
Short name T97
Test name
Test status
Simulation time 63651464 ps
CPU time 1.06 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 204332 kb
Host smart-e55d50f9-4340-49be-ae60-d05521b2b99c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127863355 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.2127863355
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.4095164109
Short name T77
Test name
Test status
Simulation time 27811998 ps
CPU time 1.01 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:50 PM PDT 24
Peak memory 204552 kb
Host smart-82481c8f-39df-462a-b340-04e682d0760b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095164109 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.4095164109
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1444689203
Short name T220
Test name
Test status
Simulation time 81372308 ps
CPU time 0.89 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 204284 kb
Host smart-9b7a657c-83ef-466e-a4a3-d6e4f51957c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444689203 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
444689203
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2969074634
Short name T192
Test name
Test status
Simulation time 11992706 ps
CPU time 0.8 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 204240 kb
Host smart-5530e12c-dcef-41e0-8c31-48877c58905f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969074634 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.2
969074634
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3255284737
Short name T251
Test name
Test status
Simulation time 282470299 ps
CPU time 2.79 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:52 PM PDT 24
Peak memory 204448 kb
Host smart-f5b3bc9d-fa12-412a-8e47-3ce3633c5637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255284737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.3255284737
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3438399445
Short name T219
Test name
Test status
Simulation time 238862082 ps
CPU time 1.9 seconds
Started Mar 23 01:16:32 PM PDT 24
Finished Mar 23 01:16:34 PM PDT 24
Peak memory 213032 kb
Host smart-23a10cb3-6c3d-4254-bb05-205ba28731bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438399445 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3438399445
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3067258508
Short name T193
Test name
Test status
Simulation time 881433057 ps
CPU time 5.2 seconds
Started Mar 23 01:16:36 PM PDT 24
Finished Mar 23 01:16:41 PM PDT 24
Peak memory 212972 kb
Host smart-ce52f132-b40a-4b11-8eee-eec3c8ab218b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067258508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.3067258508
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.4100865372
Short name T270
Test name
Test status
Simulation time 72539269 ps
CPU time 2.93 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:52 PM PDT 24
Peak memory 215712 kb
Host smart-dffb494d-e508-420f-b954-7af5c53adb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100865372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.4
100865372
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.2648294209
Short name T57
Test name
Test status
Simulation time 122983797 ps
CPU time 4.61 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:54 PM PDT 24
Peak memory 213756 kb
Host smart-a6fae8a5-4930-4619-85fd-8922a0322298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648294209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.2648294209
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.4083685590
Short name T252
Test name
Test status
Simulation time 62059569 ps
CPU time 0.87 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204280 kb
Host smart-f5eb9b19-dbdf-4643-b380-7af98856a4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083685590 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
4083685590
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.148731091
Short name T93
Test name
Test status
Simulation time 97013276 ps
CPU time 0.88 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204288 kb
Host smart-312f3809-0fea-46ad-8ff6-c9e234d7adc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148731091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.148731091
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.525462277
Short name T290
Test name
Test status
Simulation time 11197129 ps
CPU time 0.69 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204220 kb
Host smart-2dbca6ec-2d3e-40c7-9dda-5aa452de9b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525462277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.525462277
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.2983047793
Short name T277
Test name
Test status
Simulation time 49426492 ps
CPU time 0.76 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204324 kb
Host smart-4e3b34e2-cb68-4704-b464-8f1d1cffbddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983047793 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
2983047793
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.581215202
Short name T183
Test name
Test status
Simulation time 18451680 ps
CPU time 0.7 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204180 kb
Host smart-2fbcdb7d-a56f-41b8-9218-19946ef4ecd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581215202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.581215202
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.270332591
Short name T43
Test name
Test status
Simulation time 11965327 ps
CPU time 0.72 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204236 kb
Host smart-cc6c670c-1a85-432d-b28c-1dd2bc43afd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270332591 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.270332591
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.1398911304
Short name T177
Test name
Test status
Simulation time 9704321 ps
CPU time 0.74 seconds
Started Mar 23 01:17:50 PM PDT 24
Finished Mar 23 01:17:51 PM PDT 24
Peak memory 204248 kb
Host smart-ab446e34-d68b-4617-937b-95cf844ff6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398911304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
1398911304
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3471610472
Short name T198
Test name
Test status
Simulation time 10532121 ps
CPU time 0.72 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204216 kb
Host smart-0daa75cd-6db5-4838-a83f-a2a39d51f932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471610472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3471610472
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3405585232
Short name T291
Test name
Test status
Simulation time 34214348 ps
CPU time 0.82 seconds
Started Mar 23 01:17:52 PM PDT 24
Finished Mar 23 01:17:53 PM PDT 24
Peak memory 204144 kb
Host smart-cade8a88-423f-4031-834c-8687a8637998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405585232 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3405585232
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3628630323
Short name T176
Test name
Test status
Simulation time 47505248 ps
CPU time 0.82 seconds
Started Mar 23 01:17:51 PM PDT 24
Finished Mar 23 01:17:52 PM PDT 24
Peak memory 204232 kb
Host smart-78546dce-23dc-4bad-8376-6d681434cca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628630323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3628630323
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.543984791
Short name T285
Test name
Test status
Simulation time 444939133 ps
CPU time 8.47 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:57 PM PDT 24
Peak memory 204420 kb
Host smart-3855a623-0519-44e2-9628-bb5e8fbea1bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543984791 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_aliasing.543984791
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3552857199
Short name T302
Test name
Test status
Simulation time 2288213855 ps
CPU time 18.81 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:17:09 PM PDT 24
Peak memory 204460 kb
Host smart-386fce6d-5d90-40d6-9d8e-2c8b45ce5dfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552857199 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3552857199
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3596089463
Short name T184
Test name
Test status
Simulation time 324192113 ps
CPU time 1.19 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 204204 kb
Host smart-68a82d1d-ef68-4aad-b466-e0a868c17aeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596089463 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3596089463
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.3093366875
Short name T92
Test name
Test status
Simulation time 20098719 ps
CPU time 0.97 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:49 PM PDT 24
Peak memory 204300 kb
Host smart-05888858-c73e-4132-8ae3-82b8fdc489c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093366875 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.3093366875
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.1909610630
Short name T202
Test name
Test status
Simulation time 21181685 ps
CPU time 0.92 seconds
Started Mar 23 01:16:49 PM PDT 24
Finished Mar 23 01:16:50 PM PDT 24
Peak memory 204268 kb
Host smart-ca0a671c-cc5d-4d3a-a7b9-113a67efb5ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909610630 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.1
909610630
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.2963897441
Short name T283
Test name
Test status
Simulation time 123179803 ps
CPU time 0.83 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:49 PM PDT 24
Peak memory 204200 kb
Host smart-f7fdb235-05e9-41f2-a7a0-9805cb285b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963897441 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.2
963897441
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3758495764
Short name T74
Test name
Test status
Simulation time 18695002 ps
CPU time 1.19 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:50 PM PDT 24
Peak memory 204472 kb
Host smart-30c4ffd0-16ce-4204-bc6a-65e010568afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758495764 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.3758495764
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.4243865353
Short name T232
Test name
Test status
Simulation time 101152981 ps
CPU time 2.2 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 212984 kb
Host smart-c7dcf828-46ab-4c00-9682-5433d53d7e63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243865353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.4243865353
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1953165886
Short name T255
Test name
Test status
Simulation time 56047989 ps
CPU time 3.18 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:53 PM PDT 24
Peak memory 212992 kb
Host smart-0943f535-8ab9-48c0-87a6-04a725c72804
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953165886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1953165886
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.142491034
Short name T23
Test name
Test status
Simulation time 147965801 ps
CPU time 3.63 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:53 PM PDT 24
Peak memory 212612 kb
Host smart-0bf8bdd7-8648-4125-9589-38608fc6188d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142491034 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.142491034
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.621590316
Short name T278
Test name
Test status
Simulation time 15231260 ps
CPU time 0.86 seconds
Started Mar 23 01:18:01 PM PDT 24
Finished Mar 23 01:18:02 PM PDT 24
Peak memory 204180 kb
Host smart-86cbe368-8b05-45cf-a2c5-fd0c9c2b0b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621590316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.621590316
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.2532437526
Short name T241
Test name
Test status
Simulation time 26093251 ps
CPU time 0.78 seconds
Started Mar 23 01:18:02 PM PDT 24
Finished Mar 23 01:18:03 PM PDT 24
Peak memory 204180 kb
Host smart-6311c59b-eee1-4f52-a4ee-8e958ec3b756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532437526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
2532437526
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.110549448
Short name T237
Test name
Test status
Simulation time 10950078 ps
CPU time 0.71 seconds
Started Mar 23 01:18:04 PM PDT 24
Finished Mar 23 01:18:05 PM PDT 24
Peak memory 204244 kb
Host smart-5a72bdac-5a24-4ee7-acbc-ca4059ad5dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110549448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.110549448
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.243847700
Short name T223
Test name
Test status
Simulation time 13313844 ps
CPU time 0.75 seconds
Started Mar 23 01:18:11 PM PDT 24
Finished Mar 23 01:18:12 PM PDT 24
Peak memory 204216 kb
Host smart-a35c8993-079c-4eb3-89c7-1677f33d2aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243847700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.243847700
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1250867889
Short name T281
Test name
Test status
Simulation time 53277931 ps
CPU time 0.81 seconds
Started Mar 23 01:18:02 PM PDT 24
Finished Mar 23 01:18:03 PM PDT 24
Peak memory 204208 kb
Host smart-87f00c47-3f1f-4abd-92da-c27555cdfd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250867889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1250867889
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.1979186092
Short name T301
Test name
Test status
Simulation time 13305642 ps
CPU time 0.72 seconds
Started Mar 23 01:18:07 PM PDT 24
Finished Mar 23 01:18:09 PM PDT 24
Peak memory 204244 kb
Host smart-d98cb8ce-84b9-40fa-ae6d-77c4ba7f6d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979186092 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
1979186092
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.4066575336
Short name T248
Test name
Test status
Simulation time 45047993 ps
CPU time 0.79 seconds
Started Mar 23 01:18:03 PM PDT 24
Finished Mar 23 01:18:04 PM PDT 24
Peak memory 204200 kb
Host smart-abdc2d3d-049d-4623-b176-75eae1aaca68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066575336 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
4066575336
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3305360843
Short name T246
Test name
Test status
Simulation time 46268366 ps
CPU time 0.73 seconds
Started Mar 23 01:18:11 PM PDT 24
Finished Mar 23 01:18:12 PM PDT 24
Peak memory 204248 kb
Host smart-0059866b-4cfa-423a-a208-77e0bbfc1c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305360843 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3305360843
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.3688598522
Short name T123
Test name
Test status
Simulation time 116550765 ps
CPU time 0.89 seconds
Started Mar 23 01:18:03 PM PDT 24
Finished Mar 23 01:18:04 PM PDT 24
Peak memory 204244 kb
Host smart-b7395979-2f0c-4e3a-b971-a1955f1ac5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688598522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
3688598522
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3025313151
Short name T121
Test name
Test status
Simulation time 8911789 ps
CPU time 0.71 seconds
Started Mar 23 01:18:05 PM PDT 24
Finished Mar 23 01:18:06 PM PDT 24
Peak memory 204204 kb
Host smart-2128ca61-51c1-4b5d-b11e-77ff5a04d919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025313151 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3025313151
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3914966537
Short name T196
Test name
Test status
Simulation time 103230138 ps
CPU time 1.52 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:04 PM PDT 24
Peak memory 212924 kb
Host smart-d5194536-8de7-4075-af97-88feb98b5c8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914966537 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.3914966537
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1022594947
Short name T85
Test name
Test status
Simulation time 61053179 ps
CPU time 0.94 seconds
Started Mar 23 01:17:05 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 204220 kb
Host smart-2d170232-aefa-4a2b-bd43-9b0e1524d670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022594947 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.1
022594947
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.4096497385
Short name T287
Test name
Test status
Simulation time 133974053 ps
CPU time 0.73 seconds
Started Mar 23 01:17:03 PM PDT 24
Finished Mar 23 01:17:04 PM PDT 24
Peak memory 204220 kb
Host smart-7c8f851b-5528-4bd0-865a-f5a454965d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096497385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.4
096497385
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.912550686
Short name T186
Test name
Test status
Simulation time 243883431 ps
CPU time 2.88 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 204292 kb
Host smart-5f8aafc8-3f78-41f0-98c8-53f4869c29d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912550686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_dpe_same_csr_outstanding.912550686
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3180171766
Short name T212
Test name
Test status
Simulation time 129969562 ps
CPU time 4.12 seconds
Started Mar 23 01:16:50 PM PDT 24
Finished Mar 23 01:16:54 PM PDT 24
Peak memory 213032 kb
Host smart-efe48f31-90ff-469a-b238-2322d8d8843d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180171766 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3180171766
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2211968261
Short name T72
Test name
Test status
Simulation time 444994589 ps
CPU time 3.02 seconds
Started Mar 23 01:16:48 PM PDT 24
Finished Mar 23 01:16:51 PM PDT 24
Peak memory 212888 kb
Host smart-4f4b761e-927a-4832-8f30-ca5b4254ff33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211968261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.2211968261
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2885898864
Short name T216
Test name
Test status
Simulation time 51186650 ps
CPU time 3.24 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:05 PM PDT 24
Peak memory 212900 kb
Host smart-39178567-28c9-4b55-acf7-7eee9bf895dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885898864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
885898864
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.1002323864
Short name T98
Test name
Test status
Simulation time 23382426 ps
CPU time 0.91 seconds
Started Mar 23 01:17:00 PM PDT 24
Finished Mar 23 01:17:01 PM PDT 24
Peak memory 204236 kb
Host smart-d91593e6-92d3-4a20-a43b-128f1e2f2800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002323864 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.1002323864
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2104505084
Short name T171
Test name
Test status
Simulation time 36697397 ps
CPU time 1.02 seconds
Started Mar 23 01:17:00 PM PDT 24
Finished Mar 23 01:17:02 PM PDT 24
Peak memory 204308 kb
Host smart-026eb0e2-260e-405f-a0e1-b16817afcf20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104505084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
104505084
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.4012039103
Short name T45
Test name
Test status
Simulation time 11826205 ps
CPU time 0.84 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:03 PM PDT 24
Peak memory 204208 kb
Host smart-f9900862-c09c-49ee-ba2a-891af3978fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012039103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.4
012039103
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.2455011879
Short name T284
Test name
Test status
Simulation time 839259267 ps
CPU time 2.23 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:04 PM PDT 24
Peak memory 204408 kb
Host smart-6f9658c6-a593-4c2e-afbf-72f1d7c6f47e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455011879 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.2455011879
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.4249297677
Short name T48
Test name
Test status
Simulation time 185516287 ps
CPU time 2.33 seconds
Started Mar 23 01:17:06 PM PDT 24
Finished Mar 23 01:17:09 PM PDT 24
Peak memory 212860 kb
Host smart-ad9db272-aaea-4d6d-929e-3b752ed099f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249297677 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.4249297677
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.536701242
Short name T69
Test name
Test status
Simulation time 300958564 ps
CPU time 5.34 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:08 PM PDT 24
Peak memory 212944 kb
Host smart-37bc2bf1-450a-442c-9bca-7fa2876fbeeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536701242 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.536701242
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.7355031
Short name T54
Test name
Test status
Simulation time 145089037 ps
CPU time 2.62 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:05 PM PDT 24
Peak memory 214680 kb
Host smart-6bb15024-0312-4566-9849-36cbcdafca9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7355031 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.7355031
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3553413283
Short name T53
Test name
Test status
Simulation time 221683207 ps
CPU time 5.75 seconds
Started Mar 23 01:17:04 PM PDT 24
Finished Mar 23 01:17:11 PM PDT 24
Peak memory 213548 kb
Host smart-fe8216bc-4f7e-44a9-af53-b27809b73b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553413283 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3553413283
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.778207390
Short name T94
Test name
Test status
Simulation time 75764656 ps
CPU time 1.07 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:03 PM PDT 24
Peak memory 204336 kb
Host smart-85f3c9d3-f114-490a-978a-c9af4caaa488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778207390 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.778207390
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1430111222
Short name T209
Test name
Test status
Simulation time 56130191 ps
CPU time 0.86 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:02 PM PDT 24
Peak memory 204172 kb
Host smart-3d377bd1-94f3-4d5e-b784-6c291cdab0ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430111222 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1
430111222
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.965454633
Short name T190
Test name
Test status
Simulation time 80267168 ps
CPU time 0.75 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:03 PM PDT 24
Peak memory 204168 kb
Host smart-19cd2569-0cef-4832-bb00-44226463dd44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965454633 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.965454633
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.3740270965
Short name T273
Test name
Test status
Simulation time 132769114 ps
CPU time 1.88 seconds
Started Mar 23 01:17:04 PM PDT 24
Finished Mar 23 01:17:07 PM PDT 24
Peak memory 204400 kb
Host smart-d91fb04e-f30e-4f78-b122-05c3b3eb7a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740270965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.3740270965
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.2641954775
Short name T49
Test name
Test status
Simulation time 122816857 ps
CPU time 1.65 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:04 PM PDT 24
Peak memory 213060 kb
Host smart-d509047f-92f5-4ca2-b3fd-1f296280b6b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641954775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.2641954775
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3969197263
Short name T288
Test name
Test status
Simulation time 280384501 ps
CPU time 3.42 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 212860 kb
Host smart-ee9d2ead-9e99-42a5-890f-fbf63cff1e6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969197263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3969197263
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.3326231883
Short name T56
Test name
Test status
Simulation time 66036258 ps
CPU time 2.09 seconds
Started Mar 23 01:17:07 PM PDT 24
Finished Mar 23 01:17:09 PM PDT 24
Peak memory 212720 kb
Host smart-f6d88190-d522-49c2-9bc7-ec68d5b1266a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326231883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.3
326231883
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.4055964865
Short name T52
Test name
Test status
Simulation time 209443221 ps
CPU time 7.99 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:09 PM PDT 24
Peak memory 214044 kb
Host smart-a014f3be-ee80-47e7-8521-405edb4fead9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055964865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.4055964865
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.1261824676
Short name T195
Test name
Test status
Simulation time 12606010 ps
CPU time 0.87 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:02 PM PDT 24
Peak memory 204148 kb
Host smart-5cb559e8-7a90-4a93-980d-3b3df7b8ad9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261824676 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.1261824676
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.2387118442
Short name T266
Test name
Test status
Simulation time 67519900 ps
CPU time 0.99 seconds
Started Mar 23 01:17:06 PM PDT 24
Finished Mar 23 01:17:07 PM PDT 24
Peak memory 204196 kb
Host smart-4efd0b55-e73b-4630-b1bf-95fc10221823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387118442 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.2
387118442
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.2130915354
Short name T261
Test name
Test status
Simulation time 14864642 ps
CPU time 0.75 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:03 PM PDT 24
Peak memory 204172 kb
Host smart-a0502ddf-6b3f-428b-a14a-43e1dd621a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130915354 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.2
130915354
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.474108429
Short name T178
Test name
Test status
Simulation time 31949054 ps
CPU time 1.67 seconds
Started Mar 23 01:17:01 PM PDT 24
Finished Mar 23 01:17:03 PM PDT 24
Peak memory 204364 kb
Host smart-cb1a1442-505d-474c-b884-087ac914d3c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474108429 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_dpe_same_csr_outstanding.474108429
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.1000322790
Short name T243
Test name
Test status
Simulation time 246118551 ps
CPU time 2.9 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 212964 kb
Host smart-bc098d1c-6f78-4d6d-bdd9-30a880a7c6de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000322790 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.1000322790
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4141280241
Short name T249
Test name
Test status
Simulation time 1344940531 ps
CPU time 5.48 seconds
Started Mar 23 01:17:04 PM PDT 24
Finished Mar 23 01:17:10 PM PDT 24
Peak memory 212856 kb
Host smart-16a223e4-7451-44c0-b750-839cb0d109be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141280241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.4141280241
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.3598290327
Short name T280
Test name
Test status
Simulation time 174711955 ps
CPU time 3.94 seconds
Started Mar 23 01:17:02 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 212700 kb
Host smart-4a293eb2-7077-4302-8de4-44783c071ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598290327 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.3
598290327
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.1647527311
Short name T64
Test name
Test status
Simulation time 111446427 ps
CPU time 3.2 seconds
Started Mar 23 01:17:03 PM PDT 24
Finished Mar 23 01:17:06 PM PDT 24
Peak memory 213556 kb
Host smart-266b0ddb-c1b6-403c-abf8-0478489b5ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647527311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.1647527311
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.718255445
Short name T231
Test name
Test status
Simulation time 98408246 ps
CPU time 2.17 seconds
Started Mar 23 01:17:14 PM PDT 24
Finished Mar 23 01:17:16 PM PDT 24
Peak memory 212684 kb
Host smart-002ef7ec-58aa-45a1-844c-647421afef74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718255445 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.718255445
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.2320290587
Short name T306
Test name
Test status
Simulation time 37194736 ps
CPU time 0.84 seconds
Started Mar 23 01:17:10 PM PDT 24
Finished Mar 23 01:17:11 PM PDT 24
Peak memory 204244 kb
Host smart-0c5b0fbd-e260-4826-b032-f486018ba142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320290587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.2
320290587
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.782462541
Short name T44
Test name
Test status
Simulation time 65005536 ps
CPU time 0.7 seconds
Started Mar 23 01:17:14 PM PDT 24
Finished Mar 23 01:17:15 PM PDT 24
Peak memory 204204 kb
Host smart-69fbde0f-1d37-4aa7-b36c-b1a785c34626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782462541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.782462541
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.387876184
Short name T173
Test name
Test status
Simulation time 38899267 ps
CPU time 1.2 seconds
Started Mar 23 01:17:14 PM PDT 24
Finished Mar 23 01:17:16 PM PDT 24
Peak memory 204464 kb
Host smart-6ce85470-a80f-43a8-8196-ce5ef17ebbe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387876184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.ke
ymgr_dpe_same_csr_outstanding.387876184
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.2529074356
Short name T188
Test name
Test status
Simulation time 64444061 ps
CPU time 1.27 seconds
Started Mar 23 01:17:14 PM PDT 24
Finished Mar 23 01:17:16 PM PDT 24
Peak memory 212892 kb
Host smart-50ebe546-f9da-4ed3-8c65-febdbb9af2e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529074356 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.2529074356
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2257528600
Short name T228
Test name
Test status
Simulation time 430924188 ps
CPU time 3.06 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:14 PM PDT 24
Peak memory 212912 kb
Host smart-23a5c4bd-709a-4aaa-a3b1-e43932d1a898
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257528600 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2257528600
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.1950134267
Short name T22
Test name
Test status
Simulation time 42629405 ps
CPU time 2 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:13 PM PDT 24
Peak memory 213244 kb
Host smart-fb16b3d7-ec2d-44c6-821f-ba18d6f5de48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950134267 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.1
950134267
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.682189139
Short name T47
Test name
Test status
Simulation time 265218552 ps
CPU time 3.1 seconds
Started Mar 23 01:17:11 PM PDT 24
Finished Mar 23 01:17:14 PM PDT 24
Peak memory 212536 kb
Host smart-ce75d514-301d-4f96-ae72-cf9b8c39742c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682189139 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_
tl_intg_err.682189139
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.2584192747
Short name T125
Test name
Test status
Simulation time 35760491 ps
CPU time 0.81 seconds
Started Mar 23 01:44:56 PM PDT 24
Finished Mar 23 01:44:57 PM PDT 24
Peak memory 205304 kb
Host smart-14066855-d84b-4322-a877-ebfe4ccedfac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584192747 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.2
584192747
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.60981403
Short name T26
Test name
Test status
Simulation time 1227625447 ps
CPU time 14.26 seconds
Started Mar 23 01:44:53 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 232704 kb
Host smart-38400137-eb50-4d0e-a427-bc6b0dc71258
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60981403 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.60981403
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.2090447431
Short name T127
Test name
Test status
Simulation time 16847290 ps
CPU time 0.76 seconds
Started Mar 23 01:44:54 PM PDT 24
Finished Mar 23 01:44:55 PM PDT 24
Peak memory 205284 kb
Host smart-415477fe-3964-44e9-80ae-ace603d16cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090447431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.2
090447431
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.3772947544
Short name T147
Test name
Test status
Simulation time 44368080 ps
CPU time 0.75 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 205268 kb
Host smart-395ccfee-54b6-46ac-a3d2-75cbf716052a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772947544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
3772947544
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.2226891707
Short name T157
Test name
Test status
Simulation time 14888936 ps
CPU time 0.73 seconds
Started Mar 23 01:45:09 PM PDT 24
Finished Mar 23 01:45:10 PM PDT 24
Peak memory 205304 kb
Host smart-bd9ca613-543e-44b2-b5b2-caa20476db03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226891707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
2226891707
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.3330424177
Short name T143
Test name
Test status
Simulation time 55073062 ps
CPU time 0.8 seconds
Started Mar 23 01:45:10 PM PDT 24
Finished Mar 23 01:45:10 PM PDT 24
Peak memory 205288 kb
Host smart-80bf79b7-9c16-41ae-97f7-6ed9cda9e52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330424177 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
3330424177
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1002753011
Short name T2
Test name
Test status
Simulation time 46079056 ps
CPU time 0.88 seconds
Started Mar 23 01:45:09 PM PDT 24
Finished Mar 23 01:45:10 PM PDT 24
Peak memory 205344 kb
Host smart-90c7dfde-e0b6-47f9-999d-55a04791c4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002753011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1002753011
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.238908572
Short name T9
Test name
Test status
Simulation time 1334619178 ps
CPU time 15.41 seconds
Started Mar 23 01:45:08 PM PDT 24
Finished Mar 23 01:45:24 PM PDT 24
Peak memory 207592 kb
Host smart-8574f821-2ecf-4308-b53a-f84be55ede50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238908572 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.238908572
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.1489100934
Short name T28
Test name
Test status
Simulation time 13572933 ps
CPU time 0.88 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:08 PM PDT 24
Peak memory 205348 kb
Host smart-757535e5-47cc-4896-ad44-7709593f148b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489100934 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
1489100934
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.20754436
Short name T161
Test name
Test status
Simulation time 8386215763 ps
CPU time 38.27 seconds
Started Mar 23 01:45:10 PM PDT 24
Finished Mar 23 01:45:49 PM PDT 24
Peak memory 208456 kb
Host smart-9b01d4dc-d774-4e07-a7f1-0b71965e86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20754436 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.20754436
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.1207414518
Short name T133
Test name
Test status
Simulation time 11251344 ps
CPU time 0.87 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 205288 kb
Host smart-80f86433-13ba-4e81-ac7b-ec21f9cb1309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207414518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
1207414518
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.36235477
Short name T165
Test name
Test status
Simulation time 32452355 ps
CPU time 0.81 seconds
Started Mar 23 01:45:21 PM PDT 24
Finished Mar 23 01:45:22 PM PDT 24
Peak memory 205240 kb
Host smart-4e315a0e-bc27-4ed5-b9eb-c2d0acbcb09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.36235477
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.4145991263
Short name T30
Test name
Test status
Simulation time 2868425055 ps
CPU time 19.96 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:27 PM PDT 24
Peak memory 208260 kb
Host smart-95b446fb-dc11-4e27-ab35-2177472100b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145991263 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.4145991263
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.2284069240
Short name T1
Test name
Test status
Simulation time 54687374 ps
CPU time 0.88 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:20 PM PDT 24
Peak memory 205340 kb
Host smart-956a8e6b-349e-4205-a4c2-8c29901dc8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284069240 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
2284069240
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.1259556438
Short name T146
Test name
Test status
Simulation time 959649021 ps
CPU time 13.63 seconds
Started Mar 23 01:45:17 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 206496 kb
Host smart-89973406-b887-4129-b02b-7d0cd21646fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259556438 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.1259556438
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.786719697
Short name T166
Test name
Test status
Simulation time 12845307 ps
CPU time 0.7 seconds
Started Mar 23 01:45:20 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205344 kb
Host smart-a78cb1dd-d662-4ae9-adbc-8d609d0adf64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786719697 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.786719697
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.905901811
Short name T135
Test name
Test status
Simulation time 11992854 ps
CPU time 0.75 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205292 kb
Host smart-42586061-4eaf-4e23-911c-ff6efafecc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905901811 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.905901811
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.3830834618
Short name T82
Test name
Test status
Simulation time 16197867 ps
CPU time 0.91 seconds
Started Mar 23 01:44:57 PM PDT 24
Finished Mar 23 01:44:58 PM PDT 24
Peak memory 205380 kb
Host smart-580666cb-1b97-41af-86df-60881f822197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830834618 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.3
830834618
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.685148282
Short name T130
Test name
Test status
Simulation time 2729727798 ps
CPU time 27.99 seconds
Started Mar 23 01:44:54 PM PDT 24
Finished Mar 23 01:45:22 PM PDT 24
Peak memory 207244 kb
Host smart-23d98ef9-6d5a-42af-9dde-921f67cbe9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685148282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.685148282
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.2104575316
Short name T154
Test name
Test status
Simulation time 24815421 ps
CPU time 0.87 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:20 PM PDT 24
Peak memory 205280 kb
Host smart-eb1e6337-6658-4f5f-94be-81240c9f2265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104575316 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
2104575316
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.3444207510
Short name T84
Test name
Test status
Simulation time 13410707722 ps
CPU time 59.51 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:46:19 PM PDT 24
Peak memory 207684 kb
Host smart-e02a5177-a328-422c-a19c-379da43bcc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444207510 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.3444207510
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.391994742
Short name T156
Test name
Test status
Simulation time 14032936 ps
CPU time 0.78 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:19 PM PDT 24
Peak memory 205280 kb
Host smart-feca825c-80ea-49dc-b428-1c78367e3de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391994742 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.391994742
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3754345245
Short name T151
Test name
Test status
Simulation time 8442689 ps
CPU time 0.73 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:19 PM PDT 24
Peak memory 205268 kb
Host smart-23548ff9-5cde-45a9-9143-0b1d0a6a3b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754345245 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3754345245
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.3247920046
Short name T162
Test name
Test status
Simulation time 14149179 ps
CPU time 0.94 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:19 PM PDT 24
Peak memory 205476 kb
Host smart-598ce95e-145e-40ce-969e-a7ce4ed4c851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247920046 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
3247920046
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.1654388450
Short name T116
Test name
Test status
Simulation time 5069883391 ps
CPU time 121.95 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:47:21 PM PDT 24
Peak memory 221884 kb
Host smart-7e8f6399-9c80-4fc4-afd2-d39bc31a3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654388450 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.1654388450
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.618901472
Short name T32
Test name
Test status
Simulation time 15288465 ps
CPU time 0.9 seconds
Started Mar 23 01:45:20 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205428 kb
Host smart-a4f3cd05-60f3-4944-81f9-d261a85fd21d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618901472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.618901472
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.741436225
Short name T152
Test name
Test status
Simulation time 9748793 ps
CPU time 0.7 seconds
Started Mar 23 01:45:21 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205316 kb
Host smart-3d5b9856-c777-4409-8690-ac4b86e6243b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741436225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.741436225
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.575575549
Short name T149
Test name
Test status
Simulation time 43408774 ps
CPU time 0.84 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:20 PM PDT 24
Peak memory 205364 kb
Host smart-b4d94a8f-99df-457b-8a16-2a6f20ce3519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575575549 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.575575549
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.511206249
Short name T12
Test name
Test status
Simulation time 1212146742 ps
CPU time 25.15 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:43 PM PDT 24
Peak memory 208168 kb
Host smart-bc56ad34-c2e3-458d-a661-b2ac8bd1595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511206249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.511206249
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.2282390098
Short name T144
Test name
Test status
Simulation time 113116838 ps
CPU time 0.82 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205296 kb
Host smart-74aa48dc-c400-48dc-a101-91d632ee4054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282390098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
2282390098
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.672480933
Short name T103
Test name
Test status
Simulation time 461255493 ps
CPU time 17.69 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:38 PM PDT 24
Peak memory 207644 kb
Host smart-6c1d1bdf-cb5c-484c-ba72-13c8ee035bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672480933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.672480933
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.2800444852
Short name T17
Test name
Test status
Simulation time 16006336 ps
CPU time 0.96 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:19 PM PDT 24
Peak memory 205496 kb
Host smart-9972a3a0-e641-45b5-ac95-507ad4dd4dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800444852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
2800444852
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2310834572
Short name T145
Test name
Test status
Simulation time 9920265 ps
CPU time 0.84 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:19 PM PDT 24
Peak memory 205248 kb
Host smart-a328a020-947d-402e-9b2a-1738e2619d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310834572 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2310834572
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.1936889297
Short name T159
Test name
Test status
Simulation time 1164790864 ps
CPU time 29.3 seconds
Started Mar 23 01:45:17 PM PDT 24
Finished Mar 23 01:45:47 PM PDT 24
Peak memory 207588 kb
Host smart-26da7d8c-438b-4cf8-969b-8235903af081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936889297 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.1936889297
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.2252346698
Short name T137
Test name
Test status
Simulation time 132876888 ps
CPU time 0.76 seconds
Started Mar 23 01:44:53 PM PDT 24
Finished Mar 23 01:44:54 PM PDT 24
Peak memory 205344 kb
Host smart-cbf26d40-e880-40f9-8f15-e4101d02a23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252346698 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.2
252346698
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.3249049950
Short name T7
Test name
Test status
Simulation time 519923569 ps
CPU time 13.3 seconds
Started Mar 23 01:44:52 PM PDT 24
Finished Mar 23 01:45:05 PM PDT 24
Peak memory 230276 kb
Host smart-582c45c0-1406-4ae8-9e17-eca64e5f2a1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249049950 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.3249049950
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.2191459828
Short name T150
Test name
Test status
Simulation time 17965777 ps
CPU time 0.99 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:20 PM PDT 24
Peak memory 205496 kb
Host smart-9b07b397-c9b0-4097-83ee-746922fd79b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191459828 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
2191459828
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.3637554061
Short name T83
Test name
Test status
Simulation time 908381642 ps
CPU time 23.91 seconds
Started Mar 23 01:45:22 PM PDT 24
Finished Mar 23 01:45:46 PM PDT 24
Peak memory 207636 kb
Host smart-492d637d-b259-41de-bee6-f5d1c1b3f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637554061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.3637554061
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2885988755
Short name T153
Test name
Test status
Simulation time 13854189 ps
CPU time 0.72 seconds
Started Mar 23 01:45:19 PM PDT 24
Finished Mar 23 01:45:21 PM PDT 24
Peak memory 205192 kb
Host smart-14b642cb-9f38-47fe-bd6a-697bf270cbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885988755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2885988755
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1436158361
Short name T139
Test name
Test status
Simulation time 6215074824 ps
CPU time 38.46 seconds
Started Mar 23 01:45:20 PM PDT 24
Finished Mar 23 01:45:58 PM PDT 24
Peak memory 207592 kb
Host smart-4b9a57b2-2207-49bc-a1a2-0addc9f19a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436158361 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1436158361
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.909939053
Short name T19
Test name
Test status
Simulation time 23934412 ps
CPU time 0.85 seconds
Started Mar 23 01:45:16 PM PDT 24
Finished Mar 23 01:45:17 PM PDT 24
Peak memory 205308 kb
Host smart-69e4635f-e2c6-4cf5-9a2b-a8edb316172a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909939053 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.909939053
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.2249921000
Short name T14
Test name
Test status
Simulation time 463920748 ps
CPU time 13.39 seconds
Started Mar 23 01:45:18 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 208116 kb
Host smart-f9406bcf-99bd-4784-bd64-8a0ba1363cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249921000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.2249921000
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.3239318644
Short name T164
Test name
Test status
Simulation time 131242930 ps
CPU time 0.8 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 205336 kb
Host smart-593b7f56-4126-4992-8edc-ac2de98f196d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239318644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
3239318644
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.1063191295
Short name T114
Test name
Test status
Simulation time 241873676 ps
CPU time 13.21 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:43 PM PDT 24
Peak memory 208408 kb
Host smart-6865b533-944b-47a8-8b38-ef2648f85d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063191295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.1063191295
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.225619625
Short name T27
Test name
Test status
Simulation time 18057344 ps
CPU time 0.79 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205272 kb
Host smart-24ddcbe6-3a26-4e45-b6c3-d7935b8a6255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225619625 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.225619625
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3277200502
Short name T142
Test name
Test status
Simulation time 11567395048 ps
CPU time 200.93 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:48:50 PM PDT 24
Peak memory 234280 kb
Host smart-e56d3228-d1c8-4d60-93d2-58b4ad72a35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277200502 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3277200502
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.1572904813
Short name T80
Test name
Test status
Simulation time 38337992 ps
CPU time 0.66 seconds
Started Mar 23 01:45:33 PM PDT 24
Finished Mar 23 01:45:34 PM PDT 24
Peak memory 205356 kb
Host smart-08525284-c3af-4532-8cec-eaa31ea63ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572904813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
1572904813
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.2976938079
Short name T107
Test name
Test status
Simulation time 3761283068 ps
CPU time 34.64 seconds
Started Mar 23 01:45:31 PM PDT 24
Finished Mar 23 01:46:05 PM PDT 24
Peak memory 207424 kb
Host smart-f4249f9b-b4f9-4258-90d2-bf3a7ce2a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976938079 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.2976938079
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.3724986243
Short name T16
Test name
Test status
Simulation time 112822603 ps
CPU time 0.98 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 205412 kb
Host smart-5acd4634-5289-4f08-a3f7-6dc0bad71d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724986243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
3724986243
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.2292424065
Short name T89
Test name
Test status
Simulation time 964878811 ps
CPU time 18.91 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:49 PM PDT 24
Peak memory 206236 kb
Host smart-89b7f45d-80b0-4187-9068-435824c0bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292424065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.2292424065
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.2600279541
Short name T81
Test name
Test status
Simulation time 27857376 ps
CPU time 0.75 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205308 kb
Host smart-eb02e9d4-bb3e-46b9-aa02-8d93937cf2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600279541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
2600279541
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.2035845077
Short name T88
Test name
Test status
Simulation time 8036360402 ps
CPU time 46.46 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:46:16 PM PDT 24
Peak memory 208372 kb
Host smart-8dc47c45-15c0-4738-a286-57c51c370a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035845077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.2035845077
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.3896456608
Short name T163
Test name
Test status
Simulation time 20113994 ps
CPU time 0.92 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 205508 kb
Host smart-a13be6fb-1046-4473-afa5-d26512324907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896456608 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
3896456608
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1774980332
Short name T132
Test name
Test status
Simulation time 16103573 ps
CPU time 0.77 seconds
Started Mar 23 01:44:56 PM PDT 24
Finished Mar 23 01:44:57 PM PDT 24
Peak memory 205228 kb
Host smart-0e0fdf7c-a79d-487d-910e-38c7d5cab24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774980332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
774980332
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.1687352105
Short name T8
Test name
Test status
Simulation time 577924259 ps
CPU time 9.66 seconds
Started Mar 23 01:44:57 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 229688 kb
Host smart-220c4ef4-2286-4c70-808a-e6a5f6a90986
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687352105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.1687352105
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3950648758
Short name T158
Test name
Test status
Simulation time 989230443 ps
CPU time 19.69 seconds
Started Mar 23 01:44:54 PM PDT 24
Finished Mar 23 01:45:14 PM PDT 24
Peak memory 207204 kb
Host smart-6b82cfb2-a549-4fbb-8323-b11672372fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950648758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3950648758
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.2531479992
Short name T129
Test name
Test status
Simulation time 16419438 ps
CPU time 0.8 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205356 kb
Host smart-06dc7c00-413d-4dbd-8e16-90cac7825a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531479992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
2531479992
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.274747734
Short name T20
Test name
Test status
Simulation time 12207106 ps
CPU time 0.73 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205348 kb
Host smart-59ecfd02-3ca5-439b-9466-cbcc6a90b08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274747734 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.274747734
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.282224907
Short name T18
Test name
Test status
Simulation time 91573599 ps
CPU time 0.83 seconds
Started Mar 23 01:45:31 PM PDT 24
Finished Mar 23 01:45:32 PM PDT 24
Peak memory 205344 kb
Host smart-25f2a6ed-5300-4078-992e-1ac70744be9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282224907 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.282224907
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.532815877
Short name T136
Test name
Test status
Simulation time 18556816 ps
CPU time 1 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 205336 kb
Host smart-8cd16418-269f-40a4-9acb-700f9a0c2dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532815877 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.532815877
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.1387328440
Short name T141
Test name
Test status
Simulation time 10537070 ps
CPU time 0.74 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205376 kb
Host smart-68102942-3970-4f0b-89ac-74c0150a521e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387328440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
1387328440
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.580125421
Short name T148
Test name
Test status
Simulation time 1143807249 ps
CPU time 21.04 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:50 PM PDT 24
Peak memory 207520 kb
Host smart-3e387dd2-23b3-4f34-814f-cd72be6b9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580125421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.580125421
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.3092637697
Short name T155
Test name
Test status
Simulation time 21817451 ps
CPU time 0.88 seconds
Started Mar 23 01:45:28 PM PDT 24
Finished Mar 23 01:45:29 PM PDT 24
Peak memory 205204 kb
Host smart-5da6f786-9224-48b4-8cd8-1ddd954df846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092637697 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
3092637697
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.2986600119
Short name T138
Test name
Test status
Simulation time 1423162503 ps
CPU time 17.71 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:48 PM PDT 24
Peak memory 208092 kb
Host smart-17c9dad8-d97a-4bac-b241-aa7ff4060446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986600119 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.2986600119
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.419058848
Short name T79
Test name
Test status
Simulation time 23883380 ps
CPU time 0.91 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205304 kb
Host smart-f563e43b-e51a-4151-82ba-8cda80b6e48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419058848 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.419058848
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.4207272026
Short name T13
Test name
Test status
Simulation time 464375763 ps
CPU time 17.5 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:47 PM PDT 24
Peak memory 207332 kb
Host smart-bc49c7c9-83ed-44be-93b0-e9507a26728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207272026 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.4207272026
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1258503770
Short name T31
Test name
Test status
Simulation time 66834202 ps
CPU time 0.85 seconds
Started Mar 23 01:45:31 PM PDT 24
Finished Mar 23 01:45:32 PM PDT 24
Peak memory 205292 kb
Host smart-97973488-a304-45c4-8f43-87e5bbb95ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258503770 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1258503770
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.3030738377
Short name T126
Test name
Test status
Simulation time 10494154 ps
CPU time 0.85 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:31 PM PDT 24
Peak memory 205288 kb
Host smart-d033c034-f04d-4c11-ba21-2c336afc621f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030738377 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
3030738377
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.331909546
Short name T113
Test name
Test status
Simulation time 1313335293 ps
CPU time 24.89 seconds
Started Mar 23 01:45:30 PM PDT 24
Finished Mar 23 01:45:55 PM PDT 24
Peak memory 208176 kb
Host smart-0ab4966f-e714-4571-8afd-ff053f6e7d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331909546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.331909546
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.885303036
Short name T124
Test name
Test status
Simulation time 23151061 ps
CPU time 0.76 seconds
Started Mar 23 01:45:29 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 205268 kb
Host smart-af65d2cc-3557-43d1-b5e0-ae319e78645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885303036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.885303036
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.4069601561
Short name T131
Test name
Test status
Simulation time 44277851 ps
CPU time 0.74 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:08 PM PDT 24
Peak memory 205208 kb
Host smart-e3902431-5c7f-406c-b5b1-a219fa6b26c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069601561 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.4
069601561
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.1707538001
Short name T134
Test name
Test status
Simulation time 566457971 ps
CPU time 21.02 seconds
Started Mar 23 01:45:09 PM PDT 24
Finished Mar 23 01:45:30 PM PDT 24
Peak memory 208116 kb
Host smart-7938e5bf-7ab7-4a8d-b38b-28a126e50a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707538001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.1707538001
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.1463450647
Short name T78
Test name
Test status
Simulation time 18135844 ps
CPU time 0.79 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 205248 kb
Host smart-2fd4e85a-cd93-4f14-a66d-9df77ae31ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463450647 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.1
463450647
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.847305260
Short name T11
Test name
Test status
Simulation time 2094080156 ps
CPU time 10.31 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:16 PM PDT 24
Peak memory 206016 kb
Host smart-0c4d9180-302a-4404-b3c9-3baf1ef1b1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847305260 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.847305260
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.3092759006
Short name T128
Test name
Test status
Simulation time 130036336 ps
CPU time 0.82 seconds
Started Mar 23 01:45:07 PM PDT 24
Finished Mar 23 01:45:08 PM PDT 24
Peak memory 205292 kb
Host smart-56edc177-ca9c-4286-830f-87abb6629663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092759006 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.3
092759006
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.2088609100
Short name T140
Test name
Test status
Simulation time 20649283 ps
CPU time 0.72 seconds
Started Mar 23 01:45:08 PM PDT 24
Finished Mar 23 01:45:08 PM PDT 24
Peak memory 205332 kb
Host smart-a424ca5a-68a4-4072-a142-8c0e6841acbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088609100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.2
088609100
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.1959736413
Short name T118
Test name
Test status
Simulation time 1464518149 ps
CPU time 31.47 seconds
Started Mar 23 01:45:08 PM PDT 24
Finished Mar 23 01:45:40 PM PDT 24
Peak memory 207264 kb
Host smart-ff4d4fbc-219f-459a-b1db-7108def68932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959736413 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.1959736413
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1145857389
Short name T160
Test name
Test status
Simulation time 42662107 ps
CPU time 0.87 seconds
Started Mar 23 01:45:06 PM PDT 24
Finished Mar 23 01:45:07 PM PDT 24
Peak memory 205312 kb
Host smart-425823d4-8599-4e41-84c6-7f081b5d4307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145857389 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
145857389
Directory /workspace/9.keymgr_dpe_alert_test/latest
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