Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
17.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	17	4	13	76.47
Crosses	240	208	32	13.33

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	1	1	50.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	1	4	80.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	4	2	2	50.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	160	144	16	10.00	100	1	1	0
op_x_status_cross	80	64	16	20.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cdi_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Attestation]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

6880

1

T4

152

T5

154

T6

144

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	1719	1			T4	42		T5	38		T6	36
auto[Aes]	1699	1			T4	29		T5	31		T6	26
auto[Kmac]	1740	1			T4	44		T5	40		T6	49
auto[Otbn]	1722	1			T4	37		T5	45		T6	33

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeErase]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpDpeAdvance]	1536	1			T4	32		T5	34		T6	30
auto[OpDpeGenSwOut]	3450	1			T4	68		T5	75		T6	78
auto[OpDpeGenHwOut]	3430	1			T4	84		T5	79		T6	66
auto[OpDpeDisable]	100	1			T4	2		T5	2		T6	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

3365

1

T4

84

T5

54

T6

83

auto[OpDoneFail]

5151

1

T4

102

T5

136

T6

93

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

353

1

T4

15

T5

8

T6

2

auto[StWorkDpeAvailable]

8163

1

T4

171

T5

182

T6

174

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	144	16	10.00	144

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	64
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Sealing]]	*	[auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	--	--	16
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	32
[auto[OpDpeDisable]]	*	*	*	--	--	32

Covered bins

op_cp

cdi_cp

dest_cp

state_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

41

1

T4

4

T5

1

T15

3

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

857

1

T4

16

T5

20

T6

19

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

33

1

T5

1

T16

1

T30

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

818

1

T4

13

T5

9

T6

18

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

32

1

T4

1

T30

1

T99

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

796

1

T4

15

T5

19

T6

23

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

31

1

T5

1

T15

4

T99

3

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

842

1

T4

19

T5

24

T6

18

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

24

1

T4

3

T15

2

T16

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

797

1

T4

19

T5

17

T6

17

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

36

1

T4

2

T5

2

T15

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

812

1

T4

14

T5

19

T6

8

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

26

1

T4

3

T15

1

T16

3

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

886

1

T4

25

T5

21

T6

26

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

30

1

T5

1

T15

3

T16

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

819

1

T4

18

T5

19

T6

15

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	64	16	20.00	64

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	32
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	16
[auto[OpDpeDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase] , auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut] , auto[OpDpeDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp

cdi_cp

dest_cp

op_status_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

378

1

T4

9

T5

8

T6

12

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

520

1

T4

11

T5

13

T6

7

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

364

1

T4

10

T5

3

T6

8

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

487

1

T4

3

T5

7

T6

10

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

338

1

T4

9

T5

3

T6

11

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

490

1

T4

7

T5

16

T6

12

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

359

1

T4

11

T5

7

T6

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

514

1

T4

8

T5

18

T6

5

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

345

1

T4

10

T5

4

T6

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

476

1

T4

12

T5

13

T6

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

363

1

T4

6

T5

8

T6

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

485

1

T4

10

T5

13

T6

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

390

1

T4

14

T5

5

T6

9

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

522

1

T4

14

T5

16

T6

17

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

351

1

T4

5

T5

7

T6

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

498

1

T4

13

T5

13

T6

8