Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.25 97.70 90.58 57.52 76.92 94.94 98.34 17.75


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.207157431 Mar 30 12:43:46 PM PDT 24 Mar 30 12:43:47 PM PDT 24 47546380 ps
T256 /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3816236628 Mar 30 12:43:42 PM PDT 24 Mar 30 12:43:44 PM PDT 24 36218810 ps
T257 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3788563128 Mar 30 12:43:24 PM PDT 24 Mar 30 12:43:32 PM PDT 24 42429640 ps
T258 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3257061960 Mar 30 12:43:28 PM PDT 24 Mar 30 12:43:38 PM PDT 24 716682882 ps
T259 /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.4231712279 Mar 30 12:43:32 PM PDT 24 Mar 30 12:43:41 PM PDT 24 54527647 ps
T260 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.375750332 Mar 30 12:43:17 PM PDT 24 Mar 30 12:43:24 PM PDT 24 21215617 ps
T261 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.531904488 Mar 30 12:43:23 PM PDT 24 Mar 30 12:43:34 PM PDT 24 103398441 ps
T262 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.481125528 Mar 30 12:43:35 PM PDT 24 Mar 30 12:43:43 PM PDT 24 52512469 ps
T263 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2331154852 Mar 30 12:43:32 PM PDT 24 Mar 30 12:43:43 PM PDT 24 49513653 ps
T264 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.656620095 Mar 30 12:43:15 PM PDT 24 Mar 30 12:43:23 PM PDT 24 24581812 ps
T265 /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.259600313 Mar 30 12:44:12 PM PDT 24 Mar 30 12:44:13 PM PDT 24 49607394 ps
T266 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.53301859 Mar 30 12:44:12 PM PDT 24 Mar 30 12:44:13 PM PDT 24 25654689 ps
T267 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1952367679 Mar 30 12:43:10 PM PDT 24 Mar 30 12:43:18 PM PDT 24 17990499 ps
T268 /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.2812756985 Mar 30 12:43:33 PM PDT 24 Mar 30 12:43:41 PM PDT 24 24962333 ps
T269 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3185534400 Mar 30 12:43:34 PM PDT 24 Mar 30 12:43:43 PM PDT 24 56482562 ps
T270 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.4153560839 Mar 30 12:43:23 PM PDT 24 Mar 30 12:43:34 PM PDT 24 124727409 ps
T271 /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.1823802246 Mar 30 12:43:22 PM PDT 24 Mar 30 12:43:31 PM PDT 24 21929769 ps
T272 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2683726753 Mar 30 12:43:12 PM PDT 24 Mar 30 12:43:22 PM PDT 24 667552184 ps
T273 /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.346767305 Mar 30 12:43:55 PM PDT 24 Mar 30 12:43:56 PM PDT 24 10718714 ps
T274 /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2883571124 Mar 30 12:43:53 PM PDT 24 Mar 30 12:43:54 PM PDT 24 31704123 ps
T275 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3040275846 Mar 30 12:43:40 PM PDT 24 Mar 30 12:43:46 PM PDT 24 190939744 ps
T276 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1040375121 Mar 30 12:43:19 PM PDT 24 Mar 30 12:43:37 PM PDT 24 171735756 ps
T277 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.2376136069 Mar 30 12:43:26 PM PDT 24 Mar 30 12:43:36 PM PDT 24 178421191 ps
T278 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2024364323 Mar 30 12:43:40 PM PDT 24 Mar 30 12:43:47 PM PDT 24 189948513 ps
T279 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.1269259019 Mar 30 12:43:47 PM PDT 24 Mar 30 12:43:48 PM PDT 24 8078416 ps
T280 /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.881387634 Mar 30 12:43:46 PM PDT 24 Mar 30 12:43:47 PM PDT 24 12588103 ps
T281 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2817913279 Mar 30 12:43:24 PM PDT 24 Mar 30 12:43:33 PM PDT 24 356856448 ps
T282 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3512639454 Mar 30 12:43:35 PM PDT 24 Mar 30 12:43:42 PM PDT 24 14497855 ps
T283 /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.192402796 Mar 30 12:43:45 PM PDT 24 Mar 30 12:43:46 PM PDT 24 13855038 ps
T284 /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.657819045 Mar 30 12:43:53 PM PDT 24 Mar 30 12:43:54 PM PDT 24 11629531 ps
T285 /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.210741109 Mar 30 12:43:23 PM PDT 24 Mar 30 12:43:32 PM PDT 24 161383479 ps
T286 /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3576693702 Mar 30 12:43:49 PM PDT 24 Mar 30 12:43:51 PM PDT 24 60552398 ps
T287 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3472306729 Mar 30 12:43:29 PM PDT 24 Mar 30 12:43:33 PM PDT 24 489345879 ps
T288 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3487405652 Mar 30 12:43:34 PM PDT 24 Mar 30 12:43:41 PM PDT 24 11658157 ps
T289 /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2376508937 Mar 30 12:43:53 PM PDT 24 Mar 30 12:43:54 PM PDT 24 37784464 ps
T290 /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2724767156 Mar 30 12:43:28 PM PDT 24 Mar 30 12:43:33 PM PDT 24 139404511 ps
T43 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.2559147948 Mar 30 12:43:20 PM PDT 24 Mar 30 12:43:34 PM PDT 24 204075228 ps
T53 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3935059959 Mar 30 12:43:34 PM PDT 24 Mar 30 12:43:45 PM PDT 24 341385522 ps
T291 /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.1106313941 Mar 30 12:43:33 PM PDT 24 Mar 30 12:43:39 PM PDT 24 11226567 ps
T292 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2505490050 Mar 30 12:43:44 PM PDT 24 Mar 30 12:43:45 PM PDT 24 53078772 ps
T293 /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3884625795 Mar 30 12:43:45 PM PDT 24 Mar 30 12:43:46 PM PDT 24 38594669 ps
T294 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1252994192 Mar 30 12:43:33 PM PDT 24 Mar 30 12:43:41 PM PDT 24 15677658 ps
T295 /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3762263342 Mar 30 12:43:43 PM PDT 24 Mar 30 12:43:44 PM PDT 24 48095220 ps
T296 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3650458937 Mar 30 12:43:20 PM PDT 24 Mar 30 12:43:29 PM PDT 24 19250113 ps
T297 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1135500500 Mar 30 12:43:22 PM PDT 24 Mar 30 12:43:32 PM PDT 24 41102964 ps
T298 /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2911506061 Mar 30 12:43:32 PM PDT 24 Mar 30 12:43:42 PM PDT 24 113770798 ps
T299 /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3082849787 Mar 30 12:43:40 PM PDT 24 Mar 30 12:43:47 PM PDT 24 119183764 ps
T300 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.932635738 Mar 30 12:43:34 PM PDT 24 Mar 30 12:43:49 PM PDT 24 436424072 ps
T301 /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.1218573686 Mar 30 12:43:19 PM PDT 24 Mar 30 12:43:29 PM PDT 24 77593366 ps
T55 /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3710599729 Mar 30 12:43:16 PM PDT 24 Mar 30 12:43:25 PM PDT 24 380953944 ps
T302 /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2363222219 Mar 30 12:43:17 PM PDT 24 Mar 30 12:43:26 PM PDT 24 7546914 ps
T303 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1005166982 Mar 30 12:43:58 PM PDT 24 Mar 30 12:43:59 PM PDT 24 21452260 ps
T304 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.1288157196 Mar 30 12:43:35 PM PDT 24 Mar 30 12:43:42 PM PDT 24 11135956 ps
T305 /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3742176071 Mar 30 12:43:36 PM PDT 24 Mar 30 12:43:41 PM PDT 24 8854906 ps
T306 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3557219036 Mar 30 12:43:35 PM PDT 24 Mar 30 12:43:44 PM PDT 24 334859349 ps
T307 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1061118132 Mar 30 12:43:44 PM PDT 24 Mar 30 12:43:45 PM PDT 24 42378013 ps
T308 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.515238297 Mar 30 12:43:36 PM PDT 24 Mar 30 12:43:42 PM PDT 24 17062249 ps
T50 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2743908817 Mar 30 12:43:43 PM PDT 24 Mar 30 12:43:47 PM PDT 24 366382377 ps
T309 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1304902875 Mar 30 12:43:32 PM PDT 24 Mar 30 12:43:42 PM PDT 24 175943326 ps
T310 /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3339838849 Mar 30 12:43:26 PM PDT 24 Mar 30 12:43:32 PM PDT 24 79630579 ps

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.1049742485
Short name T4
Test name
Test status
Simulation time 6497597419 ps
CPU time 50.92 seconds
Started Mar 30 12:52:19 PM PDT 24
Finished Mar 30 12:53:10 PM PDT 24
Peak memory 207952 kb
Host smart-cc45dcbd-5fa0-4c74-b4e2-2cce49a0e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049742485 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.1049742485
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.3063878991
Short name T8
Test name
Test status
Simulation time 1347681138 ps
CPU time 7.17 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 233788 kb
Host smart-94c411f9-6a2f-4e29-b6eb-48231466a873
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063878991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.3063878991
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.3367811717
Short name T21
Test name
Test status
Simulation time 403426995 ps
CPU time 6.67 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212972 kb
Host smart-9b7b6874-1650-42a0-b3ec-ba0fbd977633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367811717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.3367811717
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.833543522
Short name T34
Test name
Test status
Simulation time 601240485 ps
CPU time 3.3 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212640 kb
Host smart-e2283a43-79ec-426a-a3a6-b0fa5bbf31a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833543522 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.833543522
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2188888055
Short name T62
Test name
Test status
Simulation time 207947601 ps
CPU time 3.24 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 212892 kb
Host smart-c1574f21-58aa-4c8d-b247-91f6593ea1d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188888055 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.2188888055
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3420021262
Short name T5
Test name
Test status
Simulation time 11359759434 ps
CPU time 28.85 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:57 PM PDT 24
Peak memory 208272 kb
Host smart-0f1b2ef1-e4ad-4b05-ab9b-1ac1a0f519da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420021262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3420021262
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.586519849
Short name T41
Test name
Test status
Simulation time 33750477 ps
CPU time 0.81 seconds
Started Mar 30 12:43:16 PM PDT 24
Finished Mar 30 12:43:23 PM PDT 24
Peak memory 204144 kb
Host smart-4eeef5d8-0456-4712-b3c8-108eab0ebb08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586519849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.586519849
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.205787420
Short name T3
Test name
Test status
Simulation time 14422685 ps
CPU time 0.77 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 205344 kb
Host smart-155a6525-a0c8-4083-8915-1b60b2e9afca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205787420 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.205787420
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.2937969635
Short name T58
Test name
Test status
Simulation time 317675793 ps
CPU time 2.67 seconds
Started Mar 30 12:43:08 PM PDT 24
Finished Mar 30 12:43:12 PM PDT 24
Peak memory 212832 kb
Host smart-1818a15b-762b-4b33-a6fd-600ac61c5a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937969635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.2937969635
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.3874965370
Short name T74
Test name
Test status
Simulation time 13039013 ps
CPU time 1.23 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 220776 kb
Host smart-563b3994-05dc-4564-8747-3e1beda709cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874965370 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.3874965370
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.2600294008
Short name T56
Test name
Test status
Simulation time 141015534 ps
CPU time 2.16 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212612 kb
Host smart-59094787-4f3c-46af-be62-626a237b83c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600294008 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.2
600294008
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.28981272
Short name T48
Test name
Test status
Simulation time 173138921 ps
CPU time 4.59 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 212600 kb
Host smart-0c586269-f636-47e5-9c59-1d7d890b80f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_t
l_intg_err.28981272
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.1855396707
Short name T88
Test name
Test status
Simulation time 3298178266 ps
CPU time 19.21 seconds
Started Mar 30 12:52:24 PM PDT 24
Finished Mar 30 12:52:44 PM PDT 24
Peak memory 208268 kb
Host smart-3cdab114-55a1-40fb-bfb0-47788d5ec9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855396707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.1855396707
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.1109298581
Short name T47
Test name
Test status
Simulation time 116401327 ps
CPU time 2.75 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 213756 kb
Host smart-a66d8e3e-cc41-40d1-87b4-408e0170f12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109298581 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.1109298581
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.3710599729
Short name T55
Test name
Test status
Simulation time 380953944 ps
CPU time 3.42 seconds
Started Mar 30 12:43:16 PM PDT 24
Finished Mar 30 12:43:25 PM PDT 24
Peak memory 212436 kb
Host smart-fbd9c810-3b02-43cd-9285-ed4c32e7c1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710599729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.3710599729
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1547510451
Short name T49
Test name
Test status
Simulation time 191603747 ps
CPU time 3.32 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 213604 kb
Host smart-b2085cff-89b4-4be2-91e3-ed5905f24f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547510451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1547510451
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.2262017782
Short name T7
Test name
Test status
Simulation time 3721878020 ps
CPU time 20.23 seconds
Started Mar 30 12:52:27 PM PDT 24
Finished Mar 30 12:52:48 PM PDT 24
Peak memory 233148 kb
Host smart-c4c41fd0-a2f1-454e-8597-71e9610c31e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262017782 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.2262017782
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.1609222504
Short name T44
Test name
Test status
Simulation time 435695784 ps
CPU time 2.97 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 212440 kb
Host smart-4328215f-ef1d-4040-9f5e-8b714174f594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609222504 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.1609222504
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3821026527
Short name T52
Test name
Test status
Simulation time 401417371 ps
CPU time 3.38 seconds
Started Mar 30 12:43:07 PM PDT 24
Finished Mar 30 12:43:13 PM PDT 24
Peak memory 212448 kb
Host smart-a07b3d34-5497-4677-8295-6c9da68a723a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821026527 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.3821026527
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.2743908817
Short name T50
Test name
Test status
Simulation time 366382377 ps
CPU time 3.68 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212576 kb
Host smart-00024ba1-6dc9-458d-8031-29585143d76a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743908817 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.2743908817
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.2279829230
Short name T33
Test name
Test status
Simulation time 89676108 ps
CPU time 2.43 seconds
Started Mar 30 12:43:48 PM PDT 24
Finished Mar 30 12:43:50 PM PDT 24
Peak memory 204300 kb
Host smart-2424bed0-bc76-444f-98da-64cee5f4d920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279829230 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.2279829230
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.2559147948
Short name T43
Test name
Test status
Simulation time 204075228 ps
CPU time 6.31 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 213552 kb
Host smart-6c7bcab6-306e-4b1e-958b-110244b94b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559147948 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.2559147948
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3565440338
Short name T51
Test name
Test status
Simulation time 98806540 ps
CPU time 4.06 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212608 kb
Host smart-e51900a5-3a7e-4a4e-beb6-d8e5b2a58f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565440338 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3565440338
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.2904418266
Short name T32
Test name
Test status
Simulation time 95339558 ps
CPU time 3.57 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 212548 kb
Host smart-6fc72c11-c56e-45a2-b932-475b1003f327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904418266 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.2904418266
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.3049708536
Short name T175
Test name
Test status
Simulation time 49776060 ps
CPU time 0.87 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204160 kb
Host smart-5015e8bd-e812-4468-88ff-e4123b318293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049708536 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
3049708536
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2059391659
Short name T79
Test name
Test status
Simulation time 4367230329 ps
CPU time 22.73 seconds
Started Mar 30 12:52:05 PM PDT 24
Finished Mar 30 12:52:28 PM PDT 24
Peak memory 207200 kb
Host smart-5d231d0f-abd4-4fda-b128-ee3b30e0debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059391659 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2059391659
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.2752341122
Short name T108
Test name
Test status
Simulation time 3176952207 ps
CPU time 21.36 seconds
Started Mar 30 12:52:30 PM PDT 24
Finished Mar 30 12:52:52 PM PDT 24
Peak memory 206456 kb
Host smart-752de972-7259-47c7-8143-6a2515475c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752341122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.2752341122
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.2355235864
Short name T100
Test name
Test status
Simulation time 8742955148 ps
CPU time 39.81 seconds
Started Mar 30 12:52:01 PM PDT 24
Finished Mar 30 12:52:41 PM PDT 24
Peak memory 208040 kb
Host smart-f7cac83a-1e8d-455c-b6c6-e9e5dbe0d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355235864 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.2355235864
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3486084487
Short name T114
Test name
Test status
Simulation time 2751205986 ps
CPU time 66.54 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:53:16 PM PDT 24
Peak memory 215884 kb
Host smart-4c0beeab-12aa-419b-9d9b-7ec614340785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486084487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3486084487
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.2637932118
Short name T10
Test name
Test status
Simulation time 3791302391 ps
CPU time 29.03 seconds
Started Mar 30 12:52:17 PM PDT 24
Finished Mar 30 12:52:46 PM PDT 24
Peak memory 207600 kb
Host smart-b0f18e7b-2c5c-424f-bb53-2ad74040ea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637932118 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.2637932118
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.614979670
Short name T102
Test name
Test status
Simulation time 3042551087 ps
CPU time 13.48 seconds
Started Mar 30 12:52:16 PM PDT 24
Finished Mar 30 12:52:30 PM PDT 24
Peak memory 206300 kb
Host smart-9802dd3f-317b-437d-8088-5ec47030c463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614979670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.614979670
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.1714512479
Short name T106
Test name
Test status
Simulation time 5753948563 ps
CPU time 21.93 seconds
Started Mar 30 12:52:27 PM PDT 24
Finished Mar 30 12:52:49 PM PDT 24
Peak memory 208080 kb
Host smart-0456a9a6-bf39-444d-bbb2-b190a461dfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714512479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.1714512479
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.2873520946
Short name T105
Test name
Test status
Simulation time 499279954 ps
CPU time 13.87 seconds
Started Mar 30 12:52:12 PM PDT 24
Finished Mar 30 12:52:26 PM PDT 24
Peak memory 207700 kb
Host smart-f952f80e-b5d4-41b0-8d9b-4b1603abe49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873520946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.2873520946
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.91426588
Short name T149
Test name
Test status
Simulation time 804066786 ps
CPU time 26.15 seconds
Started Mar 30 12:52:32 PM PDT 24
Finished Mar 30 12:52:59 PM PDT 24
Peak memory 207980 kb
Host smart-f853023f-c229-4376-b2d5-78c923e1f3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91426588 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.91426588
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2106239669
Short name T31
Test name
Test status
Simulation time 1792380413 ps
CPU time 33.44 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:53:03 PM PDT 24
Peak memory 208208 kb
Host smart-dfc7cd6b-fb41-4713-8885-39514e940a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106239669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2106239669
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.2855639690
Short name T113
Test name
Test status
Simulation time 2086675476 ps
CPU time 54.78 seconds
Started Mar 30 12:52:26 PM PDT 24
Finished Mar 30 12:53:22 PM PDT 24
Peak memory 218044 kb
Host smart-b4e8e89a-3612-4ca8-a0d9-c7392a479c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855639690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.2855639690
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.1669400821
Short name T109
Test name
Test status
Simulation time 1221219940 ps
CPU time 15.33 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:24 PM PDT 24
Peak memory 207276 kb
Host smart-b67eae41-39a9-4f9d-b658-5811e3c49252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669400821 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.1669400821
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.4292746614
Short name T91
Test name
Test status
Simulation time 9787653502 ps
CPU time 22 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:50 PM PDT 24
Peak memory 206252 kb
Host smart-cb5839c4-2c84-419c-881a-545cd4e521cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292746614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.4292746614
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3908813058
Short name T15
Test name
Test status
Simulation time 255467793 ps
CPU time 13.67 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:39 PM PDT 24
Peak memory 207968 kb
Host smart-5fe96e53-1cb5-43e1-9319-189fe3e5bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908813058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3908813058
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.797814330
Short name T241
Test name
Test status
Simulation time 226500323 ps
CPU time 8.11 seconds
Started Mar 30 12:43:18 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 204256 kb
Host smart-9d7fc3dd-8f31-438f-b9cf-bf414982ac5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797814330 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.797814330
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.3269356172
Short name T235
Test name
Test status
Simulation time 581957494 ps
CPU time 5.56 seconds
Started Mar 30 12:43:17 PM PDT 24
Finished Mar 30 12:43:28 PM PDT 24
Peak memory 204336 kb
Host smart-b320872b-c512-4ef1-a58a-73fbd758110c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269356172 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.3269356172
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.292559935
Short name T168
Test name
Test status
Simulation time 16547240 ps
CPU time 0.86 seconds
Started Mar 30 12:43:09 PM PDT 24
Finished Mar 30 12:43:10 PM PDT 24
Peak memory 204216 kb
Host smart-93253c02-fd46-4eee-a2df-d354d513c0de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292559935 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_hw_reset.292559935
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.375750332
Short name T260
Test name
Test status
Simulation time 21215617 ps
CPU time 1 seconds
Started Mar 30 12:43:17 PM PDT 24
Finished Mar 30 12:43:24 PM PDT 24
Peak memory 204280 kb
Host smart-9fd445d0-f596-441d-97c9-1bde59a5b303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375750332 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.375750332
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.656620095
Short name T264
Test name
Test status
Simulation time 24581812 ps
CPU time 0.89 seconds
Started Mar 30 12:43:15 PM PDT 24
Finished Mar 30 12:43:23 PM PDT 24
Peak memory 204232 kb
Host smart-ce605ce7-1b59-4a64-8daf-cbb6fcbb2081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656620095 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.656620095
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.2363222219
Short name T302
Test name
Test status
Simulation time 7546914 ps
CPU time 0.71 seconds
Started Mar 30 12:43:17 PM PDT 24
Finished Mar 30 12:43:26 PM PDT 24
Peak memory 204048 kb
Host smart-cce210ad-26d8-485e-8b37-eb5f2745f27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363222219 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.2
363222219
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.3593760058
Short name T250
Test name
Test status
Simulation time 138799106 ps
CPU time 1.94 seconds
Started Mar 30 12:43:15 PM PDT 24
Finished Mar 30 12:43:25 PM PDT 24
Peak memory 204500 kb
Host smart-ae5761d6-8061-4418-8876-090d2dcbd48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593760058 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.3593760058
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.497681022
Short name T192
Test name
Test status
Simulation time 133556595 ps
CPU time 2.46 seconds
Started Mar 30 12:43:11 PM PDT 24
Finished Mar 30 12:43:22 PM PDT 24
Peak memory 212928 kb
Host smart-514fb345-d444-443c-bd95-fbde62eb61c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497681022 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg
r_dpe_shadow_reg_errors.497681022
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1827954738
Short name T188
Test name
Test status
Simulation time 104695763 ps
CPU time 5.18 seconds
Started Mar 30 12:43:17 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 212768 kb
Host smart-791835f6-f1cd-4db9-80ac-9ee7f601198f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827954738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1827954738
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2683726753
Short name T272
Test name
Test status
Simulation time 667552184 ps
CPU time 2.89 seconds
Started Mar 30 12:43:12 PM PDT 24
Finished Mar 30 12:43:22 PM PDT 24
Peak memory 214656 kb
Host smart-f42d89a4-16ae-4772-947b-499b06f559b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683726753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
683726753
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3997539545
Short name T36
Test name
Test status
Simulation time 314403692 ps
CPU time 5.19 seconds
Started Mar 30 12:43:07 PM PDT 24
Finished Mar 30 12:43:14 PM PDT 24
Peak memory 204304 kb
Host smart-e0695bb5-72cc-4f70-99b9-0f894a5b55a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997539545 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.3997539545
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.1040375121
Short name T276
Test name
Test status
Simulation time 171735756 ps
CPU time 10.01 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:37 PM PDT 24
Peak memory 204276 kb
Host smart-ff35a549-e473-4ae4-8a8e-15d6b94ef10c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040375121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.1040375121
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1952367679
Short name T267
Test name
Test status
Simulation time 17990499 ps
CPU time 0.95 seconds
Started Mar 30 12:43:10 PM PDT 24
Finished Mar 30 12:43:18 PM PDT 24
Peak memory 204256 kb
Host smart-e1f5a98f-ae47-4937-b932-e71f135ff384
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952367679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1952367679
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.3729610066
Short name T218
Test name
Test status
Simulation time 158452830 ps
CPU time 0.99 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:29 PM PDT 24
Peak memory 204276 kb
Host smart-80a2957a-7956-49e4-96b4-5cbd1641affe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729610066 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.3729610066
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.1584981101
Short name T70
Test name
Test status
Simulation time 24350128 ps
CPU time 0.97 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 204156 kb
Host smart-37c90f82-d839-49cf-aae0-6586b51b166e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584981101 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.1
584981101
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.1218573686
Short name T301
Test name
Test status
Simulation time 77593366 ps
CPU time 1.39 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:29 PM PDT 24
Peak memory 204356 kb
Host smart-a821bf39-8084-4427-99ae-edde01be3d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218573686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.1218573686
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1156013535
Short name T246
Test name
Test status
Simulation time 159556701 ps
CPU time 3.19 seconds
Started Mar 30 12:43:15 PM PDT 24
Finished Mar 30 12:43:25 PM PDT 24
Peak memory 212808 kb
Host smart-26ce3179-5bb4-44fe-9fe0-304df0962fc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156013535 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.1156013535
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.1823054100
Short name T217
Test name
Test status
Simulation time 73206496 ps
CPU time 2.88 seconds
Started Mar 30 12:43:08 PM PDT 24
Finished Mar 30 12:43:12 PM PDT 24
Peak memory 214508 kb
Host smart-93c473e9-c554-4467-b384-35139f8d86a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823054100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.1
823054100
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.1421060512
Short name T242
Test name
Test status
Simulation time 96612655 ps
CPU time 1.47 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:40 PM PDT 24
Peak memory 212616 kb
Host smart-c9e4d10e-dcaa-4be3-b28f-26e3acb2df07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421060512 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.1421060512
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.3345163856
Short name T213
Test name
Test status
Simulation time 41284753 ps
CPU time 1.02 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204160 kb
Host smart-5a82a391-e108-4fdf-bf45-20bce8ade707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345163856 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
3345163856
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.1810817210
Short name T199
Test name
Test status
Simulation time 18684261 ps
CPU time 1.37 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:39 PM PDT 24
Peak memory 204240 kb
Host smart-b2cafd0d-57a8-4039-b356-b93860c4c8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810817210 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.1810817210
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.1304902875
Short name T309
Test name
Test status
Simulation time 175943326 ps
CPU time 2.04 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212940 kb
Host smart-f49eb2f3-381f-4e21-a4c4-22b5f82be730
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304902875 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.1304902875
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.106249453
Short name T35
Test name
Test status
Simulation time 177104840 ps
CPU time 3.4 seconds
Started Mar 30 12:43:37 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 214800 kb
Host smart-0a68acf4-55e4-4b67-a550-387b97c24b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106249453 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.106249453
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3082849787
Short name T299
Test name
Test status
Simulation time 119183764 ps
CPU time 4.43 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212872 kb
Host smart-d3e6027b-bdf3-4da6-8a4d-e12c52bc3ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082849787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3082849787
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3224743943
Short name T98
Test name
Test status
Simulation time 134288741 ps
CPU time 1.39 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212696 kb
Host smart-b5b646f6-5c0c-4f04-bc9f-ea68e7f94677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224743943 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3224743943
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.3762263342
Short name T295
Test name
Test status
Simulation time 48095220 ps
CPU time 0.96 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204188 kb
Host smart-3a0b5608-4ec6-4da7-8cdb-70372f7b40c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762263342 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
3762263342
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.2812756985
Short name T268
Test name
Test status
Simulation time 24962333 ps
CPU time 0.85 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204108 kb
Host smart-bc2bd315-91fa-4384-ab99-176e6a33dde2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812756985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
2812756985
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.3081028193
Short name T87
Test name
Test status
Simulation time 20197733 ps
CPU time 1.26 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204420 kb
Host smart-7ecec228-e358-447a-b691-f05c2ef99683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081028193 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.3081028193
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.2201479306
Short name T197
Test name
Test status
Simulation time 94747765 ps
CPU time 1.27 seconds
Started Mar 30 12:43:36 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212880 kb
Host smart-e3b72f53-32b6-4180-a064-7a28959c1bc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201479306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.2201479306
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.346624204
Short name T229
Test name
Test status
Simulation time 771499899 ps
CPU time 5.18 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 212840 kb
Host smart-cd8a9a77-8bb3-45c9-b577-76fb3a84853e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346624204 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.346624204
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1275416078
Short name T46
Test name
Test status
Simulation time 149130845 ps
CPU time 2.78 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212696 kb
Host smart-6ed5dfd3-b1d9-483b-898f-d629f0a445ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275416078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1275416078
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3935059959
Short name T53
Test name
Test status
Simulation time 341385522 ps
CPU time 4.31 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 213640 kb
Host smart-e71760ff-bcb1-48ee-92be-f5c65a423907
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935059959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3935059959
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.2959757251
Short name T186
Test name
Test status
Simulation time 23070020 ps
CPU time 1.5 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 212484 kb
Host smart-42eae3d4-1fea-4a9f-8e52-dc12b7978067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959757251 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.2959757251
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.1288157196
Short name T304
Test name
Test status
Simulation time 11135956 ps
CPU time 0.88 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204200 kb
Host smart-d660664e-8797-404b-bc7a-592ad86b7157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288157196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
1288157196
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.4231712279
Short name T259
Test name
Test status
Simulation time 54527647 ps
CPU time 0.69 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204216 kb
Host smart-cda91bb4-7435-4b68-85f2-e099f3dbcb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231712279 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
4231712279
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.1230582971
Short name T85
Test name
Test status
Simulation time 166854606 ps
CPU time 1.58 seconds
Started Mar 30 12:43:37 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204352 kb
Host smart-e892e333-3762-4c89-bf37-3d6ac1b681b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230582971 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.1230582971
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.3383324839
Short name T206
Test name
Test status
Simulation time 842514414 ps
CPU time 2.32 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:36 PM PDT 24
Peak memory 212868 kb
Host smart-320f29f5-1597-4867-99fd-320604c889e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383324839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_shadow_reg_errors.3383324839
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.416673427
Short name T96
Test name
Test status
Simulation time 1026252836 ps
CPU time 9.02 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:49 PM PDT 24
Peak memory 212976 kb
Host smart-a1280e46-a3d4-46e9-9b33-8ccb03452338
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416673427 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.416673427
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1252994192
Short name T294
Test name
Test status
Simulation time 15677658 ps
CPU time 1.07 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204216 kb
Host smart-93098486-0fa5-4962-a02c-0b9be465ed4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252994192 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1252994192
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.830815858
Short name T251
Test name
Test status
Simulation time 12092151 ps
CPU time 0.71 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204148 kb
Host smart-4060ffa1-5e3c-4456-ba3e-ab05c5f778fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830815858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.830815858
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1491048234
Short name T221
Test name
Test status
Simulation time 77148723 ps
CPU time 2.21 seconds
Started Mar 30 12:43:31 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 204348 kb
Host smart-bd66f09c-f32d-4c44-9bfc-f1c742673855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491048234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1491048234
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.481125528
Short name T262
Test name
Test status
Simulation time 52512469 ps
CPU time 2.15 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212836 kb
Host smart-e8232ae1-1496-4d51-839c-07d9e24c2025
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481125528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keym
gr_dpe_shadow_reg_errors.481125528
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3879253352
Short name T63
Test name
Test status
Simulation time 121474290 ps
CPU time 2.93 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212912 kb
Host smart-424dcc75-1ce0-4dc8-aaeb-1916e2d70ff2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879253352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.3879253352
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.1026867525
Short name T232
Test name
Test status
Simulation time 512097439 ps
CPU time 4.96 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 215008 kb
Host smart-8359804f-c5ba-485a-8a22-924e0ff5ddd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026867525 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
1026867525
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.515238297
Short name T308
Test name
Test status
Simulation time 17062249 ps
CPU time 0.96 seconds
Started Mar 30 12:43:36 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204300 kb
Host smart-2122ac4e-2dfe-4f9f-9220-856a6074125b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515238297 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.515238297
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.102920940
Short name T179
Test name
Test status
Simulation time 104317937 ps
CPU time 0.8 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204148 kb
Host smart-8c88e8d4-64de-4c87-afda-a749e0013f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102920940 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.102920940
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3742176071
Short name T305
Test name
Test status
Simulation time 8854906 ps
CPU time 0.79 seconds
Started Mar 30 12:43:36 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 203812 kb
Host smart-93b37fb2-c8f9-458b-a43d-2e9e17ee195e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742176071 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3742176071
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.815370570
Short name T239
Test name
Test status
Simulation time 78623333 ps
CPU time 1.96 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204276 kb
Host smart-d89f12c1-b80f-4932-a21e-821c737c302e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815370570 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_dpe_same_csr_outstanding.815370570
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.3467099896
Short name T67
Test name
Test status
Simulation time 148092168 ps
CPU time 1.57 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212896 kb
Host smart-c501688e-6301-4635-8daf-0346c5d78b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467099896 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.3467099896
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3185534400
Short name T269
Test name
Test status
Simulation time 56482562 ps
CPU time 2.49 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212968 kb
Host smart-8a816691-659d-4895-af11-c1d4ab9be74c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185534400 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.3185534400
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.3338154394
Short name T45
Test name
Test status
Simulation time 567588227 ps
CPU time 5.32 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:39 PM PDT 24
Peak memory 212732 kb
Host smart-89b516d6-cfab-4b57-8018-288b7b32add7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338154394 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
3338154394
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.2524383587
Short name T54
Test name
Test status
Simulation time 203928905 ps
CPU time 6.44 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212448 kb
Host smart-da54c3bb-afb4-475c-9d04-aec2f93e464b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524383587 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.2524383587
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.484268825
Short name T95
Test name
Test status
Simulation time 23982941 ps
CPU time 1.28 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:35 PM PDT 24
Peak memory 212492 kb
Host smart-65859dad-7505-4dd6-8829-2a5d01e4e12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484268825 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.484268825
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.239858458
Short name T181
Test name
Test status
Simulation time 24484738 ps
CPU time 0.88 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:40 PM PDT 24
Peak memory 204148 kb
Host smart-0833f528-d961-46a6-bafb-ecaacba7c7b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239858458 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.239858458
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.1378840205
Short name T237
Test name
Test status
Simulation time 35749874 ps
CPU time 0.72 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204144 kb
Host smart-7754b55b-0272-4415-9fec-8b386183db58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378840205 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
1378840205
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.3172018733
Short name T94
Test name
Test status
Simulation time 795530815 ps
CPU time 3.34 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 204312 kb
Host smart-815e9be1-1c88-4ea2-af4e-fa2b1c14ccc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172018733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.3172018733
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.3613824894
Short name T208
Test name
Test status
Simulation time 185527898 ps
CPU time 1.5 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 212956 kb
Host smart-cf44b143-4799-4232-a2e6-bd4e545aff1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613824894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.3613824894
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1619411608
Short name T201
Test name
Test status
Simulation time 1406710505 ps
CPU time 4.22 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 212920 kb
Host smart-ebdf01aa-30a6-40c6-ba16-7e21aef69963
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619411608 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.1619411608
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2331154852
Short name T263
Test name
Test status
Simulation time 49513653 ps
CPU time 2.27 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 213752 kb
Host smart-566f2c97-092e-4165-9fec-5baba65f9de9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331154852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2331154852
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.3310010235
Short name T227
Test name
Test status
Simulation time 26286666 ps
CPU time 1.51 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204356 kb
Host smart-26528efa-d1f0-4ff5-a878-196123d3f39a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310010235 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.3310010235
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.688780081
Short name T228
Test name
Test status
Simulation time 14049838 ps
CPU time 0.96 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 203944 kb
Host smart-9972a695-4184-4033-a62a-a4a7471117e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688780081 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.688780081
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.3487405652
Short name T288
Test name
Test status
Simulation time 11658157 ps
CPU time 0.84 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204224 kb
Host smart-992c5c88-f540-401a-ab80-361146895dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487405652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.
3487405652
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.489599182
Short name T223
Test name
Test status
Simulation time 133904086 ps
CPU time 1.68 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204332 kb
Host smart-280b359f-8f8c-4bfc-8fd9-2f839b3115e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489599182 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_dpe_same_csr_outstanding.489599182
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.2339058100
Short name T180
Test name
Test status
Simulation time 137518273 ps
CPU time 2.35 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212868 kb
Host smart-fc8e2d36-3262-4b68-aaa7-1d621c285617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339058100 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.2339058100
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1219186603
Short name T60
Test name
Test status
Simulation time 363818336 ps
CPU time 2.81 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212832 kb
Host smart-4987b87a-79b9-47a6-859e-36781d7d8850
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219186603 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.1219186603
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.2024364323
Short name T278
Test name
Test status
Simulation time 189948513 ps
CPU time 4.12 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 220548 kb
Host smart-1f2fc16a-c2b1-4a39-b17e-6ce8e8bc44c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024364323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
2024364323
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3040275846
Short name T275
Test name
Test status
Simulation time 190939744 ps
CPU time 2.57 seconds
Started Mar 30 12:43:40 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 204364 kb
Host smart-d7f04008-a5ef-4aac-87bb-e17d1129eaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040275846 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3040275846
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.138476566
Short name T234
Test name
Test status
Simulation time 16437952 ps
CPU time 0.9 seconds
Started Mar 30 12:43:47 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 204240 kb
Host smart-a661d073-82c2-4621-b8e4-f71625cc14ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138476566 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.138476566
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.881387634
Short name T280
Test name
Test status
Simulation time 12588103 ps
CPU time 1.02 seconds
Started Mar 30 12:43:46 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 204284 kb
Host smart-1229bd4d-66d1-40de-9c7d-4442be4499c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881387634 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.881387634
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.2964143840
Short name T200
Test name
Test status
Simulation time 10746768 ps
CPU time 0.67 seconds
Started Mar 30 12:43:46 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 204188 kb
Host smart-b4263242-db1f-4975-8f1c-1882a53edc84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964143840 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
2964143840
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.3576693702
Short name T286
Test name
Test status
Simulation time 60552398 ps
CPU time 1.38 seconds
Started Mar 30 12:43:49 PM PDT 24
Finished Mar 30 12:43:51 PM PDT 24
Peak memory 204232 kb
Host smart-f61c7e5b-8e5a-425a-9f59-9a78a857ae87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576693702 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.3576693702
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1423161437
Short name T249
Test name
Test status
Simulation time 57017988 ps
CPU time 1.32 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 212860 kb
Host smart-bf718a6d-89a2-4d52-9a8b-6f3b4c24b5d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423161437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1423161437
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.4226787181
Short name T243
Test name
Test status
Simulation time 59878259 ps
CPU time 3.22 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 212892 kb
Host smart-26f2ef3b-458b-4794-98bd-14f1bcb3bb53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226787181 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.4226787181
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.132642078
Short name T193
Test name
Test status
Simulation time 1363793696 ps
CPU time 3.32 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 215616 kb
Host smart-319638aa-f7cd-4e08-94ea-3ccf8a051498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132642078 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.132642078
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.3897947603
Short name T61
Test name
Test status
Simulation time 24529990 ps
CPU time 1.11 seconds
Started Mar 30 12:43:47 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 212564 kb
Host smart-c82e1c37-ac94-46d1-b286-6fe14374c22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897947603 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.3897947603
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1061118132
Short name T307
Test name
Test status
Simulation time 42378013 ps
CPU time 1.04 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204220 kb
Host smart-475f937d-fd8e-410d-9447-1bac74d9d7c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061118132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
1061118132
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.207157431
Short name T255
Test name
Test status
Simulation time 47546380 ps
CPU time 0.83 seconds
Started Mar 30 12:43:46 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 204160 kb
Host smart-c70ddbc7-f78f-4366-960c-cc9c07a00500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207157431 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.207157431
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1598720490
Short name T86
Test name
Test status
Simulation time 124333202 ps
CPU time 1.8 seconds
Started Mar 30 12:44:02 PM PDT 24
Finished Mar 30 12:44:04 PM PDT 24
Peak memory 204324 kb
Host smart-d7aee650-b31c-4970-bb74-1c200ca81d0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598720490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1598720490
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3898801243
Short name T207
Test name
Test status
Simulation time 79527151 ps
CPU time 1.53 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 221012 kb
Host smart-a02dbbe1-9989-4add-b86c-594a43a5fb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898801243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3898801243
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.180474627
Short name T173
Test name
Test status
Simulation time 329245405 ps
CPU time 4.76 seconds
Started Mar 30 12:43:51 PM PDT 24
Finished Mar 30 12:43:56 PM PDT 24
Peak memory 212824 kb
Host smart-1c529607-54ed-4086-a22e-58362c513b30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180474627 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.180474627
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1400185503
Short name T198
Test name
Test status
Simulation time 240608469 ps
CPU time 2.96 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 212680 kb
Host smart-2975c6e3-0c78-406e-9370-edbf591c0a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400185503 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1400185503
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.4271010160
Short name T248
Test name
Test status
Simulation time 23099770 ps
CPU time 1.06 seconds
Started Mar 30 12:43:52 PM PDT 24
Finished Mar 30 12:43:53 PM PDT 24
Peak memory 204216 kb
Host smart-0800d070-0102-4472-a6c4-116df3043f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271010160 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.4271010160
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.4129550451
Short name T190
Test name
Test status
Simulation time 42514912 ps
CPU time 0.96 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204196 kb
Host smart-24af5c97-4a2b-4cd1-b55a-e867a9ea1dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129550451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
4129550451
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2594055084
Short name T219
Test name
Test status
Simulation time 49225714 ps
CPU time 0.73 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204200 kb
Host smart-0a729679-21ab-46fc-906f-267563cc2ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594055084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2594055084
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.437065315
Short name T73
Test name
Test status
Simulation time 31344359 ps
CPU time 1.71 seconds
Started Mar 30 12:43:46 PM PDT 24
Finished Mar 30 12:43:47 PM PDT 24
Peak memory 204312 kb
Host smart-af4c57c4-7a40-4cf1-becb-4b7619bb8d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437065315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.437065315
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.139209253
Short name T65
Test name
Test status
Simulation time 325040206 ps
CPU time 2.19 seconds
Started Mar 30 12:43:42 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 212712 kb
Host smart-78ec6fa5-0c45-41b9-8afb-108fa9550f72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139209253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keym
gr_dpe_shadow_reg_errors.139209253
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.824673992
Short name T66
Test name
Test status
Simulation time 532990060 ps
CPU time 3.43 seconds
Started Mar 30 12:43:51 PM PDT 24
Finished Mar 30 12:43:55 PM PDT 24
Peak memory 212924 kb
Host smart-0492ee1d-fc5b-409f-8975-098b17882dd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824673992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.824673992
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.2621296090
Short name T236
Test name
Test status
Simulation time 85276943 ps
CPU time 1.71 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 212516 kb
Host smart-df0c160f-970b-4715-a8b4-cb13d96a42ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621296090 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
2621296090
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2634808574
Short name T220
Test name
Test status
Simulation time 1659664497 ps
CPU time 5.96 seconds
Started Mar 30 12:44:10 PM PDT 24
Finished Mar 30 12:44:16 PM PDT 24
Peak memory 212512 kb
Host smart-33c103cf-6ac7-4d6c-85ac-7de2abac069c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634808574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.2634808574
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.1897049321
Short name T172
Test name
Test status
Simulation time 126066724 ps
CPU time 4.18 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:35 PM PDT 24
Peak memory 204180 kb
Host smart-d5dc1b1f-7d5c-41a6-9941-908d97d4a43b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897049321 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.1897049321
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.2793751202
Short name T93
Test name
Test status
Simulation time 1814108919 ps
CPU time 13.93 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204392 kb
Host smart-5a627993-0382-433b-81ba-5afd2c3f0d49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793751202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.2793751202
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.1731750921
Short name T205
Test name
Test status
Simulation time 22810158 ps
CPU time 1.23 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 204388 kb
Host smart-b499b5bb-97e7-4fa0-92ef-2149ef312fa4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731750921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.1731750921
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.545141469
Short name T176
Test name
Test status
Simulation time 212702474 ps
CPU time 1.18 seconds
Started Mar 30 12:43:25 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212708 kb
Host smart-c007472d-77ca-4f88-a8df-065e346bd5a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545141469 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.545141469
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.1446855865
Short name T233
Test name
Test status
Simulation time 97428215 ps
CPU time 1.07 seconds
Started Mar 30 12:43:18 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 204276 kb
Host smart-315902e0-77ae-48e7-8078-f1d643692ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446855865 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.1
446855865
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.89759884
Short name T184
Test name
Test status
Simulation time 23040200 ps
CPU time 1.01 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:29 PM PDT 24
Peak memory 204320 kb
Host smart-76487b05-d9ff-4886-b1c9-5d32043dad8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89759884 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.89759884
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3339838849
Short name T310
Test name
Test status
Simulation time 79630579 ps
CPU time 1.48 seconds
Started Mar 30 12:43:26 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 204316 kb
Host smart-c599bb9a-14e1-4984-8d63-9fd9aca69607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339838849 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.3339838849
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.2823005040
Short name T64
Test name
Test status
Simulation time 242625829 ps
CPU time 2.71 seconds
Started Mar 30 12:43:27 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 212880 kb
Host smart-7936a391-95eb-423a-b67a-f15e0a334894
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823005040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keym
gr_dpe_shadow_reg_errors.2823005040
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1684007672
Short name T97
Test name
Test status
Simulation time 266692803 ps
CPU time 3.45 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 212888 kb
Host smart-2f021d34-9db8-4522-b78c-5943daf80200
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684007672 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.1684007672
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.531904488
Short name T261
Test name
Test status
Simulation time 103398441 ps
CPU time 3.97 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 212564 kb
Host smart-349d33b1-c9ba-4618-844c-2270ccb32ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531904488 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.531904488
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.3656916103
Short name T68
Test name
Test status
Simulation time 870808582 ps
CPU time 8.13 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:36 PM PDT 24
Peak memory 213500 kb
Host smart-e4685a50-c238-4103-ac86-588468fcb421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656916103 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.3656916103
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.561310278
Short name T69
Test name
Test status
Simulation time 17279106 ps
CPU time 0.8 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204188 kb
Host smart-c1f714ba-2388-4135-9d1a-809a3413e109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561310278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.561310278
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.1269259019
Short name T279
Test name
Test status
Simulation time 8078416 ps
CPU time 0.78 seconds
Started Mar 30 12:43:47 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 203548 kb
Host smart-a9ff0f4d-2c42-4ece-b2fc-12aca89efa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269259019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
1269259019
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3795420465
Short name T252
Test name
Test status
Simulation time 8408584 ps
CPU time 0.78 seconds
Started Mar 30 12:43:42 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204184 kb
Host smart-92a23656-0937-4237-b47a-fe8acaf45277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795420465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3795420465
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.4106644705
Short name T214
Test name
Test status
Simulation time 14447485 ps
CPU time 0.68 seconds
Started Mar 30 12:44:00 PM PDT 24
Finished Mar 30 12:44:01 PM PDT 24
Peak memory 204200 kb
Host smart-db22b668-41ae-4f76-9907-4aa7302123c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106644705 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.
4106644705
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.1673035325
Short name T119
Test name
Test status
Simulation time 51347934 ps
CPU time 0.86 seconds
Started Mar 30 12:43:53 PM PDT 24
Finished Mar 30 12:43:54 PM PDT 24
Peak memory 204076 kb
Host smart-26d3d217-5cd9-4a55-aa85-4b9a8cb3375f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673035325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
1673035325
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.192402796
Short name T283
Test name
Test status
Simulation time 13855038 ps
CPU time 0.7 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 204176 kb
Host smart-973eb81f-eb2e-4972-8fc5-1294831a70ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192402796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.192402796
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.2505490050
Short name T292
Test name
Test status
Simulation time 53078772 ps
CPU time 0.75 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204224 kb
Host smart-e4a4a458-1811-40f0-bd17-1ecba209c0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505490050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.
2505490050
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.232270800
Short name T209
Test name
Test status
Simulation time 20196174 ps
CPU time 0.7 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204112 kb
Host smart-87272388-c300-4716-8e86-13af897c505e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232270800 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.232270800
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2140925781
Short name T238
Test name
Test status
Simulation time 21761917 ps
CPU time 0.7 seconds
Started Mar 30 12:43:47 PM PDT 24
Finished Mar 30 12:43:48 PM PDT 24
Peak memory 203556 kb
Host smart-8d93db8d-f1ab-4727-b488-104db1b71200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140925781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2140925781
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.3146896901
Short name T40
Test name
Test status
Simulation time 47658718 ps
CPU time 0.84 seconds
Started Mar 30 12:43:43 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204160 kb
Host smart-877d03df-fe2e-4eec-b269-d42d2a5b6817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146896901 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
3146896901
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1947338005
Short name T182
Test name
Test status
Simulation time 169603513 ps
CPU time 2.93 seconds
Started Mar 30 12:43:28 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 204320 kb
Host smart-27a73203-4a46-4a71-83d7-e142d0f7582f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947338005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1947338005
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.2376136069
Short name T277
Test name
Test status
Simulation time 178421191 ps
CPU time 5.26 seconds
Started Mar 30 12:43:26 PM PDT 24
Finished Mar 30 12:43:36 PM PDT 24
Peak memory 204348 kb
Host smart-b67d9a8f-7da1-4bb4-944f-8ca76493f296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376136069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.2376136069
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.2391687964
Short name T169
Test name
Test status
Simulation time 122183254 ps
CPU time 0.9 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:29 PM PDT 24
Peak memory 204160 kb
Host smart-0580f9c8-ed2d-43bf-b50f-ffae5156123d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391687964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.2391687964
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.3650458937
Short name T296
Test name
Test status
Simulation time 19250113 ps
CPU time 1.05 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:29 PM PDT 24
Peak memory 212512 kb
Host smart-5cbd4065-5f98-4929-bb3c-75a51ca36e44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650458937 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.3650458937
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.3788563128
Short name T257
Test name
Test status
Simulation time 42429640 ps
CPU time 1.24 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 204396 kb
Host smart-da7a371e-8a55-4d86-b30b-6c5fa45b0ada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788563128 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.3
788563128
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.4111894357
Short name T194
Test name
Test status
Simulation time 32998862 ps
CPU time 0.92 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204184 kb
Host smart-ee826900-74ec-45e1-9a47-e00bcdbb29a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111894357 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.4
111894357
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2641640038
Short name T225
Test name
Test status
Simulation time 1000169286 ps
CPU time 2.15 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 204228 kb
Host smart-fe145cbf-1cbf-4813-9643-705c094c0f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641640038 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2641640038
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3472306729
Short name T287
Test name
Test status
Simulation time 489345879 ps
CPU time 2.18 seconds
Started Mar 30 12:43:29 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 212824 kb
Host smart-fc527ea1-2495-4548-a046-e17fc52777b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472306729 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3472306729
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2427384511
Short name T226
Test name
Test status
Simulation time 825554397 ps
CPU time 7.65 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 212816 kb
Host smart-6ebeef2f-dd56-42c1-837b-a1b569f2a5a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427384511 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.2427384511
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1984492676
Short name T247
Test name
Test status
Simulation time 107618883 ps
CPU time 3.81 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 212648 kb
Host smart-7dec27ec-0804-4315-83b2-2a89f306f880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984492676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
984492676
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.4153560839
Short name T270
Test name
Test status
Simulation time 124727409 ps
CPU time 4.05 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:34 PM PDT 24
Peak memory 212396 kb
Host smart-a45a00c6-88ac-4502-a889-5e5a425b0f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153560839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.4153560839
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.3615493352
Short name T77
Test name
Test status
Simulation time 51269592 ps
CPU time 0.76 seconds
Started Mar 30 12:44:13 PM PDT 24
Finished Mar 30 12:44:13 PM PDT 24
Peak memory 204116 kb
Host smart-ab7e51af-59e8-4816-9b50-9e2fac537882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615493352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
3615493352
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.259600313
Short name T265
Test name
Test status
Simulation time 49607394 ps
CPU time 0.7 seconds
Started Mar 30 12:44:12 PM PDT 24
Finished Mar 30 12:44:13 PM PDT 24
Peak memory 204152 kb
Host smart-97e1208a-7669-4a46-b4d7-7ee49ce76411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259600313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.259600313
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1962778892
Short name T204
Test name
Test status
Simulation time 10754782 ps
CPU time 0.81 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204236 kb
Host smart-a3954fba-d613-464d-9e67-c1a6beb9623e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962778892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1962778892
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3816236628
Short name T256
Test name
Test status
Simulation time 36218810 ps
CPU time 0.83 seconds
Started Mar 30 12:43:42 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 204184 kb
Host smart-d5afe218-a8a9-49f1-9d78-f7f36f4c28b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816236628 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3816236628
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2765760763
Short name T222
Test name
Test status
Simulation time 10838260 ps
CPU time 0.79 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 204120 kb
Host smart-600a6dc1-d14d-45bd-a2ca-1e890daf5420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765760763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2765760763
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.524518584
Short name T171
Test name
Test status
Simulation time 13576466 ps
CPU time 0.66 seconds
Started Mar 30 12:43:46 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 204132 kb
Host smart-dfbae955-5208-4ea5-a84b-7445e0911dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524518584 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.524518584
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3884625795
Short name T293
Test name
Test status
Simulation time 38594669 ps
CPU time 0.73 seconds
Started Mar 30 12:43:45 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 204180 kb
Host smart-2a13c4c5-1ec0-4f4a-92ce-2f4b2dc8a03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884625795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
3884625795
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.1441982613
Short name T254
Test name
Test status
Simulation time 13923717 ps
CPU time 0.82 seconds
Started Mar 30 12:44:01 PM PDT 24
Finished Mar 30 12:44:01 PM PDT 24
Peak memory 204100 kb
Host smart-70f96cf7-5f58-4ea6-8e96-315f992a880b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441982613 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
1441982613
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.447456917
Short name T118
Test name
Test status
Simulation time 35326731 ps
CPU time 0.76 seconds
Started Mar 30 12:44:17 PM PDT 24
Finished Mar 30 12:44:18 PM PDT 24
Peak memory 204136 kb
Host smart-9b94daa9-52b5-4015-b86c-d1eea4a727cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447456917 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.447456917
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3688233977
Short name T211
Test name
Test status
Simulation time 21171646 ps
CPU time 0.78 seconds
Started Mar 30 12:43:59 PM PDT 24
Finished Mar 30 12:44:00 PM PDT 24
Peak memory 204144 kb
Host smart-8219c381-200c-428c-936d-5f9d7f91a56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688233977 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3688233977
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.332068648
Short name T75
Test name
Test status
Simulation time 109855577 ps
CPU time 5.25 seconds
Started Mar 30 12:43:22 PM PDT 24
Finished Mar 30 12:43:36 PM PDT 24
Peak memory 204336 kb
Host smart-d85c40fb-5dff-4119-8224-3e0d198803f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332068648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_aliasing.332068648
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.3520983669
Short name T202
Test name
Test status
Simulation time 174375737 ps
CPU time 8.97 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:37 PM PDT 24
Peak memory 204272 kb
Host smart-880b9567-43b6-4b21-a42f-e761a8aa01d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520983669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.3520983669
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3123033051
Short name T72
Test name
Test status
Simulation time 48623707 ps
CPU time 0.82 seconds
Started Mar 30 12:43:27 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204064 kb
Host smart-00c6739e-88cf-4d45-8051-9c590c187bde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123033051 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3123033051
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1135500500
Short name T297
Test name
Test status
Simulation time 41102964 ps
CPU time 1.69 seconds
Started Mar 30 12:43:22 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212552 kb
Host smart-0c506c03-744e-4cab-9819-228667fe1841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135500500 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1135500500
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.9049837
Short name T191
Test name
Test status
Simulation time 42192538 ps
CPU time 0.86 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 204092 kb
Host smart-0dbdd4bc-f45e-4e95-a910-2943e9735b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9049837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.9049837
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.2701046325
Short name T177
Test name
Test status
Simulation time 18333967 ps
CPU time 0.71 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:28 PM PDT 24
Peak memory 204172 kb
Host smart-4ae5df10-3809-4ce6-9356-f03001cf3253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701046325 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.2
701046325
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.1247715955
Short name T185
Test name
Test status
Simulation time 108526565 ps
CPU time 1.66 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204312 kb
Host smart-34537952-574e-41e6-90cb-bbaf72d132de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247715955 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.1247715955
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1076590912
Short name T178
Test name
Test status
Simulation time 138258878 ps
CPU time 2.45 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 212776 kb
Host smart-98bdbfdc-6d11-4016-a918-99b641b80314
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076590912 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1076590912
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.932635738
Short name T300
Test name
Test status
Simulation time 436424072 ps
CPU time 8.94 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:49 PM PDT 24
Peak memory 212940 kb
Host smart-3ecd071e-50db-488f-ad37-fd2047d390ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932635738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.932635738
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3484080406
Short name T38
Test name
Test status
Simulation time 432598041 ps
CPU time 3.29 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 216100 kb
Host smart-e2a7de1d-3a00-45e2-a2c9-5ecca743b1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484080406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
484080406
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.53301859
Short name T266
Test name
Test status
Simulation time 25654689 ps
CPU time 0.74 seconds
Started Mar 30 12:44:12 PM PDT 24
Finished Mar 30 12:44:13 PM PDT 24
Peak memory 204232 kb
Host smart-105d8a59-d807-4d38-b8e9-1deedf3e1d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53301859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.53301859
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.3719051927
Short name T245
Test name
Test status
Simulation time 9186422 ps
CPU time 0.77 seconds
Started Mar 30 12:44:09 PM PDT 24
Finished Mar 30 12:44:10 PM PDT 24
Peak memory 204148 kb
Host smart-168c16ca-b88c-42be-a8d8-a8c149c644f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719051927 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
3719051927
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.4263112783
Short name T230
Test name
Test status
Simulation time 14191486 ps
CPU time 0.71 seconds
Started Mar 30 12:43:52 PM PDT 24
Finished Mar 30 12:43:53 PM PDT 24
Peak memory 204224 kb
Host smart-7a59d4f3-d655-4375-9287-0bd850add475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263112783 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
4263112783
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2376508937
Short name T289
Test name
Test status
Simulation time 37784464 ps
CPU time 0.74 seconds
Started Mar 30 12:43:53 PM PDT 24
Finished Mar 30 12:43:54 PM PDT 24
Peak memory 204216 kb
Host smart-2ba97303-6713-424a-bcfa-341b26262e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376508937 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2376508937
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.1192059430
Short name T117
Test name
Test status
Simulation time 31330973 ps
CPU time 0.74 seconds
Started Mar 30 12:44:04 PM PDT 24
Finished Mar 30 12:44:05 PM PDT 24
Peak memory 204160 kb
Host smart-5b1a3634-329f-4852-aeb2-59e5e3e00ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192059430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
1192059430
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3157725719
Short name T187
Test name
Test status
Simulation time 42976042 ps
CPU time 0.73 seconds
Started Mar 30 12:43:53 PM PDT 24
Finished Mar 30 12:43:53 PM PDT 24
Peak memory 204196 kb
Host smart-1d436680-4cb6-4979-97c4-5b485e2a47a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157725719 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
3157725719
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.346767305
Short name T273
Test name
Test status
Simulation time 10718714 ps
CPU time 0.72 seconds
Started Mar 30 12:43:55 PM PDT 24
Finished Mar 30 12:43:56 PM PDT 24
Peak memory 204192 kb
Host smart-db3f96d4-b93c-4993-ac12-a7b53411949c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346767305 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.346767305
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2883571124
Short name T274
Test name
Test status
Simulation time 31704123 ps
CPU time 0.76 seconds
Started Mar 30 12:43:53 PM PDT 24
Finished Mar 30 12:43:54 PM PDT 24
Peak memory 204092 kb
Host smart-14b5cdee-5a33-4de9-b2fc-200d08593495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883571124 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2883571124
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.1005166982
Short name T303
Test name
Test status
Simulation time 21452260 ps
CPU time 0.92 seconds
Started Mar 30 12:43:58 PM PDT 24
Finished Mar 30 12:43:59 PM PDT 24
Peak memory 204276 kb
Host smart-264bdc64-8b17-4357-9c51-ec407cfe8d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005166982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.
1005166982
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.657819045
Short name T284
Test name
Test status
Simulation time 11629531 ps
CPU time 0.68 seconds
Started Mar 30 12:43:53 PM PDT 24
Finished Mar 30 12:43:54 PM PDT 24
Peak memory 204120 kb
Host smart-5424ca74-c618-43c4-b964-7654ce64c707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657819045 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.657819045
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3512639454
Short name T282
Test name
Test status
Simulation time 14497855 ps
CPU time 1.29 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 212588 kb
Host smart-6ea27cac-7f20-4584-8214-08ed9fd382b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512639454 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.3512639454
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1764536505
Short name T196
Test name
Test status
Simulation time 20269919 ps
CPU time 1 seconds
Started Mar 30 12:43:27 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204284 kb
Host smart-ff3f82e2-8324-4387-8169-6a9e980a7d81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764536505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.1
764536505
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1309211117
Short name T170
Test name
Test status
Simulation time 40714437 ps
CPU time 0.83 seconds
Started Mar 30 12:43:18 PM PDT 24
Finished Mar 30 12:43:27 PM PDT 24
Peak memory 204100 kb
Host smart-696bc540-22f9-4a69-abac-f2d9ded638d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309211117 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.1
309211117
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.4137664152
Short name T203
Test name
Test status
Simulation time 104330706 ps
CPU time 2.5 seconds
Started Mar 30 12:43:26 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 204284 kb
Host smart-2aed859e-a837-498a-9e37-1a81a1ae938b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137664152 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.4137664152
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.1935209695
Short name T224
Test name
Test status
Simulation time 155120808 ps
CPU time 1.47 seconds
Started Mar 30 12:43:29 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212936 kb
Host smart-0ae16902-6531-4495-be27-3360c9613c61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935209695 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.1935209695
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3158479001
Short name T253
Test name
Test status
Simulation time 210942189 ps
CPU time 5.29 seconds
Started Mar 30 12:43:22 PM PDT 24
Finished Mar 30 12:43:36 PM PDT 24
Peak memory 212820 kb
Host smart-60646284-f87a-4827-a7aa-2ccfd075ba97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158479001 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.3158479001
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.214604876
Short name T57
Test name
Test status
Simulation time 129011863 ps
CPU time 2.95 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 220724 kb
Host smart-dd2e5ae9-fd05-4163-aa1c-505552d01c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214604876 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.214604876
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.4035358446
Short name T231
Test name
Test status
Simulation time 159483446 ps
CPU time 1.24 seconds
Started Mar 30 12:43:29 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212440 kb
Host smart-7d60b7e0-1670-45cf-8bc0-0f00b98e40ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035358446 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.4035358446
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.1823802246
Short name T271
Test name
Test status
Simulation time 21929769 ps
CPU time 1.02 seconds
Started Mar 30 12:43:22 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204096 kb
Host smart-f434c6ff-3a4a-4a54-8558-967976ed3fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823802246 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.1
823802246
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1837426196
Short name T76
Test name
Test status
Simulation time 13314270 ps
CPU time 0.86 seconds
Started Mar 30 12:43:28 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204104 kb
Host smart-03e1d830-2b73-4715-bd58-d0ddc5ca9805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837426196 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
837426196
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.1566117044
Short name T189
Test name
Test status
Simulation time 62944278 ps
CPU time 2.15 seconds
Started Mar 30 12:43:20 PM PDT 24
Finished Mar 30 12:43:30 PM PDT 24
Peak memory 204388 kb
Host smart-6aec1741-d786-49e7-9949-18ee255af5bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566117044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_dpe_same_csr_outstanding.1566117044
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.2437570032
Short name T215
Test name
Test status
Simulation time 222393825 ps
CPU time 2.17 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:30 PM PDT 24
Peak memory 216356 kb
Host smart-71022ef8-f778-4860-b7a1-39153622be4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437570032 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.2437570032
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2270269995
Short name T216
Test name
Test status
Simulation time 428622470 ps
CPU time 5.2 seconds
Started Mar 30 12:43:21 PM PDT 24
Finished Mar 30 12:43:35 PM PDT 24
Peak memory 212928 kb
Host smart-9c9ce83f-598f-4768-8f1f-d1f6e89acfbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270269995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2270269995
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.428125552
Short name T23
Test name
Test status
Simulation time 14054829 ps
CPU time 0.94 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204224 kb
Host smart-58be87bd-1e36-4110-85e7-474b645ddd86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428125552 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.428125552
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.119684693
Short name T212
Test name
Test status
Simulation time 43941912 ps
CPU time 0.97 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204340 kb
Host smart-1a4bee27-da89-40b9-bd23-a2d60ca7434e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119684693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.119684693
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.734758271
Short name T195
Test name
Test status
Simulation time 21302286 ps
CPU time 0.79 seconds
Started Mar 30 12:43:28 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 204148 kb
Host smart-9d5a2690-b0f6-485d-86a5-2273e6692424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734758271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.734758271
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.2724767156
Short name T290
Test name
Test status
Simulation time 139404511 ps
CPU time 2.14 seconds
Started Mar 30 12:43:28 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 204240 kb
Host smart-d00bbde2-7b91-475e-b116-6c1d799aa89c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724767156 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.2724767156
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1702235516
Short name T244
Test name
Test status
Simulation time 73475298 ps
CPU time 1.81 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212912 kb
Host smart-9873df68-e3a8-4c57-89a2-be37edec3318
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702235516 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1702235516
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1844786159
Short name T240
Test name
Test status
Simulation time 196187829 ps
CPU time 3.26 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:31 PM PDT 24
Peak memory 212996 kb
Host smart-120d2d97-bc4d-4fcc-ac45-fe2cc5892712
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844786159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1844786159
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2943225898
Short name T210
Test name
Test status
Simulation time 147508975 ps
CPU time 2.09 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212656 kb
Host smart-f5724a25-6efe-4bce-ac67-58c1db124e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943225898 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
943225898
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3368851961
Short name T120
Test name
Test status
Simulation time 114659312 ps
CPU time 2.32 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 217996 kb
Host smart-4c5e55f4-c8c0-4cbf-82a6-b2788d71d4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368851961 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3368851961
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.3643226237
Short name T37
Test name
Test status
Simulation time 20833851 ps
CPU time 0.9 seconds
Started Mar 30 12:43:30 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 204196 kb
Host smart-50f2dc65-ccd8-42c1-b636-80f0d74a3156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643226237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.3
643226237
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.1106313941
Short name T291
Test name
Test status
Simulation time 11226567 ps
CPU time 0.86 seconds
Started Mar 30 12:43:33 PM PDT 24
Finished Mar 30 12:43:39 PM PDT 24
Peak memory 204192 kb
Host smart-6ed88df7-3225-4e06-ab16-639a83ef60a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106313941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.1
106313941
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.1419281211
Short name T183
Test name
Test status
Simulation time 103841872 ps
CPU time 1.93 seconds
Started Mar 30 12:43:44 PM PDT 24
Finished Mar 30 12:43:46 PM PDT 24
Peak memory 204312 kb
Host smart-d94756bf-9751-44c6-b025-e47b5172906c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419281211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.1419281211
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.210741109
Short name T285
Test name
Test status
Simulation time 161383479 ps
CPU time 1.37 seconds
Started Mar 30 12:43:23 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212940 kb
Host smart-8967426e-102e-4732-bb1c-05aa81e7da25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210741109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymg
r_dpe_shadow_reg_errors.210741109
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3257061960
Short name T258
Test name
Test status
Simulation time 716682882 ps
CPU time 7.59 seconds
Started Mar 30 12:43:28 PM PDT 24
Finished Mar 30 12:43:38 PM PDT 24
Peak memory 212908 kb
Host smart-fed004a9-ffa5-4d4e-ab17-5e33c3669d90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257061960 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.3257061960
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.755469929
Short name T22
Test name
Test status
Simulation time 511757517 ps
CPU time 4.69 seconds
Started Mar 30 12:43:19 PM PDT 24
Finished Mar 30 12:43:32 PM PDT 24
Peak memory 212516 kb
Host smart-314c9821-0263-49fa-9d79-c1e4e1921f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755469929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.755469929
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2817913279
Short name T281
Test name
Test status
Simulation time 356856448 ps
CPU time 2.74 seconds
Started Mar 30 12:43:24 PM PDT 24
Finished Mar 30 12:43:33 PM PDT 24
Peak memory 213836 kb
Host smart-2c44328a-e4e4-44ac-9f8b-9acdb3eae39c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817913279 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2817913279
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.4266515528
Short name T174
Test name
Test status
Simulation time 133897111 ps
CPU time 1.28 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204536 kb
Host smart-3c2e2ebf-acf2-4ae6-a653-3e11cbedb2b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266515528 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.4266515528
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.4081978085
Short name T71
Test name
Test status
Simulation time 16559307 ps
CPU time 0.9 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204140 kb
Host smart-53e9fbeb-81c5-4176-86fd-d3a412d95cfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081978085 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.4
081978085
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2033379082
Short name T39
Test name
Test status
Simulation time 18536001 ps
CPU time 0.74 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:41 PM PDT 24
Peak memory 204232 kb
Host smart-28abe603-95cb-4167-98ec-c094eb03fffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033379082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
033379082
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2911506061
Short name T298
Test name
Test status
Simulation time 113770798 ps
CPU time 1.68 seconds
Started Mar 30 12:43:32 PM PDT 24
Finished Mar 30 12:43:42 PM PDT 24
Peak memory 204364 kb
Host smart-f6c1cb00-3a1f-49c7-bb01-0a565e8f235b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911506061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2911506061
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3857995461
Short name T42
Test name
Test status
Simulation time 434118979 ps
CPU time 2.14 seconds
Started Mar 30 12:43:34 PM PDT 24
Finished Mar 30 12:43:43 PM PDT 24
Peak memory 212776 kb
Host smart-fb64034f-8a9a-4764-928e-144d30a1b93f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857995461 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.3857995461
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1293785288
Short name T59
Test name
Test status
Simulation time 131652027 ps
CPU time 4.52 seconds
Started Mar 30 12:43:31 PM PDT 24
Finished Mar 30 12:43:45 PM PDT 24
Peak memory 212852 kb
Host smart-4b8a00fe-74c5-40ee-bfd6-a606e72e0e08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293785288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.1293785288
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.3557219036
Short name T306
Test name
Test status
Simulation time 334859349 ps
CPU time 3.32 seconds
Started Mar 30 12:43:35 PM PDT 24
Finished Mar 30 12:43:44 PM PDT 24
Peak memory 212648 kb
Host smart-f5c98b53-9bb1-44a2-ac05-c5fbe3f81eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557219036 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.3
557219036
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.4185681133
Short name T122
Test name
Test status
Simulation time 44553181 ps
CPU time 0.72 seconds
Started Mar 30 12:52:23 PM PDT 24
Finished Mar 30 12:52:23 PM PDT 24
Peak memory 205208 kb
Host smart-384fb8b3-a409-4b20-b22e-127080dbc034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185681133 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.4
185681133
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2019715370
Short name T24
Test name
Test status
Simulation time 1093782928 ps
CPU time 6.72 seconds
Started Mar 30 12:52:01 PM PDT 24
Finished Mar 30 12:52:07 PM PDT 24
Peak memory 233164 kb
Host smart-2a5d6f39-5d21-4d05-9ecf-67f918ee4326
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019715370 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2019715370
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.743252700
Short name T156
Test name
Test status
Simulation time 21543546 ps
CPU time 1.02 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:10 PM PDT 24
Peak memory 205368 kb
Host smart-fec03faa-e6fb-4201-adb4-1280a1a89f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743252700 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.743252700
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2261666161
Short name T123
Test name
Test status
Simulation time 2097470885 ps
CPU time 17.95 seconds
Started Mar 30 12:52:06 PM PDT 24
Finished Mar 30 12:52:24 PM PDT 24
Peak memory 207228 kb
Host smart-4b5fa194-5504-449c-ba48-9a518b98e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261666161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2261666161
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2280325157
Short name T130
Test name
Test status
Simulation time 32226759 ps
CPU time 0.92 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:10 PM PDT 24
Peak memory 205396 kb
Host smart-c0214e18-7cc2-4246-82f1-4eb019bed3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280325157 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2280325157
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.4235823512
Short name T159
Test name
Test status
Simulation time 11933935 ps
CPU time 0.76 seconds
Started Mar 30 12:52:19 PM PDT 24
Finished Mar 30 12:52:19 PM PDT 24
Peak memory 205332 kb
Host smart-15ce48b5-0ce3-4c91-b5a6-36f87229a3ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235823512 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
4235823512
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.1412143376
Short name T154
Test name
Test status
Simulation time 559266999 ps
CPU time 18.21 seconds
Started Mar 30 12:52:06 PM PDT 24
Finished Mar 30 12:52:25 PM PDT 24
Peak memory 207076 kb
Host smart-94bad71a-9c24-4d54-8fb5-465ac10fec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412143376 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.1412143376
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1012435150
Short name T132
Test name
Test status
Simulation time 20410103 ps
CPU time 0.78 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:10 PM PDT 24
Peak memory 205288 kb
Host smart-ef76d8db-d185-4701-8bc7-3f76428e3f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012435150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1012435150
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.841041542
Short name T78
Test name
Test status
Simulation time 771916267 ps
CPU time 24.3 seconds
Started Mar 30 12:52:26 PM PDT 24
Finished Mar 30 12:52:50 PM PDT 24
Peak memory 208088 kb
Host smart-0eaef228-3420-421a-9449-295820820b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841041542 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.841041542
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.4054780666
Short name T148
Test name
Test status
Simulation time 11811191 ps
CPU time 0.74 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:52:30 PM PDT 24
Peak memory 205216 kb
Host smart-f2bd88f4-7436-4c94-9178-29d6a272d742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054780666 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
4054780666
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.664363273
Short name T127
Test name
Test status
Simulation time 671567408 ps
CPU time 21.85 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:50 PM PDT 24
Peak memory 207780 kb
Host smart-fed78e45-b76e-4370-941b-5b594863a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664363273 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.664363273
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.3706181706
Short name T137
Test name
Test status
Simulation time 8477682 ps
CPU time 0.7 seconds
Started Mar 30 12:52:04 PM PDT 24
Finished Mar 30 12:52:05 PM PDT 24
Peak memory 205268 kb
Host smart-b923ec22-e0ce-470c-8e6c-863527fb20ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706181706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
3706181706
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.69325498
Short name T126
Test name
Test status
Simulation time 7068460380 ps
CPU time 32.33 seconds
Started Mar 30 12:52:07 PM PDT 24
Finished Mar 30 12:52:39 PM PDT 24
Peak memory 207920 kb
Host smart-d398aa5c-0f4e-472f-8c3e-f28729c16882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69325498 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.69325498
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.3098984990
Short name T128
Test name
Test status
Simulation time 22827989 ps
CPU time 0.88 seconds
Started Mar 30 12:52:27 PM PDT 24
Finished Mar 30 12:52:28 PM PDT 24
Peak memory 205216 kb
Host smart-c31a68d4-1b1d-4bb5-b176-08331a7557c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098984990 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
3098984990
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.2425151388
Short name T12
Test name
Test status
Simulation time 3455032814 ps
CPU time 32.51 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:53:03 PM PDT 24
Peak memory 207484 kb
Host smart-7964052e-5655-440c-8766-b1408c687d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425151388 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.2425151388
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3370045061
Short name T29
Test name
Test status
Simulation time 42681087 ps
CPU time 1.03 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:10 PM PDT 24
Peak memory 205388 kb
Host smart-845c3b6a-642a-4ce6-8e52-39999a5ffc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370045061 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3370045061
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.1499738226
Short name T166
Test name
Test status
Simulation time 11844109 ps
CPU time 0.93 seconds
Started Mar 30 12:52:10 PM PDT 24
Finished Mar 30 12:52:11 PM PDT 24
Peak memory 205300 kb
Host smart-8ae330d4-725d-420e-a44d-4ccc2ce8949c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499738226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
1499738226
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.2527708077
Short name T83
Test name
Test status
Simulation time 1718364050 ps
CPU time 21.5 seconds
Started Mar 30 12:52:24 PM PDT 24
Finished Mar 30 12:52:46 PM PDT 24
Peak memory 214872 kb
Host smart-5e20254f-7771-468f-bd09-23434677b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527708077 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.2527708077
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.2218735304
Short name T152
Test name
Test status
Simulation time 42806140 ps
CPU time 0.83 seconds
Started Mar 30 12:52:07 PM PDT 24
Finished Mar 30 12:52:08 PM PDT 24
Peak memory 205220 kb
Host smart-36504adc-0b6b-4d4a-bd43-0f521a0b9074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218735304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
2218735304
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3216487291
Short name T14
Test name
Test status
Simulation time 4401298482 ps
CPU time 39.23 seconds
Started Mar 30 12:52:10 PM PDT 24
Finished Mar 30 12:52:50 PM PDT 24
Peak memory 207636 kb
Host smart-cb6325c0-5a8b-4ace-a360-342bbba26b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216487291 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3216487291
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.2588143321
Short name T129
Test name
Test status
Simulation time 42621163 ps
CPU time 0.73 seconds
Started Mar 30 12:52:08 PM PDT 24
Finished Mar 30 12:52:09 PM PDT 24
Peak memory 205336 kb
Host smart-b3ed2de7-975d-4f1b-8947-fed3635ad13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588143321 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.2
588143321
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.671241958
Short name T25
Test name
Test status
Simulation time 481060281 ps
CPU time 12.06 seconds
Started Mar 30 12:52:23 PM PDT 24
Finished Mar 30 12:52:35 PM PDT 24
Peak memory 229804 kb
Host smart-f05d084b-c7be-452e-8cc2-0ba88692c5de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671241958 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.671241958
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3413090532
Short name T157
Test name
Test status
Simulation time 29558197 ps
CPU time 0.9 seconds
Started Mar 30 12:52:17 PM PDT 24
Finished Mar 30 12:52:18 PM PDT 24
Peak memory 205436 kb
Host smart-3ee2724c-de3b-4bb2-9cf4-284309074732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413090532 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3413090532
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.2797321062
Short name T30
Test name
Test status
Simulation time 1497736409 ps
CPU time 14.69 seconds
Started Mar 30 12:52:07 PM PDT 24
Finished Mar 30 12:52:22 PM PDT 24
Peak memory 208080 kb
Host smart-8ba13cd4-8d0a-4aaa-97a9-e5dbf4d58b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797321062 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.2797321062
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2575672580
Short name T1
Test name
Test status
Simulation time 11718357 ps
CPU time 0.82 seconds
Started Mar 30 12:52:08 PM PDT 24
Finished Mar 30 12:52:09 PM PDT 24
Peak memory 205220 kb
Host smart-b3d55477-b46f-4a25-8ba8-57ad521c3c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575672580 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2575672580
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3241376412
Short name T27
Test name
Test status
Simulation time 43810271 ps
CPU time 0.86 seconds
Started Mar 30 12:52:08 PM PDT 24
Finished Mar 30 12:52:09 PM PDT 24
Peak memory 205296 kb
Host smart-03475693-cccb-40d0-8231-43e5713dce4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241376412 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3241376412
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.3950450753
Short name T99
Test name
Test status
Simulation time 1631728789 ps
CPU time 16.95 seconds
Started Mar 30 12:52:06 PM PDT 24
Finished Mar 30 12:52:23 PM PDT 24
Peak memory 208260 kb
Host smart-8a8bdda3-719b-432b-bfd6-600cba462609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950450753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.3950450753
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.2667532476
Short name T145
Test name
Test status
Simulation time 19003176 ps
CPU time 0.8 seconds
Started Mar 30 12:52:39 PM PDT 24
Finished Mar 30 12:52:40 PM PDT 24
Peak memory 205256 kb
Host smart-55ef7ddc-3705-4a23-9aee-9963c79a23ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667532476 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
2667532476
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.711029821
Short name T131
Test name
Test status
Simulation time 22158819 ps
CPU time 0.88 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:26 PM PDT 24
Peak memory 205320 kb
Host smart-36dc1f28-c559-461a-9ec2-96bcc2249323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711029821 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.711029821
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.4060823921
Short name T160
Test name
Test status
Simulation time 39119710 ps
CPU time 0.87 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:26 PM PDT 24
Peak memory 205324 kb
Host smart-77f4dd44-9769-470f-b369-c1345417cb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060823921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
4060823921
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.1165374931
Short name T82
Test name
Test status
Simulation time 27870100 ps
CPU time 0.73 seconds
Started Mar 30 12:52:21 PM PDT 24
Finished Mar 30 12:52:21 PM PDT 24
Peak memory 205232 kb
Host smart-3a24931b-744e-473b-987f-d41e874715a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165374931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
1165374931
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.2620476989
Short name T124
Test name
Test status
Simulation time 20273569 ps
CPU time 0.8 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 205320 kb
Host smart-b68d8b40-b7a1-4dc7-ad4d-6ea0ad2129d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620476989 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
2620476989
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.881988972
Short name T133
Test name
Test status
Simulation time 3985564256 ps
CPU time 24.88 seconds
Started Mar 30 12:52:36 PM PDT 24
Finished Mar 30 12:53:02 PM PDT 24
Peak memory 208192 kb
Host smart-761ccaed-5af7-45e7-81e3-81ae3672b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881988972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.881988972
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.1129256027
Short name T121
Test name
Test status
Simulation time 55575542 ps
CPU time 0.99 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:52:31 PM PDT 24
Peak memory 205488 kb
Host smart-bb0c0182-56c5-462b-a7d2-c860ece2066b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129256027 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.
1129256027
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.359417711
Short name T84
Test name
Test status
Simulation time 172259637 ps
CPU time 10.82 seconds
Started Mar 30 12:52:12 PM PDT 24
Finished Mar 30 12:52:23 PM PDT 24
Peak memory 206060 kb
Host smart-7c8dcb8e-2254-49ee-8d9d-9a9f996b0b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359417711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.359417711
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.4043146394
Short name T164
Test name
Test status
Simulation time 13200022 ps
CPU time 0.89 seconds
Started Mar 30 12:52:21 PM PDT 24
Finished Mar 30 12:52:22 PM PDT 24
Peak memory 205304 kb
Host smart-f5b5d4e3-cba7-440e-840f-d7d82009d543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043146394 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
4043146394
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.3997279112
Short name T138
Test name
Test status
Simulation time 20474346 ps
CPU time 0.72 seconds
Started Mar 30 12:52:06 PM PDT 24
Finished Mar 30 12:52:07 PM PDT 24
Peak memory 205264 kb
Host smart-78ba2515-13e7-4be6-97b6-db6917ba5948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997279112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.3
997279112
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.2207906434
Short name T167
Test name
Test status
Simulation time 13572843 ps
CPU time 0.76 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:29 PM PDT 24
Peak memory 205320 kb
Host smart-7e813560-791b-4374-a770-192a646611fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207906434 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
2207906434
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.629212054
Short name T151
Test name
Test status
Simulation time 573322410 ps
CPU time 9.49 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:52:41 PM PDT 24
Peak memory 208108 kb
Host smart-6b5bd4c2-6161-455c-ba27-68472842e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629212054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.629212054
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.1368061478
Short name T147
Test name
Test status
Simulation time 14445119 ps
CPU time 0.94 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:29 PM PDT 24
Peak memory 205168 kb
Host smart-7f35650e-1ca7-4cfa-ba44-c76fc9c66c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368061478 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
1368061478
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.1910360852
Short name T6
Test name
Test status
Simulation time 5138025609 ps
CPU time 44.66 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:53:16 PM PDT 24
Peak memory 207716 kb
Host smart-fc037567-d798-47b0-8cd7-543aee9ba674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910360852 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.1910360852
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.3820293483
Short name T18
Test name
Test status
Simulation time 14569485 ps
CPU time 0.75 seconds
Started Mar 30 12:52:12 PM PDT 24
Finished Mar 30 12:52:13 PM PDT 24
Peak memory 205224 kb
Host smart-eda25fe1-9dc1-4822-a636-b989dc2420d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820293483 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
3820293483
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.2066228097
Short name T104
Test name
Test status
Simulation time 535333460 ps
CPU time 19.07 seconds
Started Mar 30 12:52:35 PM PDT 24
Finished Mar 30 12:52:54 PM PDT 24
Peak memory 207944 kb
Host smart-26e644cf-170c-46d9-9a60-0f591d8f9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066228097 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.2066228097
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.2929844455
Short name T28
Test name
Test status
Simulation time 49804272 ps
CPU time 0.75 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:29 PM PDT 24
Peak memory 204956 kb
Host smart-7b59d11d-c698-47b3-9fa8-a874aaefed84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929844455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
2929844455
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.1120564826
Short name T89
Test name
Test status
Simulation time 3011482014 ps
CPU time 17.26 seconds
Started Mar 30 12:52:20 PM PDT 24
Finished Mar 30 12:52:37 PM PDT 24
Peak memory 207912 kb
Host smart-12126333-b312-44db-8efc-f67ef31d1332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120564826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.1120564826
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.308130222
Short name T142
Test name
Test status
Simulation time 8155079 ps
CPU time 0.68 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:25 PM PDT 24
Peak memory 205344 kb
Host smart-24c91ecc-96f7-42b2-a459-46d788b87c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308130222 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.308130222
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.1433460283
Short name T143
Test name
Test status
Simulation time 18158673 ps
CPU time 0.78 seconds
Started Mar 30 12:52:13 PM PDT 24
Finished Mar 30 12:52:14 PM PDT 24
Peak memory 205304 kb
Host smart-586e55cb-16b5-467a-8601-f00358229f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433460283 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
1433460283
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.1436207231
Short name T2
Test name
Test status
Simulation time 51712787 ps
CPU time 0.72 seconds
Started Mar 30 12:52:38 PM PDT 24
Finished Mar 30 12:52:39 PM PDT 24
Peak memory 205268 kb
Host smart-0b6207e3-625e-4e72-9491-544ec5d87c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436207231 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
1436207231
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.4186489396
Short name T165
Test name
Test status
Simulation time 788377354 ps
CPU time 12.23 seconds
Started Mar 30 12:52:30 PM PDT 24
Finished Mar 30 12:52:42 PM PDT 24
Peak memory 207576 kb
Host smart-95d76efe-aaea-40f7-bef6-6a95cdd559c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186489396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.4186489396
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.2668353040
Short name T139
Test name
Test status
Simulation time 13159117 ps
CPU time 0.79 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 205244 kb
Host smart-5a37ecf7-1154-495f-a0c2-c6c9bbda480b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668353040 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
2668353040
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.4206057730
Short name T116
Test name
Test status
Simulation time 1161672910 ps
CPU time 20.52 seconds
Started Mar 30 12:52:10 PM PDT 24
Finished Mar 30 12:52:31 PM PDT 24
Peak memory 207712 kb
Host smart-34e3583b-47f5-4584-ae22-4c9bfe36266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206057730 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.4206057730
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.2360712290
Short name T163
Test name
Test status
Simulation time 216373399 ps
CPU time 0.75 seconds
Started Mar 30 12:52:30 PM PDT 24
Finished Mar 30 12:52:31 PM PDT 24
Peak memory 205232 kb
Host smart-6be87fd1-6194-4bd6-9505-9872c77b0a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360712290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
2360712290
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.617935065
Short name T107
Test name
Test status
Simulation time 1517059942 ps
CPU time 15.22 seconds
Started Mar 30 12:52:12 PM PDT 24
Finished Mar 30 12:52:27 PM PDT 24
Peak memory 205960 kb
Host smart-abc18648-2156-424b-a462-464fdffe4007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617935065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.617935065
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.3842214837
Short name T150
Test name
Test status
Simulation time 24152303 ps
CPU time 0.81 seconds
Started Mar 30 12:52:13 PM PDT 24
Finished Mar 30 12:52:14 PM PDT 24
Peak memory 205304 kb
Host smart-c464fb36-75fc-4d2e-b5c0-674efaec558d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842214837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
3842214837
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.1682954637
Short name T16
Test name
Test status
Simulation time 1078003249 ps
CPU time 15.87 seconds
Started Mar 30 12:52:26 PM PDT 24
Finished Mar 30 12:52:43 PM PDT 24
Peak memory 208180 kb
Host smart-0b948a26-108c-41c3-93e3-89658b2c0f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682954637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.1682954637
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.3731372706
Short name T140
Test name
Test status
Simulation time 40071995 ps
CPU time 0.85 seconds
Started Mar 30 12:52:09 PM PDT 24
Finished Mar 30 12:52:10 PM PDT 24
Peak memory 205212 kb
Host smart-ab938467-4eff-4eb5-b0d9-b45b592ac51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731372706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.3
731372706
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.1124978418
Short name T9
Test name
Test status
Simulation time 231852664 ps
CPU time 7.36 seconds
Started Mar 30 12:52:25 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 233020 kb
Host smart-0b785790-8719-4c4e-ab6d-ba916ed07980
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124978418 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.1124978418
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.2177297134
Short name T141
Test name
Test status
Simulation time 23483841 ps
CPU time 0.73 seconds
Started Mar 30 12:52:12 PM PDT 24
Finished Mar 30 12:52:13 PM PDT 24
Peak memory 205232 kb
Host smart-2cf00f49-5ba5-429b-91a7-846a397e87ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177297134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
2177297134
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.1651991759
Short name T90
Test name
Test status
Simulation time 653537543 ps
CPU time 18.46 seconds
Started Mar 30 12:52:41 PM PDT 24
Finished Mar 30 12:52:59 PM PDT 24
Peak memory 206200 kb
Host smart-6acce530-c86a-43c7-baa8-8e5c81db3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651991759 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.1651991759
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.959920930
Short name T153
Test name
Test status
Simulation time 76175589 ps
CPU time 0.74 seconds
Started Mar 30 12:52:33 PM PDT 24
Finished Mar 30 12:52:34 PM PDT 24
Peak memory 205268 kb
Host smart-a3591018-eb10-4540-bdad-d70854f97b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959920930 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.959920930
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.4256175211
Short name T17
Test name
Test status
Simulation time 10961591 ps
CPU time 0.84 seconds
Started Mar 30 12:52:38 PM PDT 24
Finished Mar 30 12:52:39 PM PDT 24
Peak memory 205184 kb
Host smart-abe611b5-ffc3-443f-b65c-aa571c9e5c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256175211 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
4256175211
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1335316552
Short name T162
Test name
Test status
Simulation time 1181370538 ps
CPU time 19.77 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:52:48 PM PDT 24
Peak memory 207648 kb
Host smart-645fd637-b96a-4b56-86e3-a147a4dd0ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335316552 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1335316552
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.1486938141
Short name T134
Test name
Test status
Simulation time 14129332 ps
CPU time 0.76 seconds
Started Mar 30 12:52:32 PM PDT 24
Finished Mar 30 12:52:33 PM PDT 24
Peak memory 205216 kb
Host smart-a4ebef4b-7312-4061-9798-4fd1c62e8694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486938141 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
1486938141
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.652531863
Short name T13
Test name
Test status
Simulation time 9698770698 ps
CPU time 16.04 seconds
Started Mar 30 12:52:39 PM PDT 24
Finished Mar 30 12:52:55 PM PDT 24
Peak memory 214524 kb
Host smart-2ceb7042-b6fe-4c2c-9da3-a443d25b383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652531863 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.652531863
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2341888043
Short name T125
Test name
Test status
Simulation time 19350878 ps
CPU time 0.71 seconds
Started Mar 30 12:52:11 PM PDT 24
Finished Mar 30 12:52:12 PM PDT 24
Peak memory 205224 kb
Host smart-e08192ab-b247-453d-b103-6403f47a2da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341888043 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2341888043
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.1119421105
Short name T101
Test name
Test status
Simulation time 885079013 ps
CPU time 16.25 seconds
Started Mar 30 12:52:24 PM PDT 24
Finished Mar 30 12:52:41 PM PDT 24
Peak memory 208100 kb
Host smart-d965ccb9-17f8-487d-b218-c218b0647812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119421105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.1119421105
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.2885622515
Short name T144
Test name
Test status
Simulation time 160114487 ps
CPU time 0.78 seconds
Started Mar 30 12:52:26 PM PDT 24
Finished Mar 30 12:52:27 PM PDT 24
Peak memory 205328 kb
Host smart-e78bc2bf-572d-487b-abd5-29c4cd173977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885622515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
2885622515
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.2362223065
Short name T112
Test name
Test status
Simulation time 2111011918 ps
CPU time 14.1 seconds
Started Mar 30 12:52:20 PM PDT 24
Finished Mar 30 12:52:34 PM PDT 24
Peak memory 206524 kb
Host smart-7ffd081f-4f06-40a1-a369-ad9a39bc3fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362223065 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.2362223065
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3187812098
Short name T135
Test name
Test status
Simulation time 33024965 ps
CPU time 0.73 seconds
Started Mar 30 12:52:29 PM PDT 24
Finished Mar 30 12:52:31 PM PDT 24
Peak memory 205244 kb
Host smart-d286efe1-5a17-4920-96dd-cc3582acd6a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187812098 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3187812098
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.3089045480
Short name T111
Test name
Test status
Simulation time 1244481844 ps
CPU time 21.63 seconds
Started Mar 30 12:52:35 PM PDT 24
Finished Mar 30 12:52:57 PM PDT 24
Peak memory 208060 kb
Host smart-bdf4c2c5-e9d2-432f-b1d8-750b37d0cd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089045480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.3089045480
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1534980972
Short name T161
Test name
Test status
Simulation time 45746068 ps
CPU time 0.9 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:52:32 PM PDT 24
Peak memory 205332 kb
Host smart-d79a6548-fab6-4f9b-8cd6-c6aa913e0d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534980972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1534980972
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.3989490454
Short name T158
Test name
Test status
Simulation time 29904607 ps
CPU time 0.96 seconds
Started Mar 30 12:52:27 PM PDT 24
Finished Mar 30 12:52:28 PM PDT 24
Peak memory 205420 kb
Host smart-361b289b-af08-4ce5-ac11-1e8d57000c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989490454 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
3989490454
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.2885477473
Short name T11
Test name
Test status
Simulation time 364070044 ps
CPU time 14.29 seconds
Started Mar 30 12:52:32 PM PDT 24
Finished Mar 30 12:52:47 PM PDT 24
Peak memory 206360 kb
Host smart-ac8ab5d1-13f8-4c9e-8bbb-8334c1c6afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885477473 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.2885477473
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.3641394718
Short name T155
Test name
Test status
Simulation time 9908628 ps
CPU time 0.76 seconds
Started Mar 30 12:52:40 PM PDT 24
Finished Mar 30 12:52:41 PM PDT 24
Peak memory 205188 kb
Host smart-038a9489-a815-4089-be46-638f571c54c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641394718 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
3641394718
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.1557636459
Short name T80
Test name
Test status
Simulation time 9102019659 ps
CPU time 76.77 seconds
Started Mar 30 12:52:31 PM PDT 24
Finished Mar 30 12:53:48 PM PDT 24
Peak memory 207768 kb
Host smart-51bb9120-d77c-400d-9fe3-2e2b9568522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557636459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.1557636459
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.1436767198
Short name T81
Test name
Test status
Simulation time 10089667 ps
CPU time 0.85 seconds
Started Mar 30 12:52:15 PM PDT 24
Finished Mar 30 12:52:16 PM PDT 24
Peak memory 205336 kb
Host smart-ccf1d296-3326-493c-a16f-9dd69707a57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436767198 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.1
436767198
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.3320669641
Short name T103
Test name
Test status
Simulation time 567372750 ps
CPU time 18.74 seconds
Started Mar 30 12:52:15 PM PDT 24
Finished Mar 30 12:52:34 PM PDT 24
Peak memory 207880 kb
Host smart-7c29ef4b-0025-46d3-94f1-182476537f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320669641 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.3320669641
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.3139524972
Short name T20
Test name
Test status
Simulation time 47427780 ps
CPU time 0.79 seconds
Started Mar 30 12:52:03 PM PDT 24
Finished Mar 30 12:52:04 PM PDT 24
Peak memory 205292 kb
Host smart-7c734527-b07e-434b-afe2-6cdb2a4e4d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139524972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.3
139524972
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3698898122
Short name T92
Test name
Test status
Simulation time 1034149400 ps
CPU time 14.42 seconds
Started Mar 30 12:52:28 PM PDT 24
Finished Mar 30 12:52:42 PM PDT 24
Peak memory 207928 kb
Host smart-22fccdfd-7df6-4a40-97eb-0f5a49445b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698898122 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3698898122
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.807725707
Short name T26
Test name
Test status
Simulation time 17279000 ps
CPU time 0.75 seconds
Started Mar 30 12:52:18 PM PDT 24
Finished Mar 30 12:52:19 PM PDT 24
Peak memory 205216 kb
Host smart-8977c9c9-f4f1-4f3c-a75d-c9c3b0cadd84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807725707 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.807725707
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.986591060
Short name T115
Test name
Test status
Simulation time 840259675 ps
CPU time 16.95 seconds
Started Mar 30 12:52:13 PM PDT 24
Finished Mar 30 12:52:30 PM PDT 24
Peak memory 206436 kb
Host smart-0fffda69-9671-4b74-9e47-3f387892626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986591060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.986591060
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.279656173
Short name T19
Test name
Test status
Simulation time 15448958 ps
CPU time 0.92 seconds
Started Mar 30 12:52:08 PM PDT 24
Finished Mar 30 12:52:09 PM PDT 24
Peak memory 205428 kb
Host smart-e40d7957-47da-4c41-a267-73ecddca4b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279656173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.279656173
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2143442195
Short name T146
Test name
Test status
Simulation time 5334900226 ps
CPU time 27.79 seconds
Started Mar 30 12:52:14 PM PDT 24
Finished Mar 30 12:52:42 PM PDT 24
Peak memory 208036 kb
Host smart-678b6282-b7f3-488c-ae54-bc1f38e9a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143442195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2143442195
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1724085011
Short name T136
Test name
Test status
Simulation time 14400313 ps
CPU time 0.75 seconds
Started Mar 30 12:52:18 PM PDT 24
Finished Mar 30 12:52:19 PM PDT 24
Peak memory 205340 kb
Host smart-fd6ae163-e9d5-42d1-aca7-f7ec6584a921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724085011 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
724085011
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.2740082134
Short name T110
Test name
Test status
Simulation time 491719021 ps
CPU time 18.3 seconds
Started Mar 30 12:52:05 PM PDT 24
Finished Mar 30 12:52:28 PM PDT 24
Peak memory 208152 kb
Host smart-7226a0a5-4ddb-4fb2-87e4-ec22db34a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740082134 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.2740082134
Directory /workspace/9.keymgr_dpe_smoke/latest
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