Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.28 97.70 90.76 57.52 76.92 94.94 98.34 17.78


Total test records in report: 309
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3268878218 Apr 20 03:08:14 PM PDT 24 Apr 20 03:08:16 PM PDT 24 47826295 ps
T258 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.815491070 Apr 20 03:06:49 PM PDT 24 Apr 20 03:06:55 PM PDT 24 312199241 ps
T259 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2637011684 Apr 20 03:08:32 PM PDT 24 Apr 20 03:08:35 PM PDT 24 80773164 ps
T260 /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2610480688 Apr 20 03:09:21 PM PDT 24 Apr 20 03:09:22 PM PDT 24 11311391 ps
T261 /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.4046385145 Apr 20 03:09:24 PM PDT 24 Apr 20 03:09:25 PM PDT 24 60162803 ps
T262 /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2491221515 Apr 20 03:06:45 PM PDT 24 Apr 20 03:06:47 PM PDT 24 23958744 ps
T263 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.3860256669 Apr 20 03:07:17 PM PDT 24 Apr 20 03:07:19 PM PDT 24 131643380 ps
T264 /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.1706065202 Apr 20 03:08:08 PM PDT 24 Apr 20 03:08:14 PM PDT 24 156698622 ps
T265 /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.734526583 Apr 20 03:09:27 PM PDT 24 Apr 20 03:09:28 PM PDT 24 8342833 ps
T266 /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.575475528 Apr 20 03:07:30 PM PDT 24 Apr 20 03:07:34 PM PDT 24 261703192 ps
T267 /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2003255894 Apr 20 03:08:58 PM PDT 24 Apr 20 03:09:00 PM PDT 24 81979888 ps
T268 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.791668717 Apr 20 03:07:16 PM PDT 24 Apr 20 03:07:18 PM PDT 24 1146313390 ps
T269 /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1830179380 Apr 20 03:09:07 PM PDT 24 Apr 20 03:09:09 PM PDT 24 221228767 ps
T270 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.334688350 Apr 20 03:08:30 PM PDT 24 Apr 20 03:08:34 PM PDT 24 229605044 ps
T271 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1751119406 Apr 20 03:09:06 PM PDT 24 Apr 20 03:09:09 PM PDT 24 264643443 ps
T50 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2958162995 Apr 20 03:08:37 PM PDT 24 Apr 20 03:08:41 PM PDT 24 93096122 ps
T48 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.1891870753 Apr 20 03:08:34 PM PDT 24 Apr 20 03:08:43 PM PDT 24 496766456 ps
T272 /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.1072160605 Apr 20 03:09:26 PM PDT 24 Apr 20 03:09:27 PM PDT 24 16825805 ps
T273 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1197903147 Apr 20 03:08:37 PM PDT 24 Apr 20 03:08:41 PM PDT 24 121792558 ps
T274 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2029373300 Apr 20 03:07:34 PM PDT 24 Apr 20 03:07:37 PM PDT 24 294720396 ps
T275 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1119520992 Apr 20 03:08:38 PM PDT 24 Apr 20 03:08:41 PM PDT 24 66409704 ps
T276 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2715623016 Apr 20 03:08:13 PM PDT 24 Apr 20 03:08:16 PM PDT 24 52671505 ps
T46 /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3065610204 Apr 20 03:08:01 PM PDT 24 Apr 20 03:08:05 PM PDT 24 370018077 ps
T277 /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1048844254 Apr 20 03:08:45 PM PDT 24 Apr 20 03:08:46 PM PDT 24 37953670 ps
T42 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3807530396 Apr 20 03:08:53 PM PDT 24 Apr 20 03:09:04 PM PDT 24 901934037 ps
T278 /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.1385297253 Apr 20 03:09:05 PM PDT 24 Apr 20 03:09:11 PM PDT 24 373585291 ps
T279 /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3627138795 Apr 20 03:09:22 PM PDT 24 Apr 20 03:09:23 PM PDT 24 11833974 ps
T280 /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.678706596 Apr 20 03:09:14 PM PDT 24 Apr 20 03:09:15 PM PDT 24 39826511 ps
T281 /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.757155257 Apr 20 03:08:34 PM PDT 24 Apr 20 03:08:36 PM PDT 24 43427489 ps
T282 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.796881726 Apr 20 03:08:53 PM PDT 24 Apr 20 03:08:54 PM PDT 24 13466849 ps
T283 /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.3196612404 Apr 20 03:08:42 PM PDT 24 Apr 20 03:08:45 PM PDT 24 65892017 ps
T284 /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.3475176276 Apr 20 03:08:14 PM PDT 24 Apr 20 03:08:16 PM PDT 24 168180265 ps
T55 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3869016525 Apr 20 03:07:54 PM PDT 24 Apr 20 03:08:02 PM PDT 24 3158111910 ps
T285 /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.2725693569 Apr 20 03:09:00 PM PDT 24 Apr 20 03:09:02 PM PDT 24 169157326 ps
T286 /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.979049257 Apr 20 03:08:01 PM PDT 24 Apr 20 03:08:04 PM PDT 24 394685824 ps
T287 /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.854132021 Apr 20 03:09:18 PM PDT 24 Apr 20 03:09:20 PM PDT 24 69543124 ps
T288 /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1074959622 Apr 20 03:07:39 PM PDT 24 Apr 20 03:07:42 PM PDT 24 109802135 ps
T289 /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2101679680 Apr 20 03:09:12 PM PDT 24 Apr 20 03:09:14 PM PDT 24 150531355 ps
T290 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1489454581 Apr 20 03:07:08 PM PDT 24 Apr 20 03:07:09 PM PDT 24 45349453 ps
T291 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1101008638 Apr 20 03:07:25 PM PDT 24 Apr 20 03:07:30 PM PDT 24 111220568 ps
T292 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.537929600 Apr 20 03:07:20 PM PDT 24 Apr 20 03:07:30 PM PDT 24 1186955430 ps
T53 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1278894706 Apr 20 03:08:16 PM PDT 24 Apr 20 03:08:22 PM PDT 24 182664109 ps
T293 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3305023644 Apr 20 03:07:47 PM PDT 24 Apr 20 03:07:51 PM PDT 24 576278659 ps
T294 /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.727733967 Apr 20 03:09:18 PM PDT 24 Apr 20 03:09:19 PM PDT 24 19388667 ps
T295 /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1724842615 Apr 20 03:08:37 PM PDT 24 Apr 20 03:08:40 PM PDT 24 263594328 ps
T296 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1720288594 Apr 20 03:09:15 PM PDT 24 Apr 20 03:09:16 PM PDT 24 11963847 ps
T297 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1349144017 Apr 20 03:07:49 PM PDT 24 Apr 20 03:07:51 PM PDT 24 84799781 ps
T298 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1183677688 Apr 20 03:07:31 PM PDT 24 Apr 20 03:07:37 PM PDT 24 356019698 ps
T299 /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3818698675 Apr 20 03:09:14 PM PDT 24 Apr 20 03:09:16 PM PDT 24 30579818 ps
T300 /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3612885434 Apr 20 03:09:26 PM PDT 24 Apr 20 03:09:27 PM PDT 24 10021508 ps
T301 /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3154224094 Apr 20 03:08:29 PM PDT 24 Apr 20 03:08:32 PM PDT 24 52243753 ps
T302 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.3614343076 Apr 20 03:08:49 PM PDT 24 Apr 20 03:08:51 PM PDT 24 102488964 ps
T303 /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.556294315 Apr 20 03:08:17 PM PDT 24 Apr 20 03:08:20 PM PDT 24 61712153 ps
T304 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.276446505 Apr 20 03:08:21 PM PDT 24 Apr 20 03:08:23 PM PDT 24 108984109 ps
T305 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.931311921 Apr 20 03:09:22 PM PDT 24 Apr 20 03:09:23 PM PDT 24 8463605 ps
T306 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2394300870 Apr 20 03:07:58 PM PDT 24 Apr 20 03:08:02 PM PDT 24 226071040 ps
T307 /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.1677120885 Apr 20 03:08:54 PM PDT 24 Apr 20 03:08:57 PM PDT 24 129745507 ps
T308 /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1901008946 Apr 20 03:08:33 PM PDT 24 Apr 20 03:08:34 PM PDT 24 12758500 ps
T309 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1545066920 Apr 20 03:07:53 PM PDT 24 Apr 20 03:07:56 PM PDT 24 100513087 ps

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.3648470209
Short name T4
Test name
Test status
Simulation time 2730201945 ps
CPU time 16.9 seconds
Started Apr 20 01:40:00 PM PDT 24
Finished Apr 20 01:40:17 PM PDT 24
Peak memory 208176 kb
Host smart-1398ca48-9a98-493e-8fca-a84239a02ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648470209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.3648470209
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.3980058656
Short name T5
Test name
Test status
Simulation time 406798298 ps
CPU time 10.1 seconds
Started Apr 20 01:39:53 PM PDT 24
Finished Apr 20 01:40:04 PM PDT 24
Peak memory 229432 kb
Host smart-12f24923-fcd3-461e-9b1b-fed5626b7fd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980058656 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.3980058656
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.3388727360
Short name T20
Test name
Test status
Simulation time 138046479 ps
CPU time 3.8 seconds
Started Apr 20 03:09:02 PM PDT 24
Finished Apr 20 03:09:06 PM PDT 24
Peak memory 212696 kb
Host smart-c3eb13f3-a1a1-4c5a-8ba4-f6ec8709e05d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388727360 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.3388727360
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.1326490165
Short name T59
Test name
Test status
Simulation time 209073898 ps
CPU time 1.97 seconds
Started Apr 20 03:09:08 PM PDT 24
Finished Apr 20 03:09:10 PM PDT 24
Peak memory 213032 kb
Host smart-7b01609b-cbd0-4f6d-8e90-32e6c2f63c95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326490165 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.1326490165
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.461333440
Short name T13
Test name
Test status
Simulation time 1152191100 ps
CPU time 24.47 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:42 PM PDT 24
Peak memory 207456 kb
Host smart-5c04e908-5e2f-477a-96e2-5ba04109d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461333440 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.461333440
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.1930009309
Short name T19
Test name
Test status
Simulation time 94019279 ps
CPU time 3.57 seconds
Started Apr 20 03:08:46 PM PDT 24
Finished Apr 20 03:08:50 PM PDT 24
Peak memory 212600 kb
Host smart-ab4deae3-48ea-4a7d-8814-ec75a9150796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930009309 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
1930009309
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.684108261
Short name T61
Test name
Test status
Simulation time 122956247 ps
CPU time 5.1 seconds
Started Apr 20 03:08:10 PM PDT 24
Finished Apr 20 03:08:16 PM PDT 24
Peak memory 213092 kb
Host smart-ff825db3-a112-4fa9-9de1-c97e4f4eacf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684108261 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.684108261
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.2934369752
Short name T28
Test name
Test status
Simulation time 48907368 ps
CPU time 0.93 seconds
Started Apr 20 01:40:14 PM PDT 24
Finished Apr 20 01:40:15 PM PDT 24
Peak memory 205400 kb
Host smart-a0485b81-7805-468b-a28e-c42d2ba4344e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934369752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
2934369752
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.3348192579
Short name T38
Test name
Test status
Simulation time 12544851 ps
CPU time 0.73 seconds
Started Apr 20 03:09:15 PM PDT 24
Finished Apr 20 03:09:16 PM PDT 24
Peak memory 204168 kb
Host smart-89ab80b0-70dc-453c-9e4c-4b0a4a6a02dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348192579 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
3348192579
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.1312016889
Short name T35
Test name
Test status
Simulation time 353792321 ps
CPU time 2.47 seconds
Started Apr 20 03:08:50 PM PDT 24
Finished Apr 20 03:08:52 PM PDT 24
Peak memory 212656 kb
Host smart-eb5038f2-def2-490c-9dce-640e64778046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312016889 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
1312016889
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3807530396
Short name T42
Test name
Test status
Simulation time 901934037 ps
CPU time 10.02 seconds
Started Apr 20 03:08:53 PM PDT 24
Finished Apr 20 03:09:04 PM PDT 24
Peak memory 214876 kb
Host smart-0104203c-4354-4f48-a2e6-bb81fba4f7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807530396 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3807530396
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2337245916
Short name T3
Test name
Test status
Simulation time 593413311 ps
CPU time 10.43 seconds
Started Apr 20 01:39:47 PM PDT 24
Finished Apr 20 01:39:57 PM PDT 24
Peak memory 208120 kb
Host smart-209b1fb2-570e-4225-bd4b-cfd4dc057d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337245916 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2337245916
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.1742766751
Short name T31
Test name
Test status
Simulation time 198785392 ps
CPU time 2.57 seconds
Started Apr 20 03:08:25 PM PDT 24
Finished Apr 20 03:08:28 PM PDT 24
Peak memory 213040 kb
Host smart-3fd7c2e9-d52d-4349-a4ae-9324fef7775b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742766751 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.1742766751
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.2539804278
Short name T51
Test name
Test status
Simulation time 188126782 ps
CPU time 2.6 seconds
Started Apr 20 03:08:49 PM PDT 24
Finished Apr 20 03:08:52 PM PDT 24
Peak memory 213580 kb
Host smart-5f3801ab-f620-431d-af12-12959b68368b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539804278 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.2539804278
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1124274225
Short name T183
Test name
Test status
Simulation time 1167341892 ps
CPU time 9.46 seconds
Started Apr 20 03:06:36 PM PDT 24
Finished Apr 20 03:06:45 PM PDT 24
Peak memory 212936 kb
Host smart-f1232e7f-c7ad-4374-a146-5cdec3cf5df5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124274225 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1124274225
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1809066437
Short name T52
Test name
Test status
Simulation time 831196405 ps
CPU time 5.38 seconds
Started Apr 20 03:06:40 PM PDT 24
Finished Apr 20 03:06:46 PM PDT 24
Peak memory 213680 kb
Host smart-f5abd75d-8158-4a93-aa2c-3f8c6a56c8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809066437 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1809066437
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.1891870753
Short name T48
Test name
Test status
Simulation time 496766456 ps
CPU time 8.92 seconds
Started Apr 20 03:08:34 PM PDT 24
Finished Apr 20 03:08:43 PM PDT 24
Peak memory 213804 kb
Host smart-9f5f0d29-04f5-454e-967a-dba234b5d4f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891870753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.1891870753
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.2317868541
Short name T6
Test name
Test status
Simulation time 2681120217 ps
CPU time 6.11 seconds
Started Apr 20 01:39:47 PM PDT 24
Finished Apr 20 01:39:53 PM PDT 24
Peak memory 233560 kb
Host smart-d87ac922-2e3b-4ab0-b8af-48fa9cc93a18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317868541 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.2317868541
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.4196635466
Short name T56
Test name
Test status
Simulation time 135799308 ps
CPU time 4.99 seconds
Started Apr 20 03:07:41 PM PDT 24
Finished Apr 20 03:07:47 PM PDT 24
Peak memory 213636 kb
Host smart-b35b9f21-3574-44ac-b0e1-db469c9a519f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196635466 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.4196635466
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.316187633
Short name T26
Test name
Test status
Simulation time 212831515 ps
CPU time 11.87 seconds
Started Apr 20 01:40:04 PM PDT 24
Finished Apr 20 01:40:16 PM PDT 24
Peak memory 207892 kb
Host smart-7aadb9ce-50b8-4e31-b513-6f3cd0474aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316187633 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.316187633
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.3388487386
Short name T54
Test name
Test status
Simulation time 670272735 ps
CPU time 4.96 seconds
Started Apr 20 03:07:02 PM PDT 24
Finished Apr 20 03:07:07 PM PDT 24
Peak memory 212620 kb
Host smart-0f595d2c-f960-42ab-aa7f-cdaf3b9b896e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388487386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.3388487386
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.4220925781
Short name T44
Test name
Test status
Simulation time 606378924 ps
CPU time 5.44 seconds
Started Apr 20 03:08:41 PM PDT 24
Finished Apr 20 03:08:47 PM PDT 24
Peak memory 212692 kb
Host smart-6836268f-e80a-46c8-a05d-e8b74faafc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220925781 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.4220925781
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.1798684385
Short name T41
Test name
Test status
Simulation time 239840108 ps
CPU time 4.79 seconds
Started Apr 20 03:07:29 PM PDT 24
Finished Apr 20 03:07:35 PM PDT 24
Peak memory 212564 kb
Host smart-961948f1-dd97-4a15-ab0e-9e90acb63c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798684385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.1798684385
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.3974397166
Short name T58
Test name
Test status
Simulation time 141180077 ps
CPU time 5.76 seconds
Started Apr 20 03:08:09 PM PDT 24
Finished Apr 20 03:08:15 PM PDT 24
Peak memory 212760 kb
Host smart-d04352d8-4b5e-4ae8-a56c-28f0f0e48182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974397166 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.3974397166
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.18139570
Short name T194
Test name
Test status
Simulation time 74204549 ps
CPU time 1.36 seconds
Started Apr 20 03:07:20 PM PDT 24
Finished Apr 20 03:07:21 PM PDT 24
Peak memory 212752 kb
Host smart-204624ac-b534-4b4e-bc90-ceb051abfdd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139570 -assert nopostproc +UVM_TESTNAME=k
eymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.18139570
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.3936005483
Short name T39
Test name
Test status
Simulation time 19716535 ps
CPU time 0.7 seconds
Started Apr 20 03:08:28 PM PDT 24
Finished Apr 20 03:08:29 PM PDT 24
Peak memory 204268 kb
Host smart-327bd769-d88e-4d12-9a2a-28b69cb79e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936005483 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.
3936005483
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.4176121060
Short name T84
Test name
Test status
Simulation time 7385453111 ps
CPU time 34.27 seconds
Started Apr 20 01:40:09 PM PDT 24
Finished Apr 20 01:40:44 PM PDT 24
Peak memory 207396 kb
Host smart-5eac837a-3b3b-4857-b4aa-52efb22efacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176121060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.4176121060
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.2768562563
Short name T94
Test name
Test status
Simulation time 617486495 ps
CPU time 21.62 seconds
Started Apr 20 01:39:52 PM PDT 24
Finished Apr 20 01:40:14 PM PDT 24
Peak memory 207908 kb
Host smart-dc6690b1-1d93-42b7-9434-bcf1334bc0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768562563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.2768562563
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.3447534035
Short name T11
Test name
Test status
Simulation time 1760246233 ps
CPU time 17.4 seconds
Started Apr 20 01:39:49 PM PDT 24
Finished Apr 20 01:40:07 PM PDT 24
Peak memory 206576 kb
Host smart-1eaba752-31cc-409f-80e9-30154a824058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447534035 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.3447534035
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.3988843066
Short name T103
Test name
Test status
Simulation time 7001515877 ps
CPU time 21.67 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:40:17 PM PDT 24
Peak memory 207908 kb
Host smart-e5106330-cab1-4937-8a13-a0f95b8379be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988843066 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.3988843066
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.1068080104
Short name T95
Test name
Test status
Simulation time 1552176712 ps
CPU time 21.82 seconds
Started Apr 20 01:39:59 PM PDT 24
Finished Apr 20 01:40:21 PM PDT 24
Peak memory 208160 kb
Host smart-f4d10f2d-8d3a-42a8-a992-be67ee04f2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068080104 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.1068080104
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.8525777
Short name T25
Test name
Test status
Simulation time 6138189049 ps
CPU time 31.38 seconds
Started Apr 20 01:39:49 PM PDT 24
Finished Apr 20 01:40:21 PM PDT 24
Peak memory 207860 kb
Host smart-c96781fa-ef17-4305-8a02-1387a26372e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8525777 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.8525777
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.3324986076
Short name T92
Test name
Test status
Simulation time 2519397737 ps
CPU time 25.84 seconds
Started Apr 20 01:40:00 PM PDT 24
Finished Apr 20 01:40:26 PM PDT 24
Peak memory 207320 kb
Host smart-cbb6fdf0-abc6-4ccc-a4bb-781ce0f06850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324986076 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.3324986076
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.4067388136
Short name T101
Test name
Test status
Simulation time 785191706 ps
CPU time 19.14 seconds
Started Apr 20 01:40:24 PM PDT 24
Finished Apr 20 01:40:44 PM PDT 24
Peak memory 206280 kb
Host smart-849120a2-cfc7-4978-a49a-c246dfc87c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067388136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.4067388136
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.1441311280
Short name T96
Test name
Test status
Simulation time 1011485065 ps
CPU time 18.75 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:40:15 PM PDT 24
Peak memory 208052 kb
Host smart-cee01310-15d6-41bc-96ad-3db32841b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441311280 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.1441311280
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.694063514
Short name T100
Test name
Test status
Simulation time 12290259207 ps
CPU time 142.93 seconds
Started Apr 20 01:40:06 PM PDT 24
Finished Apr 20 01:42:30 PM PDT 24
Peak memory 208020 kb
Host smart-5d948dcc-fcdb-4634-bfb1-0b105f176f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694063514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.694063514
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.3309718241
Short name T98
Test name
Test status
Simulation time 140134405 ps
CPU time 9.32 seconds
Started Apr 20 01:40:17 PM PDT 24
Finished Apr 20 01:40:27 PM PDT 24
Peak memory 206848 kb
Host smart-521aaa01-95a7-41e6-93ff-066383933f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309718241 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.3309718241
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.2826246390
Short name T93
Test name
Test status
Simulation time 352674321 ps
CPU time 13.21 seconds
Started Apr 20 01:40:05 PM PDT 24
Finished Apr 20 01:40:18 PM PDT 24
Peak memory 207588 kb
Host smart-a41839b7-52a1-41c2-b122-5f26b01f33b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826246390 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.2826246390
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.4160975535
Short name T105
Test name
Test status
Simulation time 652155536 ps
CPU time 19.61 seconds
Started Apr 20 01:40:20 PM PDT 24
Finished Apr 20 01:40:40 PM PDT 24
Peak memory 207268 kb
Host smart-4970a128-51ab-4bd3-b6bd-6896e8a030c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160975535 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.4160975535
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1911742786
Short name T97
Test name
Test status
Simulation time 998631981 ps
CPU time 17.94 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:36 PM PDT 24
Peak memory 206060 kb
Host smart-a8ecf714-dfa4-4f12-b77b-f52f9ab4d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911742786 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1911742786
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.2232234965
Short name T75
Test name
Test status
Simulation time 45380903 ps
CPU time 3.34 seconds
Started Apr 20 03:06:48 PM PDT 24
Finished Apr 20 03:06:51 PM PDT 24
Peak memory 204388 kb
Host smart-2b0e7a9a-5ff1-41e4-a669-dc4b38569ba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232234965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_aliasing.2232234965
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.815491070
Short name T258
Test name
Test status
Simulation time 312199241 ps
CPU time 5.42 seconds
Started Apr 20 03:06:49 PM PDT 24
Finished Apr 20 03:06:55 PM PDT 24
Peak memory 204392 kb
Host smart-e70209f5-6bdd-4b52-ae5a-b169d530f2c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815491070 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_bit_bash.815491070
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.2491221515
Short name T262
Test name
Test status
Simulation time 23958744 ps
CPU time 0.9 seconds
Started Apr 20 03:06:45 PM PDT 24
Finished Apr 20 03:06:47 PM PDT 24
Peak memory 204244 kb
Host smart-1ee67f3e-8678-470c-9800-b0b31ec9f6c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491221515 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.2491221515
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.3611520021
Short name T222
Test name
Test status
Simulation time 112899676 ps
CPU time 1.22 seconds
Started Apr 20 03:06:51 PM PDT 24
Finished Apr 20 03:06:53 PM PDT 24
Peak memory 212696 kb
Host smart-544bd373-af9f-4cdb-81f5-3e0e738069f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611520021 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.3611520021
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.2075840120
Short name T248
Test name
Test status
Simulation time 54175108 ps
CPU time 0.85 seconds
Started Apr 20 03:06:45 PM PDT 24
Finished Apr 20 03:06:46 PM PDT 24
Peak memory 204268 kb
Host smart-8694acba-4ff9-473d-97bd-1551af92ca40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075840120 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.2
075840120
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.104311843
Short name T170
Test name
Test status
Simulation time 21143887 ps
CPU time 1.03 seconds
Started Apr 20 03:06:41 PM PDT 24
Finished Apr 20 03:06:43 PM PDT 24
Peak memory 204408 kb
Host smart-30fb8f0f-4ae3-4cef-946e-cc941c9dd594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104311843 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.104311843
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.849752277
Short name T90
Test name
Test status
Simulation time 316511331 ps
CPU time 2.2 seconds
Started Apr 20 03:06:55 PM PDT 24
Finished Apr 20 03:06:57 PM PDT 24
Peak memory 212600 kb
Host smart-a9c3f881-9903-4411-b096-74d942d7f8ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849752277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_dpe_same_csr_outstanding.849752277
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.880734271
Short name T225
Test name
Test status
Simulation time 263306576 ps
CPU time 1.64 seconds
Started Apr 20 03:06:35 PM PDT 24
Finished Apr 20 03:06:37 PM PDT 24
Peak memory 212968 kb
Host smart-496044fc-a05e-4557-b263-24ea3b35f2a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880734271 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymg
r_dpe_shadow_reg_errors.880734271
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.2608257295
Short name T66
Test name
Test status
Simulation time 260428857 ps
CPU time 1.8 seconds
Started Apr 20 03:06:40 PM PDT 24
Finished Apr 20 03:06:42 PM PDT 24
Peak memory 212724 kb
Host smart-87f296e5-ebab-41ab-ae1a-fc68d573e2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608257295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.2
608257295
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.3365426401
Short name T216
Test name
Test status
Simulation time 84828955 ps
CPU time 5.72 seconds
Started Apr 20 03:07:12 PM PDT 24
Finished Apr 20 03:07:18 PM PDT 24
Peak memory 204420 kb
Host smart-510c6054-5346-4937-9128-b0e8b9bbe56d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365426401 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.3365426401
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.3108872658
Short name T218
Test name
Test status
Simulation time 675748265 ps
CPU time 10.36 seconds
Started Apr 20 03:07:13 PM PDT 24
Finished Apr 20 03:07:23 PM PDT 24
Peak memory 204420 kb
Host smart-7a22343d-b70a-421a-ac91-4885d326a112
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108872658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_bit_bash.3108872658
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1489454581
Short name T290
Test name
Test status
Simulation time 45349453 ps
CPU time 0.95 seconds
Started Apr 20 03:07:08 PM PDT 24
Finished Apr 20 03:07:09 PM PDT 24
Peak memory 204356 kb
Host smart-abbe3d16-2789-43b5-abf1-d4bab7355562
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489454581 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1489454581
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.549771679
Short name T227
Test name
Test status
Simulation time 54428988 ps
CPU time 1.04 seconds
Started Apr 20 03:07:08 PM PDT 24
Finished Apr 20 03:07:09 PM PDT 24
Peak memory 204416 kb
Host smart-2f582196-858e-493d-a219-5979039e678f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549771679 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.549771679
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1209391295
Short name T212
Test name
Test status
Simulation time 38134488 ps
CPU time 0.7 seconds
Started Apr 20 03:07:09 PM PDT 24
Finished Apr 20 03:07:10 PM PDT 24
Peak memory 204276 kb
Host smart-460c4630-66bb-4e65-ab32-79ceae3c6176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209391295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1
209391295
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.1080382921
Short name T79
Test name
Test status
Simulation time 34485238 ps
CPU time 1.82 seconds
Started Apr 20 03:07:19 PM PDT 24
Finished Apr 20 03:07:21 PM PDT 24
Peak memory 204428 kb
Host smart-212c2502-1e1d-4d0b-a4e8-4ba78c38e7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080382921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_dpe_same_csr_outstanding.1080382921
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.222915382
Short name T63
Test name
Test status
Simulation time 61580465 ps
CPU time 1.7 seconds
Started Apr 20 03:06:56 PM PDT 24
Finished Apr 20 03:06:58 PM PDT 24
Peak memory 212860 kb
Host smart-df2e0875-d109-48ed-a147-760770b994cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222915382 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymg
r_dpe_shadow_reg_errors.222915382
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.739344457
Short name T91
Test name
Test status
Simulation time 967974412 ps
CPU time 6.56 seconds
Started Apr 20 03:06:57 PM PDT 24
Finished Apr 20 03:07:04 PM PDT 24
Peak memory 212896 kb
Host smart-4726fd0b-d65d-45c3-9403-8762aaef0b6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739344457 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.739344457
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.134546417
Short name T191
Test name
Test status
Simulation time 39393186 ps
CPU time 2.34 seconds
Started Apr 20 03:07:00 PM PDT 24
Finished Apr 20 03:07:03 PM PDT 24
Peak memory 212708 kb
Host smart-af81d1cd-05cb-4e0c-b494-026b789a2cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134546417 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.134546417
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.3979502666
Short name T32
Test name
Test status
Simulation time 72643198 ps
CPU time 1.3 seconds
Started Apr 20 03:08:29 PM PDT 24
Finished Apr 20 03:08:30 PM PDT 24
Peak memory 212752 kb
Host smart-f6b43ccd-f888-424d-8713-c49e45f6564e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979502666 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.3979502666
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.3908466147
Short name T254
Test name
Test status
Simulation time 24748393 ps
CPU time 1.34 seconds
Started Apr 20 03:08:29 PM PDT 24
Finished Apr 20 03:08:31 PM PDT 24
Peak memory 204368 kb
Host smart-bd076fdd-f76f-4314-9383-77ec3e551cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908466147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
3908466147
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.3154224094
Short name T301
Test name
Test status
Simulation time 52243753 ps
CPU time 2.18 seconds
Started Apr 20 03:08:29 PM PDT 24
Finished Apr 20 03:08:32 PM PDT 24
Peak memory 204476 kb
Host smart-8605f171-7e17-47e7-b9c8-9c3d0dda6e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154224094 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.3154224094
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.276446505
Short name T304
Test name
Test status
Simulation time 108984109 ps
CPU time 2.23 seconds
Started Apr 20 03:08:21 PM PDT 24
Finished Apr 20 03:08:23 PM PDT 24
Peak memory 212932 kb
Host smart-b676b1ff-2bad-4387-9d3e-a41bc9fe8526
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276446505 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keym
gr_dpe_shadow_reg_errors.276446505
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.506199920
Short name T204
Test name
Test status
Simulation time 115209825 ps
CPU time 5.85 seconds
Started Apr 20 03:08:27 PM PDT 24
Finished Apr 20 03:08:33 PM PDT 24
Peak memory 212976 kb
Host smart-36041087-6a17-41b7-a43f-62978d76e658
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506199920 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.506199920
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.1154970996
Short name T29
Test name
Test status
Simulation time 320795852 ps
CPU time 2.61 seconds
Started Apr 20 03:08:25 PM PDT 24
Finished Apr 20 03:08:28 PM PDT 24
Peak memory 212724 kb
Host smart-1709f7ce-b72e-4c40-9c24-20d5ac5edfe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154970996 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
1154970996
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.619795741
Short name T238
Test name
Test status
Simulation time 14147317 ps
CPU time 1.09 seconds
Started Apr 20 03:08:33 PM PDT 24
Finished Apr 20 03:08:34 PM PDT 24
Peak memory 212564 kb
Host smart-5a176149-1902-46be-bd2e-12f3602c7bf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619795741 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.619795741
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.1855729611
Short name T196
Test name
Test status
Simulation time 12685699 ps
CPU time 1.01 seconds
Started Apr 20 03:08:33 PM PDT 24
Finished Apr 20 03:08:34 PM PDT 24
Peak memory 204340 kb
Host smart-9d230678-2a7b-434b-b699-2fa5133617ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855729611 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.
1855729611
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.771160490
Short name T68
Test name
Test status
Simulation time 11319154 ps
CPU time 0.74 seconds
Started Apr 20 03:08:34 PM PDT 24
Finished Apr 20 03:08:35 PM PDT 24
Peak memory 204236 kb
Host smart-730d451f-dcef-48e1-bd4b-4d81e6d01b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771160490 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.771160490
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1724842615
Short name T295
Test name
Test status
Simulation time 263594328 ps
CPU time 2.47 seconds
Started Apr 20 03:08:37 PM PDT 24
Finished Apr 20 03:08:40 PM PDT 24
Peak memory 212668 kb
Host smart-0f8f2935-daf7-4b41-80f7-15b200144ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724842615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1724842615
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.334688350
Short name T270
Test name
Test status
Simulation time 229605044 ps
CPU time 2.95 seconds
Started Apr 20 03:08:30 PM PDT 24
Finished Apr 20 03:08:34 PM PDT 24
Peak memory 212984 kb
Host smart-afc25428-eb7d-4558-bfa2-605227ffa0e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334688350 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keym
gr_dpe_shadow_reg_errors.334688350
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2637011684
Short name T259
Test name
Test status
Simulation time 80773164 ps
CPU time 3.4 seconds
Started Apr 20 03:08:32 PM PDT 24
Finished Apr 20 03:08:35 PM PDT 24
Peak memory 213000 kb
Host smart-fedeeef7-da39-4493-aca0-b6094fc3d4e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637011684 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.2637011684
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.594088115
Short name T251
Test name
Test status
Simulation time 152814254 ps
CPU time 3.26 seconds
Started Apr 20 03:08:30 PM PDT 24
Finished Apr 20 03:08:34 PM PDT 24
Peak memory 215060 kb
Host smart-f1a8a2bc-ae80-4884-bf8f-cebf6641e054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594088115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.594088115
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.2958162995
Short name T50
Test name
Test status
Simulation time 93096122 ps
CPU time 4.06 seconds
Started Apr 20 03:08:37 PM PDT 24
Finished Apr 20 03:08:41 PM PDT 24
Peak memory 213656 kb
Host smart-215e4902-81dd-4077-a4a1-ab5f4257c768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958162995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.2958162995
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.1075960555
Short name T178
Test name
Test status
Simulation time 90495469 ps
CPU time 1.12 seconds
Started Apr 20 03:08:38 PM PDT 24
Finished Apr 20 03:08:39 PM PDT 24
Peak memory 204372 kb
Host smart-3a75a8a2-0a13-4b71-ada1-a3632445e837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075960555 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.1075960555
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.757155257
Short name T281
Test name
Test status
Simulation time 43427489 ps
CPU time 0.92 seconds
Started Apr 20 03:08:34 PM PDT 24
Finished Apr 20 03:08:36 PM PDT 24
Peak memory 204240 kb
Host smart-015783b1-c579-4124-9879-46ac13d4153c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757155257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.757155257
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.1901008946
Short name T308
Test name
Test status
Simulation time 12758500 ps
CPU time 0.84 seconds
Started Apr 20 03:08:33 PM PDT 24
Finished Apr 20 03:08:34 PM PDT 24
Peak memory 204240 kb
Host smart-ba53a190-1c93-42df-bf39-ed9c00ac8316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901008946 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
1901008946
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.5130873
Short name T242
Test name
Test status
Simulation time 213282917 ps
CPU time 1.42 seconds
Started Apr 20 03:08:36 PM PDT 24
Finished Apr 20 03:08:37 PM PDT 24
Peak memory 204372 kb
Host smart-f89c532c-670f-4508-9f7b-1083b1f1eb39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5130873 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.key
mgr_dpe_same_csr_outstanding.5130873
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.902407423
Short name T246
Test name
Test status
Simulation time 56617449 ps
CPU time 1.24 seconds
Started Apr 20 03:08:34 PM PDT 24
Finished Apr 20 03:08:36 PM PDT 24
Peak memory 212924 kb
Host smart-c7506454-5158-4526-bd57-7d3095eb6398
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902407423 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym
gr_dpe_shadow_reg_errors.902407423
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3307876847
Short name T76
Test name
Test status
Simulation time 276913136 ps
CPU time 4.35 seconds
Started Apr 20 03:08:35 PM PDT 24
Finished Apr 20 03:08:39 PM PDT 24
Peak memory 213004 kb
Host smart-d77e66f6-7c16-4de3-9686-03ad16d6d0de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307876847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.3307876847
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.2088755704
Short name T36
Test name
Test status
Simulation time 315669875 ps
CPU time 2.36 seconds
Started Apr 20 03:08:35 PM PDT 24
Finished Apr 20 03:08:37 PM PDT 24
Peak memory 212676 kb
Host smart-12d3f6fa-8500-4313-9b83-259aa23eff29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088755704 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.
2088755704
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.793767067
Short name T250
Test name
Test status
Simulation time 15500976 ps
CPU time 1.37 seconds
Started Apr 20 03:08:43 PM PDT 24
Finished Apr 20 03:08:45 PM PDT 24
Peak memory 204504 kb
Host smart-16aa0b70-9ab7-473b-b464-c895ae7056ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793767067 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.793767067
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.1671719353
Short name T208
Test name
Test status
Simulation time 81318935 ps
CPU time 1.24 seconds
Started Apr 20 03:08:42 PM PDT 24
Finished Apr 20 03:08:43 PM PDT 24
Peak memory 204412 kb
Host smart-ea99ee9c-9aa4-4b5b-8378-23fa4d35b2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671719353 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.
1671719353
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.1260783009
Short name T245
Test name
Test status
Simulation time 10505167 ps
CPU time 0.84 seconds
Started Apr 20 03:08:41 PM PDT 24
Finished Apr 20 03:08:42 PM PDT 24
Peak memory 204204 kb
Host smart-e1fe5eaf-fcff-4bf3-ae1b-ac14c77105c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260783009 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.
1260783009
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.272658293
Short name T175
Test name
Test status
Simulation time 48591124 ps
CPU time 1.68 seconds
Started Apr 20 03:08:41 PM PDT 24
Finished Apr 20 03:08:43 PM PDT 24
Peak memory 204392 kb
Host smart-62c29345-7ebb-4ea1-ba48-0c117704ba12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272658293 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.k
eymgr_dpe_same_csr_outstanding.272658293
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.1119520992
Short name T275
Test name
Test status
Simulation time 66409704 ps
CPU time 2.69 seconds
Started Apr 20 03:08:38 PM PDT 24
Finished Apr 20 03:08:41 PM PDT 24
Peak memory 213028 kb
Host smart-3ae5e642-1bc2-42fe-ba67-bcc1f07c863b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119520992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.1119520992
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1197903147
Short name T273
Test name
Test status
Simulation time 121792558 ps
CPU time 3.1 seconds
Started Apr 20 03:08:37 PM PDT 24
Finished Apr 20 03:08:41 PM PDT 24
Peak memory 213032 kb
Host smart-86335962-cd29-4efd-adf6-053868a60207
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197903147 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.1197903147
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.2719061439
Short name T182
Test name
Test status
Simulation time 104691052 ps
CPU time 3.72 seconds
Started Apr 20 03:08:37 PM PDT 24
Finished Apr 20 03:08:41 PM PDT 24
Peak memory 215160 kb
Host smart-18a28328-ccdb-427c-8775-ad4126246b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719061439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
2719061439
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.1048844254
Short name T277
Test name
Test status
Simulation time 37953670 ps
CPU time 0.93 seconds
Started Apr 20 03:08:45 PM PDT 24
Finished Apr 20 03:08:46 PM PDT 24
Peak memory 204280 kb
Host smart-2ccf386c-0672-4699-8949-753cec0e62ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048844254 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.1048844254
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.3427287384
Short name T211
Test name
Test status
Simulation time 14237371 ps
CPU time 1.03 seconds
Started Apr 20 03:08:47 PM PDT 24
Finished Apr 20 03:08:48 PM PDT 24
Peak memory 204380 kb
Host smart-5048ce7d-68e0-484e-8847-1d0b5c719257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427287384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
3427287384
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.51266210
Short name T240
Test name
Test status
Simulation time 105871556 ps
CPU time 0.83 seconds
Started Apr 20 03:08:46 PM PDT 24
Finished Apr 20 03:08:47 PM PDT 24
Peak memory 204176 kb
Host smart-8620d27a-592b-4f54-bfe3-5a2f448c7421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51266210 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.51266210
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.1787235643
Short name T77
Test name
Test status
Simulation time 68841444 ps
CPU time 2.56 seconds
Started Apr 20 03:08:46 PM PDT 24
Finished Apr 20 03:08:49 PM PDT 24
Peak memory 204408 kb
Host smart-c2e5a602-b6f1-48fa-81fa-f678287d5d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787235643 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.1787235643
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.3196612404
Short name T283
Test name
Test status
Simulation time 65892017 ps
CPU time 2.36 seconds
Started Apr 20 03:08:42 PM PDT 24
Finished Apr 20 03:08:45 PM PDT 24
Peak memory 212948 kb
Host smart-fe629653-648b-4738-84dc-53bfdff99acf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196612404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.3196612404
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1095723200
Short name T236
Test name
Test status
Simulation time 302876375 ps
CPU time 8.97 seconds
Started Apr 20 03:08:49 PM PDT 24
Finished Apr 20 03:08:58 PM PDT 24
Peak memory 212988 kb
Host smart-a9045295-6d3a-45dc-bcb4-60129155096d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095723200 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.1095723200
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1396392290
Short name T45
Test name
Test status
Simulation time 392829578 ps
CPU time 5.19 seconds
Started Apr 20 03:08:46 PM PDT 24
Finished Apr 20 03:08:52 PM PDT 24
Peak memory 212620 kb
Host smart-3aaebebc-c1a7-49a6-81fc-014368afd8db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396392290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1396392290
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.3614343076
Short name T302
Test name
Test status
Simulation time 102488964 ps
CPU time 1.55 seconds
Started Apr 20 03:08:49 PM PDT 24
Finished Apr 20 03:08:51 PM PDT 24
Peak memory 214972 kb
Host smart-0d3c3ef1-e407-4842-9ae8-92a0e6a51dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614343076 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.3614343076
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.1547373642
Short name T234
Test name
Test status
Simulation time 80770272 ps
CPU time 0.99 seconds
Started Apr 20 03:08:51 PM PDT 24
Finished Apr 20 03:08:52 PM PDT 24
Peak memory 204320 kb
Host smart-59ae9f00-9dda-4b7c-aad7-472560d9bf5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547373642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
1547373642
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.358396130
Short name T195
Test name
Test status
Simulation time 48552335 ps
CPU time 0.77 seconds
Started Apr 20 03:08:49 PM PDT 24
Finished Apr 20 03:08:50 PM PDT 24
Peak memory 204184 kb
Host smart-e5d96871-645c-4d00-9630-4f134dc4f45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358396130 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.358396130
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.2126095366
Short name T72
Test name
Test status
Simulation time 28545821 ps
CPU time 1.95 seconds
Started Apr 20 03:08:52 PM PDT 24
Finished Apr 20 03:08:54 PM PDT 24
Peak memory 204440 kb
Host smart-85af7d0f-340c-49d2-b292-384c00de442c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126095366 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_dpe_same_csr_outstanding.2126095366
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.142119171
Short name T89
Test name
Test status
Simulation time 117068539 ps
CPU time 2.37 seconds
Started Apr 20 03:08:46 PM PDT 24
Finished Apr 20 03:08:49 PM PDT 24
Peak memory 212996 kb
Host smart-de4e5331-0cdb-4aad-9fec-da8c7412201f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142119171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keym
gr_dpe_shadow_reg_errors.142119171
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.317801408
Short name T33
Test name
Test status
Simulation time 427377677 ps
CPU time 8.15 seconds
Started Apr 20 03:08:51 PM PDT 24
Finished Apr 20 03:08:59 PM PDT 24
Peak memory 212928 kb
Host smart-326e0f5a-86df-4e09-b684-3be76513a47b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317801408 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.317801408
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.2725693569
Short name T285
Test name
Test status
Simulation time 169157326 ps
CPU time 1.3 seconds
Started Apr 20 03:09:00 PM PDT 24
Finished Apr 20 03:09:02 PM PDT 24
Peak memory 204560 kb
Host smart-8e05f962-a32b-47fb-a768-9c9e1b0666eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725693569 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.2725693569
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.735348563
Short name T80
Test name
Test status
Simulation time 19430452 ps
CPU time 1.03 seconds
Started Apr 20 03:08:57 PM PDT 24
Finished Apr 20 03:08:58 PM PDT 24
Peak memory 204244 kb
Host smart-fe6821dc-21a2-400f-923d-5317231a8213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735348563 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.735348563
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.796881726
Short name T282
Test name
Test status
Simulation time 13466849 ps
CPU time 0.89 seconds
Started Apr 20 03:08:53 PM PDT 24
Finished Apr 20 03:08:54 PM PDT 24
Peak memory 204432 kb
Host smart-039ab0a4-6c38-4520-909f-1bd29c1ae7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796881726 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.796881726
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.2003255894
Short name T267
Test name
Test status
Simulation time 81979888 ps
CPU time 1.71 seconds
Started Apr 20 03:08:58 PM PDT 24
Finished Apr 20 03:09:00 PM PDT 24
Peak memory 212628 kb
Host smart-1e756511-80a0-49f0-b1d8-95e09c907c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003255894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_dpe_same_csr_outstanding.2003255894
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1422158724
Short name T221
Test name
Test status
Simulation time 844523430 ps
CPU time 2.67 seconds
Started Apr 20 03:08:51 PM PDT 24
Finished Apr 20 03:08:54 PM PDT 24
Peak memory 213020 kb
Host smart-2d7a2a3f-d9ba-43fc-9adf-728edbb386d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422158724 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1422158724
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2315580168
Short name T235
Test name
Test status
Simulation time 209661769 ps
CPU time 3.11 seconds
Started Apr 20 03:08:55 PM PDT 24
Finished Apr 20 03:08:58 PM PDT 24
Peak memory 212956 kb
Host smart-c393adc9-0d0c-4143-aef0-1690408ffef8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315580168 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.2315580168
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.1677120885
Short name T307
Test name
Test status
Simulation time 129745507 ps
CPU time 3.11 seconds
Started Apr 20 03:08:54 PM PDT 24
Finished Apr 20 03:08:57 PM PDT 24
Peak memory 214732 kb
Host smart-a66560ec-2abc-4201-aac8-970ec5eb6ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677120885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
1677120885
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.2164412181
Short name T67
Test name
Test status
Simulation time 67592798 ps
CPU time 1.69 seconds
Started Apr 20 03:09:06 PM PDT 24
Finished Apr 20 03:09:09 PM PDT 24
Peak memory 220852 kb
Host smart-423dc240-a270-42f3-b6cb-068ed5e71686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164412181 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.2164412181
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2964801811
Short name T210
Test name
Test status
Simulation time 12850764 ps
CPU time 1.07 seconds
Started Apr 20 03:09:06 PM PDT 24
Finished Apr 20 03:09:08 PM PDT 24
Peak memory 204272 kb
Host smart-e2957579-8a46-4062-8c79-66c3b15de6af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964801811 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2964801811
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.3382820557
Short name T174
Test name
Test status
Simulation time 9151985 ps
CPU time 0.76 seconds
Started Apr 20 03:09:02 PM PDT 24
Finished Apr 20 03:09:03 PM PDT 24
Peak memory 204260 kb
Host smart-445118c6-4208-4310-befe-f33935f763d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382820557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
3382820557
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.1830179380
Short name T269
Test name
Test status
Simulation time 221228767 ps
CPU time 1.67 seconds
Started Apr 20 03:09:07 PM PDT 24
Finished Apr 20 03:09:09 PM PDT 24
Peak memory 204352 kb
Host smart-08540067-48a1-445a-9b1d-07d0b946c442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830179380 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_dpe_same_csr_outstanding.1830179380
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.3848576855
Short name T186
Test name
Test status
Simulation time 644668415 ps
CPU time 2.5 seconds
Started Apr 20 03:09:03 PM PDT 24
Finished Apr 20 03:09:06 PM PDT 24
Peak memory 212916 kb
Host smart-4c09b588-17e3-4e0d-be95-dd3f42025a86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848576855 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.3848576855
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3936809010
Short name T184
Test name
Test status
Simulation time 463903762 ps
CPU time 2.54 seconds
Started Apr 20 03:09:02 PM PDT 24
Finished Apr 20 03:09:05 PM PDT 24
Peak memory 213032 kb
Host smart-c39d364d-9f4b-4878-af0c-6dbaf22508d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936809010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.3936809010
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.1544616279
Short name T201
Test name
Test status
Simulation time 282482477 ps
CPU time 3.67 seconds
Started Apr 20 03:09:04 PM PDT 24
Finished Apr 20 03:09:08 PM PDT 24
Peak memory 216004 kb
Host smart-6fdc29e0-d5b6-4c39-9b7e-cf9f6243eb57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544616279 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.
1544616279
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.300004784
Short name T203
Test name
Test status
Simulation time 38044466 ps
CPU time 1.04 seconds
Started Apr 20 03:09:09 PM PDT 24
Finished Apr 20 03:09:11 PM PDT 24
Peak memory 204292 kb
Host smart-4a1ff45a-b892-4a07-a1a8-62aaa1ec70c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300004784 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.300004784
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.1781547262
Short name T205
Test name
Test status
Simulation time 17630587 ps
CPU time 0.89 seconds
Started Apr 20 03:09:06 PM PDT 24
Finished Apr 20 03:09:07 PM PDT 24
Peak memory 204284 kb
Host smart-033697c8-1fbb-4ec9-b0b1-4c21085165a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781547262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
1781547262
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.2008140311
Short name T239
Test name
Test status
Simulation time 34066058 ps
CPU time 0.88 seconds
Started Apr 20 03:09:06 PM PDT 24
Finished Apr 20 03:09:07 PM PDT 24
Peak memory 204248 kb
Host smart-b20b8c39-faac-47ad-be02-87c3fcf87b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008140311 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.
2008140311
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.1751119406
Short name T271
Test name
Test status
Simulation time 264643443 ps
CPU time 2.13 seconds
Started Apr 20 03:09:06 PM PDT 24
Finished Apr 20 03:09:09 PM PDT 24
Peak memory 204312 kb
Host smart-8ed2fa15-a741-4f4c-a680-b2ebf7745280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751119406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.1751119406
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.1385297253
Short name T278
Test name
Test status
Simulation time 373585291 ps
CPU time 5 seconds
Started Apr 20 03:09:05 PM PDT 24
Finished Apr 20 03:09:11 PM PDT 24
Peak memory 213036 kb
Host smart-c162e5f0-854c-4ae6-92f9-99b049db7cb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385297253 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.1385297253
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.2018671891
Short name T21
Test name
Test status
Simulation time 112617067 ps
CPU time 2.88 seconds
Started Apr 20 03:09:08 PM PDT 24
Finished Apr 20 03:09:11 PM PDT 24
Peak memory 215680 kb
Host smart-764af839-c3ee-4241-bb77-121d49298bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018671891 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
2018671891
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.4261523715
Short name T30
Test name
Test status
Simulation time 2489538191 ps
CPU time 5.69 seconds
Started Apr 20 03:09:07 PM PDT 24
Finished Apr 20 03:09:13 PM PDT 24
Peak memory 213712 kb
Host smart-49e6e716-a17c-4adb-b85e-19e05f172cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261523715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.4261523715
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.1253804741
Short name T171
Test name
Test status
Simulation time 37290297 ps
CPU time 1.16 seconds
Started Apr 20 03:09:15 PM PDT 24
Finished Apr 20 03:09:17 PM PDT 24
Peak memory 204376 kb
Host smart-d1aba624-5809-424f-bfbf-72e41f6604b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253804741 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.1253804741
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.3910576486
Short name T190
Test name
Test status
Simulation time 27632424 ps
CPU time 1.44 seconds
Started Apr 20 03:09:10 PM PDT 24
Finished Apr 20 03:09:12 PM PDT 24
Peak memory 204428 kb
Host smart-2ac995d8-1ca5-42a8-98da-a7aa8caa48c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910576486 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.
3910576486
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.2072385480
Short name T220
Test name
Test status
Simulation time 47400388 ps
CPU time 0.8 seconds
Started Apr 20 03:09:11 PM PDT 24
Finished Apr 20 03:09:12 PM PDT 24
Peak memory 204192 kb
Host smart-eb67a4c2-d13d-4b85-9818-255af8558d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072385480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
2072385480
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.854132021
Short name T287
Test name
Test status
Simulation time 69543124 ps
CPU time 2.14 seconds
Started Apr 20 03:09:18 PM PDT 24
Finished Apr 20 03:09:20 PM PDT 24
Peak memory 204512 kb
Host smart-52de37f3-b04b-415e-80b2-09564279dd47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854132021 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_dpe_same_csr_outstanding.854132021
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.333101650
Short name T199
Test name
Test status
Simulation time 167570324 ps
CPU time 2.39 seconds
Started Apr 20 03:09:11 PM PDT 24
Finished Apr 20 03:09:14 PM PDT 24
Peak memory 213004 kb
Host smart-46d53bb9-4b0e-49c9-a352-26bfe61c30cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333101650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keym
gr_dpe_shadow_reg_errors.333101650
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1961088385
Short name T229
Test name
Test status
Simulation time 250665504 ps
CPU time 4.16 seconds
Started Apr 20 03:09:11 PM PDT 24
Finished Apr 20 03:09:15 PM PDT 24
Peak memory 213088 kb
Host smart-e7323eaf-f7ba-48f3-9d08-6c576d4fd85b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961088385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.1961088385
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3722628669
Short name T193
Test name
Test status
Simulation time 203933978 ps
CPU time 3.98 seconds
Started Apr 20 03:09:11 PM PDT 24
Finished Apr 20 03:09:15 PM PDT 24
Peak memory 215956 kb
Host smart-8e0cc7dd-fb92-495a-8fdb-47e40c2813ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722628669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3722628669
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.2101679680
Short name T289
Test name
Test status
Simulation time 150531355 ps
CPU time 2.19 seconds
Started Apr 20 03:09:12 PM PDT 24
Finished Apr 20 03:09:14 PM PDT 24
Peak memory 212732 kb
Host smart-5c1ae84f-4bff-4c39-bb78-d524a2495fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101679680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.2101679680
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.58115794
Short name T253
Test name
Test status
Simulation time 228865419 ps
CPU time 4.86 seconds
Started Apr 20 03:07:21 PM PDT 24
Finished Apr 20 03:07:26 PM PDT 24
Peak memory 204432 kb
Host smart-693c3302-4b96-4766-add1-548f87db981e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58115794 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_
aliasing.58115794
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.537929600
Short name T292
Test name
Test status
Simulation time 1186955430 ps
CPU time 9.43 seconds
Started Apr 20 03:07:20 PM PDT 24
Finished Apr 20 03:07:30 PM PDT 24
Peak memory 204396 kb
Host smart-c7076cfb-9e12-4825-98b1-2ba69d23e37e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537929600 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr
_bit_bash.537929600
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2838353179
Short name T181
Test name
Test status
Simulation time 27926622 ps
CPU time 1.27 seconds
Started Apr 20 03:07:20 PM PDT 24
Finished Apr 20 03:07:22 PM PDT 24
Peak memory 204380 kb
Host smart-5da15ea1-1344-4aa8-8e8f-c5f0c2c0c346
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838353179 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2838353179
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.589965021
Short name T202
Test name
Test status
Simulation time 36794019 ps
CPU time 0.95 seconds
Started Apr 20 03:07:25 PM PDT 24
Finished Apr 20 03:07:27 PM PDT 24
Peak memory 204224 kb
Host smart-ac8dc3a1-d5d5-4ee2-8ee2-1d97a49ce21c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589965021 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.589965021
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.651850731
Short name T198
Test name
Test status
Simulation time 34297048 ps
CPU time 0.96 seconds
Started Apr 20 03:07:23 PM PDT 24
Finished Apr 20 03:07:24 PM PDT 24
Peak memory 204140 kb
Host smart-d3c08e0a-7686-4def-a82a-5bae58ee08f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651850731 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.651850731
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.774031957
Short name T217
Test name
Test status
Simulation time 12656891 ps
CPU time 0.86 seconds
Started Apr 20 03:07:20 PM PDT 24
Finished Apr 20 03:07:21 PM PDT 24
Peak memory 204296 kb
Host smart-a8020f9b-ed31-4e0d-9a5a-a5778c2df681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774031957 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.774031957
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.1366624262
Short name T189
Test name
Test status
Simulation time 1087528224 ps
CPU time 2.87 seconds
Started Apr 20 03:07:24 PM PDT 24
Finished Apr 20 03:07:27 PM PDT 24
Peak memory 204384 kb
Host smart-2389a59a-3a10-4a97-9584-4c0902a45671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366624262 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.1366624262
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.791668717
Short name T268
Test name
Test status
Simulation time 1146313390 ps
CPU time 1.88 seconds
Started Apr 20 03:07:16 PM PDT 24
Finished Apr 20 03:07:18 PM PDT 24
Peak memory 212984 kb
Host smart-f7df6c31-a553-4240-aeae-b03d301d9c50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791668717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymg
r_dpe_shadow_reg_errors.791668717
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.505287469
Short name T219
Test name
Test status
Simulation time 309407198 ps
CPU time 4.09 seconds
Started Apr 20 03:07:16 PM PDT 24
Finished Apr 20 03:07:21 PM PDT 24
Peak memory 212908 kb
Host smart-a7f1ed08-1806-4f01-9d0b-5557d8491846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505287469 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.505287469
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.3860256669
Short name T263
Test name
Test status
Simulation time 131643380 ps
CPU time 1.82 seconds
Started Apr 20 03:07:17 PM PDT 24
Finished Apr 20 03:07:19 PM PDT 24
Peak memory 212644 kb
Host smart-25fa4ebe-0d52-4d0c-9449-ef4c8c0970bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860256669 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.3
860256669
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.410419386
Short name T57
Test name
Test status
Simulation time 308663729 ps
CPU time 2.79 seconds
Started Apr 20 03:07:20 PM PDT 24
Finished Apr 20 03:07:23 PM PDT 24
Peak memory 213676 kb
Host smart-dbaa8e10-95a0-41f5-afd7-c249e3252093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410419386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_
tl_intg_err.410419386
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.4160400903
Short name T177
Test name
Test status
Simulation time 9052071 ps
CPU time 0.72 seconds
Started Apr 20 03:09:16 PM PDT 24
Finished Apr 20 03:09:17 PM PDT 24
Peak memory 204252 kb
Host smart-36595cf4-1fc2-4215-9df5-693c4bf39e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160400903 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
4160400903
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3205147126
Short name T226
Test name
Test status
Simulation time 30214208 ps
CPU time 0.81 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204180 kb
Host smart-1d7b92f8-dac4-4ca5-bd0c-4e4fc6d3ceb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205147126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3205147126
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.727733967
Short name T294
Test name
Test status
Simulation time 19388667 ps
CPU time 0.78 seconds
Started Apr 20 03:09:18 PM PDT 24
Finished Apr 20 03:09:19 PM PDT 24
Peak memory 204272 kb
Host smart-f879bd3b-e213-4171-9f9a-bdfb33a84aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727733967 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.727733967
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.3818698675
Short name T299
Test name
Test status
Simulation time 30579818 ps
CPU time 0.86 seconds
Started Apr 20 03:09:14 PM PDT 24
Finished Apr 20 03:09:16 PM PDT 24
Peak memory 204192 kb
Host smart-3facde0d-707a-4ff0-8573-e01db7d9baac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818698675 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.
3818698675
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.2610480688
Short name T260
Test name
Test status
Simulation time 11311391 ps
CPU time 0.83 seconds
Started Apr 20 03:09:21 PM PDT 24
Finished Apr 20 03:09:22 PM PDT 24
Peak memory 204180 kb
Host smart-7c8352c0-cc2e-46de-906b-65b34c8e4e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610480688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
2610480688
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.678706596
Short name T280
Test name
Test status
Simulation time 39826511 ps
CPU time 0.82 seconds
Started Apr 20 03:09:14 PM PDT 24
Finished Apr 20 03:09:15 PM PDT 24
Peak memory 204272 kb
Host smart-4f1f6a67-2306-4c33-be88-437718ad59bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678706596 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.678706596
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.1720288594
Short name T296
Test name
Test status
Simulation time 11963847 ps
CPU time 0.84 seconds
Started Apr 20 03:09:15 PM PDT 24
Finished Apr 20 03:09:16 PM PDT 24
Peak memory 204292 kb
Host smart-065a98bb-72ab-4f3e-9fc8-f34b15f43d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720288594 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.
1720288594
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.2723461444
Short name T180
Test name
Test status
Simulation time 48079129 ps
CPU time 0.76 seconds
Started Apr 20 03:09:14 PM PDT 24
Finished Apr 20 03:09:15 PM PDT 24
Peak memory 204244 kb
Host smart-eaa2dfa0-a72f-4f60-85bf-05361928a892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723461444 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
2723461444
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.3536869358
Short name T231
Test name
Test status
Simulation time 26342674 ps
CPU time 0.7 seconds
Started Apr 20 03:09:15 PM PDT 24
Finished Apr 20 03:09:16 PM PDT 24
Peak memory 204296 kb
Host smart-66ef92af-d36e-437f-85cc-cfd629558ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536869358 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
3536869358
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1727015693
Short name T74
Test name
Test status
Simulation time 60929881 ps
CPU time 3.35 seconds
Started Apr 20 03:07:33 PM PDT 24
Finished Apr 20 03:07:37 PM PDT 24
Peak memory 204444 kb
Host smart-ef54fdf7-29b5-4572-9bf8-cd3c200c6675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727015693 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1727015693
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1183677688
Short name T298
Test name
Test status
Simulation time 356019698 ps
CPU time 5.77 seconds
Started Apr 20 03:07:31 PM PDT 24
Finished Apr 20 03:07:37 PM PDT 24
Peak memory 204400 kb
Host smart-509b458f-51e3-4431-9f3f-1803b43c8e6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183677688 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1183677688
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.3906562583
Short name T197
Test name
Test status
Simulation time 136848857 ps
CPU time 0.95 seconds
Started Apr 20 03:07:29 PM PDT 24
Finished Apr 20 03:07:30 PM PDT 24
Peak memory 204312 kb
Host smart-f4afe7eb-0166-4c9e-b4a0-9135a6e05793
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906562583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_hw_reset.3906562583
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.173660715
Short name T65
Test name
Test status
Simulation time 34887074 ps
CPU time 1.35 seconds
Started Apr 20 03:07:38 PM PDT 24
Finished Apr 20 03:07:39 PM PDT 24
Peak memory 212712 kb
Host smart-35bddf87-c177-4186-aa90-4c704780a852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173660715 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.173660715
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.1221064806
Short name T232
Test name
Test status
Simulation time 15493549 ps
CPU time 1.16 seconds
Started Apr 20 03:07:31 PM PDT 24
Finished Apr 20 03:07:32 PM PDT 24
Peak memory 204352 kb
Host smart-d5d1757e-8183-41e6-9581-6edb1497a0cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221064806 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.1
221064806
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.286257839
Short name T206
Test name
Test status
Simulation time 26334455 ps
CPU time 0.73 seconds
Started Apr 20 03:07:31 PM PDT 24
Finished Apr 20 03:07:32 PM PDT 24
Peak memory 204240 kb
Host smart-3985a2f6-df9f-4df9-9596-4f56fc568add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286257839 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.286257839
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.2029373300
Short name T274
Test name
Test status
Simulation time 294720396 ps
CPU time 3.05 seconds
Started Apr 20 03:07:34 PM PDT 24
Finished Apr 20 03:07:37 PM PDT 24
Peak memory 204380 kb
Host smart-836e534e-cb20-4433-9b25-08a2e6d4368c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029373300 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.2029373300
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3705341054
Short name T256
Test name
Test status
Simulation time 148626331 ps
CPU time 1.27 seconds
Started Apr 20 03:07:25 PM PDT 24
Finished Apr 20 03:07:27 PM PDT 24
Peak memory 213060 kb
Host smart-6feb316d-313e-451a-8e2b-3385799350a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705341054 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3705341054
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1101008638
Short name T291
Test name
Test status
Simulation time 111220568 ps
CPU time 3.8 seconds
Started Apr 20 03:07:25 PM PDT 24
Finished Apr 20 03:07:30 PM PDT 24
Peak memory 213024 kb
Host smart-9b3b2ed3-6ed5-4ac0-8442-c2130ebcff91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101008638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1101008638
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.575475528
Short name T266
Test name
Test status
Simulation time 261703192 ps
CPU time 3.64 seconds
Started Apr 20 03:07:30 PM PDT 24
Finished Apr 20 03:07:34 PM PDT 24
Peak memory 212664 kb
Host smart-a67599f2-6d12-494e-bebb-5549a1a860ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575475528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.575475528
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.4020608235
Short name T200
Test name
Test status
Simulation time 11438949 ps
CPU time 0.85 seconds
Started Apr 20 03:09:16 PM PDT 24
Finished Apr 20 03:09:17 PM PDT 24
Peak memory 204144 kb
Host smart-5a166008-afaa-4f05-94e7-865753b95b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020608235 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
4020608235
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.4259522275
Short name T228
Test name
Test status
Simulation time 9037253 ps
CPU time 0.79 seconds
Started Apr 20 03:09:18 PM PDT 24
Finished Apr 20 03:09:19 PM PDT 24
Peak memory 204196 kb
Host smart-f0af69e4-482f-4526-90e4-dba9cc08c25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259522275 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
4259522275
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.1313614528
Short name T213
Test name
Test status
Simulation time 30887656 ps
CPU time 0.8 seconds
Started Apr 20 03:09:16 PM PDT 24
Finished Apr 20 03:09:17 PM PDT 24
Peak memory 204176 kb
Host smart-1300d949-f50b-4d27-8d57-8974c62056cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313614528 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
1313614528
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.3627138795
Short name T279
Test name
Test status
Simulation time 11833974 ps
CPU time 0.75 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204180 kb
Host smart-3a44277a-5448-4d36-b13d-4913e9884677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627138795 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
3627138795
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.1818499558
Short name T40
Test name
Test status
Simulation time 57319535 ps
CPU time 0.85 seconds
Started Apr 20 03:09:18 PM PDT 24
Finished Apr 20 03:09:19 PM PDT 24
Peak memory 204292 kb
Host smart-0f025edb-58f9-45e9-820e-931bf432fa51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818499558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
1818499558
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.931311921
Short name T305
Test name
Test status
Simulation time 8463605 ps
CPU time 0.71 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204196 kb
Host smart-429997fa-493a-4c79-985b-a4bbd4749d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931311921 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.931311921
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3612885434
Short name T300
Test name
Test status
Simulation time 10021508 ps
CPU time 0.84 seconds
Started Apr 20 03:09:26 PM PDT 24
Finished Apr 20 03:09:27 PM PDT 24
Peak memory 204180 kb
Host smart-eb7e53e2-2b6a-41bb-abb1-c453c3aa54da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612885434 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
3612885434
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.4211225421
Short name T169
Test name
Test status
Simulation time 11670636 ps
CPU time 0.76 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204232 kb
Host smart-6ef49eda-8c60-4f0d-8fc5-5f69b0bfa333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211225421 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
4211225421
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.3608606470
Short name T87
Test name
Test status
Simulation time 54712267 ps
CPU time 0.72 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204264 kb
Host smart-76b712b1-7881-4263-97c5-26cfa8754288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608606470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
3608606470
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.3350805270
Short name T172
Test name
Test status
Simulation time 13397832 ps
CPU time 0.7 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204244 kb
Host smart-be058970-5b3c-4885-bc0d-8073b2796c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350805270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
3350805270
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1649476154
Short name T215
Test name
Test status
Simulation time 1077163806 ps
CPU time 10.29 seconds
Started Apr 20 03:07:50 PM PDT 24
Finished Apr 20 03:08:01 PM PDT 24
Peak memory 204408 kb
Host smart-a560572b-1b95-49cf-a5f6-497e6350053e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649476154 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1649476154
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.2284882768
Short name T188
Test name
Test status
Simulation time 951502082 ps
CPU time 9.87 seconds
Started Apr 20 03:07:46 PM PDT 24
Finished Apr 20 03:07:56 PM PDT 24
Peak memory 204396 kb
Host smart-1196fbd6-c616-422d-99f5-660ccd7757db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284882768 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_bit_bash.2284882768
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.1014267244
Short name T209
Test name
Test status
Simulation time 14581045 ps
CPU time 0.85 seconds
Started Apr 20 03:07:41 PM PDT 24
Finished Apr 20 03:07:42 PM PDT 24
Peak memory 204240 kb
Host smart-6892fc91-29d9-4507-9f78-15766ca99bae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014267244 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.1014267244
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.1349144017
Short name T297
Test name
Test status
Simulation time 84799781 ps
CPU time 1.14 seconds
Started Apr 20 03:07:49 PM PDT 24
Finished Apr 20 03:07:51 PM PDT 24
Peak memory 204528 kb
Host smart-ec84da07-d1b6-4897-9c0f-0efdfc329682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349144017 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.1349144017
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.2193808939
Short name T214
Test name
Test status
Simulation time 20848927 ps
CPU time 1.13 seconds
Started Apr 20 03:07:45 PM PDT 24
Finished Apr 20 03:07:46 PM PDT 24
Peak memory 204428 kb
Host smart-87b79a52-24a7-4e49-a153-06f0b7242d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193808939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.2
193808939
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1974971546
Short name T108
Test name
Test status
Simulation time 10293765 ps
CPU time 0.77 seconds
Started Apr 20 03:07:47 PM PDT 24
Finished Apr 20 03:07:49 PM PDT 24
Peak memory 204228 kb
Host smart-8e3ac83e-0877-4a24-ba50-ce3756aa757c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974971546 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
974971546
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.682798084
Short name T88
Test name
Test status
Simulation time 291433817 ps
CPU time 2.16 seconds
Started Apr 20 03:07:48 PM PDT 24
Finished Apr 20 03:07:50 PM PDT 24
Peak memory 204384 kb
Host smart-1051789a-ffbc-42b7-8864-cdc0104cb5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682798084 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_dpe_same_csr_outstanding.682798084
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.1701611060
Short name T62
Test name
Test status
Simulation time 236271037 ps
CPU time 2.65 seconds
Started Apr 20 03:07:38 PM PDT 24
Finished Apr 20 03:07:41 PM PDT 24
Peak memory 213024 kb
Host smart-5ae47814-eb56-49e4-8b6b-5ab560ee8581
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701611060 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_dpe_shadow_reg_errors.1701611060
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1074959622
Short name T288
Test name
Test status
Simulation time 109802135 ps
CPU time 2.44 seconds
Started Apr 20 03:07:39 PM PDT 24
Finished Apr 20 03:07:42 PM PDT 24
Peak memory 213152 kb
Host smart-bcdee009-2aae-4ae5-a62d-69c21b2c825a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074959622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.1074959622
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.3305023644
Short name T293
Test name
Test status
Simulation time 576278659 ps
CPU time 3.66 seconds
Started Apr 20 03:07:47 PM PDT 24
Finished Apr 20 03:07:51 PM PDT 24
Peak memory 214632 kb
Host smart-507901fc-dc8d-4537-bbd3-fe1cf6760cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305023644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.3
305023644
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.3646578968
Short name T168
Test name
Test status
Simulation time 19353981 ps
CPU time 0.74 seconds
Started Apr 20 03:09:23 PM PDT 24
Finished Apr 20 03:09:24 PM PDT 24
Peak memory 204276 kb
Host smart-1b7f9d19-f3a0-4aa4-82e8-587440a68196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646578968 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.
3646578968
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.4046385145
Short name T261
Test name
Test status
Simulation time 60162803 ps
CPU time 0.86 seconds
Started Apr 20 03:09:24 PM PDT 24
Finished Apr 20 03:09:25 PM PDT 24
Peak memory 204272 kb
Host smart-5c893543-3b54-4c7e-893d-5943cf894c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046385145 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
4046385145
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.1072160605
Short name T272
Test name
Test status
Simulation time 16825805 ps
CPU time 0.86 seconds
Started Apr 20 03:09:26 PM PDT 24
Finished Apr 20 03:09:27 PM PDT 24
Peak memory 204212 kb
Host smart-0bf8f8b6-079a-4fb4-bf43-df0374191b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072160605 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
1072160605
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.212536827
Short name T243
Test name
Test status
Simulation time 22509955 ps
CPU time 0.85 seconds
Started Apr 20 03:09:22 PM PDT 24
Finished Apr 20 03:09:23 PM PDT 24
Peak memory 204240 kb
Host smart-e57d73e4-f894-42d3-8ffd-a4900a97d567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212536827 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.212536827
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.2362670119
Short name T252
Test name
Test status
Simulation time 108932234 ps
CPU time 0.77 seconds
Started Apr 20 03:09:27 PM PDT 24
Finished Apr 20 03:09:28 PM PDT 24
Peak memory 204216 kb
Host smart-71651ccf-4c87-411e-954b-5f03806a5b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362670119 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.
2362670119
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3246995091
Short name T85
Test name
Test status
Simulation time 63270113 ps
CPU time 0.73 seconds
Started Apr 20 03:09:27 PM PDT 24
Finished Apr 20 03:09:29 PM PDT 24
Peak memory 204284 kb
Host smart-92eb2812-a6f2-461e-95ea-69a5dd0b1d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246995091 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
3246995091
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.1317612819
Short name T167
Test name
Test status
Simulation time 9859057 ps
CPU time 0.84 seconds
Started Apr 20 03:09:27 PM PDT 24
Finished Apr 20 03:09:28 PM PDT 24
Peak memory 204304 kb
Host smart-8cd7a439-91f2-49de-9b9d-e46b4c9d533f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317612819 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
1317612819
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.2078946489
Short name T237
Test name
Test status
Simulation time 10040633 ps
CPU time 0.7 seconds
Started Apr 20 03:09:27 PM PDT 24
Finished Apr 20 03:09:28 PM PDT 24
Peak memory 204296 kb
Host smart-e6caa2bb-f5cd-4658-883b-8475dadebf54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078946489 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
2078946489
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.734526583
Short name T265
Test name
Test status
Simulation time 8342833 ps
CPU time 0.76 seconds
Started Apr 20 03:09:27 PM PDT 24
Finished Apr 20 03:09:28 PM PDT 24
Peak memory 204180 kb
Host smart-3e541ac6-9895-4405-bd5c-770b8fbf7acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734526583 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.734526583
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3070115890
Short name T86
Test name
Test status
Simulation time 14434053 ps
CPU time 0.79 seconds
Started Apr 20 03:09:30 PM PDT 24
Finished Apr 20 03:09:31 PM PDT 24
Peak memory 204272 kb
Host smart-c2695e49-96e2-478a-8e68-63010bb80d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070115890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3070115890
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.3817609380
Short name T255
Test name
Test status
Simulation time 201305732 ps
CPU time 1.2 seconds
Started Apr 20 03:07:57 PM PDT 24
Finished Apr 20 03:07:58 PM PDT 24
Peak memory 216236 kb
Host smart-65a1045e-d4ed-4d5b-a6a9-17033e94f79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817609380 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.3817609380
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.1864405557
Short name T78
Test name
Test status
Simulation time 12423174 ps
CPU time 0.94 seconds
Started Apr 20 03:07:53 PM PDT 24
Finished Apr 20 03:07:55 PM PDT 24
Peak memory 204348 kb
Host smart-c4f01a4f-9420-4402-a537-3af3376e4a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864405557 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.1
864405557
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.3452095992
Short name T176
Test name
Test status
Simulation time 45747202 ps
CPU time 0.74 seconds
Started Apr 20 03:08:00 PM PDT 24
Finished Apr 20 03:08:01 PM PDT 24
Peak memory 204152 kb
Host smart-7de02276-5c03-421e-804e-d8745e19b318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452095992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.3
452095992
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.2339578163
Short name T192
Test name
Test status
Simulation time 53809984 ps
CPU time 1.69 seconds
Started Apr 20 03:07:54 PM PDT 24
Finished Apr 20 03:07:55 PM PDT 24
Peak memory 204364 kb
Host smart-9060d325-0408-488b-bd02-729ffa11d8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339578163 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_dpe_same_csr_outstanding.2339578163
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.3090530254
Short name T64
Test name
Test status
Simulation time 208903903 ps
CPU time 1.36 seconds
Started Apr 20 03:07:53 PM PDT 24
Finished Apr 20 03:07:54 PM PDT 24
Peak memory 212960 kb
Host smart-9fa8828b-c251-4e16-9bec-21312ccdab61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090530254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.3090530254
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1195396625
Short name T185
Test name
Test status
Simulation time 132165039 ps
CPU time 5.84 seconds
Started Apr 20 03:07:53 PM PDT 24
Finished Apr 20 03:07:59 PM PDT 24
Peak memory 221160 kb
Host smart-6b3b4978-047e-408e-828b-a776e5cab015
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195396625 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.1195396625
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.1545066920
Short name T309
Test name
Test status
Simulation time 100513087 ps
CPU time 2.76 seconds
Started Apr 20 03:07:53 PM PDT 24
Finished Apr 20 03:07:56 PM PDT 24
Peak memory 215368 kb
Host smart-a51195fb-dabd-4280-84a4-29727d705c32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545066920 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.1
545066920
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.3869016525
Short name T55
Test name
Test status
Simulation time 3158111910 ps
CPU time 7.39 seconds
Started Apr 20 03:07:54 PM PDT 24
Finished Apr 20 03:08:02 PM PDT 24
Peak memory 214048 kb
Host smart-88cab048-cf46-44c5-89b0-1429730beed4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869016525 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.3869016525
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.2455279202
Short name T60
Test name
Test status
Simulation time 78293453 ps
CPU time 1.02 seconds
Started Apr 20 03:08:07 PM PDT 24
Finished Apr 20 03:08:08 PM PDT 24
Peak memory 204296 kb
Host smart-f38cd3cd-a28c-4130-bd8b-373255ed950a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455279202 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.2455279202
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2201973067
Short name T249
Test name
Test status
Simulation time 40267393 ps
CPU time 0.97 seconds
Started Apr 20 03:08:01 PM PDT 24
Finished Apr 20 03:08:02 PM PDT 24
Peak memory 204212 kb
Host smart-2d31bd9e-5df1-4806-98db-d850854ae0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201973067 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
201973067
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.3408783288
Short name T69
Test name
Test status
Simulation time 38795932 ps
CPU time 0.8 seconds
Started Apr 20 03:08:08 PM PDT 24
Finished Apr 20 03:08:09 PM PDT 24
Peak memory 204192 kb
Host smart-40db5eb9-e385-41ac-9253-247913e14466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408783288 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.3
408783288
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.979049257
Short name T286
Test name
Test status
Simulation time 394685824 ps
CPU time 1.85 seconds
Started Apr 20 03:08:01 PM PDT 24
Finished Apr 20 03:08:04 PM PDT 24
Peak memory 204464 kb
Host smart-4f90809f-787d-454c-8544-c86640ff56f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979049257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_dpe_same_csr_outstanding.979049257
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.3694886481
Short name T187
Test name
Test status
Simulation time 26939111 ps
CPU time 1.42 seconds
Started Apr 20 03:07:56 PM PDT 24
Finished Apr 20 03:07:58 PM PDT 24
Peak memory 212988 kb
Host smart-b6df31fd-d998-4773-a02d-36e7ad31a09e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694886481 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.3694886481
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2394300870
Short name T306
Test name
Test status
Simulation time 226071040 ps
CPU time 4.47 seconds
Started Apr 20 03:07:58 PM PDT 24
Finished Apr 20 03:08:02 PM PDT 24
Peak memory 217860 kb
Host smart-2bda5859-7db3-4b57-a867-e61dcc27e109
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394300870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2394300870
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.2122453717
Short name T179
Test name
Test status
Simulation time 90884126 ps
CPU time 2.12 seconds
Started Apr 20 03:08:00 PM PDT 24
Finished Apr 20 03:08:02 PM PDT 24
Peak memory 212604 kb
Host smart-243a28f2-75fb-47a5-91e6-dcd9bff8d8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122453717 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.2
122453717
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.3065610204
Short name T46
Test name
Test status
Simulation time 370018077 ps
CPU time 2.96 seconds
Started Apr 20 03:08:01 PM PDT 24
Finished Apr 20 03:08:05 PM PDT 24
Peak memory 212744 kb
Host smart-19041828-9e43-44a6-a040-de56b548b2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065610204 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe
_tl_intg_err.3065610204
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.1767147708
Short name T244
Test name
Test status
Simulation time 16002523 ps
CPU time 0.94 seconds
Started Apr 20 03:08:09 PM PDT 24
Finished Apr 20 03:08:10 PM PDT 24
Peak memory 204284 kb
Host smart-8ce3437b-2e26-4430-b833-28452233fdb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767147708 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.1767147708
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.332585328
Short name T230
Test name
Test status
Simulation time 29980448 ps
CPU time 1.08 seconds
Started Apr 20 03:08:05 PM PDT 24
Finished Apr 20 03:08:07 PM PDT 24
Peak memory 204400 kb
Host smart-621c475b-2c58-4529-b47a-c2f29c45c226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332585328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.332585328
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.293449527
Short name T224
Test name
Test status
Simulation time 22496912 ps
CPU time 0.73 seconds
Started Apr 20 03:08:10 PM PDT 24
Finished Apr 20 03:08:11 PM PDT 24
Peak memory 204232 kb
Host smart-39533671-ee54-476a-8951-5cdb6fcb1a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293449527 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.293449527
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.1483622859
Short name T34
Test name
Test status
Simulation time 21135479 ps
CPU time 1.25 seconds
Started Apr 20 03:08:05 PM PDT 24
Finished Apr 20 03:08:07 PM PDT 24
Peak memory 204364 kb
Host smart-514791e2-03b3-484b-a8ee-a325e3d40142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483622859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.1483622859
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.1211375025
Short name T43
Test name
Test status
Simulation time 181853311 ps
CPU time 1.19 seconds
Started Apr 20 03:08:07 PM PDT 24
Finished Apr 20 03:08:09 PM PDT 24
Peak memory 212928 kb
Host smart-e2c5a3c8-ef4c-4a9e-9cf8-22a26d129b88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211375025 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.1211375025
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3956154933
Short name T247
Test name
Test status
Simulation time 247564364 ps
CPU time 2.47 seconds
Started Apr 20 03:08:01 PM PDT 24
Finished Apr 20 03:08:04 PM PDT 24
Peak memory 212972 kb
Host smart-00e4cb8d-167f-44e4-9411-82208dd2d23e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956154933 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.3956154933
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.1706065202
Short name T264
Test name
Test status
Simulation time 156698622 ps
CPU time 5.67 seconds
Started Apr 20 03:08:08 PM PDT 24
Finished Apr 20 03:08:14 PM PDT 24
Peak memory 212624 kb
Host smart-89ad1be2-9846-463c-921f-523a6499126f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706065202 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.1
706065202
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1404418471
Short name T49
Test name
Test status
Simulation time 95524029 ps
CPU time 3.55 seconds
Started Apr 20 03:08:08 PM PDT 24
Finished Apr 20 03:08:12 PM PDT 24
Peak memory 212556 kb
Host smart-59459650-3cd4-4f3c-83ae-7a7c8526c0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404418471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1404418471
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3268878218
Short name T257
Test name
Test status
Simulation time 47826295 ps
CPU time 1.22 seconds
Started Apr 20 03:08:14 PM PDT 24
Finished Apr 20 03:08:16 PM PDT 24
Peak memory 220264 kb
Host smart-67e005d7-7804-4cc6-af6a-2902292fe18d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268878218 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3268878218
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.2294733673
Short name T70
Test name
Test status
Simulation time 74312880 ps
CPU time 1.03 seconds
Started Apr 20 03:08:12 PM PDT 24
Finished Apr 20 03:08:14 PM PDT 24
Peak memory 204184 kb
Host smart-2342cff7-a56c-4744-80a5-548372398fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294733673 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.2
294733673
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.4209330459
Short name T173
Test name
Test status
Simulation time 12049807 ps
CPU time 0.85 seconds
Started Apr 20 03:08:11 PM PDT 24
Finished Apr 20 03:08:12 PM PDT 24
Peak memory 204272 kb
Host smart-a1fbfb39-5f52-48cc-8f79-bec0122fa1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209330459 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.4
209330459
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.3475176276
Short name T284
Test name
Test status
Simulation time 168180265 ps
CPU time 2.05 seconds
Started Apr 20 03:08:14 PM PDT 24
Finished Apr 20 03:08:16 PM PDT 24
Peak memory 204388 kb
Host smart-20641fcb-2799-4470-a892-2ae302af8caf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475176276 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.3475176276
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.2228776290
Short name T223
Test name
Test status
Simulation time 73616083 ps
CPU time 2.82 seconds
Started Apr 20 03:08:08 PM PDT 24
Finished Apr 20 03:08:11 PM PDT 24
Peak memory 212928 kb
Host smart-d87d3e47-455a-4218-b8a5-22eaf432da08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228776290 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.2228776290
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.2898341514
Short name T47
Test name
Test status
Simulation time 300559026 ps
CPU time 2.62 seconds
Started Apr 20 03:08:09 PM PDT 24
Finished Apr 20 03:08:11 PM PDT 24
Peak memory 212656 kb
Host smart-5b6742dc-1913-4d5d-b4e5-1e70eeacce1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898341514 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.2
898341514
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.544342497
Short name T37
Test name
Test status
Simulation time 33940263 ps
CPU time 1.44 seconds
Started Apr 20 03:08:21 PM PDT 24
Finished Apr 20 03:08:23 PM PDT 24
Peak memory 212692 kb
Host smart-6480cf45-5897-49e2-b8e2-13f6df8f0128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544342497 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.544342497
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.3240454859
Short name T241
Test name
Test status
Simulation time 163667706 ps
CPU time 0.99 seconds
Started Apr 20 03:08:17 PM PDT 24
Finished Apr 20 03:08:18 PM PDT 24
Peak memory 204224 kb
Host smart-cdb68510-7d5c-47a6-9613-b9735fa63f53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240454859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.3
240454859
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.1117090696
Short name T233
Test name
Test status
Simulation time 38500534 ps
CPU time 0.73 seconds
Started Apr 20 03:08:18 PM PDT 24
Finished Apr 20 03:08:19 PM PDT 24
Peak memory 204256 kb
Host smart-fe6f7c01-c012-4599-a41a-784cb478e5b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117090696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.1
117090696
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.1544974162
Short name T73
Test name
Test status
Simulation time 144230214 ps
CPU time 2.96 seconds
Started Apr 20 03:08:21 PM PDT 24
Finished Apr 20 03:08:24 PM PDT 24
Peak memory 204504 kb
Host smart-b9efd076-919b-42e1-b3cc-e5230e30629c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544974162 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.1544974162
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.983415755
Short name T207
Test name
Test status
Simulation time 70122493 ps
CPU time 1.25 seconds
Started Apr 20 03:08:14 PM PDT 24
Finished Apr 20 03:08:15 PM PDT 24
Peak memory 212860 kb
Host smart-fe9c8bbb-524a-48f3-8a98-5cb56328c288
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983415755 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymg
r_dpe_shadow_reg_errors.983415755
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2715623016
Short name T276
Test name
Test status
Simulation time 52671505 ps
CPU time 3.16 seconds
Started Apr 20 03:08:13 PM PDT 24
Finished Apr 20 03:08:16 PM PDT 24
Peak memory 212936 kb
Host smart-8174931e-24d7-44d9-af9f-e44a564fe97c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715623016 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2715623016
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.556294315
Short name T303
Test name
Test status
Simulation time 61712153 ps
CPU time 2.03 seconds
Started Apr 20 03:08:17 PM PDT 24
Finished Apr 20 03:08:20 PM PDT 24
Peak memory 212604 kb
Host smart-407f125a-8820-4925-a807-9754c16b09f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556294315 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.556294315
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1278894706
Short name T53
Test name
Test status
Simulation time 182664109 ps
CPU time 5 seconds
Started Apr 20 03:08:16 PM PDT 24
Finished Apr 20 03:08:22 PM PDT 24
Peak memory 212640 kb
Host smart-87661b54-db10-4bca-a2c8-a7f7c6bece1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278894706 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1278894706
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.1833609482
Short name T127
Test name
Test status
Simulation time 125570112 ps
CPU time 0.76 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:56 PM PDT 24
Peak memory 205180 kb
Host smart-7232e52e-fd29-4bff-b409-fef2e60306fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833609482 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.1
833609482
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.1777803451
Short name T24
Test name
Test status
Simulation time 13655747 ps
CPU time 0.85 seconds
Started Apr 20 01:39:49 PM PDT 24
Finished Apr 20 01:39:50 PM PDT 24
Peak memory 205268 kb
Host smart-e7637d9c-ed19-4bca-a702-8d6e9d6d0344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777803451 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.1
777803451
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.1086825796
Short name T23
Test name
Test status
Simulation time 349367028 ps
CPU time 7.4 seconds
Started Apr 20 01:39:56 PM PDT 24
Finished Apr 20 01:40:04 PM PDT 24
Peak memory 228552 kb
Host smart-94f69ff1-e58f-430e-9c93-44bd00037c30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086825796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.1086825796
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.3872507701
Short name T133
Test name
Test status
Simulation time 150085969 ps
CPU time 9.81 seconds
Started Apr 20 01:39:58 PM PDT 24
Finished Apr 20 01:40:08 PM PDT 24
Peak memory 208048 kb
Host smart-0754c3cd-859e-4ba4-b30a-c7cf858f461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872507701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.3872507701
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2017296491
Short name T119
Test name
Test status
Simulation time 71502734 ps
CPU time 0.85 seconds
Started Apr 20 01:39:52 PM PDT 24
Finished Apr 20 01:39:58 PM PDT 24
Peak memory 205336 kb
Host smart-ec29235f-5319-4ccf-8a6f-897692c62a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017296491 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2017296491
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.3170314224
Short name T162
Test name
Test status
Simulation time 110177559 ps
CPU time 0.8 seconds
Started Apr 20 01:39:57 PM PDT 24
Finished Apr 20 01:39:58 PM PDT 24
Peak memory 205376 kb
Host smart-88539640-cb58-454a-abfd-684c9ab987a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170314224 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
3170314224
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.491918380
Short name T146
Test name
Test status
Simulation time 43914489 ps
CPU time 0.77 seconds
Started Apr 20 01:39:53 PM PDT 24
Finished Apr 20 01:39:55 PM PDT 24
Peak memory 205340 kb
Host smart-3970729f-6eec-4646-b5f6-c4357096fe8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491918380 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.491918380
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.3311268699
Short name T2
Test name
Test status
Simulation time 5893720690 ps
CPU time 26 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:40:21 PM PDT 24
Peak memory 208196 kb
Host smart-67d1e117-40b6-4de8-a479-ff86c5429fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311268699 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.3311268699
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.1691893087
Short name T166
Test name
Test status
Simulation time 11471950 ps
CPU time 0.84 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:39:57 PM PDT 24
Peak memory 205340 kb
Host smart-5da21850-f90d-4f84-a505-80075eb0caec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691893087 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
1691893087
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.3954399752
Short name T128
Test name
Test status
Simulation time 1743698985 ps
CPU time 18 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:40:13 PM PDT 24
Peak memory 208012 kb
Host smart-b045d67b-3f72-4c2b-982e-41bf240cf7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954399752 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.3954399752
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.1154692807
Short name T16
Test name
Test status
Simulation time 72005968 ps
CPU time 0.9 seconds
Started Apr 20 01:40:01 PM PDT 24
Finished Apr 20 01:40:03 PM PDT 24
Peak memory 205300 kb
Host smart-939729a1-6330-47ee-9acb-5c555e0225f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154692807 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
1154692807
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.115952055
Short name T154
Test name
Test status
Simulation time 9546060 ps
CPU time 0.77 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:39:57 PM PDT 24
Peak memory 205336 kb
Host smart-aaecf88f-a096-47c4-817d-afec6518bb33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115952055 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.115952055
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.501703149
Short name T151
Test name
Test status
Simulation time 15113127 ps
CPU time 0.96 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:56 PM PDT 24
Peak memory 205456 kb
Host smart-5e14394a-5728-47b3-9771-78b4be89bc61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501703149 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.501703149
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.1524678014
Short name T150
Test name
Test status
Simulation time 1530450250 ps
CPU time 18.38 seconds
Started Apr 20 01:39:51 PM PDT 24
Finished Apr 20 01:40:09 PM PDT 24
Peak memory 207224 kb
Host smart-9ada11a0-385d-41a6-976b-e7b0d5fc5e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524678014 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.1524678014
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.1221448580
Short name T126
Test name
Test status
Simulation time 55340110 ps
CPU time 0.79 seconds
Started Apr 20 01:39:56 PM PDT 24
Finished Apr 20 01:40:02 PM PDT 24
Peak memory 205292 kb
Host smart-71932c05-30cd-46b0-9ed4-711d2c39ddc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221448580 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
1221448580
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.4143079972
Short name T118
Test name
Test status
Simulation time 16905738 ps
CPU time 0.81 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:12 PM PDT 24
Peak memory 205348 kb
Host smart-147613e1-c0f6-47aa-8354-355a0bf54463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143079972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
4143079972
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.2520919133
Short name T132
Test name
Test status
Simulation time 850176530 ps
CPU time 18.1 seconds
Started Apr 20 01:40:01 PM PDT 24
Finished Apr 20 01:40:20 PM PDT 24
Peak memory 208092 kb
Host smart-e895ee09-2cef-4f78-8279-5de61266f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520919133 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.2520919133
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.1331745987
Short name T114
Test name
Test status
Simulation time 28211046 ps
CPU time 0.77 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:18 PM PDT 24
Peak memory 205248 kb
Host smart-a082e905-9e48-4118-8ed8-f740ccd2ddd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331745987 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.
1331745987
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.3608269943
Short name T149
Test name
Test status
Simulation time 357808282 ps
CPU time 14.28 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:40:10 PM PDT 24
Peak memory 206196 kb
Host smart-b37b1aa0-4d03-4fc9-9f96-fe0d63145fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608269943 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.3608269943
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1531246340
Short name T163
Test name
Test status
Simulation time 15938726 ps
CPU time 0.8 seconds
Started Apr 20 01:39:48 PM PDT 24
Finished Apr 20 01:39:49 PM PDT 24
Peak memory 205284 kb
Host smart-ba72dc08-e8bb-4850-a446-6ef4b9cab996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531246340 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
531246340
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.4288934460
Short name T22
Test name
Test status
Simulation time 685806446 ps
CPU time 10.77 seconds
Started Apr 20 01:39:46 PM PDT 24
Finished Apr 20 01:40:03 PM PDT 24
Peak memory 228620 kb
Host smart-f1ee1040-5bee-4763-a3fb-a3fe8672b5d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288934460 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.4288934460
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.3374878114
Short name T122
Test name
Test status
Simulation time 25403825 ps
CPU time 0.94 seconds
Started Apr 20 01:40:03 PM PDT 24
Finished Apr 20 01:40:04 PM PDT 24
Peak memory 205392 kb
Host smart-9bfd827a-9336-4073-a7d5-d914733b9bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374878114 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.
3374878114
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.1295689995
Short name T10
Test name
Test status
Simulation time 5079018111 ps
CPU time 45.74 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:40:40 PM PDT 24
Peak memory 207548 kb
Host smart-9ce2f995-2354-48da-82b6-ac0317268a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295689995 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.1295689995
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2083574847
Short name T159
Test name
Test status
Simulation time 44152126 ps
CPU time 0.88 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:56 PM PDT 24
Peak memory 205400 kb
Host smart-c402f109-71bd-4c3d-9bee-b330e211995f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083574847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2083574847
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.4012907050
Short name T144
Test name
Test status
Simulation time 2611317726 ps
CPU time 24.26 seconds
Started Apr 20 01:40:01 PM PDT 24
Finished Apr 20 01:40:25 PM PDT 24
Peak memory 206404 kb
Host smart-3056bd89-a86f-40d1-8e5e-559b47bd25f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012907050 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.4012907050
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.3912685805
Short name T112
Test name
Test status
Simulation time 48651973 ps
CPU time 0.77 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:12 PM PDT 24
Peak memory 205376 kb
Host smart-6404a5e7-3276-4f1e-ab18-3adafe6305b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912685805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
3912685805
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.505487313
Short name T131
Test name
Test status
Simulation time 19522053 ps
CPU time 0.74 seconds
Started Apr 20 01:39:57 PM PDT 24
Finished Apr 20 01:39:58 PM PDT 24
Peak memory 205376 kb
Host smart-3a0178f4-894e-424f-ba6b-05070d276ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505487313 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.505487313
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.2539519965
Short name T27
Test name
Test status
Simulation time 545980083 ps
CPU time 18.37 seconds
Started Apr 20 01:40:13 PM PDT 24
Finished Apr 20 01:40:32 PM PDT 24
Peak memory 207820 kb
Host smart-c68c0299-d1c5-40d6-bbeb-0bff63230a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539519965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.2539519965
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1064645787
Short name T111
Test name
Test status
Simulation time 12312598 ps
CPU time 0.88 seconds
Started Apr 20 01:40:19 PM PDT 24
Finished Apr 20 01:40:20 PM PDT 24
Peak memory 205304 kb
Host smart-da377195-5c5e-4f70-9632-5ba5ea022e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064645787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1064645787
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1863812237
Short name T152
Test name
Test status
Simulation time 11580532 ps
CPU time 0.87 seconds
Started Apr 20 01:39:52 PM PDT 24
Finished Apr 20 01:39:54 PM PDT 24
Peak memory 205356 kb
Host smart-81eced71-ffec-4eb7-8277-0205a3c7deba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863812237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1863812237
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.3161021616
Short name T15
Test name
Test status
Simulation time 47019615 ps
CPU time 0.8 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:56 PM PDT 24
Peak memory 205276 kb
Host smart-25c32cbf-1cdc-4f24-a46a-0104ecce917d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161021616 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
3161021616
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.262874691
Short name T147
Test name
Test status
Simulation time 11569373 ps
CPU time 0.78 seconds
Started Apr 20 01:40:08 PM PDT 24
Finished Apr 20 01:40:09 PM PDT 24
Peak memory 205352 kb
Host smart-194accff-53fa-4957-8352-17411ce9729a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262874691 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.262874691
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.344651146
Short name T1
Test name
Test status
Simulation time 46425304 ps
CPU time 0.89 seconds
Started Apr 20 01:40:07 PM PDT 24
Finished Apr 20 01:40:08 PM PDT 24
Peak memory 205256 kb
Host smart-a17f3c01-bb42-46aa-97bd-2771b244c9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344651146 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.344651146
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.2144117226
Short name T145
Test name
Test status
Simulation time 29945903 ps
CPU time 0.85 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:55 PM PDT 24
Peak memory 205348 kb
Host smart-a92b33fa-ac48-44aa-b19a-6b67d12fe124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144117226 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
2144117226
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.3958035716
Short name T12
Test name
Test status
Simulation time 515375958 ps
CPU time 18.18 seconds
Started Apr 20 01:40:14 PM PDT 24
Finished Apr 20 01:40:34 PM PDT 24
Peak memory 208092 kb
Host smart-10c9fe81-797f-4051-bb57-7c675bdcc990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958035716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.3958035716
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.3782404845
Short name T18
Test name
Test status
Simulation time 44161417 ps
CPU time 0.75 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:56 PM PDT 24
Peak memory 205220 kb
Host smart-0d8f8e9c-769b-44a9-b911-bb0622ce9292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782404845 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.3
782404845
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.1767850941
Short name T99
Test name
Test status
Simulation time 1522571608 ps
CPU time 28.5 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:40:24 PM PDT 24
Peak memory 207564 kb
Host smart-cf1b2701-874a-4fba-b23e-2ef61697e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767850941 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.1767850941
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.2714097155
Short name T148
Test name
Test status
Simulation time 22270137 ps
CPU time 0.77 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:55 PM PDT 24
Peak memory 205256 kb
Host smart-9274336c-a317-4012-9cfc-56719eaa3bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714097155 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.
2714097155
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.344924796
Short name T116
Test name
Test status
Simulation time 172467561 ps
CPU time 0.78 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:39:57 PM PDT 24
Peak memory 205212 kb
Host smart-bccd1ea8-0c2a-4a97-b5da-68807e504fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344924796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.344924796
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.983899137
Short name T113
Test name
Test status
Simulation time 17987409 ps
CPU time 0.75 seconds
Started Apr 20 01:40:06 PM PDT 24
Finished Apr 20 01:40:07 PM PDT 24
Peak memory 205344 kb
Host smart-f734d226-1f26-4a2b-ac31-d5d586524a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983899137 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.983899137
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.1643741322
Short name T124
Test name
Test status
Simulation time 1221863042 ps
CPU time 20.76 seconds
Started Apr 20 01:40:02 PM PDT 24
Finished Apr 20 01:40:23 PM PDT 24
Peak memory 207908 kb
Host smart-63614a1e-0dfa-4d6b-b17a-ae542efeda82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643741322 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.1643741322
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.3994991799
Short name T120
Test name
Test status
Simulation time 21607488 ps
CPU time 0.86 seconds
Started Apr 20 01:40:05 PM PDT 24
Finished Apr 20 01:40:06 PM PDT 24
Peak memory 205352 kb
Host smart-73d44f0c-2022-4b7b-8a98-be74e416d27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994991799 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
3994991799
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.3861705277
Short name T136
Test name
Test status
Simulation time 241484747 ps
CPU time 12.88 seconds
Started Apr 20 01:40:14 PM PDT 24
Finished Apr 20 01:40:28 PM PDT 24
Peak memory 207964 kb
Host smart-ad5f1e7b-a9d7-4235-8f74-0aab0bb1e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861705277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.3861705277
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.946119410
Short name T165
Test name
Test status
Simulation time 19572627 ps
CPU time 0.89 seconds
Started Apr 20 01:39:56 PM PDT 24
Finished Apr 20 01:39:57 PM PDT 24
Peak memory 205264 kb
Host smart-d4de8aaf-97f5-4563-968f-b9b414bab385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946119410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.946119410
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.3921466216
Short name T102
Test name
Test status
Simulation time 5387728168 ps
CPU time 92.25 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:41:27 PM PDT 24
Peak memory 207632 kb
Host smart-06df7773-8a7e-41e0-a383-ddf3f559798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921466216 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.3921466216
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.1148931274
Short name T139
Test name
Test status
Simulation time 19290242 ps
CPU time 0.8 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:12 PM PDT 24
Peak memory 205308 kb
Host smart-80d38c84-794c-4c6f-8e2e-ae4e0f506bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148931274 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
1148931274
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.3714031480
Short name T82
Test name
Test status
Simulation time 2174957405 ps
CPU time 14.28 seconds
Started Apr 20 01:40:07 PM PDT 24
Finished Apr 20 01:40:21 PM PDT 24
Peak memory 208168 kb
Host smart-d930e1ce-039e-46a2-b9e7-19d814ba8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714031480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.3714031480
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.3372502859
Short name T155
Test name
Test status
Simulation time 37344668 ps
CPU time 0.68 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:12 PM PDT 24
Peak memory 205380 kb
Host smart-57ae175d-8858-424e-9006-cac27419b9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372502859 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
3372502859
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.143450270
Short name T142
Test name
Test status
Simulation time 75635002 ps
CPU time 0.9 seconds
Started Apr 20 01:39:59 PM PDT 24
Finished Apr 20 01:40:00 PM PDT 24
Peak memory 205360 kb
Host smart-635b95e8-2bcb-4d9e-8ebe-3ee96c27a720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143450270 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.143450270
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.1475004282
Short name T83
Test name
Test status
Simulation time 10176958706 ps
CPU time 224.73 seconds
Started Apr 20 01:40:15 PM PDT 24
Finished Apr 20 01:44:01 PM PDT 24
Peak memory 228652 kb
Host smart-45635162-7cc5-47d4-a91e-98e6d5754579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475004282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.1475004282
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.2029490487
Short name T130
Test name
Test status
Simulation time 58824795 ps
CPU time 0.74 seconds
Started Apr 20 01:40:07 PM PDT 24
Finished Apr 20 01:40:08 PM PDT 24
Peak memory 205196 kb
Host smart-5380bfdf-bdfd-44dd-b16d-0b41bc21dcfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029490487 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
2029490487
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.2448404184
Short name T125
Test name
Test status
Simulation time 101078779 ps
CPU time 0.76 seconds
Started Apr 20 01:39:51 PM PDT 24
Finished Apr 20 01:39:52 PM PDT 24
Peak memory 205260 kb
Host smart-be6cf550-3b90-4fc4-a5f1-bdb316ca9d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448404184 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.2
448404184
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.3106739746
Short name T7
Test name
Test status
Simulation time 2495356022 ps
CPU time 19.52 seconds
Started Apr 20 01:39:56 PM PDT 24
Finished Apr 20 01:40:16 PM PDT 24
Peak memory 236472 kb
Host smart-985a4c9a-092e-4252-ab39-84eadd8e6e08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106739746 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.3106739746
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3704088736
Short name T141
Test name
Test status
Simulation time 1321146295 ps
CPU time 21.89 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:40:16 PM PDT 24
Peak memory 208432 kb
Host smart-883a5f69-67c4-4e8c-a962-cac0717250c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704088736 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3704088736
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.3683636530
Short name T109
Test name
Test status
Simulation time 15030162 ps
CPU time 0.83 seconds
Started Apr 20 01:40:15 PM PDT 24
Finished Apr 20 01:40:27 PM PDT 24
Peak memory 205380 kb
Host smart-383215f7-df68-40d3-a0af-f48d5383f628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683636530 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
3683636530
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.2387487480
Short name T71
Test name
Test status
Simulation time 618652343 ps
CPU time 20.26 seconds
Started Apr 20 01:40:06 PM PDT 24
Finished Apr 20 01:40:27 PM PDT 24
Peak memory 207304 kb
Host smart-4a013221-1e6a-4aaf-8868-a06ccf10b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387487480 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.2387487480
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.3063421868
Short name T115
Test name
Test status
Simulation time 11838495 ps
CPU time 0.9 seconds
Started Apr 20 01:40:09 PM PDT 24
Finished Apr 20 01:40:10 PM PDT 24
Peak memory 205400 kb
Host smart-2a530960-20e0-46c8-b2df-def6a7cc9b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063421868 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
3063421868
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.2451037650
Short name T104
Test name
Test status
Simulation time 15538006785 ps
CPU time 31.39 seconds
Started Apr 20 01:40:10 PM PDT 24
Finished Apr 20 01:40:42 PM PDT 24
Peak memory 207800 kb
Host smart-1357be57-5ea8-490a-a23b-b8291173162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451037650 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.2451037650
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.466374862
Short name T17
Test name
Test status
Simulation time 13863902 ps
CPU time 0.91 seconds
Started Apr 20 01:40:09 PM PDT 24
Finished Apr 20 01:40:10 PM PDT 24
Peak memory 205268 kb
Host smart-b3586f1e-477b-4b77-934d-50f25f437259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466374862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.466374862
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.361700886
Short name T9
Test name
Test status
Simulation time 2608741346 ps
CPU time 15.81 seconds
Started Apr 20 01:40:10 PM PDT 24
Finished Apr 20 01:40:26 PM PDT 24
Peak memory 207692 kb
Host smart-d102c49b-2ec4-410f-90c9-15ce9ec4c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361700886 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.361700886
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.3326404385
Short name T164
Test name
Test status
Simulation time 19564041 ps
CPU time 0.74 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:19 PM PDT 24
Peak memory 205308 kb
Host smart-cd30a2db-7268-40e2-92e2-75f0befb247e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326404385 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
3326404385
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2458834931
Short name T129
Test name
Test status
Simulation time 711927734 ps
CPU time 20.74 seconds
Started Apr 20 01:40:02 PM PDT 24
Finished Apr 20 01:40:24 PM PDT 24
Peak memory 207884 kb
Host smart-786099fa-3c37-4e01-84aa-22a4e9e68e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458834931 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2458834931
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2086738533
Short name T143
Test name
Test status
Simulation time 20083749 ps
CPU time 0.76 seconds
Started Apr 20 01:40:09 PM PDT 24
Finished Apr 20 01:40:10 PM PDT 24
Peak memory 205280 kb
Host smart-b5cef8cb-c6cd-4204-a6e9-396917e89946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086738533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2086738533
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.1701555152
Short name T137
Test name
Test status
Simulation time 558817176 ps
CPU time 19.95 seconds
Started Apr 20 01:40:05 PM PDT 24
Finished Apr 20 01:40:25 PM PDT 24
Peak memory 206436 kb
Host smart-aacd39f3-bd99-4841-9985-b770e18cd271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701555152 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.1701555152
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.909969314
Short name T121
Test name
Test status
Simulation time 12941516 ps
CPU time 0.77 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:18 PM PDT 24
Peak memory 205356 kb
Host smart-64b89b59-00eb-4284-aed2-1b6c0fdb51fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909969314 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.909969314
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.3256835364
Short name T161
Test name
Test status
Simulation time 6055463016 ps
CPU time 32.88 seconds
Started Apr 20 01:40:06 PM PDT 24
Finished Apr 20 01:40:39 PM PDT 24
Peak memory 207920 kb
Host smart-cbc94585-b11b-47ef-8ea8-51ed780b2666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256835364 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.3256835364
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3131909985
Short name T110
Test name
Test status
Simulation time 47972428 ps
CPU time 0.85 seconds
Started Apr 20 01:40:15 PM PDT 24
Finished Apr 20 01:40:17 PM PDT 24
Peak memory 205308 kb
Host smart-9e11aa26-ae13-40ab-8316-84db28f06295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131909985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3131909985
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.2245786599
Short name T138
Test name
Test status
Simulation time 128863870 ps
CPU time 0.92 seconds
Started Apr 20 01:40:07 PM PDT 24
Finished Apr 20 01:40:08 PM PDT 24
Peak memory 205440 kb
Host smart-b2008a19-5770-486b-9df1-858669c5d9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245786599 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
2245786599
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3398898116
Short name T157
Test name
Test status
Simulation time 427194126 ps
CPU time 13.53 seconds
Started Apr 20 01:40:12 PM PDT 24
Finished Apr 20 01:40:26 PM PDT 24
Peak memory 207972 kb
Host smart-e04c4e8a-5026-4a5b-b383-03aff8e935d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398898116 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3398898116
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.2302790639
Short name T158
Test name
Test status
Simulation time 21690531 ps
CPU time 1.06 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:13 PM PDT 24
Peak memory 205472 kb
Host smart-061e1ac7-dc6a-495d-ab23-a29c9bb39265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302790639 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.
2302790639
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.192567151
Short name T117
Test name
Test status
Simulation time 754738875 ps
CPU time 15.32 seconds
Started Apr 20 01:40:23 PM PDT 24
Finished Apr 20 01:40:39 PM PDT 24
Peak memory 207840 kb
Host smart-ead4a174-6f80-430a-9a48-f64d19ab0ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192567151 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.192567151
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.4078992837
Short name T134
Test name
Test status
Simulation time 15296717 ps
CPU time 0.92 seconds
Started Apr 20 01:40:11 PM PDT 24
Finished Apr 20 01:40:12 PM PDT 24
Peak memory 205384 kb
Host smart-dfa54c3b-2ca0-45f2-8401-e06a57aace75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078992837 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
4078992837
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.759766728
Short name T14
Test name
Test status
Simulation time 5764456402 ps
CPU time 126.77 seconds
Started Apr 20 01:40:20 PM PDT 24
Finished Apr 20 01:42:28 PM PDT 24
Peak memory 208212 kb
Host smart-1993c6a7-3e61-4485-8f74-d0c247c330f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759766728 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.759766728
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.2484268674
Short name T160
Test name
Test status
Simulation time 55660120 ps
CPU time 0.86 seconds
Started Apr 20 01:39:48 PM PDT 24
Finished Apr 20 01:39:49 PM PDT 24
Peak memory 205380 kb
Host smart-e713e8e1-1d01-4be9-ac1b-acec45406866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484268674 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.2
484268674
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.180527737
Short name T8
Test name
Test status
Simulation time 2261063850 ps
CPU time 19.87 seconds
Started Apr 20 01:39:55 PM PDT 24
Finished Apr 20 01:40:16 PM PDT 24
Peak memory 206332 kb
Host smart-079e1a9b-51a3-4895-941e-18f4da61a1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180527737 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.180527737
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.4061450443
Short name T156
Test name
Test status
Simulation time 10521405 ps
CPU time 0.79 seconds
Started Apr 20 01:40:16 PM PDT 24
Finished Apr 20 01:40:18 PM PDT 24
Peak memory 205264 kb
Host smart-be6793dc-801d-4727-a473-60e77b00bf2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061450443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.4
061450443
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.2254039005
Short name T140
Test name
Test status
Simulation time 2520126551 ps
CPU time 21.42 seconds
Started Apr 20 01:39:53 PM PDT 24
Finished Apr 20 01:40:15 PM PDT 24
Peak memory 207488 kb
Host smart-50bdb165-06d3-4706-a482-1af4c4db7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254039005 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.2254039005
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.8196968
Short name T135
Test name
Test status
Simulation time 118237655 ps
CPU time 0.9 seconds
Started Apr 20 01:40:03 PM PDT 24
Finished Apr 20 01:40:04 PM PDT 24
Peak memory 205472 kb
Host smart-0a27d9eb-28e8-4061-9119-4edefa92f99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8196968 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.8196968
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.489851970
Short name T107
Test name
Test status
Simulation time 11142777402 ps
CPU time 35.52 seconds
Started Apr 20 01:39:58 PM PDT 24
Finished Apr 20 01:40:33 PM PDT 24
Peak memory 207728 kb
Host smart-f1fa2cb4-46c1-460b-8c4b-e9a7cde933af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489851970 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.489851970
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.584677778
Short name T123
Test name
Test status
Simulation time 46755495 ps
CPU time 0.8 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:55 PM PDT 24
Peak memory 205252 kb
Host smart-efc575ae-367e-4c9e-93ea-814927cd3cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584677778 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.584677778
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2835727831
Short name T106
Test name
Test status
Simulation time 621412058 ps
CPU time 20.18 seconds
Started Apr 20 01:39:52 PM PDT 24
Finished Apr 20 01:40:13 PM PDT 24
Peak memory 208140 kb
Host smart-cdec547f-797a-49dc-afd3-7f44a8f9ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835727831 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2835727831
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.1396076073
Short name T153
Test name
Test status
Simulation time 24596366 ps
CPU time 0.82 seconds
Started Apr 20 01:39:54 PM PDT 24
Finished Apr 20 01:39:55 PM PDT 24
Peak memory 205308 kb
Host smart-599df0de-7d27-4cc4-b931-98122ad70e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396076073 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.1
396076073
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.1855959775
Short name T81
Test name
Test status
Simulation time 4012152039 ps
CPU time 33.7 seconds
Started Apr 20 01:39:52 PM PDT 24
Finished Apr 20 01:40:27 PM PDT 24
Peak memory 207948 kb
Host smart-7d454668-9e74-429f-9239-6b0a77bc6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855959775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.1855959775
Directory /workspace/9.keymgr_dpe_smoke/latest
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