Unified Coverage Report :: Group :: keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

Group : keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
17.51	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_dpe_env_0.1/keymgr_dpe_env_cov.sv

---

Summary for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	17	4	13	76.47
Crosses	240	208	32	13.33

Variables for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	1	1	50.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	1	4	80.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	4	2	2	50.00	100	1	1	0

Crosses for Group keymgr_dpe_env_pkg::keymgr_dpe_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	160	144	16	10.00	100	1	1	0
op_x_status_cross	80	64	16	20.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cdi_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Attestation]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

6882

1

T1

133

T2

124

T3

114

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	1692	1			T1	31		T2	28		T3	26
auto[Aes]	1681	1			T1	29		T2	36		T3	31
auto[Kmac]	1763	1			T1	43		T2	32		T3	32
auto[Otbn]	1746	1			T1	30		T2	28		T3	25

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDpeErase]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpDpeAdvance]	1555	1			T1	30		T2	32		T3	31
auto[OpDpeGenSwOut]	3378	1			T1	75		T2	47		T3	54
auto[OpDpeGenHwOut]	3504	1			T1	58		T2	77		T3	60
auto[OpDpeDisable]	100	1			T1	2		T2	2		T3	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

3499

1

T1

90

T2

66

T3

102

auto[OpDoneFail]

5038

1

T1

75

T2

92

T3

45

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	2	2	50.00

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StWorkDpeDisabled]	0	1	1
auto[StWorkDpeInvalid]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[StWorkDpeReset]

266

1

T1

6

T2

4

T3

2

auto[StWorkDpeAvailable]

8271

1

T1

159

T2

154

T3

145

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	160	144	16	10.00	144

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	64
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Sealing]]	*	[auto[StWorkDpeDisabled] , auto[StWorkDpeInvalid]]	--	--	16
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	32
[auto[OpDpeDisable]]	*	*	*	--	--	32

Covered bins

op_cp

cdi_cp

dest_cp

state_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

11

1

T1

1

T9

2

T10

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

789

1

T1

17

T2

12

T3

16

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

22

1

T1

1

T11

2

T105

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

819

1

T1

19

T2

11

T3

15

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

22

1

T9

1

T11

1

T12

2

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

854

1

T1

21

T2

11

T3

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

23

1

T9

2

T10

1

T11

3

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

838

1

T1

16

T2

13

T3

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeReset]

27

1

T1

1

T2

1

T9

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[StWorkDpeAvailable]

865

1

T1

12

T2

15

T3

10

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeReset]

15

1

T9

3

T11

1

T105

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[StWorkDpeAvailable]

825

1

T1

9

T2

25

T3

16

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeReset]

26

1

T9

1

T11

1

T12

2

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[StWorkDpeAvailable]

861

1

T1

22

T2

21

T3

19

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeReset]

20

1

T1

1

T2

1

T12

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[StWorkDpeAvailable]

865

1

T1

13

T2

14

T3

15

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	64	16	20.00	64

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase]]	*	*	*	--	--	32
[auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut]]	[auto[Attestation]]	*	*	--	--	16
[auto[OpDpeDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpDpeAdvance] , auto[OpDpeErase] , auto[OpDpeGenSwOut] , auto[OpDpeGenHwOut] , auto[OpDpeDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp

cdi_cp

dest_cp

op_status_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

356

1

T1

9

T2

7

T3

11

auto[OpDpeGenSwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

444

1

T1

9

T2

5

T3

5

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

375

1

T1

15

T2

6

T3

13

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

466

1

T1

5

T2

5

T3

2

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

372

1

T1

12

T2

3

T3

12

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

504

1

T1

9

T2

8

T3

1

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

367

1

T1

8

T2

8

T3

7

auto[OpDpeGenSwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

494

1

T1

8

T2

5

T3

3

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneSuccess]

390

1

T1

8

T2

10

T3

9

auto[OpDpeGenHwOut]

auto[Sealing]

auto[None]

auto[OpDoneFail]

502

1

T1

5

T2

6

T3

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneSuccess]

379

1

T1

5

T2

6

T3

15

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Aes]

auto[OpDoneFail]

461

1

T1

4

T2

19

T3

1

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneSuccess]

389

1

T1

16

T2

6

T3

12

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Kmac]

auto[OpDoneFail]

498

1

T1

6

T2

15

T3

7

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneSuccess]

399

1

T1

7

T2

10

T3

14

auto[OpDpeGenHwOut]

auto[Sealing]

auto[Otbn]

auto[OpDoneFail]

486

1

T1

7

T2

5

T3

1