Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
76.27 97.70 90.67 57.52 76.92 94.94 98.34 17.82


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T45 /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.3269912384 Apr 27 01:46:17 PM PDT 24 Apr 27 01:46:23 PM PDT 24 259854224 ps
T256 /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.3444769000 Apr 27 01:46:27 PM PDT 24 Apr 27 01:46:29 PM PDT 24 45799218 ps
T43 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.4070214792 Apr 27 01:46:06 PM PDT 24 Apr 27 01:46:09 PM PDT 24 174404390 ps
T257 /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.2166342446 Apr 27 01:46:43 PM PDT 24 Apr 27 01:46:44 PM PDT 24 71906502 ps
T258 /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.955216190 Apr 27 01:46:32 PM PDT 24 Apr 27 01:46:33 PM PDT 24 7467368 ps
T259 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.737679555 Apr 27 01:46:17 PM PDT 24 Apr 27 01:46:21 PM PDT 24 158194469 ps
T260 /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2061301425 Apr 27 01:46:09 PM PDT 24 Apr 27 01:46:14 PM PDT 24 1116618566 ps
T261 /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1236604180 Apr 27 01:46:24 PM PDT 24 Apr 27 01:46:29 PM PDT 24 114192222 ps
T262 /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1081799701 Apr 27 01:46:32 PM PDT 24 Apr 27 01:46:36 PM PDT 24 450562218 ps
T263 /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.2332231564 Apr 27 01:46:28 PM PDT 24 Apr 27 01:46:31 PM PDT 24 92110184 ps
T264 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3187249344 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:14 PM PDT 24 17996612 ps
T265 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1369354779 Apr 27 01:46:19 PM PDT 24 Apr 27 01:46:21 PM PDT 24 41007241 ps
T266 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2409632344 Apr 27 01:46:55 PM PDT 24 Apr 27 01:47:01 PM PDT 24 200441031 ps
T267 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.3234380596 Apr 27 01:46:08 PM PDT 24 Apr 27 01:46:10 PM PDT 24 13589921 ps
T268 /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.2564810557 Apr 27 01:46:29 PM PDT 24 Apr 27 01:46:31 PM PDT 24 16596402 ps
T46 /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1594891861 Apr 27 01:46:37 PM PDT 24 Apr 27 01:46:41 PM PDT 24 165670613 ps
T269 /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.791134426 Apr 27 01:46:36 PM PDT 24 Apr 27 01:46:45 PM PDT 24 273956536 ps
T270 /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2964678102 Apr 27 01:46:15 PM PDT 24 Apr 27 01:46:17 PM PDT 24 25755860 ps
T271 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3003208388 Apr 27 01:46:29 PM PDT 24 Apr 27 01:46:33 PM PDT 24 433554923 ps
T272 /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2740751574 Apr 27 01:46:24 PM PDT 24 Apr 27 01:46:29 PM PDT 24 811056529 ps
T273 /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.1019511686 Apr 27 01:46:10 PM PDT 24 Apr 27 01:46:14 PM PDT 24 1039768769 ps
T274 /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1789633813 Apr 27 01:46:14 PM PDT 24 Apr 27 01:46:16 PM PDT 24 38440623 ps
T275 /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2839935965 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:14 PM PDT 24 8495628 ps
T47 /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2234238888 Apr 27 01:46:17 PM PDT 24 Apr 27 01:46:22 PM PDT 24 179015088 ps
T276 /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2557374626 Apr 27 01:46:15 PM PDT 24 Apr 27 01:46:17 PM PDT 24 8806287 ps
T277 /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3947181277 Apr 27 01:46:27 PM PDT 24 Apr 27 01:46:29 PM PDT 24 36259640 ps
T278 /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.855771644 Apr 27 01:46:43 PM PDT 24 Apr 27 01:46:49 PM PDT 24 26002693 ps
T279 /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2921508106 Apr 27 01:46:38 PM PDT 24 Apr 27 01:46:39 PM PDT 24 96464372 ps
T280 /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3427626486 Apr 27 01:46:54 PM PDT 24 Apr 27 01:46:56 PM PDT 24 30133783 ps
T281 /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2854247032 Apr 27 01:46:29 PM PDT 24 Apr 27 01:46:31 PM PDT 24 9684196 ps
T282 /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1682977234 Apr 27 01:46:15 PM PDT 24 Apr 27 01:46:17 PM PDT 24 11482541 ps
T283 /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3451844727 Apr 27 01:46:35 PM PDT 24 Apr 27 01:46:36 PM PDT 24 26758651 ps
T284 /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.505534283 Apr 27 01:46:15 PM PDT 24 Apr 27 01:46:24 PM PDT 24 406497103 ps
T285 /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.1048194405 Apr 27 01:46:31 PM PDT 24 Apr 27 01:46:32 PM PDT 24 43525489 ps
T286 /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1756724343 Apr 27 01:46:09 PM PDT 24 Apr 27 01:46:16 PM PDT 24 318450093 ps
T287 /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.400687833 Apr 27 01:46:18 PM PDT 24 Apr 27 01:46:20 PM PDT 24 27825371 ps
T288 /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4123135159 Apr 27 01:46:09 PM PDT 24 Apr 27 01:46:13 PM PDT 24 795175666 ps
T289 /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3590954386 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:15 PM PDT 24 62356759 ps
T290 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3913137858 Apr 27 01:46:33 PM PDT 24 Apr 27 01:46:35 PM PDT 24 208965691 ps
T291 /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.4235066462 Apr 27 01:46:32 PM PDT 24 Apr 27 01:46:40 PM PDT 24 226276381 ps
T292 /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.230639082 Apr 27 01:46:15 PM PDT 24 Apr 27 01:46:18 PM PDT 24 34698577 ps
T293 /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3997565169 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:24 PM PDT 24 341398816 ps
T294 /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1182907888 Apr 27 01:46:17 PM PDT 24 Apr 27 01:46:21 PM PDT 24 88985628 ps
T295 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2031319009 Apr 27 01:46:32 PM PDT 24 Apr 27 01:46:34 PM PDT 24 20203108 ps
T296 /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1834099696 Apr 27 01:46:30 PM PDT 24 Apr 27 01:46:32 PM PDT 24 44207531 ps
T297 /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.574721862 Apr 27 01:46:16 PM PDT 24 Apr 27 01:46:22 PM PDT 24 230480962 ps
T298 /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.546490638 Apr 27 01:46:29 PM PDT 24 Apr 27 01:46:32 PM PDT 24 39375994 ps
T299 /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.97300860 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:15 PM PDT 24 28570089 ps
T57 /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3001712012 Apr 27 01:46:32 PM PDT 24 Apr 27 01:46:41 PM PDT 24 340129016 ps
T300 /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4060735825 Apr 27 01:46:07 PM PDT 24 Apr 27 01:46:12 PM PDT 24 85695962 ps
T301 /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.1971281981 Apr 27 01:46:28 PM PDT 24 Apr 27 01:46:31 PM PDT 24 50835152 ps
T302 /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219955573 Apr 27 01:46:21 PM PDT 24 Apr 27 01:46:31 PM PDT 24 737179380 ps
T303 /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2981324533 Apr 27 01:46:11 PM PDT 24 Apr 27 01:46:15 PM PDT 24 64352356 ps
T304 /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.176703787 Apr 27 01:46:30 PM PDT 24 Apr 27 01:46:34 PM PDT 24 132944047 ps
T305 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1885429939 Apr 27 01:46:10 PM PDT 24 Apr 27 01:46:20 PM PDT 24 900235575 ps
T306 /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.710350320 Apr 27 01:46:09 PM PDT 24 Apr 27 01:46:16 PM PDT 24 203457822 ps
T307 /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1215421404 Apr 27 01:46:13 PM PDT 24 Apr 27 01:46:16 PM PDT 24 23758765 ps
T308 /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3567917310 Apr 27 01:46:49 PM PDT 24 Apr 27 01:46:50 PM PDT 24 43727636 ps
T309 /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3323618651 Apr 27 01:46:30 PM PDT 24 Apr 27 01:46:33 PM PDT 24 228089934 ps
T310 /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2599655363 Apr 27 01:46:30 PM PDT 24 Apr 27 01:46:33 PM PDT 24 488384721 ps

Test location /workspace/coverage/default/29.keymgr_dpe_smoke.1881287959
Short name T9
Test name
Test status
Simulation time 5853837683 ps
CPU time 43.28 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:10:23 PM PDT 24
Peak memory 208084 kb
Host smart-2e658fa7-5558-48e8-a4d7-dea87839de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881287959 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_smoke.1881287959
Directory /workspace/29.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_sec_cm.675699287
Short name T4
Test name
Test status
Simulation time 373806799 ps
CPU time 11.34 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:38 PM PDT 24
Peak memory 230200 kb
Host smart-beea2e61-fd20-443f-8bf3-a4cb9536e7ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675699287 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_sec_cm.675699287
Directory /workspace/1.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_same_csr_outstanding.2611914003
Short name T69
Test name
Test status
Simulation time 994106610 ps
CPU time 2.61 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 204456 kb
Host smart-9b46cf8c-03d3-4826-8175-8d883d6d8020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611914003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_dpe_same_csr_outstanding.2611914003
Directory /workspace/9.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_mem_rw_with_rand_reset.4013384482
Short name T18
Test name
Test status
Simulation time 70881482 ps
CPU time 1.63 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 212744 kb
Host smart-8f8da142-4f27-44be-9f37-da89405b370f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013384482 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_mem_rw_with_rand_reset.4013384482
Directory /workspace/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors.1440815976
Short name T60
Test name
Test status
Simulation time 197240694 ps
CPU time 1.94 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 212972 kb
Host smart-0c5838fb-3862-45f0-ae61-b3ebbda589a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440815976 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.key
mgr_dpe_shadow_reg_errors.1440815976
Directory /workspace/14.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_errors.1347534971
Short name T32
Test name
Test status
Simulation time 55104166 ps
CPU time 3.1 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 215740 kb
Host smart-f2467451-a958-4d44-abc2-b404d4aaf7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347534971 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_tl_errors.
1347534971
Directory /workspace/18.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_intg_err.1169742738
Short name T26
Test name
Test status
Simulation time 643722957 ps
CPU time 3.01 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 213860 kb
Host smart-a4098248-1a51-4901-95d7-3e8152053cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169742738 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe
_tl_intg_err.1169742738
Directory /workspace/5.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_dpe_smoke.576906352
Short name T12
Test name
Test status
Simulation time 1594958977 ps
CPU time 15.77 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:09:55 PM PDT 24
Peak memory 208148 kb
Host smart-06a9231c-1481-4d8f-8ad8-bce42c0a4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576906352 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_smoke.576906352
Directory /workspace/30.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_alert_test.2577338471
Short name T131
Test name
Test status
Simulation time 67946163 ps
CPU time 0.82 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:34 PM PDT 24
Peak memory 205336 kb
Host smart-a7a10f0a-69b2-4195-ba47-cac4dbd24a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577338471 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_alert_test.
2577338471
Directory /workspace/13.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_intr_test.2760805984
Short name T102
Test name
Test status
Simulation time 14773705 ps
CPU time 0.93 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 204400 kb
Host smart-d65b02df-28d5-4a67-838b-ec94731424b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760805984 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_intr_test.
2760805984
Directory /workspace/15.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors.3973567237
Short name T63
Test name
Test status
Simulation time 115037464 ps
CPU time 1.97 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 212932 kb
Host smart-4785e8e7-9682-4c9f-9a77-ba99e1685ee0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973567237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.key
mgr_dpe_shadow_reg_errors.3973567237
Directory /workspace/13.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.keymgr_dpe_smoke.3387671982
Short name T105
Test name
Test status
Simulation time 370148520 ps
CPU time 12.57 seconds
Started Apr 27 02:09:25 PM PDT 24
Finished Apr 27 02:09:38 PM PDT 24
Peak memory 208144 kb
Host smart-76e96834-817e-4a43-972b-3e3b70025679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387671982 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_smoke.3387671982
Directory /workspace/6.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_intg_err.1743764397
Short name T41
Test name
Test status
Simulation time 89280599 ps
CPU time 2.58 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:36 PM PDT 24
Peak memory 213668 kb
Host smart-4491c09f-97e7-48e6-a784-cf58568585f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743764397 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe
_tl_intg_err.1743764397
Directory /workspace/9.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_intg_err.2868236574
Short name T49
Test name
Test status
Simulation time 1028278763 ps
CPU time 8.94 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:38 PM PDT 24
Peak memory 214296 kb
Host smart-a4af3249-f470-4697-86fc-b3878f8f50ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868236574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dp
e_tl_intg_err.2868236574
Directory /workspace/13.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_intg_err.2234238888
Short name T47
Test name
Test status
Simulation time 179015088 ps
CPU time 3.95 seconds
Started Apr 27 01:46:17 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 212584 kb
Host smart-47ad7bfe-2b92-4d85-a05e-130753f997c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234238888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe
_tl_intg_err.2234238888
Directory /workspace/1.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_intg_err.4155412862
Short name T53
Test name
Test status
Simulation time 218771479 ps
CPU time 4.96 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 212680 kb
Host smart-bbf9f1d5-1b5e-4e38-b6b7-e3c79d63afe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155412862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dp
e_tl_intg_err.4155412862
Directory /workspace/12.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_intg_err.3633446676
Short name T58
Test name
Test status
Simulation time 471735399 ps
CPU time 2.99 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 212460 kb
Host smart-50cf4969-7538-4990-a32b-438cc80280ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633446676 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe
_tl_intg_err.3633446676
Directory /workspace/4.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_dpe_intr_test.3997063544
Short name T37
Test name
Test status
Simulation time 49014116 ps
CPU time 0.73 seconds
Started Apr 27 01:46:36 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 204180 kb
Host smart-445d60bf-7259-4178-994a-4a50d9748171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997063544 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_intr_test.
3997063544
Directory /workspace/37.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_intg_err.3765035269
Short name T55
Test name
Test status
Simulation time 211206685 ps
CPU time 7.64 seconds
Started Apr 27 01:46:25 PM PDT 24
Finished Apr 27 01:46:38 PM PDT 24
Peak memory 213696 kb
Host smart-e5ffd45e-537a-4905-8f76-e814c63b3e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765035269 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dp
e_tl_intg_err.3765035269
Directory /workspace/10.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_intg_err.3269912384
Short name T45
Test name
Test status
Simulation time 259854224 ps
CPU time 4.17 seconds
Started Apr 27 01:46:17 PM PDT 24
Finished Apr 27 01:46:23 PM PDT 24
Peak memory 213960 kb
Host smart-338e196b-33f9-41fb-9c69-eed66a31df7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269912384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dp
e_tl_intg_err.3269912384
Directory /workspace/15.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_intg_err.1852695988
Short name T27
Test name
Test status
Simulation time 664085580 ps
CPU time 6.57 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:40 PM PDT 24
Peak memory 212624 kb
Host smart-7ded76fc-53b1-454a-9b0f-21bc3e13837a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852695988 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dp
e_tl_intg_err.1852695988
Directory /workspace/17.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_intg_err.4070214792
Short name T43
Test name
Test status
Simulation time 174404390 ps
CPU time 2.61 seconds
Started Apr 27 01:46:06 PM PDT 24
Finished Apr 27 01:46:09 PM PDT 24
Peak memory 212672 kb
Host smart-fadd2af2-13ea-409c-ad51-f277f4bbf756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070214792 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe
_tl_intg_err.4070214792
Directory /workspace/2.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_intg_err.2842629384
Short name T59
Test name
Test status
Simulation time 225343639 ps
CPU time 5.2 seconds
Started Apr 27 01:46:22 PM PDT 24
Finished Apr 27 01:46:27 PM PDT 24
Peak memory 213600 kb
Host smart-c81a1427-1835-4899-a98c-d088e4e51d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842629384 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe
_tl_intg_err.2842629384
Directory /workspace/8.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_dpe_sec_cm.1399440264
Short name T21
Test name
Test status
Simulation time 1122085349 ps
CPU time 12.37 seconds
Started Apr 27 02:09:25 PM PDT 24
Finished Apr 27 02:09:38 PM PDT 24
Peak memory 231616 kb
Host smart-13160723-7fae-465e-8d57-04c7a7322f45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399440264 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_sec_cm.1399440264
Directory /workspace/0.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_mem_rw_with_rand_reset.187316387
Short name T249
Test name
Test status
Simulation time 32612381 ps
CPU time 1.64 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 212648 kb
Host smart-49b6c85a-ff2d-4a02-8790-e6fe7e93cac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187316387 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_mem_rw_with_rand_reset.187316387
Directory /workspace/1.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_dpe_smoke.2439812439
Short name T75
Test name
Test status
Simulation time 1147765675 ps
CPU time 31.87 seconds
Started Apr 27 02:09:28 PM PDT 24
Finished Apr 27 02:10:00 PM PDT 24
Peak memory 207308 kb
Host smart-22d9cefa-c0c3-4ebb-a46e-ed602557fab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439812439 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_smoke.2439812439
Directory /workspace/0.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/1.keymgr_dpe_smoke.2045926651
Short name T120
Test name
Test status
Simulation time 386842923 ps
CPU time 10.72 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:39 PM PDT 24
Peak memory 207732 kb
Host smart-73ee991d-ae46-40b0-ba71-cc24f6f421f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045926651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_smoke.2045926651
Directory /workspace/1.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_smoke.3674820894
Short name T114
Test name
Test status
Simulation time 3992173564 ps
CPU time 21.25 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:48 PM PDT 24
Peak memory 207980 kb
Host smart-44a12919-5884-4cb4-8886-0b90393de623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674820894 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_smoke.3674820894
Directory /workspace/11.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/12.keymgr_dpe_smoke.1884034978
Short name T71
Test name
Test status
Simulation time 11035834615 ps
CPU time 30.56 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:58 PM PDT 24
Peak memory 207148 kb
Host smart-55d2f6c4-56d3-4a35-ab5c-079cdbb75691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884034978 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_smoke.1884034978
Directory /workspace/12.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/13.keymgr_dpe_smoke.1460353539
Short name T117
Test name
Test status
Simulation time 8381031455 ps
CPU time 31.02 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:10:06 PM PDT 24
Peak memory 207844 kb
Host smart-49bf9de7-c82c-4cfa-810d-02204a2e6d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460353539 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_smoke.1460353539
Directory /workspace/13.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_smoke.1893541972
Short name T77
Test name
Test status
Simulation time 1660400729 ps
CPU time 31.42 seconds
Started Apr 27 02:09:36 PM PDT 24
Finished Apr 27 02:10:08 PM PDT 24
Peak memory 217760 kb
Host smart-2fe41894-74bf-40e1-8b94-bb7d57a9b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893541972 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_smoke.1893541972
Directory /workspace/15.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_smoke.3036801126
Short name T107
Test name
Test status
Simulation time 301410858 ps
CPU time 9.81 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:44 PM PDT 24
Peak memory 208000 kb
Host smart-4a7be685-035c-4977-8ccf-8f673dcfbb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036801126 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_smoke.3036801126
Directory /workspace/25.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_smoke.429732526
Short name T92
Test name
Test status
Simulation time 1066037652 ps
CPU time 20.54 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:10:01 PM PDT 24
Peak memory 207976 kb
Host smart-c4f8c95f-c39f-47d8-8005-b12feb655b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429732526 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_smoke.429732526
Directory /workspace/32.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_smoke.113667246
Short name T106
Test name
Test status
Simulation time 686628119 ps
CPU time 11.21 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:09:55 PM PDT 24
Peak memory 206612 kb
Host smart-37da6b92-9857-47c6-ab18-4d1d20f71d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113667246 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_smoke.113667246
Directory /workspace/34.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_smoke.2934995753
Short name T112
Test name
Test status
Simulation time 266753078 ps
CPU time 14.67 seconds
Started Apr 27 02:09:48 PM PDT 24
Finished Apr 27 02:10:04 PM PDT 24
Peak memory 208048 kb
Host smart-c0729137-042c-45b5-af80-35c92db1cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934995753 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_smoke.2934995753
Directory /workspace/38.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/39.keymgr_dpe_smoke.461017553
Short name T1
Test name
Test status
Simulation time 6287984174 ps
CPU time 134.09 seconds
Started Apr 27 02:09:46 PM PDT 24
Finished Apr 27 02:12:00 PM PDT 24
Peak memory 208268 kb
Host smart-234e6fe1-b670-413b-b23a-dad756422670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461017553 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_smoke.461017553
Directory /workspace/39.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_smoke.4042859593
Short name T111
Test name
Test status
Simulation time 552924378 ps
CPU time 19.35 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:10:05 PM PDT 24
Peak memory 208320 kb
Host smart-2c99c4a0-7ad5-4121-8638-8ba56135b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042859593 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_smoke.4042859593
Directory /workspace/41.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_smoke.3954958785
Short name T109
Test name
Test status
Simulation time 152634880 ps
CPU time 9.4 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:09:55 PM PDT 24
Peak memory 206260 kb
Host smart-b3c170a8-7559-4dcc-b6c6-b4d704b1f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954958785 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_smoke.3954958785
Directory /workspace/47.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/48.keymgr_dpe_smoke.2109132465
Short name T108
Test name
Test status
Simulation time 627653693 ps
CPU time 15.23 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:10:00 PM PDT 24
Peak memory 207328 kb
Host smart-8bfb1f59-19c5-4a81-9300-d2901dc1f619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109132465 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_smoke.2109132465
Directory /workspace/48.keymgr_dpe_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_aliasing.292938194
Short name T227
Test name
Test status
Simulation time 86848353 ps
CPU time 5.58 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:23 PM PDT 24
Peak memory 204508 kb
Host smart-38bbc481-65e8-4851-b867-ac6d0a3d9bb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292938194 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr
_aliasing.292938194
Directory /workspace/0.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_bit_bash.2300791748
Short name T182
Test name
Test status
Simulation time 5208012030 ps
CPU time 17.66 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 204380 kb
Host smart-239fcbc7-8f44-4214-a12c-01b27d4ea47f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300791748 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_bit_bash.2300791748
Directory /workspace/0.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_hw_reset.4162706658
Short name T241
Test name
Test status
Simulation time 64578459 ps
CPU time 1 seconds
Started Apr 27 01:46:19 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 204312 kb
Host smart-19c0f5e7-9939-432c-a8f6-013ea2f4a887
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162706658 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_cs
r_hw_reset.4162706658
Directory /workspace/0.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_mem_rw_with_rand_reset.1919305600
Short name T208
Test name
Test status
Simulation time 105728544 ps
CPU time 1.84 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 212616 kb
Host smart-c34ccdcc-4011-476d-ae63-62c6b1d65d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919305600 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1919305600
Directory /workspace/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_csr_rw.3705977976
Short name T224
Test name
Test status
Simulation time 12557320 ps
CPU time 0.9 seconds
Started Apr 27 01:46:36 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 204220 kb
Host smart-88c74227-1b39-4f6c-9a2c-783897811cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705977976 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_csr_rw.3
705977976
Directory /workspace/0.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_intr_test.803503472
Short name T67
Test name
Test status
Simulation time 19997199 ps
CPU time 0.71 seconds
Started Apr 27 01:46:07 PM PDT 24
Finished Apr 27 01:46:08 PM PDT 24
Peak memory 204204 kb
Host smart-bda40ae1-fb2d-470b-ba96-e08ac541325a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803503472 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_intr_test.803503472
Directory /workspace/0.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_same_csr_outstanding.2875124136
Short name T89
Test name
Test status
Simulation time 18275187 ps
CPU time 1.36 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 204372 kb
Host smart-1778e396-7935-436f-8427-c518d86b7c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875124136 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_dpe_same_csr_outstanding.2875124136
Directory /workspace/0.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors.3483896479
Short name T216
Test name
Test status
Simulation time 46582019 ps
CPU time 1.78 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 212888 kb
Host smart-e2ced1e9-ebf8-4e48-9f06-165c8ce303ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483896479 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keym
gr_dpe_shadow_reg_errors.3483896479
Directory /workspace/0.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_shadow_reg_errors_with_csr_rw.4169943044
Short name T61
Test name
Test status
Simulation time 233799740 ps
CPU time 4.13 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 212980 kb
Host smart-2391f4fe-eb5e-4981-b08e-9803eb6b1c60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169943044 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.4169943044
Directory /workspace/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_errors.3746043805
Short name T33
Test name
Test status
Simulation time 62380275 ps
CPU time 1.81 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:20 PM PDT 24
Peak memory 212676 kb
Host smart-a8d4ddb0-625b-4eb1-8936-cf98eec722e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746043805 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_tl_errors.3
746043805
Directory /workspace/0.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_dpe_tl_intg_err.1733934249
Short name T191
Test name
Test status
Simulation time 77257081 ps
CPU time 2.32 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 212508 kb
Host smart-10cc8184-4408-45d8-ae26-1b6ac60149e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733934249 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe
_tl_intg_err.1733934249
Directory /workspace/0.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_aliasing.4123135159
Short name T288
Test name
Test status
Simulation time 795175666 ps
CPU time 3.56 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 204364 kb
Host smart-3335a84f-60c7-4306-b1c2-7c9ceeca23ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123135159 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_aliasing.4123135159
Directory /workspace/1.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_bit_bash.217570410
Short name T251
Test name
Test status
Simulation time 89974983 ps
CPU time 4.45 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 204348 kb
Host smart-1f81f042-7d4b-408a-ae1f-ab1b09a56c6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217570410 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr
_bit_bash.217570410
Directory /workspace/1.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_hw_reset.1464797816
Short name T179
Test name
Test status
Simulation time 22313990 ps
CPU time 0.87 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 204248 kb
Host smart-7080ee72-f797-4705-b840-d43823df355b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464797816 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_cs
r_hw_reset.1464797816
Directory /workspace/1.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_csr_rw.803179610
Short name T209
Test name
Test status
Simulation time 11437566 ps
CPU time 0.86 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204152 kb
Host smart-0a7d67f1-02fa-41d6-ae5f-a22c40ca122e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803179610 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_csr_rw.803179610
Directory /workspace/1.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_intr_test.1789633813
Short name T274
Test name
Test status
Simulation time 38440623 ps
CPU time 0.84 seconds
Started Apr 27 01:46:14 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204212 kb
Host smart-a258ece3-13dc-48ff-a40f-c9ae29e63f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789633813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_intr_test.1
789633813
Directory /workspace/1.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_same_csr_outstanding.623664295
Short name T225
Test name
Test status
Simulation time 161700829 ps
CPU time 1.38 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 204464 kb
Host smart-054e8e04-b1e5-4161-b80e-c04315d6866e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623664295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_dpe_same_csr_outstanding.623664295
Directory /workspace/1.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors.1693254030
Short name T234
Test name
Test status
Simulation time 169513918 ps
CPU time 1.3 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:12 PM PDT 24
Peak memory 212944 kb
Host smart-d4605d01-1559-4cad-b392-a0b731d9bbb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693254030 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keym
gr_dpe_shadow_reg_errors.1693254030
Directory /workspace/1.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_shadow_reg_errors_with_csr_rw.688141406
Short name T217
Test name
Test status
Simulation time 270349922 ps
CPU time 3.12 seconds
Started Apr 27 01:46:07 PM PDT 24
Finished Apr 27 01:46:11 PM PDT 24
Peak memory 212976 kb
Host smart-f435c482-1a60-4044-8166-965e93bb3726
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688141406 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.keymgr_dpe_shadow_reg_errors_with_csr_rw.688141406
Directory /workspace/1.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_dpe_tl_errors.3646439533
Short name T226
Test name
Test status
Simulation time 63231835 ps
CPU time 2.56 seconds
Started Apr 27 01:46:12 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 220212 kb
Host smart-9c53a368-1633-40eb-8788-1037c80d421e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646439533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_tl_errors.3
646439533
Directory /workspace/1.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_mem_rw_with_rand_reset.2031319009
Short name T295
Test name
Test status
Simulation time 20203108 ps
CPU time 1.03 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 204388 kb
Host smart-61e7fdf9-f79d-497b-9713-03d98e71d1b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031319009 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_mem_rw_with_rand_reset.2031319009
Directory /workspace/10.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_csr_rw.2981324533
Short name T303
Test name
Test status
Simulation time 64352356 ps
CPU time 0.96 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 204284 kb
Host smart-6b69cc7b-0998-48f7-8ee9-6f04a4b4fc21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981324533 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_csr_rw.
2981324533
Directory /workspace/10.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_intr_test.173424302
Short name T196
Test name
Test status
Simulation time 9370893 ps
CPU time 0.74 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:20 PM PDT 24
Peak memory 204212 kb
Host smart-fe1739d1-9854-454c-8f1c-22976f679b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173424302 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_intr_test.173424302
Directory /workspace/10.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_same_csr_outstanding.4200546687
Short name T212
Test name
Test status
Simulation time 28221417 ps
CPU time 1.84 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 204432 kb
Host smart-575db028-5f26-4335-af17-541bb7619f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200546687 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_dpe_same_csr_outstanding.4200546687
Directory /workspace/10.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors.2646816519
Short name T44
Test name
Test status
Simulation time 417600865 ps
CPU time 1.94 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 212984 kb
Host smart-f93ca5ee-aeed-422b-8e7b-1d184d3e3b60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646816519 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.key
mgr_dpe_shadow_reg_errors.2646816519
Directory /workspace/10.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_shadow_reg_errors_with_csr_rw.710350320
Short name T306
Test name
Test status
Simulation time 203457822 ps
CPU time 5.51 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 212916 kb
Host smart-6710618b-de6c-4619-baed-4789addab6f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710350320 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.keymgr_dpe_shadow_reg_errors_with_csr_rw.710350320
Directory /workspace/10.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_dpe_tl_errors.1981408508
Short name T23
Test name
Test status
Simulation time 200405376 ps
CPU time 2.01 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 220760 kb
Host smart-5b328b50-a81f-4054-b6ea-26056d48cb1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981408508 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_tl_errors.
1981408508
Directory /workspace/10.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_mem_rw_with_rand_reset.3898051166
Short name T101
Test name
Test status
Simulation time 35545203 ps
CPU time 1.15 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 204440 kb
Host smart-7a331cc6-8b78-41cf-b576-cd01a93bd4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898051166 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_mem_rw_with_rand_reset.3898051166
Directory /workspace/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_csr_rw.229392723
Short name T29
Test name
Test status
Simulation time 56418675 ps
CPU time 0.93 seconds
Started Apr 27 01:46:35 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 204180 kb
Host smart-7f3122b8-f60b-4043-be2f-d665b1d3f07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229392723 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_csr_rw.229392723
Directory /workspace/11.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_intr_test.2193366161
Short name T192
Test name
Test status
Simulation time 38043084 ps
CPU time 0.72 seconds
Started Apr 27 01:46:24 PM PDT 24
Finished Apr 27 01:46:25 PM PDT 24
Peak memory 204124 kb
Host smart-2f8c6544-b955-4008-a944-39cb853cc843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193366161 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_intr_test.
2193366161
Directory /workspace/11.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_same_csr_outstanding.1336213690
Short name T197
Test name
Test status
Simulation time 187284648 ps
CPU time 2.27 seconds
Started Apr 27 01:46:26 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 204356 kb
Host smart-27d77d71-5753-4776-97b6-4a57df1bb787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336213690 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_dpe_same_csr_outstanding.1336213690
Directory /workspace/11.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors.1173789649
Short name T255
Test name
Test status
Simulation time 105991975 ps
CPU time 1.28 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 212956 kb
Host smart-61009d60-df85-4df7-b851-26daa21ef5b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173789649 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.key
mgr_dpe_shadow_reg_errors.1173789649
Directory /workspace/11.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_shadow_reg_errors_with_csr_rw.4235066462
Short name T291
Test name
Test status
Simulation time 226276381 ps
CPU time 2.71 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:40 PM PDT 24
Peak memory 212932 kb
Host smart-5b1863ca-4cde-4504-ae22-5af3eccb9917
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235066462 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.keymgr_dpe_shadow_reg_errors_with_csr_rw.4235066462
Directory /workspace/11.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_errors.1369354779
Short name T265
Test name
Test status
Simulation time 41007241 ps
CPU time 1.68 seconds
Started Apr 27 01:46:19 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 212580 kb
Host smart-464c6b19-23c4-4a0b-bc50-bf52aa346c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369354779 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_tl_errors.
1369354779
Directory /workspace/11.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_dpe_tl_intg_err.3001712012
Short name T57
Test name
Test status
Simulation time 340129016 ps
CPU time 3.56 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:41 PM PDT 24
Peak memory 212620 kb
Host smart-56a51ec1-c394-45f7-b9e3-2a5dce084c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001712012 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_dp
e_tl_intg_err.3001712012
Directory /workspace/11.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_mem_rw_with_rand_reset.3007010733
Short name T17
Test name
Test status
Simulation time 12583237 ps
CPU time 1.06 seconds
Started Apr 27 01:46:26 PM PDT 24
Finished Apr 27 01:46:27 PM PDT 24
Peak memory 204404 kb
Host smart-44f13d21-6513-4cd4-be4d-fd53dd76f7bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007010733 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_mem_rw_with_rand_reset.3007010733
Directory /workspace/12.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_csr_rw.3662650914
Short name T243
Test name
Test status
Simulation time 16094049 ps
CPU time 1.23 seconds
Started Apr 27 01:46:26 PM PDT 24
Finished Apr 27 01:46:28 PM PDT 24
Peak memory 204416 kb
Host smart-9a8cb837-67eb-4443-9e01-3d540cafb7f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662650914 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_csr_rw.
3662650914
Directory /workspace/12.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_intr_test.2854247032
Short name T281
Test name
Test status
Simulation time 9684196 ps
CPU time 0.81 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 204212 kb
Host smart-a5c842d4-ccf2-457d-b447-a65ae4eced91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854247032 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_intr_test.
2854247032
Directory /workspace/12.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_same_csr_outstanding.2140638953
Short name T91
Test name
Test status
Simulation time 30561269 ps
CPU time 1.39 seconds
Started Apr 27 01:46:27 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 204408 kb
Host smart-12760397-71c0-464a-84bf-173310714719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140638953 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_dpe_same_csr_outstanding.2140638953
Directory /workspace/12.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors.737679555
Short name T259
Test name
Test status
Simulation time 158194469 ps
CPU time 2.79 seconds
Started Apr 27 01:46:17 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 213048 kb
Host smart-4ec82637-6cbe-408d-b156-cda543d910c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737679555 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keym
gr_dpe_shadow_reg_errors.737679555
Directory /workspace/12.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1236604180
Short name T261
Test name
Test status
Simulation time 114192222 ps
CPU time 4.28 seconds
Started Apr 27 01:46:24 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 212916 kb
Host smart-d008b71d-4281-437b-a1fa-48121103df36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236604180 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.keymgr_dpe_shadow_reg_errors_with_csr_rw.1236604180
Directory /workspace/12.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_dpe_tl_errors.574721862
Short name T297
Test name
Test status
Simulation time 230480962 ps
CPU time 4.08 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 212524 kb
Host smart-bcf30f36-3fb4-4acb-999f-6b70d9455ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574721862 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_tl_errors.574721862
Directory /workspace/12.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_mem_rw_with_rand_reset.2564810557
Short name T268
Test name
Test status
Simulation time 16596402 ps
CPU time 1.25 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 204380 kb
Host smart-2fa4ba35-9adc-49d9-a89d-3658e862fba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564810557 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_mem_rw_with_rand_reset.2564810557
Directory /workspace/13.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_csr_rw.489608258
Short name T84
Test name
Test status
Simulation time 167710700 ps
CPU time 1.07 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 204136 kb
Host smart-38b8124b-a2ab-4421-9e2d-c30b4f1eef43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489608258 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_csr_rw.489608258
Directory /workspace/13.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_intr_test.626394615
Short name T122
Test name
Test status
Simulation time 22206539 ps
CPU time 0.71 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:30 PM PDT 24
Peak memory 204184 kb
Host smart-10bb50ce-c77a-4c47-96cd-9d55935be7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626394615 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_intr_test.626394615
Directory /workspace/13.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_same_csr_outstanding.1885029292
Short name T205
Test name
Test status
Simulation time 212382699 ps
CPU time 1.8 seconds
Started Apr 27 01:46:25 PM PDT 24
Finished Apr 27 01:46:27 PM PDT 24
Peak memory 204372 kb
Host smart-18919d03-a7b9-474f-b71b-0cc7a7a6a260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885029292 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_dpe_same_csr_outstanding.1885029292
Directory /workspace/13.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2740751574
Short name T272
Test name
Test status
Simulation time 811056529 ps
CPU time 5.25 seconds
Started Apr 27 01:46:24 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 212936 kb
Host smart-f04b79fb-cde9-4aee-bad2-977dbcb24e88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740751574 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.keymgr_dpe_shadow_reg_errors_with_csr_rw.2740751574
Directory /workspace/13.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_dpe_tl_errors.3764776243
Short name T232
Test name
Test status
Simulation time 44368881 ps
CPU time 2.43 seconds
Started Apr 27 01:46:39 PM PDT 24
Finished Apr 27 01:46:42 PM PDT 24
Peak memory 216088 kb
Host smart-fc09ccd6-73d8-4d06-a841-b1d7c7eda319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764776243 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_dpe_tl_errors.
3764776243
Directory /workspace/13.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_mem_rw_with_rand_reset.3666957512
Short name T239
Test name
Test status
Simulation time 43909596 ps
CPU time 1.27 seconds
Started Apr 27 01:46:38 PM PDT 24
Finished Apr 27 01:46:40 PM PDT 24
Peak memory 204408 kb
Host smart-5802bedb-2a82-4e61-94d6-c0f223e32714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666957512 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_mem_rw_with_rand_reset.3666957512
Directory /workspace/14.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_csr_rw.2159605019
Short name T222
Test name
Test status
Simulation time 48514733 ps
CPU time 1.47 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:20 PM PDT 24
Peak memory 204472 kb
Host smart-72830e6e-117f-44f9-a482-7e6dba0f30ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159605019 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_csr_rw.
2159605019
Directory /workspace/14.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_intr_test.3705399348
Short name T230
Test name
Test status
Simulation time 10228943 ps
CPU time 0.68 seconds
Started Apr 27 01:46:26 PM PDT 24
Finished Apr 27 01:46:27 PM PDT 24
Peak memory 204168 kb
Host smart-49661218-4268-45df-9191-2b0e49fb9b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705399348 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_intr_test.
3705399348
Directory /workspace/14.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_same_csr_outstanding.2332231564
Short name T263
Test name
Test status
Simulation time 92110184 ps
CPU time 1.77 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 204328 kb
Host smart-fcadcff9-2eca-4801-a980-c899959017d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332231564 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_dpe_same_csr_outstanding.2332231564
Directory /workspace/14.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2756738331
Short name T90
Test name
Test status
Simulation time 151665044 ps
CPU time 5.29 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:38 PM PDT 24
Peak memory 212996 kb
Host smart-a0e5b103-7dba-4c6a-a11c-d1c6379187c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756738331 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.keymgr_dpe_shadow_reg_errors_with_csr_rw.2756738331
Directory /workspace/14.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_errors.2142663286
Short name T48
Test name
Test status
Simulation time 779300512 ps
CPU time 6.21 seconds
Started Apr 27 01:46:27 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 215848 kb
Host smart-513a98db-15a7-40e5-82fc-64fc03ae53da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142663286 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_tl_errors.
2142663286
Directory /workspace/14.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_dpe_tl_intg_err.1594891861
Short name T46
Test name
Test status
Simulation time 165670613 ps
CPU time 3.29 seconds
Started Apr 27 01:46:37 PM PDT 24
Finished Apr 27 01:46:41 PM PDT 24
Peak memory 204340 kb
Host smart-ab1c1eeb-11e5-4982-9a1c-9e4338e1704e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594891861 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_dp
e_tl_intg_err.1594891861
Directory /workspace/14.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_mem_rw_with_rand_reset.85494789
Short name T99
Test name
Test status
Simulation time 48326514 ps
CPU time 1.05 seconds
Started Apr 27 01:46:27 PM PDT 24
Finished Apr 27 01:46:28 PM PDT 24
Peak memory 212492 kb
Host smart-aaea3e12-6e26-4c0d-94a6-01529fcfa5d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85494789 -assert nopostproc +UVM_TESTNAME=k
eymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_mem_rw_with_rand_reset.85494789
Directory /workspace/15.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_csr_rw.3444769000
Short name T256
Test name
Test status
Simulation time 45799218 ps
CPU time 1.19 seconds
Started Apr 27 01:46:27 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 204368 kb
Host smart-460bc73d-f86b-4852-ae40-4edd25ced4a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444769000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_csr_rw.
3444769000
Directory /workspace/15.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_same_csr_outstanding.372582094
Short name T70
Test name
Test status
Simulation time 76990161 ps
CPU time 1.24 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 204340 kb
Host smart-620280f2-ff15-470b-8b15-f023f6098cda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372582094 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_dpe_same_csr_outstanding.372582094
Directory /workspace/15.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors.1971281981
Short name T301
Test name
Test status
Simulation time 50835152 ps
CPU time 1.59 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 213072 kb
Host smart-d83abb5c-ec8d-43a5-9652-9e75e2df19a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971281981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.key
mgr_dpe_shadow_reg_errors.1971281981
Directory /workspace/15.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3003208388
Short name T271
Test name
Test status
Simulation time 433554923 ps
CPU time 3.28 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:33 PM PDT 24
Peak memory 212952 kb
Host smart-4d69da92-196e-4a05-86a7-fccfc1c0492d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003208388 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.keymgr_dpe_shadow_reg_errors_with_csr_rw.3003208388
Directory /workspace/15.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_dpe_tl_errors.2592937153
Short name T35
Test name
Test status
Simulation time 55083225 ps
CPU time 1.63 seconds
Started Apr 27 01:46:37 PM PDT 24
Finished Apr 27 01:46:39 PM PDT 24
Peak memory 214300 kb
Host smart-ec6dc34a-afc0-4cdd-ba6f-eba65b966250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592937153 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_tl_errors.
2592937153
Directory /workspace/15.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_mem_rw_with_rand_reset.475397336
Short name T66
Test name
Test status
Simulation time 46920817 ps
CPU time 1.3 seconds
Started Apr 27 01:46:39 PM PDT 24
Finished Apr 27 01:46:40 PM PDT 24
Peak memory 220848 kb
Host smart-b137ecaf-e77f-4807-b360-c8a3f5cf61c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475397336 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_mem_rw_with_rand_reset.475397336
Directory /workspace/16.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_csr_rw.2346382129
Short name T218
Test name
Test status
Simulation time 20546516 ps
CPU time 1.01 seconds
Started Apr 27 01:46:39 PM PDT 24
Finished Apr 27 01:46:40 PM PDT 24
Peak memory 204272 kb
Host smart-2ce4df06-5764-4d2b-8937-7a25bac69370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346382129 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_csr_rw.
2346382129
Directory /workspace/16.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_intr_test.400687833
Short name T287
Test name
Test status
Simulation time 27825371 ps
CPU time 0.73 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:20 PM PDT 24
Peak memory 204272 kb
Host smart-83f10516-608d-4e38-87e9-2fad88c6d0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400687833 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_intr_test.400687833
Directory /workspace/16.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_same_csr_outstanding.908373120
Short name T200
Test name
Test status
Simulation time 56360673 ps
CPU time 2 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 204464 kb
Host smart-6ba6fb24-6ce9-4c3f-a06a-db84fee32abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908373120 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.k
eymgr_dpe_same_csr_outstanding.908373120
Directory /workspace/16.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors.1670923277
Short name T207
Test name
Test status
Simulation time 254204753 ps
CPU time 2.1 seconds
Started Apr 27 01:46:21 PM PDT 24
Finished Apr 27 01:46:23 PM PDT 24
Peak memory 212908 kb
Host smart-e3adc1f6-965a-43a2-b04a-d970aab45cf4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670923277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.key
mgr_dpe_shadow_reg_errors.1670923277
Directory /workspace/16.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3577444611
Short name T206
Test name
Test status
Simulation time 294003731 ps
CPU time 6.06 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 218504 kb
Host smart-8b63f20c-8c55-431f-8c2a-38cafb08cfc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577444611 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.keymgr_dpe_shadow_reg_errors_with_csr_rw.3577444611
Directory /workspace/16.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_errors.3144516372
Short name T34
Test name
Test status
Simulation time 702550608 ps
CPU time 3.58 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:33 PM PDT 24
Peak memory 220640 kb
Host smart-a001c17b-222d-471d-82f2-680b75a48737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144516372 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_tl_errors.
3144516372
Directory /workspace/16.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_dpe_tl_intg_err.3694657306
Short name T56
Test name
Test status
Simulation time 290091925 ps
CPU time 3.81 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 212612 kb
Host smart-dc33605e-194d-430e-b708-9be5b2846cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694657306 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_dp
e_tl_intg_err.3694657306
Directory /workspace/16.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_mem_rw_with_rand_reset.3486466994
Short name T68
Test name
Test status
Simulation time 20042890 ps
CPU time 1.44 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 212660 kb
Host smart-a05b6185-ec70-4456-af65-a6c1b0ad5c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486466994 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_mem_rw_with_rand_reset.3486466994
Directory /workspace/17.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_csr_rw.2822881624
Short name T30
Test name
Test status
Simulation time 24697672 ps
CPU time 0.9 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 204256 kb
Host smart-d5a30e76-19a8-4485-9750-c996c91f230c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822881624 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_csr_rw.
2822881624
Directory /workspace/17.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_intr_test.1048194405
Short name T285
Test name
Test status
Simulation time 43525489 ps
CPU time 0.74 seconds
Started Apr 27 01:46:31 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 204276 kb
Host smart-0047b638-8c33-4cc4-bd79-b5f5f7c59569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048194405 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_intr_test.
1048194405
Directory /workspace/17.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_same_csr_outstanding.525525772
Short name T81
Test name
Test status
Simulation time 92529979 ps
CPU time 3.34 seconds
Started Apr 27 01:46:31 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 212572 kb
Host smart-5fbee6e4-0926-44c7-90c0-cfc9152dc42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525525772 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_dpe_same_csr_outstanding.525525772
Directory /workspace/17.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors.1834099696
Short name T296
Test name
Test status
Simulation time 44207531 ps
CPU time 1.83 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 212920 kb
Host smart-63c05b61-e891-4443-a6d7-8a08dbadfced
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834099696 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.key
mgr_dpe_shadow_reg_errors.1834099696
Directory /workspace/17.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_shadow_reg_errors_with_csr_rw.4085242260
Short name T228
Test name
Test status
Simulation time 254137518 ps
CPU time 5.41 seconds
Started Apr 27 01:46:43 PM PDT 24
Finished Apr 27 01:46:49 PM PDT 24
Peak memory 213016 kb
Host smart-83b8bfd7-92f0-4f9a-bc65-b78c49e88d79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085242260 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.keymgr_dpe_shadow_reg_errors_with_csr_rw.4085242260
Directory /workspace/17.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_dpe_tl_errors.176703787
Short name T304
Test name
Test status
Simulation time 132944047 ps
CPU time 3.17 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 212736 kb
Host smart-c558d0aa-5d95-47d3-a932-39cd803baa02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176703787 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_tl_errors.176703787
Directory /workspace/17.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_mem_rw_with_rand_reset.683806103
Short name T50
Test name
Test status
Simulation time 44131698 ps
CPU time 1.33 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 212584 kb
Host smart-5389fc5d-0130-456b-839d-86ba7306fda2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683806103 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_mem_rw_with_rand_reset.683806103
Directory /workspace/18.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_csr_rw.3947181277
Short name T277
Test name
Test status
Simulation time 36259640 ps
CPU time 1.34 seconds
Started Apr 27 01:46:27 PM PDT 24
Finished Apr 27 01:46:29 PM PDT 24
Peak memory 204356 kb
Host smart-b94d5135-cb4e-4c20-9c97-84847398a9bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947181277 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_csr_rw.
3947181277
Directory /workspace/18.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_intr_test.997134747
Short name T203
Test name
Test status
Simulation time 70947028 ps
CPU time 0.75 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:30 PM PDT 24
Peak memory 204244 kb
Host smart-98cc395c-3bda-4b8b-a6e1-eee68e19569c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997134747 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_intr_test.997134747
Directory /workspace/18.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_same_csr_outstanding.2166342446
Short name T257
Test name
Test status
Simulation time 71906502 ps
CPU time 1.17 seconds
Started Apr 27 01:46:43 PM PDT 24
Finished Apr 27 01:46:44 PM PDT 24
Peak memory 204424 kb
Host smart-50359b0e-3827-491a-8da5-0b55b4b902fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166342446 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_dpe_same_csr_outstanding.2166342446
Directory /workspace/18.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors.3311998430
Short name T233
Test name
Test status
Simulation time 376128349 ps
CPU time 1.71 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 212948 kb
Host smart-8db33d42-f113-4045-a8d8-c42bc391cc7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311998430 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.key
mgr_dpe_shadow_reg_errors.3311998430
Directory /workspace/18.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_shadow_reg_errors_with_csr_rw.395830648
Short name T64
Test name
Test status
Simulation time 53979570 ps
CPU time 2.52 seconds
Started Apr 27 01:46:44 PM PDT 24
Finished Apr 27 01:46:47 PM PDT 24
Peak memory 218080 kb
Host smart-eabf2ed9-a168-40a6-a620-931aa18e191b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395830648 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.keymgr_dpe_shadow_reg_errors_with_csr_rw.395830648
Directory /workspace/18.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_dpe_tl_intg_err.3047516319
Short name T54
Test name
Test status
Simulation time 108931165 ps
CPU time 4.02 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 213528 kb
Host smart-20dd20a3-57a4-4c77-a1ee-f3918aa1786f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047516319 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_dp
e_tl_intg_err.3047516319
Directory /workspace/18.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_csr_rw.196329254
Short name T235
Test name
Test status
Simulation time 84560493 ps
CPU time 1.47 seconds
Started Apr 27 01:46:53 PM PDT 24
Finished Apr 27 01:46:55 PM PDT 24
Peak memory 204420 kb
Host smart-5dab95d7-6688-48c7-898a-beaddd7bb41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196329254 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_csr_rw.196329254
Directory /workspace/19.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_intr_test.4162552150
Short name T202
Test name
Test status
Simulation time 49368975 ps
CPU time 0.7 seconds
Started Apr 27 01:46:36 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 204200 kb
Host smart-b71fed0c-e132-4837-ad46-a124c6373383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162552150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_intr_test.
4162552150
Directory /workspace/19.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_same_csr_outstanding.2346982981
Short name T250
Test name
Test status
Simulation time 46894018 ps
CPU time 1.46 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:34 PM PDT 24
Peak memory 204308 kb
Host smart-01768e80-b58a-42ba-9911-5d47e8f8a44c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346982981 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_dpe_same_csr_outstanding.2346982981
Directory /workspace/19.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors.2409632344
Short name T266
Test name
Test status
Simulation time 200441031 ps
CPU time 4.72 seconds
Started Apr 27 01:46:55 PM PDT 24
Finished Apr 27 01:47:01 PM PDT 24
Peak memory 212956 kb
Host smart-740cd4b7-d3cd-4d2c-a804-2a4221da35fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409632344 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.key
mgr_dpe_shadow_reg_errors.2409632344
Directory /workspace/19.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_shadow_reg_errors_with_csr_rw.791134426
Short name T269
Test name
Test status
Simulation time 273956536 ps
CPU time 9.17 seconds
Started Apr 27 01:46:36 PM PDT 24
Finished Apr 27 01:46:45 PM PDT 24
Peak memory 212832 kb
Host smart-07fb459a-1a5f-4d71-83cf-b2fb6545f81a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791134426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.keymgr_dpe_shadow_reg_errors_with_csr_rw.791134426
Directory /workspace/19.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_errors.3834209646
Short name T252
Test name
Test status
Simulation time 312785747 ps
CPU time 3.94 seconds
Started Apr 27 01:46:31 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 212592 kb
Host smart-06185063-a964-4e58-aade-bfe7c592717e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834209646 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_tl_errors.
3834209646
Directory /workspace/19.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_dpe_tl_intg_err.1235848796
Short name T52
Test name
Test status
Simulation time 97127741 ps
CPU time 3.56 seconds
Started Apr 27 01:46:34 PM PDT 24
Finished Apr 27 01:46:38 PM PDT 24
Peak memory 212640 kb
Host smart-c99fc7a9-184f-4371-bbb2-11d61f57c4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235848796 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_dp
e_tl_intg_err.1235848796
Directory /workspace/19.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_aliasing.3193530426
Short name T184
Test name
Test status
Simulation time 527714419 ps
CPU time 5.96 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 204348 kb
Host smart-3ed611a6-5c37-4ed1-a55d-5706b6d0fd3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193530426 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_aliasing.3193530426
Directory /workspace/2.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_bit_bash.3997565169
Short name T293
Test name
Test status
Simulation time 341398816 ps
CPU time 10.53 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:24 PM PDT 24
Peak memory 204404 kb
Host smart-12cfd736-ab45-49a7-a911-336998eab3b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997565169 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_bit_bash.3997565169
Directory /workspace/2.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_hw_reset.2177897106
Short name T254
Test name
Test status
Simulation time 58332288 ps
CPU time 1.4 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 204336 kb
Host smart-34ed5bfd-4c29-4843-984f-d122c02d96ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177897106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_cs
r_hw_reset.2177897106
Directory /workspace/2.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_mem_rw_with_rand_reset.2036994235
Short name T246
Test name
Test status
Simulation time 27769308 ps
CPU time 1.28 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 212772 kb
Host smart-aeac557e-0e2c-48a6-80a4-07d2f191a82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036994235 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_mem_rw_with_rand_reset.2036994235
Directory /workspace/2.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_csr_rw.3952027683
Short name T223
Test name
Test status
Simulation time 13745124 ps
CPU time 0.95 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:12 PM PDT 24
Peak memory 204428 kb
Host smart-c083898e-dab6-4039-b6f2-9c35a0c7b311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952027683 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_csr_rw.3
952027683
Directory /workspace/2.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_intr_test.188304614
Short name T195
Test name
Test status
Simulation time 18011887 ps
CPU time 0.68 seconds
Started Apr 27 01:46:07 PM PDT 24
Finished Apr 27 01:46:08 PM PDT 24
Peak memory 204204 kb
Host smart-14f75a2e-e3ac-429b-91d7-7a5fd2392c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188304614 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_intr_test.188304614
Directory /workspace/2.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_same_csr_outstanding.3577976801
Short name T215
Test name
Test status
Simulation time 254107791 ps
CPU time 1.94 seconds
Started Apr 27 01:46:20 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 204316 kb
Host smart-76154e64-c503-4a44-b506-a93bc2181a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577976801 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_dpe_same_csr_outstanding.3577976801
Directory /workspace/2.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors.33807743
Short name T185
Test name
Test status
Simulation time 113354355 ps
CPU time 2.26 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 212992 kb
Host smart-5b49509e-2287-4121-990e-f0731fffbe5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33807743 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keym
gr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr
_dpe_shadow_reg_errors.33807743
Directory /workspace/2.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4060735825
Short name T300
Test name
Test status
Simulation time 85695962 ps
CPU time 3.68 seconds
Started Apr 27 01:46:07 PM PDT 24
Finished Apr 27 01:46:12 PM PDT 24
Peak memory 212988 kb
Host smart-f2224247-935f-4775-9994-d6aa7fe8cab6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060735825 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.keymgr_dpe_shadow_reg_errors_with_csr_rw.4060735825
Directory /workspace/2.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_dpe_tl_errors.97300860
Short name T299
Test name
Test status
Simulation time 28570089 ps
CPU time 1.9 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 215024 kb
Host smart-a6142f0b-37af-4727-be29-ab18645b11b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300860 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_tl_errors.97300860
Directory /workspace/2.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_dpe_intr_test.1226085443
Short name T213
Test name
Test status
Simulation time 19522277 ps
CPU time 0.98 seconds
Started Apr 27 01:46:40 PM PDT 24
Finished Apr 27 01:46:42 PM PDT 24
Peak memory 204344 kb
Host smart-753d3874-dbec-4986-abf3-a09591186102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226085443 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_intr_test.
1226085443
Directory /workspace/20.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_dpe_intr_test.2921508106
Short name T279
Test name
Test status
Simulation time 96464372 ps
CPU time 0.72 seconds
Started Apr 27 01:46:38 PM PDT 24
Finished Apr 27 01:46:39 PM PDT 24
Peak memory 204200 kb
Host smart-497ffa40-d729-4d6e-beb7-eb06f0c0e604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921508106 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_intr_test.
2921508106
Directory /workspace/21.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_dpe_intr_test.3451844727
Short name T283
Test name
Test status
Simulation time 26758651 ps
CPU time 0.71 seconds
Started Apr 27 01:46:35 PM PDT 24
Finished Apr 27 01:46:36 PM PDT 24
Peak memory 204256 kb
Host smart-397a17b7-81c9-4a51-8aed-1738430f624f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451844727 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_intr_test.
3451844727
Directory /workspace/22.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_dpe_intr_test.932854750
Short name T198
Test name
Test status
Simulation time 73242368 ps
CPU time 0.73 seconds
Started Apr 27 01:46:46 PM PDT 24
Finished Apr 27 01:46:47 PM PDT 24
Peak memory 204236 kb
Host smart-54889653-302d-4602-bd36-abf8e38ba0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932854750 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_intr_test.932854750
Directory /workspace/23.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_dpe_intr_test.379671123
Short name T219
Test name
Test status
Simulation time 14828771 ps
CPU time 0.72 seconds
Started Apr 27 01:46:47 PM PDT 24
Finished Apr 27 01:46:48 PM PDT 24
Peak memory 204220 kb
Host smart-a427998d-be46-4f9e-b45e-28d55e221865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379671123 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_intr_test.379671123
Directory /workspace/24.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_dpe_intr_test.1252636558
Short name T121
Test name
Test status
Simulation time 20613378 ps
CPU time 0.83 seconds
Started Apr 27 01:46:37 PM PDT 24
Finished Apr 27 01:46:39 PM PDT 24
Peak memory 204308 kb
Host smart-7db80e22-ea5f-4b4d-b4ca-8945179ddee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252636558 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_intr_test.
1252636558
Directory /workspace/25.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_dpe_intr_test.705570562
Short name T214
Test name
Test status
Simulation time 9942992 ps
CPU time 0.7 seconds
Started Apr 27 01:46:38 PM PDT 24
Finished Apr 27 01:46:39 PM PDT 24
Peak memory 204264 kb
Host smart-8b75a29f-3699-4d46-a94e-114a9c3a6101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705570562 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_intr_test.705570562
Directory /workspace/26.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_dpe_intr_test.855771644
Short name T278
Test name
Test status
Simulation time 26002693 ps
CPU time 0.69 seconds
Started Apr 27 01:46:43 PM PDT 24
Finished Apr 27 01:46:49 PM PDT 24
Peak memory 204308 kb
Host smart-22b16687-6d01-4850-aa9b-3fb37a7c8c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855771644 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_intr_test.855771644
Directory /workspace/27.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_dpe_intr_test.1263910892
Short name T253
Test name
Test status
Simulation time 55876741 ps
CPU time 0.89 seconds
Started Apr 27 01:46:42 PM PDT 24
Finished Apr 27 01:46:43 PM PDT 24
Peak memory 204372 kb
Host smart-5be6349c-f2cb-4274-ac20-3ac78eba4574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263910892 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_intr_test.
1263910892
Directory /workspace/28.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_dpe_intr_test.2134113003
Short name T193
Test name
Test status
Simulation time 16178515 ps
CPU time 0.79 seconds
Started Apr 27 01:46:35 PM PDT 24
Finished Apr 27 01:46:36 PM PDT 24
Peak memory 204184 kb
Host smart-0ec139da-0118-471c-a60a-04e599111d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134113003 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_intr_test.
2134113003
Directory /workspace/29.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_aliasing.1182907888
Short name T294
Test name
Test status
Simulation time 88985628 ps
CPU time 2.49 seconds
Started Apr 27 01:46:17 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 204444 kb
Host smart-323bf247-f5f5-48b8-a2e2-52a6ac719b48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182907888 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_aliasing.1182907888
Directory /workspace/3.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_bit_bash.1411579237
Short name T83
Test name
Test status
Simulation time 845277025 ps
CPU time 6.31 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 204384 kb
Host smart-04c6b622-8426-43d0-b6fb-cd8dc5e6ba8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411579237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_cs
r_bit_bash.1411579237
Directory /workspace/3.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_hw_reset.17188111
Short name T199
Test name
Test status
Simulation time 65212350 ps
CPU time 1.01 seconds
Started Apr 27 01:46:22 PM PDT 24
Finished Apr 27 01:46:23 PM PDT 24
Peak memory 204184 kb
Host smart-2a24183b-5716-4ae0-94c9-a7252643f21a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17188111 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_
hw_reset.17188111
Directory /workspace/3.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_mem_rw_with_rand_reset.1383376623
Short name T180
Test name
Test status
Simulation time 336564970 ps
CPU time 1.09 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:12 PM PDT 24
Peak memory 212680 kb
Host smart-98315cff-e8d8-4f98-87c7-64560afb001b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383376623 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_mem_rw_with_rand_reset.1383376623
Directory /workspace/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_csr_rw.4017560156
Short name T88
Test name
Test status
Simulation time 79605722 ps
CPU time 0.99 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 204216 kb
Host smart-6b47b415-ace5-4b07-9494-17a075badb03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017560156 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_csr_rw.4
017560156
Directory /workspace/3.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_intr_test.2839935965
Short name T275
Test name
Test status
Simulation time 8495628 ps
CPU time 0.78 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 204248 kb
Host smart-d7d42625-e5f9-4bb5-af55-7ea754438c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839935965 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_intr_test.2
839935965
Directory /workspace/3.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_same_csr_outstanding.3590954386
Short name T289
Test name
Test status
Simulation time 62356759 ps
CPU time 1.54 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 204428 kb
Host smart-d90c48a7-46ca-485b-a3f5-4c99678a8bc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590954386 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_dpe_same_csr_outstanding.3590954386
Directory /workspace/3.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors.3323618651
Short name T309
Test name
Test status
Simulation time 228089934 ps
CPU time 1.69 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:33 PM PDT 24
Peak memory 213032 kb
Host smart-0d1b1096-f07e-4af5-8def-deeab5f61425
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323618651 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keym
gr_dpe_shadow_reg_errors.3323618651
Directory /workspace/3.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1885429939
Short name T305
Test name
Test status
Simulation time 900235575 ps
CPU time 9.19 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:20 PM PDT 24
Peak memory 212936 kb
Host smart-4e28e090-8906-4cb0-bd22-7691b017da56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885429939 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.keymgr_dpe_shadow_reg_errors_with_csr_rw.1885429939
Directory /workspace/3.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_errors.1156450622
Short name T40
Test name
Test status
Simulation time 193476093 ps
CPU time 2.51 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 220796 kb
Host smart-1660aba2-d7fc-431f-b6bc-e9609082303f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156450622 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_tl_errors.1
156450622
Directory /workspace/3.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_dpe_tl_intg_err.3597502986
Short name T42
Test name
Test status
Simulation time 186200031 ps
CPU time 4.64 seconds
Started Apr 27 01:46:16 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 212692 kb
Host smart-3b561447-0cff-47f6-946e-891c6a2a33f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597502986 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe
_tl_intg_err.3597502986
Directory /workspace/3.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_dpe_intr_test.1496731665
Short name T201
Test name
Test status
Simulation time 27291097 ps
CPU time 0.74 seconds
Started Apr 27 01:46:35 PM PDT 24
Finished Apr 27 01:46:37 PM PDT 24
Peak memory 204204 kb
Host smart-0181f540-d5cd-4c8e-b26a-8139c2d96f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496731665 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_intr_test.
1496731665
Directory /workspace/30.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_dpe_intr_test.2193331812
Short name T183
Test name
Test status
Simulation time 18255413 ps
CPU time 0.76 seconds
Started Apr 27 01:46:50 PM PDT 24
Finished Apr 27 01:46:52 PM PDT 24
Peak memory 204316 kb
Host smart-76317140-1ff7-48f5-986d-23adb355c274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193331812 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_intr_test.
2193331812
Directory /workspace/31.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_dpe_intr_test.2870771010
Short name T181
Test name
Test status
Simulation time 48520122 ps
CPU time 0.76 seconds
Started Apr 27 01:46:40 PM PDT 24
Finished Apr 27 01:46:42 PM PDT 24
Peak memory 204296 kb
Host smart-86d0175c-34b6-48d2-b627-7b63fb431f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870771010 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_intr_test.
2870771010
Directory /workspace/32.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_dpe_intr_test.2201833209
Short name T240
Test name
Test status
Simulation time 9847178 ps
CPU time 0.81 seconds
Started Apr 27 01:46:40 PM PDT 24
Finished Apr 27 01:46:41 PM PDT 24
Peak memory 204272 kb
Host smart-790e1db8-bb95-47ab-bcac-787505d700a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201833209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_intr_test.
2201833209
Directory /workspace/33.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_dpe_intr_test.2651447470
Short name T36
Test name
Test status
Simulation time 32520264 ps
CPU time 0.7 seconds
Started Apr 27 01:46:37 PM PDT 24
Finished Apr 27 01:46:39 PM PDT 24
Peak memory 204264 kb
Host smart-4678865b-caca-4d38-bca3-a66a76a372eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651447470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_intr_test.
2651447470
Directory /workspace/34.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_dpe_intr_test.3567917310
Short name T308
Test name
Test status
Simulation time 43727636 ps
CPU time 0.68 seconds
Started Apr 27 01:46:49 PM PDT 24
Finished Apr 27 01:46:50 PM PDT 24
Peak memory 204208 kb
Host smart-72207dbb-20f8-43cd-a324-80da3f5983bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567917310 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_intr_test.
3567917310
Directory /workspace/35.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_dpe_intr_test.3640909626
Short name T87
Test name
Test status
Simulation time 13992528 ps
CPU time 0.69 seconds
Started Apr 27 01:46:47 PM PDT 24
Finished Apr 27 01:46:49 PM PDT 24
Peak memory 204184 kb
Host smart-f95e2456-0d28-4700-9ff5-1bbae97e8cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640909626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_intr_test.
3640909626
Directory /workspace/36.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_dpe_intr_test.2517126985
Short name T210
Test name
Test status
Simulation time 134926303 ps
CPU time 0.8 seconds
Started Apr 27 01:47:02 PM PDT 24
Finished Apr 27 01:47:04 PM PDT 24
Peak memory 204292 kb
Host smart-963ddc41-7386-460d-b252-fec57a10c1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517126985 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_intr_test.
2517126985
Directory /workspace/38.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_dpe_intr_test.2467066623
Short name T247
Test name
Test status
Simulation time 10566206 ps
CPU time 0.81 seconds
Started Apr 27 01:46:37 PM PDT 24
Finished Apr 27 01:46:38 PM PDT 24
Peak memory 204228 kb
Host smart-a7e918c5-4b50-4cae-8c36-64bb61030a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467066623 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_intr_test.
2467066623
Directory /workspace/39.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_aliasing.1756724343
Short name T286
Test name
Test status
Simulation time 318450093 ps
CPU time 5.55 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204404 kb
Host smart-8910695f-de07-44b9-b755-cf630c56cabd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756724343 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_aliasing.1756724343
Directory /workspace/4.keymgr_dpe_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_bit_bash.199162085
Short name T211
Test name
Test status
Simulation time 624367075 ps
CPU time 10.98 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:25 PM PDT 24
Peak memory 204424 kb
Host smart-9058b359-8eb4-44af-b961-fc763c58adcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199162085 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr
_bit_bash.199162085
Directory /workspace/4.keymgr_dpe_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_hw_reset.3187249344
Short name T264
Test name
Test status
Simulation time 17996612 ps
CPU time 0.86 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 204280 kb
Host smart-682ffc1f-5604-4b75-8748-926f47193f86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187249344 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_cs
r_hw_reset.3187249344
Directory /workspace/4.keymgr_dpe_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_mem_rw_with_rand_reset.4272338239
Short name T190
Test name
Test status
Simulation time 38735857 ps
CPU time 0.89 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 204260 kb
Host smart-18a919c6-6179-4389-8521-91eab4051da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272338239 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_mem_rw_with_rand_reset.4272338239
Directory /workspace/4.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_csr_rw.3234380596
Short name T267
Test name
Test status
Simulation time 13589921 ps
CPU time 1.12 seconds
Started Apr 27 01:46:08 PM PDT 24
Finished Apr 27 01:46:10 PM PDT 24
Peak memory 204392 kb
Host smart-a925d2ae-a900-4559-af82-03ec74031d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234380596 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_csr_rw.3
234380596
Directory /workspace/4.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_intr_test.1493906733
Short name T86
Test name
Test status
Simulation time 51507166 ps
CPU time 0.79 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 204296 kb
Host smart-b0388647-1188-44ae-9451-e4128a4b5209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493906733 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_intr_test.1
493906733
Directory /workspace/4.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_same_csr_outstanding.3681172826
Short name T248
Test name
Test status
Simulation time 44842234 ps
CPU time 1.39 seconds
Started Apr 27 01:46:20 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 204324 kb
Host smart-38cae825-88ee-4f95-a5bc-23aeb1846ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681172826 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_dpe_same_csr_outstanding.3681172826
Directory /workspace/4.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors.913049518
Short name T186
Test name
Test status
Simulation time 92678692 ps
CPU time 2.01 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 212988 kb
Host smart-9d77931e-a294-4efd-9a0e-3ebc2b562d11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913049518 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=key
mgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymg
r_dpe_shadow_reg_errors.913049518
Directory /workspace/4.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_shadow_reg_errors_with_csr_rw.313601112
Short name T103
Test name
Test status
Simulation time 926194518 ps
CPU time 8.01 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:24 PM PDT 24
Peak memory 212888 kb
Host smart-39287dbc-69cb-4b45-a4e1-4678d759f77b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313601112 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.keymgr_dpe_shadow_reg_errors_with_csr_rw.313601112
Directory /workspace/4.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_dpe_tl_errors.1019511686
Short name T273
Test name
Test status
Simulation time 1039768769 ps
CPU time 2.5 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 212576 kb
Host smart-0e0231c9-754c-4dc3-9a95-0de84cfc4715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019511686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_tl_errors.1
019511686
Directory /workspace/4.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_dpe_intr_test.955216190
Short name T258
Test name
Test status
Simulation time 7467368 ps
CPU time 0.67 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:33 PM PDT 24
Peak memory 204260 kb
Host smart-a460b4ef-4ee9-4a8b-98ef-90c569377d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955216190 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_intr_test.955216190
Directory /workspace/40.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_dpe_intr_test.1347474740
Short name T187
Test name
Test status
Simulation time 22141850 ps
CPU time 0.73 seconds
Started Apr 27 01:46:47 PM PDT 24
Finished Apr 27 01:46:48 PM PDT 24
Peak memory 204212 kb
Host smart-1e6dd80f-1b6f-480a-a1c3-735ec00003d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347474740 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_intr_test.
1347474740
Directory /workspace/41.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_dpe_intr_test.3839851121
Short name T229
Test name
Test status
Simulation time 25573717 ps
CPU time 0.72 seconds
Started Apr 27 01:46:43 PM PDT 24
Finished Apr 27 01:46:44 PM PDT 24
Peak memory 204224 kb
Host smart-33f18230-2a6d-453f-8fee-e1ec6090abfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839851121 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_intr_test.
3839851121
Directory /workspace/42.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_dpe_intr_test.2839596295
Short name T236
Test name
Test status
Simulation time 35628072 ps
CPU time 0.71 seconds
Started Apr 27 01:46:35 PM PDT 24
Finished Apr 27 01:46:36 PM PDT 24
Peak memory 204232 kb
Host smart-1499df03-e88e-4fb2-805b-463fb57d9269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839596295 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_intr_test.
2839596295
Directory /workspace/43.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_dpe_intr_test.143201173
Short name T123
Test name
Test status
Simulation time 11854903 ps
CPU time 0.72 seconds
Started Apr 27 01:46:59 PM PDT 24
Finished Apr 27 01:47:01 PM PDT 24
Peak memory 204264 kb
Host smart-d88f645b-b11f-499e-be77-f7d55be52924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143201173 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_intr_test.143201173
Directory /workspace/44.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_dpe_intr_test.3427626486
Short name T280
Test name
Test status
Simulation time 30133783 ps
CPU time 0.68 seconds
Started Apr 27 01:46:54 PM PDT 24
Finished Apr 27 01:46:56 PM PDT 24
Peak memory 204196 kb
Host smart-8e38459e-70c9-42a9-a933-15de72a87fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427626486 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_intr_test.
3427626486
Directory /workspace/45.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_dpe_intr_test.1645255798
Short name T204
Test name
Test status
Simulation time 30812920 ps
CPU time 0.73 seconds
Started Apr 27 01:46:57 PM PDT 24
Finished Apr 27 01:46:59 PM PDT 24
Peak memory 204200 kb
Host smart-f1af2241-de72-46f1-be5d-8325fef1a338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645255798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_intr_test.
1645255798
Directory /workspace/46.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_dpe_intr_test.3431122652
Short name T178
Test name
Test status
Simulation time 13113291 ps
CPU time 0.7 seconds
Started Apr 27 01:47:01 PM PDT 24
Finished Apr 27 01:47:02 PM PDT 24
Peak memory 204212 kb
Host smart-689ef5e9-da5a-4a04-b365-0587d34d3b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431122652 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_intr_test.
3431122652
Directory /workspace/47.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_dpe_intr_test.400939304
Short name T38
Test name
Test status
Simulation time 45740179 ps
CPU time 0.74 seconds
Started Apr 27 01:46:56 PM PDT 24
Finished Apr 27 01:46:58 PM PDT 24
Peak memory 204280 kb
Host smart-8e9709c5-eb46-4e8e-8429-2f55627f9474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400939304 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_intr_test.400939304
Directory /workspace/48.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_dpe_intr_test.3567121109
Short name T220
Test name
Test status
Simulation time 35756280 ps
CPU time 0.74 seconds
Started Apr 27 01:46:47 PM PDT 24
Finished Apr 27 01:46:48 PM PDT 24
Peak memory 204248 kb
Host smart-fa561861-2390-4240-ba1a-cab684add0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567121109 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_intr_test.
3567121109
Directory /workspace/49.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_mem_rw_with_rand_reset.230639082
Short name T292
Test name
Test status
Simulation time 34698577 ps
CPU time 0.98 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 204196 kb
Host smart-ed9dc3cf-9c5d-4a93-9b98-b00b90662ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230639082 -assert nopostproc +UVM_TESTNAME=
keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_mem_rw_with_rand_reset.230639082
Directory /workspace/5.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_csr_rw.3816104172
Short name T237
Test name
Test status
Simulation time 22023581 ps
CPU time 0.86 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:15 PM PDT 24
Peak memory 204296 kb
Host smart-44568da0-5f1b-4f18-a098-25bc5dba0956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816104172 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_csr_rw.3
816104172
Directory /workspace/5.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_intr_test.1682977234
Short name T282
Test name
Test status
Simulation time 11482541 ps
CPU time 0.84 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 204204 kb
Host smart-b9d2e74b-8d9e-4920-836e-a665d84a6230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682977234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_intr_test.1
682977234
Directory /workspace/5.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_same_csr_outstanding.111258890
Short name T104
Test name
Test status
Simulation time 91330656 ps
CPU time 2.37 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204416 kb
Host smart-5d49e7ca-1a18-4532-8a97-0ac3737e8376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111258890 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_dpe_same_csr_outstanding.111258890
Directory /workspace/5.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors.2635145992
Short name T65
Test name
Test status
Simulation time 230903547 ps
CPU time 2.17 seconds
Started Apr 27 01:46:18 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 212960 kb
Host smart-03629736-5b8c-488d-be1f-7af6cc9d5dc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635145992 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keym
gr_dpe_shadow_reg_errors.2635145992
Directory /workspace/5.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_shadow_reg_errors_with_csr_rw.505534283
Short name T284
Test name
Test status
Simulation time 406497103 ps
CPU time 7.67 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:24 PM PDT 24
Peak memory 212936 kb
Host smart-592f37a1-a27e-4c0b-a031-2eee79542552
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505534283 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_
TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.keymgr_dpe_shadow_reg_errors_with_csr_rw.505534283
Directory /workspace/5.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_dpe_tl_errors.2061301425
Short name T260
Test name
Test status
Simulation time 1116618566 ps
CPU time 3.59 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 212632 kb
Host smart-abfc9eff-d227-4ff5-9412-1c0dcf701bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061301425 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_tl_errors.2
061301425
Directory /workspace/5.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_mem_rw_with_rand_reset.1991578591
Short name T100
Test name
Test status
Simulation time 22038088 ps
CPU time 1 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 212660 kb
Host smart-f9590cd8-3f41-4ffd-a6d9-01caa34264ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991578591 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_mem_rw_with_rand_reset.1991578591
Directory /workspace/6.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_csr_rw.2000268900
Short name T177
Test name
Test status
Simulation time 32692060 ps
CPU time 1.01 seconds
Started Apr 27 01:46:11 PM PDT 24
Finished Apr 27 01:46:14 PM PDT 24
Peak memory 204188 kb
Host smart-c7483c31-f2ba-4169-b8b7-5c376b3ebe4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000268900 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_csr_rw.2
000268900
Directory /workspace/6.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_intr_test.1215421404
Short name T307
Test name
Test status
Simulation time 23758765 ps
CPU time 0.79 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204236 kb
Host smart-388ee6e5-ef80-4d77-a719-4264d1a1dd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215421404 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_intr_test.1
215421404
Directory /workspace/6.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_same_csr_outstanding.405734642
Short name T221
Test name
Test status
Simulation time 61503053 ps
CPU time 1.25 seconds
Started Apr 27 01:46:12 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 204456 kb
Host smart-a1472abc-e216-41f6-9350-215bdd5e3c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405734642 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=
keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.ke
ymgr_dpe_same_csr_outstanding.405734642
Directory /workspace/6.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors.3774947162
Short name T82
Test name
Test status
Simulation time 141726979 ps
CPU time 2.68 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 212928 kb
Host smart-8654eff4-4dee-4139-ace8-8f7a4e7cc798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774947162 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keym
gr_dpe_shadow_reg_errors.3774947162
Directory /workspace/6.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219955573
Short name T302
Test name
Test status
Simulation time 737179380 ps
CPU time 9.62 seconds
Started Apr 27 01:46:21 PM PDT 24
Finished Apr 27 01:46:31 PM PDT 24
Peak memory 212880 kb
Host smart-28c56291-30f9-436f-80a8-a944f17695ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219955573 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.keymgr_dpe_shadow_reg_errors_with_csr_rw.2219955573
Directory /workspace/6.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_errors.3288349715
Short name T231
Test name
Test status
Simulation time 57698030 ps
CPU time 2.08 seconds
Started Apr 27 01:46:07 PM PDT 24
Finished Apr 27 01:46:10 PM PDT 24
Peak memory 212692 kb
Host smart-b87f17af-ef38-4163-b0b1-3efaeed5845e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288349715 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_tl_errors.3
288349715
Directory /workspace/6.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_dpe_tl_intg_err.139469052
Short name T25
Test name
Test status
Simulation time 164202401 ps
CPU time 2.66 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 212972 kb
Host smart-8c8c243f-8a28-4ecc-8f30-de8ecbf636e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139469052 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dp
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_
tl_intg_err.139469052
Directory /workspace/6.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_mem_rw_with_rand_reset.3607614483
Short name T28
Test name
Test status
Simulation time 46162521 ps
CPU time 1.29 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:10 PM PDT 24
Peak memory 212708 kb
Host smart-0346399b-5b22-4a62-bdf5-307d0b38b176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607614483 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_mem_rw_with_rand_reset.3607614483
Directory /workspace/7.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_csr_rw.1322493964
Short name T238
Test name
Test status
Simulation time 9624022 ps
CPU time 0.82 seconds
Started Apr 27 01:46:10 PM PDT 24
Finished Apr 27 01:46:13 PM PDT 24
Peak memory 204288 kb
Host smart-6c364af5-5515-431c-8714-54ce13aeb3a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322493964 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_csr_rw.1
322493964
Directory /workspace/7.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_intr_test.2557374626
Short name T276
Test name
Test status
Simulation time 8806287 ps
CPU time 0.87 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 204276 kb
Host smart-56c7f9d7-0084-44e7-be6f-15eec346df3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557374626 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_intr_test.2
557374626
Directory /workspace/7.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_same_csr_outstanding.4031182086
Short name T244
Test name
Test status
Simulation time 697751375 ps
CPU time 1.89 seconds
Started Apr 27 01:46:13 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 204444 kb
Host smart-a7313651-09a9-429c-a00d-0822f056532b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031182086 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_dpe_same_csr_outstanding.4031182086
Directory /workspace/7.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors.4199111250
Short name T62
Test name
Test status
Simulation time 101630462 ps
CPU time 3.02 seconds
Started Apr 27 01:46:12 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 212892 kb
Host smart-332598bd-a5b7-4e29-9bf2-c771a39a16f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199111250 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keym
gr_dpe_shadow_reg_errors.4199111250
Directory /workspace/7.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1081799701
Short name T262
Test name
Test status
Simulation time 450562218 ps
CPU time 3.12 seconds
Started Apr 27 01:46:32 PM PDT 24
Finished Apr 27 01:46:36 PM PDT 24
Peak memory 212960 kb
Host smart-8825dc62-c963-45b6-a3ea-4c7c8d46f720
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081799701 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.keymgr_dpe_shadow_reg_errors_with_csr_rw.1081799701
Directory /workspace/7.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_errors.2639074332
Short name T242
Test name
Test status
Simulation time 839244036 ps
CPU time 2.64 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 212700 kb
Host smart-2dbbd4be-3d68-4dd3-8b34-82f22dd33c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639074332 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_tl_errors.2
639074332
Directory /workspace/7.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_dpe_tl_intg_err.1127031804
Short name T51
Test name
Test status
Simulation time 708575004 ps
CPU time 6.89 seconds
Started Apr 27 01:46:12 PM PDT 24
Finished Apr 27 01:46:21 PM PDT 24
Peak memory 213776 kb
Host smart-446c3a3b-f280-444e-9cb8-7c70fe6f40d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127031804 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_d
pe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe
_tl_intg_err.1127031804
Directory /workspace/7.keymgr_dpe_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_mem_rw_with_rand_reset.3457069836
Short name T24
Test name
Test status
Simulation time 66364250 ps
CPU time 1.36 seconds
Started Apr 27 01:46:09 PM PDT 24
Finished Apr 27 01:46:12 PM PDT 24
Peak memory 212612 kb
Host smart-1b074a19-2592-44d4-bc16-c9668c891051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457069836 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_mem_rw_with_rand_reset.3457069836
Directory /workspace/8.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_csr_rw.1570415798
Short name T31
Test name
Test status
Simulation time 68416359 ps
CPU time 1.3 seconds
Started Apr 27 01:46:41 PM PDT 24
Finished Apr 27 01:46:43 PM PDT 24
Peak memory 204320 kb
Host smart-a98f8fd5-660c-4b6c-b73f-affbfdc0d281
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570415798 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_csr_rw.1
570415798
Directory /workspace/8.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_intr_test.4234204033
Short name T189
Test name
Test status
Simulation time 18417084 ps
CPU time 0.72 seconds
Started Apr 27 01:46:34 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 204184 kb
Host smart-5558f891-49e6-427f-b7d8-bda3ea505a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234204033 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_intr_test.4
234204033
Directory /workspace/8.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_same_csr_outstanding.3153915131
Short name T245
Test name
Test status
Simulation time 136687796 ps
CPU time 1.79 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:18 PM PDT 24
Peak memory 204332 kb
Host smart-0f49dc41-5707-4a52-8a12-b94440ea558b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153915131 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ
=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_dpe_same_csr_outstanding.3153915131
Directory /workspace/8.keymgr_dpe_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors.2142564909
Short name T194
Test name
Test status
Simulation time 116009642 ps
CPU time 2.01 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:19 PM PDT 24
Peak memory 212944 kb
Host smart-b2822dde-881e-49a6-a9c5-bbf1497d0edc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142564909 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keym
gr_dpe_shadow_reg_errors.2142564909
Directory /workspace/8.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_shadow_reg_errors_with_csr_rw.1750229328
Short name T188
Test name
Test status
Simulation time 85262765 ps
CPU time 3.58 seconds
Started Apr 27 01:46:17 PM PDT 24
Finished Apr 27 01:46:22 PM PDT 24
Peak memory 212952 kb
Host smart-7d5c4dd5-811e-4f1a-8477-0b5248949e68
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750229328 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.keymgr_dpe_shadow_reg_errors_with_csr_rw.1750229328
Directory /workspace/8.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_dpe_tl_errors.546490638
Short name T298
Test name
Test status
Simulation time 39375994 ps
CPU time 2.27 seconds
Started Apr 27 01:46:29 PM PDT 24
Finished Apr 27 01:46:32 PM PDT 24
Peak memory 220544 kb
Host smart-a4921cae-8c24-4922-bc2c-1d7c50ba87f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546490638 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_tl_errors.546490638
Directory /workspace/8.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_mem_rw_with_rand_reset.2863868620
Short name T19
Test name
Test status
Simulation time 57486036 ps
CPU time 1.45 seconds
Started Apr 27 01:46:28 PM PDT 24
Finished Apr 27 01:46:30 PM PDT 24
Peak memory 212632 kb
Host smart-5b5e6f8b-4719-4c47-add8-04cb06ee9986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863868620 -assert nopostproc +UVM_TESTNAME
=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_mem_rw_with_rand_reset.2863868620
Directory /workspace/9.keymgr_dpe_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_csr_rw.602258828
Short name T85
Test name
Test status
Simulation time 21700664 ps
CPU time 1.12 seconds
Started Apr 27 01:46:26 PM PDT 24
Finished Apr 27 01:46:27 PM PDT 24
Peak memory 204424 kb
Host smart-7a9894e8-9e1c-42cf-93c4-35983634b514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602258828 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_csr_rw.602258828
Directory /workspace/9.keymgr_dpe_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_intr_test.2964678102
Short name T270
Test name
Test status
Simulation time 25755860 ps
CPU time 0.77 seconds
Started Apr 27 01:46:15 PM PDT 24
Finished Apr 27 01:46:17 PM PDT 24
Peak memory 204208 kb
Host smart-a9691ee6-2b12-4dd2-89ec-4878095c662d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964678102 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_intr_test.2
964678102
Directory /workspace/9.keymgr_dpe_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors.3913137858
Short name T290
Test name
Test status
Simulation time 208965691 ps
CPU time 1.84 seconds
Started Apr 27 01:46:33 PM PDT 24
Finished Apr 27 01:46:35 PM PDT 24
Peak memory 212900 kb
Host smart-29f8a912-25da-43a9-b018-a441ebce622f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913137858 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=ke
ymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keym
gr_dpe_shadow_reg_errors.3913137858
Directory /workspace/9.keymgr_dpe_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2599655363
Short name T310
Test name
Test status
Simulation time 488384721 ps
CPU time 2.71 seconds
Started Apr 27 01:46:30 PM PDT 24
Finished Apr 27 01:46:33 PM PDT 24
Peak memory 212928 kb
Host smart-1182578c-e907-4971-92df-d84c8935c20b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599655363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM
_TEST_SEQ=keymgr_dpe_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.keymgr_dpe_shadow_reg_errors_with_csr_rw.2599655363
Directory /workspace/9.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_dpe_tl_errors.4139148760
Short name T39
Test name
Test status
Simulation time 205434451 ps
CPU time 2.32 seconds
Started Apr 27 01:46:12 PM PDT 24
Finished Apr 27 01:46:16 PM PDT 24
Peak memory 212552 kb
Host smart-71a6dbdd-cab6-41e9-9e00-7cc96208a787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139148760 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_tl_errors.4
139148760
Directory /workspace/9.keymgr_dpe_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_dpe_alert_test.227311364
Short name T127
Test name
Test status
Simulation time 17123193 ps
CPU time 0.69 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:28 PM PDT 24
Peak memory 205352 kb
Host smart-bcedb713-5654-463b-b3a8-c826af23cbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227311364 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_dpe_alert_test.227311364
Directory /workspace/0.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_dpe_alert_test.542470832
Short name T154
Test name
Test status
Simulation time 39541238 ps
CPU time 0.85 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:28 PM PDT 24
Peak memory 205256 kb
Host smart-77973c89-c548-43bb-b806-11427ae245c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542470832 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_dpe_alert_test.542470832
Directory /workspace/1.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_alert_test.2301141299
Short name T134
Test name
Test status
Simulation time 42321251 ps
CPU time 0.86 seconds
Started Apr 27 02:09:28 PM PDT 24
Finished Apr 27 02:09:29 PM PDT 24
Peak memory 205304 kb
Host smart-ae6bb8b1-154d-4c39-9535-1be80d9b1d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301141299 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_alert_test.
2301141299
Directory /workspace/10.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_dpe_smoke.1346887272
Short name T10
Test name
Test status
Simulation time 1494076816 ps
CPU time 23.97 seconds
Started Apr 27 02:09:24 PM PDT 24
Finished Apr 27 02:09:49 PM PDT 24
Peak memory 207764 kb
Host smart-e4a7d945-aa7f-418e-9621-0c7b79a4583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346887272 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_dpe_smoke.1346887272
Directory /workspace/10.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/11.keymgr_dpe_alert_test.3822799495
Short name T15
Test name
Test status
Simulation time 24524285 ps
CPU time 0.77 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:28 PM PDT 24
Peak memory 205312 kb
Host smart-df91d6ed-254a-43bc-aa3d-2a591d68070e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822799495 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_dpe_alert_test.
3822799495
Directory /workspace/11.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_dpe_alert_test.1204329883
Short name T133
Test name
Test status
Simulation time 11147289 ps
CPU time 0.74 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:09:33 PM PDT 24
Peak memory 205372 kb
Host smart-090faa65-0f67-4cc0-8f15-3fad3d752503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204329883 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_dpe_alert_test.
1204329883
Directory /workspace/12.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_alert_test.1867878980
Short name T161
Test name
Test status
Simulation time 11461297 ps
CPU time 0.75 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:35 PM PDT 24
Peak memory 205328 kb
Host smart-df6bacab-0c47-4032-8f8b-25fb692c4c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867878980 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_alert_test.
1867878980
Directory /workspace/14.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_dpe_smoke.2277305115
Short name T118
Test name
Test status
Simulation time 2099706094 ps
CPU time 16.08 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:50 PM PDT 24
Peak memory 206448 kb
Host smart-3f2e88f3-fd95-4816-9f81-0d4bda136fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277305115 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_dpe_smoke.2277305115
Directory /workspace/14.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/15.keymgr_dpe_alert_test.4066237554
Short name T172
Test name
Test status
Simulation time 57103530 ps
CPU time 0.71 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:09:34 PM PDT 24
Peak memory 205336 kb
Host smart-cf5f7795-a7a5-4107-b112-d30406daaea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066237554 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_dpe_alert_test.
4066237554
Directory /workspace/15.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_alert_test.3815013711
Short name T144
Test name
Test status
Simulation time 22362463 ps
CPU time 0.99 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 205564 kb
Host smart-5467c246-ad2e-4d7a-b17a-7fce65f1148a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815013711 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_alert_test.
3815013711
Directory /workspace/16.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_dpe_smoke.376601925
Short name T160
Test name
Test status
Simulation time 11082425452 ps
CPU time 259.72 seconds
Started Apr 27 02:09:37 PM PDT 24
Finished Apr 27 02:13:57 PM PDT 24
Peak memory 232216 kb
Host smart-02ecdd8c-921a-473e-b8eb-e1873c0d697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376601925 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_dpe_smoke.376601925
Directory /workspace/16.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/17.keymgr_dpe_alert_test.3438408507
Short name T176
Test name
Test status
Simulation time 20133512 ps
CPU time 1.02 seconds
Started Apr 27 02:09:36 PM PDT 24
Finished Apr 27 02:09:37 PM PDT 24
Peak memory 205504 kb
Host smart-b1e602ea-9c5a-4dc7-b4d8-0ec52a487354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438408507 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_alert_test.
3438408507
Directory /workspace/17.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_dpe_smoke.3963158813
Short name T159
Test name
Test status
Simulation time 615785951 ps
CPU time 9.93 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:45 PM PDT 24
Peak memory 208084 kb
Host smart-d8d4d737-2a46-45ab-a193-a0aa66464255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963158813 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_dpe_smoke.3963158813
Directory /workspace/17.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/18.keymgr_dpe_alert_test.1508026993
Short name T148
Test name
Test status
Simulation time 12108253 ps
CPU time 0.88 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 205392 kb
Host smart-b9819bd0-b64c-4684-9be3-4caab1198dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508026993 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_alert_test.
1508026993
Directory /workspace/18.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_dpe_smoke.1290843381
Short name T115
Test name
Test status
Simulation time 2037393989 ps
CPU time 21.76 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:56 PM PDT 24
Peak memory 206212 kb
Host smart-7dce6c20-50b1-43ec-acbb-23c803a99468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290843381 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_dpe_smoke.1290843381
Directory /workspace/18.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/19.keymgr_dpe_alert_test.140015566
Short name T142
Test name
Test status
Simulation time 21644688 ps
CPU time 0.71 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 205388 kb
Host smart-d0dac3a2-d6bb-4813-9c9e-05eb0577db2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140015566 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_alert_test.140015566
Directory /workspace/19.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_dpe_smoke.2169032303
Short name T119
Test name
Test status
Simulation time 21710855072 ps
CPU time 99.42 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:11:12 PM PDT 24
Peak memory 221868 kb
Host smart-58a4e315-ff9a-4a14-ae55-cd9031ec912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169032303 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_dpe_smoke.2169032303
Directory /workspace/19.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/2.keymgr_dpe_alert_test.1843329160
Short name T137
Test name
Test status
Simulation time 10678434 ps
CPU time 0.73 seconds
Started Apr 27 02:09:28 PM PDT 24
Finished Apr 27 02:09:29 PM PDT 24
Peak memory 205276 kb
Host smart-1dc9c593-d5d2-4d3d-85cd-dbdaa2d4147b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843329160 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_alert_test.1
843329160
Directory /workspace/2.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_dpe_sec_cm.2750205582
Short name T20
Test name
Test status
Simulation time 1796203003 ps
CPU time 6.56 seconds
Started Apr 27 02:09:29 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 232792 kb
Host smart-c0c2fe57-fcb0-4fc5-837f-cc41eb7a138a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750205582 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_sec_cm.2750205582
Directory /workspace/2.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_dpe_smoke.1145335164
Short name T95
Test name
Test status
Simulation time 902137824 ps
CPU time 18.3 seconds
Started Apr 27 02:09:28 PM PDT 24
Finished Apr 27 02:09:46 PM PDT 24
Peak memory 206292 kb
Host smart-0f3a4bc1-ab0a-4053-8e61-91326bf6ae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145335164 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_dpe_smoke.1145335164
Directory /workspace/2.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/20.keymgr_dpe_alert_test.930883000
Short name T165
Test name
Test status
Simulation time 26817643 ps
CPU time 0.75 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 205236 kb
Host smart-35b50d39-7a0d-4efe-a9aa-c4634c42c448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930883000 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_alert_test.930883000
Directory /workspace/20.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_dpe_smoke.582112282
Short name T158
Test name
Test status
Simulation time 274640142 ps
CPU time 11.7 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:45 PM PDT 24
Peak memory 207988 kb
Host smart-373cc56f-f1f2-47cf-a8f2-f21b2872ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582112282 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_dpe_smoke.582112282
Directory /workspace/20.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/21.keymgr_dpe_alert_test.2496204991
Short name T164
Test name
Test status
Simulation time 11673632 ps
CPU time 0.73 seconds
Started Apr 27 02:09:36 PM PDT 24
Finished Apr 27 02:09:37 PM PDT 24
Peak memory 205212 kb
Host smart-b53d4bf5-35fd-45db-aa52-0aa84fb3f27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496204991 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_alert_test.
2496204991
Directory /workspace/21.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_dpe_smoke.219345448
Short name T76
Test name
Test status
Simulation time 2331411603 ps
CPU time 35.81 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:10:08 PM PDT 24
Peak memory 207432 kb
Host smart-1cd69c2e-2a45-4052-806b-2ac7b8d94cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219345448 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_dpe_smoke.219345448
Directory /workspace/21.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/22.keymgr_dpe_alert_test.4089089885
Short name T128
Test name
Test status
Simulation time 22432237 ps
CPU time 0.76 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:34 PM PDT 24
Peak memory 205296 kb
Host smart-c8e66cb9-0972-4974-a0fa-12b20d8b7e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089089885 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_alert_test.
4089089885
Directory /workspace/22.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_dpe_smoke.1846561741
Short name T3
Test name
Test status
Simulation time 3498443690 ps
CPU time 19.18 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:54 PM PDT 24
Peak memory 207508 kb
Host smart-140fc0f8-56e6-4760-a14e-5854f2c516fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846561741 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_dpe_smoke.1846561741
Directory /workspace/22.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/23.keymgr_dpe_alert_test.4049221209
Short name T73
Test name
Test status
Simulation time 51522418 ps
CPU time 0.95 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:36 PM PDT 24
Peak memory 205520 kb
Host smart-cb2a210c-77a4-4286-b895-493e43f28c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049221209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_alert_test.
4049221209
Directory /workspace/23.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_dpe_smoke.543879132
Short name T149
Test name
Test status
Simulation time 3501340232 ps
CPU time 21.88 seconds
Started Apr 27 02:09:34 PM PDT 24
Finished Apr 27 02:09:57 PM PDT 24
Peak memory 208048 kb
Host smart-b6af9485-f976-4496-8d20-f68c019bd14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543879132 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_dpe_smoke.543879132
Directory /workspace/23.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/24.keymgr_dpe_alert_test.1190613763
Short name T135
Test name
Test status
Simulation time 44164907 ps
CPU time 0.87 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:09:34 PM PDT 24
Peak memory 205340 kb
Host smart-8d525ba1-a5b6-4b14-b80a-d209b854c235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190613763 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_alert_test.
1190613763
Directory /workspace/24.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_dpe_smoke.70096455
Short name T11
Test name
Test status
Simulation time 522578366 ps
CPU time 19.37 seconds
Started Apr 27 02:09:33 PM PDT 24
Finished Apr 27 02:09:54 PM PDT 24
Peak memory 208188 kb
Host smart-1e7e8827-bc3b-4d33-8074-fb5033c341dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70096455 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_dpe_smoke.70096455
Directory /workspace/24.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/25.keymgr_dpe_alert_test.1501597237
Short name T168
Test name
Test status
Simulation time 15524597 ps
CPU time 0.92 seconds
Started Apr 27 02:09:32 PM PDT 24
Finished Apr 27 02:09:34 PM PDT 24
Peak memory 205412 kb
Host smart-a7b40d7e-7462-4dff-ad5f-01699a5e3ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501597237 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_dpe_alert_test.
1501597237
Directory /workspace/25.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_alert_test.2852848248
Short name T125
Test name
Test status
Simulation time 13032781 ps
CPU time 0.8 seconds
Started Apr 27 02:09:38 PM PDT 24
Finished Apr 27 02:09:39 PM PDT 24
Peak memory 205368 kb
Host smart-6c64b45c-5809-493c-ad42-e80f3e493948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852848248 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_alert_test.
2852848248
Directory /workspace/26.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_dpe_smoke.4222849138
Short name T93
Test name
Test status
Simulation time 1600374505 ps
CPU time 15.44 seconds
Started Apr 27 02:09:41 PM PDT 24
Finished Apr 27 02:09:57 PM PDT 24
Peak memory 208096 kb
Host smart-7569b953-f263-47c9-b0de-63bd32996ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222849138 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_dpe_smoke.4222849138
Directory /workspace/26.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/27.keymgr_dpe_alert_test.3112188470
Short name T166
Test name
Test status
Simulation time 34010145 ps
CPU time 1.01 seconds
Started Apr 27 02:09:40 PM PDT 24
Finished Apr 27 02:09:41 PM PDT 24
Peak memory 205536 kb
Host smart-2bcd3385-9852-457d-90c6-90176569e4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112188470 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_alert_test.
3112188470
Directory /workspace/27.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_dpe_smoke.2283022830
Short name T157
Test name
Test status
Simulation time 9833832846 ps
CPU time 36.54 seconds
Started Apr 27 02:09:40 PM PDT 24
Finished Apr 27 02:10:18 PM PDT 24
Peak memory 208008 kb
Host smart-36f4855d-036e-4519-a60d-37978647e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283022830 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_dpe_smoke.2283022830
Directory /workspace/27.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/28.keymgr_dpe_alert_test.129088477
Short name T150
Test name
Test status
Simulation time 14713621 ps
CPU time 0.94 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:09:41 PM PDT 24
Peak memory 205468 kb
Host smart-4f0bed39-07c6-4286-ab49-cbb838b41acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129088477 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_alert_test.129088477
Directory /workspace/28.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_dpe_smoke.539805714
Short name T96
Test name
Test status
Simulation time 559333756 ps
CPU time 18.84 seconds
Started Apr 27 02:09:43 PM PDT 24
Finished Apr 27 02:10:02 PM PDT 24
Peak memory 207324 kb
Host smart-472228e5-d9de-414e-ad8c-745cb006754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539805714 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_dpe_smoke.539805714
Directory /workspace/28.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/29.keymgr_dpe_alert_test.1654688818
Short name T14
Test name
Test status
Simulation time 43932475 ps
CPU time 0.84 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:09:40 PM PDT 24
Peak memory 205292 kb
Host smart-89d962ef-ce24-4aa5-8a58-cc7f4bd1f535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654688818 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_dpe_alert_test.
1654688818
Directory /workspace/29.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_alert_test.4131669929
Short name T152
Test name
Test status
Simulation time 17836260 ps
CPU time 0.83 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:27 PM PDT 24
Peak memory 205372 kb
Host smart-1ad2f6ec-aca8-4901-9986-f1eaae763ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131669929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_alert_test.4
131669929
Directory /workspace/3.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_dpe_sec_cm.4167379746
Short name T5
Test name
Test status
Simulation time 808935405 ps
CPU time 10.04 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:38 PM PDT 24
Peak memory 233752 kb
Host smart-8f26d27f-0aa0-4160-b514-87a4c20bf608
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167379746 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_sec_cm.4167379746
Directory /workspace/3.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_dpe_smoke.2046802882
Short name T22
Test name
Test status
Simulation time 6907091338 ps
CPU time 30.81 seconds
Started Apr 27 02:09:28 PM PDT 24
Finished Apr 27 02:10:00 PM PDT 24
Peak memory 207544 kb
Host smart-7d765a95-8158-4420-b7ac-b8a4c454466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046802882 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_dpe_smoke.2046802882
Directory /workspace/3.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/30.keymgr_dpe_alert_test.483332467
Short name T74
Test name
Test status
Simulation time 12872505 ps
CPU time 0.86 seconds
Started Apr 27 02:09:41 PM PDT 24
Finished Apr 27 02:09:42 PM PDT 24
Peak memory 205324 kb
Host smart-2ac21cd8-12fc-48b5-9561-a81f621849d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483332467 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_dpe_alert_test.483332467
Directory /workspace/30.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_alert_test.2760337932
Short name T173
Test name
Test status
Simulation time 90591197 ps
CPU time 0.82 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:09:41 PM PDT 24
Peak memory 205248 kb
Host smart-90e3fb9a-6aed-4669-a820-991ef86a69c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760337932 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_alert_test.
2760337932
Directory /workspace/31.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_dpe_smoke.2108407082
Short name T141
Test name
Test status
Simulation time 596685925 ps
CPU time 20.73 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:10:01 PM PDT 24
Peak memory 207780 kb
Host smart-d2afc4e7-8c9c-4d5b-af3b-967c02bf13de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108407082 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_dpe_smoke.2108407082
Directory /workspace/31.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/32.keymgr_dpe_alert_test.2131207234
Short name T175
Test name
Test status
Simulation time 39183465 ps
CPU time 0.73 seconds
Started Apr 27 02:09:37 PM PDT 24
Finished Apr 27 02:09:39 PM PDT 24
Peak memory 205280 kb
Host smart-fe889b29-3f51-4185-bd1b-188aba26e386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131207234 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_dpe_alert_test.
2131207234
Directory /workspace/32.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_alert_test.2773340880
Short name T153
Test name
Test status
Simulation time 21849099 ps
CPU time 0.83 seconds
Started Apr 27 02:09:41 PM PDT 24
Finished Apr 27 02:09:43 PM PDT 24
Peak memory 205320 kb
Host smart-01bd3e2d-564d-478e-8526-be8553517826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773340880 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_alert_test.
2773340880
Directory /workspace/33.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_dpe_smoke.475339235
Short name T110
Test name
Test status
Simulation time 149770054 ps
CPU time 9.17 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:09:54 PM PDT 24
Peak memory 206784 kb
Host smart-2da0cb4e-dd4f-40f6-8883-057dab302e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475339235 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_dpe_smoke.475339235
Directory /workspace/33.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/34.keymgr_dpe_alert_test.4281734474
Short name T170
Test name
Test status
Simulation time 12444588 ps
CPU time 0.84 seconds
Started Apr 27 02:09:42 PM PDT 24
Finished Apr 27 02:09:43 PM PDT 24
Peak memory 205304 kb
Host smart-eb74399a-e669-4124-bd61-4e2328469d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281734474 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_dpe_alert_test.
4281734474
Directory /workspace/34.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_alert_test.2028853716
Short name T162
Test name
Test status
Simulation time 12066019 ps
CPU time 0.89 seconds
Started Apr 27 02:09:40 PM PDT 24
Finished Apr 27 02:09:42 PM PDT 24
Peak memory 205380 kb
Host smart-13c43cbb-ea79-49dc-8ae9-5a220a1ea171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028853716 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_alert_test.
2028853716
Directory /workspace/35.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_dpe_smoke.3142321069
Short name T98
Test name
Test status
Simulation time 1060501927 ps
CPU time 16.22 seconds
Started Apr 27 02:09:38 PM PDT 24
Finished Apr 27 02:09:55 PM PDT 24
Peak memory 207632 kb
Host smart-2bb51cf8-df0c-49e3-b204-41b04b13e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142321069 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_dpe_smoke.3142321069
Directory /workspace/35.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/36.keymgr_dpe_alert_test.1863554444
Short name T163
Test name
Test status
Simulation time 41081795 ps
CPU time 0.8 seconds
Started Apr 27 02:09:39 PM PDT 24
Finished Apr 27 02:09:40 PM PDT 24
Peak memory 205312 kb
Host smart-865d952e-5c4f-42e2-8b49-04074fe8b045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863554444 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_alert_test.
1863554444
Directory /workspace/36.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_dpe_smoke.2598049323
Short name T97
Test name
Test status
Simulation time 1639884607 ps
CPU time 16.16 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:10:00 PM PDT 24
Peak memory 207804 kb
Host smart-5d16e770-f3b0-477c-bf79-1c846c34b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598049323 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_dpe_smoke.2598049323
Directory /workspace/36.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/37.keymgr_dpe_alert_test.2965805929
Short name T155
Test name
Test status
Simulation time 50954495 ps
CPU time 0.87 seconds
Started Apr 27 02:09:40 PM PDT 24
Finished Apr 27 02:09:42 PM PDT 24
Peak memory 205392 kb
Host smart-ac30506c-e1a1-4029-ac4f-6113bddf9f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965805929 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_alert_test.
2965805929
Directory /workspace/37.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_dpe_smoke.1412348551
Short name T2
Test name
Test status
Simulation time 23581057086 ps
CPU time 94.2 seconds
Started Apr 27 02:09:41 PM PDT 24
Finished Apr 27 02:11:16 PM PDT 24
Peak memory 207892 kb
Host smart-770223bd-b5b6-41a7-a669-3290caa17a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412348551 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_dpe_smoke.1412348551
Directory /workspace/37.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/38.keymgr_dpe_alert_test.3745824637
Short name T130
Test name
Test status
Simulation time 17036795 ps
CPU time 0.76 seconds
Started Apr 27 02:09:46 PM PDT 24
Finished Apr 27 02:09:47 PM PDT 24
Peak memory 205200 kb
Host smart-426279e8-5f90-4f06-82c2-ca2549732944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745824637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_dpe_alert_test.
3745824637
Directory /workspace/38.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_dpe_alert_test.1445160944
Short name T169
Test name
Test status
Simulation time 15884069 ps
CPU time 0.78 seconds
Started Apr 27 02:09:47 PM PDT 24
Finished Apr 27 02:09:49 PM PDT 24
Peak memory 205324 kb
Host smart-701d5df0-f048-473a-94fe-5000268ac02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445160944 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_dpe_alert_test.
1445160944
Directory /workspace/39.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_alert_test.1840923758
Short name T147
Test name
Test status
Simulation time 94821034 ps
CPU time 0.8 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:28 PM PDT 24
Peak memory 205216 kb
Host smart-eeffdde3-eb97-4bb7-8523-d08d9f63fa30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840923758 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_alert_test.1
840923758
Directory /workspace/4.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_dpe_sec_cm.580625171
Short name T6
Test name
Test status
Simulation time 1029375908 ps
CPU time 23.56 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:50 PM PDT 24
Peak memory 238232 kb
Host smart-caf09fb9-72d5-46da-be2b-eb63e803bca9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580625171 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_sec_cm.580625171
Directory /workspace/4.keymgr_dpe_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_dpe_smoke.3445669835
Short name T7
Test name
Test status
Simulation time 2367646767 ps
CPU time 37.49 seconds
Started Apr 27 02:09:24 PM PDT 24
Finished Apr 27 02:10:02 PM PDT 24
Peak memory 207740 kb
Host smart-dd806009-82a5-412a-a0d0-ca77765ef682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445669835 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_dpe_smoke.3445669835
Directory /workspace/4.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/40.keymgr_dpe_alert_test.1896399028
Short name T78
Test name
Test status
Simulation time 42202500 ps
CPU time 0.74 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:09:46 PM PDT 24
Peak memory 205340 kb
Host smart-c6b3b84f-4c13-459a-9a57-8213ccd9db64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896399028 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_alert_test.
1896399028
Directory /workspace/40.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_dpe_smoke.3210568509
Short name T167
Test name
Test status
Simulation time 379178702 ps
CPU time 15.38 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:10:00 PM PDT 24
Peak memory 207656 kb
Host smart-c5a6ffc2-08ff-4e6d-811e-f320c2e2aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210568509 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_dpe_smoke.3210568509
Directory /workspace/40.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/41.keymgr_dpe_alert_test.1216870870
Short name T145
Test name
Test status
Simulation time 16369378 ps
CPU time 0.7 seconds
Started Apr 27 02:09:51 PM PDT 24
Finished Apr 27 02:09:52 PM PDT 24
Peak memory 205200 kb
Host smart-0054ad5a-ea71-40fe-887b-4e92c8e01f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216870870 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_dpe_alert_test.
1216870870
Directory /workspace/41.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_alert_test.1845171363
Short name T80
Test name
Test status
Simulation time 44092561 ps
CPU time 0.83 seconds
Started Apr 27 02:09:47 PM PDT 24
Finished Apr 27 02:09:49 PM PDT 24
Peak memory 205248 kb
Host smart-f301749a-c7d6-4836-bb5f-020f4a73f8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845171363 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_alert_test.
1845171363
Directory /workspace/42.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_dpe_smoke.1642197333
Short name T72
Test name
Test status
Simulation time 1075237239 ps
CPU time 19.97 seconds
Started Apr 27 02:09:46 PM PDT 24
Finished Apr 27 02:10:06 PM PDT 24
Peak memory 208108 kb
Host smart-54baece4-fd4b-45de-b950-d4ff07a46664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642197333 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_dpe_smoke.1642197333
Directory /workspace/42.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/43.keymgr_dpe_alert_test.1283898293
Short name T151
Test name
Test status
Simulation time 87565852 ps
CPU time 0.72 seconds
Started Apr 27 02:09:47 PM PDT 24
Finished Apr 27 02:09:48 PM PDT 24
Peak memory 205280 kb
Host smart-5336000a-24a6-46db-bb84-c57b36b59c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283898293 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_alert_test.
1283898293
Directory /workspace/43.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_dpe_smoke.2800561775
Short name T113
Test name
Test status
Simulation time 905368927 ps
CPU time 17.57 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:10:03 PM PDT 24
Peak memory 207232 kb
Host smart-17b786f4-be41-45ea-9140-8a1adb979880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800561775 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_dpe_smoke.2800561775
Directory /workspace/43.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/44.keymgr_dpe_alert_test.2800765105
Short name T138
Test name
Test status
Simulation time 12613643 ps
CPU time 0.85 seconds
Started Apr 27 02:09:48 PM PDT 24
Finished Apr 27 02:09:50 PM PDT 24
Peak memory 205348 kb
Host smart-bc182554-7c26-43d6-93cf-d848a408f08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800765105 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_alert_test.
2800765105
Directory /workspace/44.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_dpe_smoke.2809789399
Short name T174
Test name
Test status
Simulation time 211077659 ps
CPU time 11.77 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:09:58 PM PDT 24
Peak memory 208032 kb
Host smart-8c7491f7-a0d2-4dd6-be6b-ea93a47a107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809789399 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_dpe_smoke.2809789399
Directory /workspace/44.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/45.keymgr_dpe_alert_test.2666747512
Short name T16
Test name
Test status
Simulation time 82676787 ps
CPU time 0.73 seconds
Started Apr 27 02:09:44 PM PDT 24
Finished Apr 27 02:09:45 PM PDT 24
Peak memory 205276 kb
Host smart-36a3bcd4-922f-42ce-ad31-0e1729afb092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666747512 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_alert_test.
2666747512
Directory /workspace/45.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_dpe_smoke.3199051686
Short name T126
Test name
Test status
Simulation time 4727070862 ps
CPU time 25.87 seconds
Started Apr 27 02:09:48 PM PDT 24
Finished Apr 27 02:10:14 PM PDT 24
Peak memory 207880 kb
Host smart-8c274002-abb8-4cd4-9220-8f30cb545481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199051686 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_dpe_smoke.3199051686
Directory /workspace/45.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/46.keymgr_dpe_alert_test.3567179473
Short name T79
Test name
Test status
Simulation time 15459764 ps
CPU time 0.95 seconds
Started Apr 27 02:09:46 PM PDT 24
Finished Apr 27 02:09:47 PM PDT 24
Peak memory 205588 kb
Host smart-3a59622d-e030-4d96-8d97-076713b6edcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567179473 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_alert_test.
3567179473
Directory /workspace/46.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_dpe_smoke.1108951150
Short name T140
Test name
Test status
Simulation time 3585149630 ps
CPU time 22.01 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:10:07 PM PDT 24
Peak memory 207332 kb
Host smart-d7baa127-d0e1-4274-850d-0497c64309cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108951150 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_dpe_smoke.1108951150
Directory /workspace/46.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/47.keymgr_dpe_alert_test.1961644347
Short name T129
Test name
Test status
Simulation time 17203119 ps
CPU time 0.74 seconds
Started Apr 27 02:09:45 PM PDT 24
Finished Apr 27 02:09:46 PM PDT 24
Peak memory 205312 kb
Host smart-5b33b2fb-54f5-4863-a3fe-82222862c76a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961644347 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_dpe_alert_test.
1961644347
Directory /workspace/47.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_dpe_alert_test.828445209
Short name T136
Test name
Test status
Simulation time 44901732 ps
CPU time 0.73 seconds
Started Apr 27 02:09:47 PM PDT 24
Finished Apr 27 02:09:48 PM PDT 24
Peak memory 205388 kb
Host smart-6961f2ae-ce71-44c0-b4ff-b38c3d965a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828445209 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_dpe_alert_test.828445209
Directory /workspace/48.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_alert_test.1091583637
Short name T143
Test name
Test status
Simulation time 25675508 ps
CPU time 0.92 seconds
Started Apr 27 02:09:47 PM PDT 24
Finished Apr 27 02:09:48 PM PDT 24
Peak memory 205392 kb
Host smart-fae38dcf-e540-4e38-bbbe-8c037efa88cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091583637 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_alert_test.
1091583637
Directory /workspace/49.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_dpe_smoke.878916417
Short name T124
Test name
Test status
Simulation time 1602951416 ps
CPU time 17.48 seconds
Started Apr 27 02:09:48 PM PDT 24
Finished Apr 27 02:10:06 PM PDT 24
Peak memory 207740 kb
Host smart-285ea575-63ed-4236-b288-840e5b578d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878916417 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_dpe_smoke.878916417
Directory /workspace/49.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/5.keymgr_dpe_alert_test.2574198195
Short name T156
Test name
Test status
Simulation time 36888165 ps
CPU time 0.71 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:28 PM PDT 24
Peak memory 205332 kb
Host smart-7b32950e-e8fd-4d1d-a696-67284c0d8dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574198195 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_alert_test.2
574198195
Directory /workspace/5.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_dpe_smoke.1317534228
Short name T8
Test name
Test status
Simulation time 256722980 ps
CPU time 14.03 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:41 PM PDT 24
Peak memory 206200 kb
Host smart-75401db6-74b7-4b25-8dd6-efc4bca1288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317534228 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_dpe_smoke.1317534228
Directory /workspace/5.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/6.keymgr_dpe_alert_test.303668680
Short name T132
Test name
Test status
Simulation time 95776088 ps
CPU time 0.81 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:29 PM PDT 24
Peak memory 205368 kb
Host smart-e57c2867-945a-4d61-9e20-e915de8c4798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303668680 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_dpe_alert_test.303668680
Directory /workspace/6.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_alert_test.1674578324
Short name T139
Test name
Test status
Simulation time 26839863 ps
CPU time 0.94 seconds
Started Apr 27 02:09:25 PM PDT 24
Finished Apr 27 02:09:26 PM PDT 24
Peak memory 205556 kb
Host smart-08cd23f5-b304-4d30-b092-e798f58efc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674578324 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_alert_test.1
674578324
Directory /workspace/7.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_dpe_smoke.2054781847
Short name T13
Test name
Test status
Simulation time 6592826751 ps
CPU time 23.91 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:51 PM PDT 24
Peak memory 206580 kb
Host smart-455bf69d-d813-4d70-a227-27cc634ddf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054781847 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_dpe_smoke.2054781847
Directory /workspace/7.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/8.keymgr_dpe_alert_test.695373635
Short name T146
Test name
Test status
Simulation time 10651954 ps
CPU time 0.82 seconds
Started Apr 27 02:09:26 PM PDT 24
Finished Apr 27 02:09:27 PM PDT 24
Peak memory 205280 kb
Host smart-fc3f035e-e950-41aa-b1ad-71f305b1caf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695373635 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_alert_test.695373635
Directory /workspace/8.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_dpe_smoke.2396894257
Short name T94
Test name
Test status
Simulation time 499996415 ps
CPU time 13.69 seconds
Started Apr 27 02:09:27 PM PDT 24
Finished Apr 27 02:09:42 PM PDT 24
Peak memory 206044 kb
Host smart-53c60c4c-8684-4ba9-a528-f921c70849b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396894257 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_dpe_smoke.2396894257
Directory /workspace/8.keymgr_dpe_smoke/latest

Test location /workspace/coverage/default/9.keymgr_dpe_alert_test.2906814670
Short name T171
Test name
Test status
Simulation time 33622412 ps
CPU time 0.92 seconds
Started Apr 27 02:09:25 PM PDT 24
Finished Apr 27 02:09:27 PM PDT 24
Peak memory 205376 kb
Host smart-1ad7be97-8c2a-4510-aa9d-2a73220d2694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906814670 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_alert_test.2
906814670
Directory /workspace/9.keymgr_dpe_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_dpe_smoke.3011454984
Short name T116
Test name
Test status
Simulation time 2104588555 ps
CPU time 18.73 seconds
Started Apr 27 02:09:24 PM PDT 24
Finished Apr 27 02:09:43 PM PDT 24
Peak memory 207356 kb
Host smart-f448ae03-2635-427b-a4b8-ac9c3082ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011454984 -assert nopostproc +UVM_TESTNAME=keymgr_dpe_base_test +UVM_TEST_SEQ=keymgr_dpe_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_dpe_smoke.3011454984
Directory /workspace/9.keymgr_dpe_smoke/latest
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